1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" /* mv88e1xxx.h */ 27 28 #ifndef CHELSIO_MV8E1XXX_H 29 #define CHELSIO_MV8E1XXX_H 30 31 #ifndef BMCR_SPEED1000 32 # define BMCR_SPEED1000 0x40 33 #endif 34 35 #ifndef ADVERTISE_PAUSE 36 # define ADVERTISE_PAUSE 0x400 37 #endif 38 #ifndef ADVERTISE_PAUSE_ASYM 39 # define ADVERTISE_PAUSE_ASYM 0x800 40 #endif 41 42 /* Gigabit MII registers */ 43 #define MII_GBCR 9 /* 1000Base-T control register */ 44 #define MII_GBSR 10 /* 1000Base-T status register */ 45 46 /* 1000Base-T control register fields */ 47 #define GBCR_ADV_1000HALF 0x100 48 #define GBCR_ADV_1000FULL 0x200 49 #define GBCR_PREFER_MASTER 0x400 50 #define GBCR_MANUAL_AS_MASTER 0x800 51 #define GBCR_MANUAL_CONFIG_ENABLE 0x1000 52 53 /* 1000Base-T status register fields */ 54 #define GBSR_LP_1000HALF 0x400 55 #define GBSR_LP_1000FULL 0x800 56 #define GBSR_REMOTE_OK 0x1000 57 #define GBSR_LOCAL_OK 0x2000 58 #define GBSR_LOCAL_MASTER 0x4000 59 #define GBSR_MASTER_FAULT 0x8000 60 61 /* Marvell PHY interrupt status bits. */ 62 #define MV88E1XXX_INTR_JABBER 0x0001 63 #define MV88E1XXX_INTR_POLARITY_CHNG 0x0002 64 #define MV88E1XXX_INTR_ENG_DETECT_CHNG 0x0010 65 #define MV88E1XXX_INTR_DOWNSHIFT 0x0020 66 #define MV88E1XXX_INTR_MDI_XOVER_CHNG 0x0040 67 #define MV88E1XXX_INTR_FIFO_OVER_UNDER 0x0080 68 #define MV88E1XXX_INTR_FALSE_CARRIER 0x0100 69 #define MV88E1XXX_INTR_SYMBOL_ERROR 0x0200 70 #define MV88E1XXX_INTR_LINK_CHNG 0x0400 71 #define MV88E1XXX_INTR_AUTONEG_DONE 0x0800 72 #define MV88E1XXX_INTR_PAGE_RECV 0x1000 73 #define MV88E1XXX_INTR_DUPLEX_CHNG 0x2000 74 #define MV88E1XXX_INTR_SPEED_CHNG 0x4000 75 #define MV88E1XXX_INTR_AUTONEG_ERR 0x8000 76 77 /* Marvell PHY specific registers. */ 78 #define MV88E1XXX_SPECIFIC_CNTRL_REGISTER 16 79 #define MV88E1XXX_SPECIFIC_STATUS_REGISTER 17 80 #define MV88E1XXX_INTERRUPT_ENABLE_REGISTER 18 81 #define MV88E1XXX_INTERRUPT_STATUS_REGISTER 19 82 #define MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER 20 83 #define MV88E1XXX_RECV_ERR_CNTR_REGISTER 21 84 #define MV88E1XXX_RES_REGISTER 22 85 #define MV88E1XXX_GLOBAL_STATUS_REGISTER 23 86 #define MV88E1XXX_LED_CONTROL_REGISTER 24 87 #define MV88E1XXX_MANUAL_LED_OVERRIDE_REGISTER 25 88 #define MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_2_REGISTER 26 89 #define MV88E1XXX_EXT_PHY_SPECIFIC_STATUS_REGISTER 27 90 #define MV88E1XXX_VIRTUAL_CABLE_TESTER_REGISTER 28 91 #define MV88E1XXX_EXTENDED_ADDR_REGISTER 29 92 #define MV88E1XXX_EXTENDED_REGISTER 30 93 94 /* PHY specific control register fields */ 95 #define S_PSCR_MDI_XOVER_MODE 5 96 #define M_PSCR_MDI_XOVER_MODE 0x3 97 #define V_PSCR_MDI_XOVER_MODE(x) ((x) << S_PSCR_MDI_XOVER_MODE) 98 #define G_PSCR_MDI_XOVER_MODE(x) (((x) >> S_PSCR_MDI_XOVER_MODE) & M_PSCR_MDI_XOVER_MODE) 99 100 /* Extended PHY specific control register fields */ 101 #define S_DOWNSHIFT_ENABLE 8 102 #define V_DOWNSHIFT_ENABLE (1 << S_DOWNSHIFT_ENABLE) 103 104 #define S_DOWNSHIFT_CNT 9 105 #define M_DOWNSHIFT_CNT 0x7 106 #define V_DOWNSHIFT_CNT(x) ((x) << S_DOWNSHIFT_CNT) 107 #define G_DOWNSHIFT_CNT(x) (((x) >> S_DOWNSHIFT_CNT) & M_DOWNSHIFT_CNT) 108 109 /* PHY specific status register fields */ 110 #define S_PSSR_JABBER 0 111 #define V_PSSR_JABBER (1 << S_PSSR_JABBER) 112 113 #define S_PSSR_POLARITY 1 114 #define V_PSSR_POLARITY (1 << S_PSSR_POLARITY) 115 116 #define S_PSSR_RX_PAUSE 2 117 #define V_PSSR_RX_PAUSE (1 << S_PSSR_RX_PAUSE) 118 119 #define S_PSSR_TX_PAUSE 3 120 #define V_PSSR_TX_PAUSE (1 << S_PSSR_TX_PAUSE) 121 122 #define S_PSSR_ENERGY_DETECT 4 123 #define V_PSSR_ENERGY_DETECT (1 << S_PSSR_ENERGY_DETECT) 124 125 #define S_PSSR_DOWNSHIFT_STATUS 5 126 #define V_PSSR_DOWNSHIFT_STATUS (1 << S_PSSR_DOWNSHIFT_STATUS) 127 128 #define S_PSSR_MDI 6 129 #define V_PSSR_MDI (1 << S_PSSR_MDI) 130 131 #define S_PSSR_CABLE_LEN 7 132 #define M_PSSR_CABLE_LEN 0x7 133 #define V_PSSR_CABLE_LEN(x) ((x) << S_PSSR_CABLE_LEN) 134 #define G_PSSR_CABLE_LEN(x) (((x) >> S_PSSR_CABLE_LEN) & M_PSSR_CABLE_LEN) 135 136 #define S_PSSR_LINK 10 137 #define V_PSSR_LINK (1 << S_PSSR_LINK) 138 139 #define S_PSSR_STATUS_RESOLVED 11 140 #define V_PSSR_STATUS_RESOLVED (1 << S_PSSR_STATUS_RESOLVED) 141 142 #define S_PSSR_PAGE_RECEIVED 12 143 #define V_PSSR_PAGE_RECEIVED (1 << S_PSSR_PAGE_RECEIVED) 144 145 #define S_PSSR_DUPLEX 13 146 #define V_PSSR_DUPLEX (1 << S_PSSR_DUPLEX) 147 148 #define S_PSSR_SPEED 14 149 #define M_PSSR_SPEED 0x3 150 #define V_PSSR_SPEED(x) ((x) << S_PSSR_SPEED) 151 #define G_PSSR_SPEED(x) (((x) >> S_PSSR_SPEED) & M_PSSR_SPEED) 152 153 #endif 154