1 //===--- SIProgramInfo.h ----------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// Defines struct to track resource usage and hardware flags for kernels and 11 /// entry functions. 12 /// 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_LIB_TARGET_AMDGPU_SIPROGRAMINFO_H 17 #define LLVM_LIB_TARGET_AMDGPU_SIPROGRAMINFO_H 18 19 #include "llvm/IR/CallingConv.h" 20 #include "llvm/Support/Compiler.h" 21 #include <cstdint> 22 23 namespace llvm { 24 25 class GCNSubtarget; 26 class MCContext; 27 class MCExpr; 28 class MachineFunction; 29 30 /// Track resource usage for kernels / entry functions. 31 struct LLVM_EXTERNAL_VISIBILITY SIProgramInfo { 32 // Fields set in PGM_RSRC1 pm4 packet. 33 const MCExpr *VGPRBlocks = nullptr; 34 const MCExpr *SGPRBlocks = nullptr; 35 uint32_t Priority = 0; 36 uint32_t FloatMode = 0; 37 uint32_t Priv = 0; 38 uint32_t DX10Clamp = 0; 39 uint32_t DebugMode = 0; 40 uint32_t IEEEMode = 0; 41 uint32_t WgpMode = 0; // GFX10+ 42 uint32_t MemOrdered = 0; // GFX10+ 43 uint32_t RrWgMode = 0; // GFX12+ 44 const MCExpr *ScratchSize = nullptr; 45 46 // State used to calculate fields set in PGM_RSRC2 pm4 packet. 47 uint32_t LDSBlocks = 0; 48 const MCExpr *ScratchBlocks = nullptr; 49 50 // Fields set in PGM_RSRC2 pm4 packet 51 const MCExpr *ScratchEnable = nullptr; 52 uint32_t UserSGPR = 0; 53 uint32_t TrapHandlerEnable = 0; 54 uint32_t TGIdXEnable = 0; 55 uint32_t TGIdYEnable = 0; 56 uint32_t TGIdZEnable = 0; 57 uint32_t TGSizeEnable = 0; 58 uint32_t TIdIGCompCount = 0; 59 uint32_t EXCPEnMSB = 0; 60 uint32_t LdsSize = 0; 61 uint32_t EXCPEnable = 0; 62 63 const MCExpr *ComputePGMRSrc3GFX90A = nullptr; 64 65 const MCExpr *NumVGPR = nullptr; 66 const MCExpr *NumArchVGPR = nullptr; 67 const MCExpr *NumAccVGPR = nullptr; 68 const MCExpr *AccumOffset = nullptr; 69 uint32_t TgSplit = 0; 70 const MCExpr *NumSGPR = nullptr; 71 unsigned SGPRSpill = 0; 72 unsigned VGPRSpill = 0; 73 uint32_t LDSSize = 0; 74 const MCExpr *FlatUsed = nullptr; 75 76 // Number of SGPRs that meets number of waves per execution unit request. 77 const MCExpr *NumSGPRsForWavesPerEU = nullptr; 78 79 // Number of VGPRs that meets number of waves per execution unit request. 80 const MCExpr *NumVGPRsForWavesPerEU = nullptr; 81 82 // Final occupancy. 83 const MCExpr *Occupancy = nullptr; 84 85 // Whether there is recursion, dynamic allocas, indirect calls or some other 86 // reason there may be statically unknown stack usage. 87 const MCExpr *DynamicCallStack = nullptr; 88 89 // Bonus information for debugging. 90 const MCExpr *VCCUsed = nullptr; 91 92 SIProgramInfo() = default; 93 94 // The constructor sets the values for each member as shown in the struct. 95 // However, setting the MCExpr members to their zero value equivalent 96 // happens in reset together with (duplicated) value re-set for the 97 // non-MCExpr members. 98 void reset(const MachineFunction &MF); 99 100 /// Compute the value of the ComputePGMRsrc1 register. 101 const MCExpr *getComputePGMRSrc1(const GCNSubtarget &ST, 102 MCContext &Ctx) const; 103 const MCExpr *getPGMRSrc1(CallingConv::ID CC, const GCNSubtarget &ST, 104 MCContext &Ctx) const; 105 106 /// Compute the value of the ComputePGMRsrc2 register. 107 const MCExpr *getComputePGMRSrc2(MCContext &Ctx) const; 108 const MCExpr *getPGMRSrc2(CallingConv::ID CC, MCContext &Ctx) const; 109 }; 110 111 } // namespace llvm 112 113 #endif // LLVM_LIB_TARGET_AMDGPU_SIPROGRAMINFO_H 114