| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsMCCodeEmitter.cpp | 152 encodeInstruction(const MCInst & MI,raw_ostream & OS,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodeInstruction() argument
235 getBranchTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValue() argument
257 getBranchTargetOpValue1SImm16(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValue1SImm16() argument
279 getBranchTargetOpValueMMR6(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValueMMR6() argument
302 getBranchTargetOpValueLsl2MMR6(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValueLsl2MMR6() argument
325 getBranchTarget7OpValueMM(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTarget7OpValueMM() argument
346 getBranchTargetOpValueMMPC10(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValueMMPC10() argument
367 getBranchTargetOpValueMM(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValueMM() argument
389 getBranchTarget21OpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTarget21OpValue() argument
411 getBranchTarget21OpValueMM(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTarget21OpValueMM() argument
433 getBranchTarget26OpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTarget26OpValue() argument
454 getBranchTarget26OpValueMM(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTarget26OpValueMM() argument
477 getJumpOffset16OpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getJumpOffset16OpValue() argument
498 getJumpTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getJumpTargetOpValue() argument
515 getJumpTargetOpValueMM(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getJumpTargetOpValueMM() argument
532 getUImm5Lsl2Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getUImm5Lsl2Encoding() argument
550 getSImm3Lsa2Value(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSImm3Lsa2Value() argument
563 getUImm6Lsl2Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getUImm6Lsl2Encoding() argument
576 getSImm9AddiuspValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSImm9AddiuspValue() argument
588 getExprOpValue(const MCExpr * Expr,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getExprOpValue() argument
733 getMachineOpValue(const MCInst & MI,const MCOperand & MO,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMachineOpValue() argument
753 getMemEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncoding() argument
769 getMemEncodingMMImm4(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMImm4() argument
783 getMemEncodingMMImm4Lsl1(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMImm4Lsl1() argument
797 getMemEncodingMMImm4Lsl2(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMImm4Lsl2() argument
811 getMemEncodingMMSPImm5Lsl2(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMSPImm5Lsl2() argument
826 getMemEncodingMMGPImm7Lsl2(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMGPImm7Lsl2() argument
841 getMemEncodingMMImm9(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMImm9() argument
855 getMemEncodingMMImm11(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMImm11() argument
868 getMemEncodingMMImm12(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMImm12() argument
892 getMemEncodingMMImm16(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMImm16() argument
905 getMemEncodingMMImm4sp(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMImm4sp() argument
933 getSizeInsEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSizeInsEncoding() argument
946 getUImmWithOffsetEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getUImmWithOffsetEncoding() argument
956 getSimm19Lsl2Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSimm19Lsl2Encoding() argument
978 getSimm18Lsl3Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSimm18Lsl3Encoding() argument
1000 getUImm3Mod8Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getUImm3Mod8Encoding() argument
1009 getUImm4AndValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getUImm4AndValue() argument
1037 getRegisterListOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getRegisterListOpValue() argument
1057 getRegisterListOpValue16(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getRegisterListOpValue16() argument
1064 getMovePRegPairOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMovePRegPairOpValue() argument
1098 getMovePRegSingleOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMovePRegSingleOpValue() argument
1121 getSimm23Lsl2Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSimm23Lsl2Encoding() argument
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| H A D | PPCMCCodeEmitter.cpp | 43 getDirectBrEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDirectBrEncoding() argument
61 getCondBrEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getCondBrEncoding() argument
74 getAbsDirectBrEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAbsDirectBrEncoding() argument
87 getAbsCondBrEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAbsCondBrEncoding() argument
100 getVSRpEvenEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVSRpEvenEncoding() argument
109 getImm16Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getImm16Encoding() argument
121 getImm34Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI,MCFixupKind Fixup) const getImm34Encoding() argument
136 getImm34EncodingNoPCRel(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getImm34EncodingNoPCRel() argument
144 getImm34EncodingPCRel(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getImm34EncodingPCRel() argument
151 getDispRIEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispRIEncoding() argument
165 getDispRIXEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispRIXEncoding() argument
179 getDispRIX16Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispRIX16Encoding() argument
196 getDispRIHashEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispRIHashEncoding() argument
211 getDispRI34PCRelEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispRI34PCRelEncoding() argument
294 getDispRI34Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispRI34Encoding() argument
303 getDispSPE8Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispSPE8Encoding() argument
313 getDispSPE4Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispSPE4Encoding() argument
323 getDispSPE2Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispSPE2Encoding() argument
332 getTLSRegEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getTLSRegEncoding() argument
352 getTLSCallEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getTLSCallEncoding() argument
365 get_crbitm_encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const get_crbitm_encoding() argument
390 getMachineOpValue(const MCInst & MI,const MCOperand & MO,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMachineOpValue() argument
412 encodeInstruction(const MCInst & MI,SmallVectorImpl<char> & CB,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodeInstruction() argument
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCCodeEmitter.cpp | 218 getMachineOpValue(const MCInst & MI,const MCOperand & MO,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMachineOpValue() argument
229 getLdStUImm12OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getLdStUImm12OpValue() argument
250 getAdrLabelOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAdrLabelOpValue() argument
276 getAddSubImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddSubImmOpValue() argument
312 getCondBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getCondBranchTargetOpValue() argument
334 getLoadLiteralOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getLoadLiteralOpValue() argument
354 getMemExtendOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemExtendOpValue() argument
363 getMoveWideImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMoveWideImmOpValue() argument
382 getTestBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getTestBranchTargetOpValue() argument
404 getBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValue() argument
432 getVecShifterOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShifterOpValue() argument
456 getFixedPointScaleOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getFixedPointScaleOpValue() argument
465 getVecShiftR64OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftR64OpValue() argument
474 getVecShiftR32OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftR32OpValue() argument
483 getVecShiftR16OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftR16OpValue() argument
492 getVecShiftR8OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftR8OpValue() argument
501 getVecShiftL64OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftL64OpValue() argument
510 getVecShiftL32OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftL32OpValue() argument
519 getVecShiftL16OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftL16OpValue() argument
528 getVecShiftL8OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftL8OpValue() argument
538 EncodeRegAsMultipleOf(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const EncodeRegAsMultipleOf() argument
548 EncodePPR_p8to15(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const EncodePPR_p8to15() argument
555 EncodeZPR2StridedRegisterClass(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const EncodeZPR2StridedRegisterClass() argument
565 EncodeZPR4StridedRegisterClass(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const EncodeZPR4StridedRegisterClass() argument
575 EncodeMatrixTileListRegisterClass(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const EncodeMatrixTileListRegisterClass() argument
585 encodeMatrixIndexGPR32(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodeMatrixIndexGPR32() argument
593 getImm8OptLsl(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getImm8OptLsl() argument
611 getSVEIncDecImm(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSVEIncDecImm() argument
622 getMoveVecShifterOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMoveVecShifterOpValue() argument
667 encodeInstruction(const MCInst & MI,SmallVectorImpl<char> & CB,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodeInstruction() argument
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 233 getLdStmModeOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getLdStmModeOpValue() argument
308 getCCOutOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getCCOutOpValue() argument
316 getModImmOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & ST) const getModImmOpValue() argument
335 getT2SOImmOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2SOImmOpValue() argument
376 getNEONVcvtImm32OpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getNEONVcvtImm32OpValue() argument
554 getMachineOpValue(const MCInst & MI,const MCOperand & MO,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMachineOpValue() argument
593 EncodeAddrModeOpValues(const MCInst & MI,unsigned OpIdx,unsigned & Reg,unsigned & Imm,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const EncodeAddrModeOpValues() argument
623 getBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,unsigned FixupKind,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) getBranchTargetOpValue() argument
660 getThumbBLTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbBLTargetOpValue() argument
673 getThumbBLXTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbBLXTargetOpValue() argument
685 getThumbBRTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbBRTargetOpValue() argument
697 getThumbBCCTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbBCCTargetOpValue() argument
709 getThumbCBTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbCBTargetOpValue() argument
738 getBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValue() argument
752 getARMBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getARMBranchTargetOpValue() argument
768 getARMBLTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getARMBLTargetOpValue() argument
783 getARMBLXTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getARMBLXTargetOpValue() argument
795 getThumbBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbBranchTargetOpValue() argument
825 getAdrLabelOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAdrLabelOpValue() argument
866 getT2AdrLabelOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2AdrLabelOpValue() argument
886 getITMaskOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getITMaskOpValue() argument
913 getThumbAdrLabelOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbAdrLabelOpValue() argument
942 getMVEShiftImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMVEShiftImmOpValue() argument
976 getAddrModeImm12OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrModeImm12OpValue() argument
1031 getT2ScaledImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2ScaledImmOpValue() argument
1062 getMveAddrModeRQOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMveAddrModeRQOpValue() argument
1082 getMveAddrModeQOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMveAddrModeQOpValue() argument
1113 getT2AddrModeImm8s4OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2AddrModeImm8s4OpValue() argument
1155 getT2AddrModeImm7s4OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2AddrModeImm7s4OpValue() argument
1182 getT2AddrModeImm0_1020s4OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2AddrModeImm0_1020s4OpValue() argument
1194 getHiLoImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getHiLoImmOpValue() argument
1282 getLdStSORegOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getLdStSORegOpValue() argument
1316 getAddrMode2OffsetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode2OffsetOpValue() argument
1339 getPostIdxRegOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getPostIdxRegOpValue() argument
1351 getAddrMode3OffsetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode3OffsetOpValue() argument
1371 getAddrMode3OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode3OpValue() argument
1408 getAddrModeThumbSPOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrModeThumbSPOpValue() argument
1424 getAddrModeISOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrModeISOpValue() argument
1439 getAddrModePCOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrModePCOpValue() argument
1450 getAddrMode5OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode5OpValue() argument
1490 getAddrMode5FP16OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode5FP16OpValue() argument
1529 getSORegRegOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSORegRegOpValue() argument
1577 getSORegImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSORegImmOpValue() argument
1624 getT2AddrModeSORegOpValue(const MCInst & MI,unsigned OpNum,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2AddrModeSORegOpValue() argument
1644 getT2AddrModeImmOpValue(const MCInst & MI,unsigned OpNum,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2AddrModeImmOpValue() argument
1669 getT2AddrModeImm8OffsetOpValue(const MCInst & MI,unsigned OpNum,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2AddrModeImm8OffsetOpValue() argument
1686 getT2SORegOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2SORegOpValue() argument
1729 getBitfieldInvertedMaskOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBitfieldInvertedMaskOpValue() argument
1743 getRegisterListOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getRegisterListOpValue() argument
1790 getAddrMode6AddressOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode6AddressOpValue() argument
1814 getAddrMode6OneLane32AddressOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode6OneLane32AddressOpValue() argument
1841 getAddrMode6DupAddressOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode6DupAddressOpValue() argument
1862 getAddrMode6OffsetOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode6OffsetOpValue() argument
1871 getShiftRight8Imm(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getShiftRight8Imm() argument
1878 getShiftRight16Imm(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getShiftRight16Imm() argument
1885 getShiftRight32Imm(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getShiftRight32Imm() argument
1892 getShiftRight64Imm(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getShiftRight64Imm() argument
1899 encodeInstruction(const MCInst & MI,raw_ostream & OS,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodeInstruction() argument
1927 getBFTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBFTargetOpValue() argument
1937 getBFAfterTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBFAfterTargetOpValue() argument
1959 getVPTMaskOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVPTMaskOpValue() argument
1990 getRestrictedCondCodeOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getRestrictedCondCodeOpValue() argument
2019 getPowerTwoOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getPowerTwoOpValue() argument
2029 getMVEPairVectorIndexOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMVEPairVectorIndexOpValue() argument
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| H A D | SystemZMCCodeEmitter.cpp | 88 SmallVectorImpl<MCFixup> &Fixups, in getPC16DBLEncoding()
94 SmallVectorImpl<MCFixup> &Fixups, in getPC32DBLEncoding()
100 SmallVectorImpl<MCFixup> &Fixups, in getPC16DBLTLSEncoding()
106 SmallVectorImpl<MCFixup> &Fixups, in getPC32DBLTLSEncoding()
112 SmallVectorImpl<MCFixup> &Fixups, in getPC12DBLBPPEncoding()
118 SmallVectorImpl<MCFixup> &Fixups, in getPC16DBLBPPEncoding()
124 SmallVectorImpl<MCFixup> &Fixups, in getPC24DBLBPPEncoding()
135 SmallVectorImpl<MCFixup> &Fixups, in encodeInstruction()
149 SmallVectorImpl<MCFixup> &Fixups, in getMachineOpValue()
162 SmallVectorImpl<MCFixup> &Fixups, in getImmOpValue()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/MCTargetDesc/ |
| H A D | XtensaMCCodeEmitter.cpp | 127 SmallVectorImpl<MCFixup> &Fixups, in encodeInstruction()
147 SmallVectorImpl<MCFixup> &Fixups, in getMachineOpValue()
162 SmallVectorImpl<MCFixup> &Fixups, in getJumpTargetEncoding()
176 const MCInst &MI, unsigned int OpNum, SmallVectorImpl<MCFixup> &Fixups, in getBranchTargetEncoding()
200 SmallVectorImpl<MCFixup> &Fixups, in getCallEncoding()
221 SmallVectorImpl<MCFixup> &Fixups, in getL32RTargetEncoding()
241 SmallVectorImpl<MCFixup> &Fixups, in getMemRegEncoding()
274 SmallVectorImpl<MCFixup> &Fixups, in getImm8OpValue()
286 SmallVectorImpl<MCFixup> &Fixups, in getImm8_sh8OpValue()
299 SmallVectorImpl<MCFixup> &Fixups, in getImm12OpValue()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/ |
| H A D | CSKYMCCodeEmitter.cpp | 31 SmallVectorImpl<MCFixup> &Fixups, in getOImmOpValue() argument
40 SmallVectorImpl<MCFixup> &Fixups, in getImmOpValueIDLY() argument
51 SmallVectorImpl<MCFixup> &Fixups, in getImmOpValueMSBSize() argument
71 expandJBTF(const MCInst & MI,raw_ostream & OS,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const expandJBTF() argument
97 expandNEG(const MCInst & MI,raw_ostream & OS,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const expandNEG() argument
119 expandRSUBI(const MCInst & MI,raw_ostream & OS,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const expandRSUBI() argument
141 encodeInstruction(const MCInst & MI,raw_ostream & OS,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodeInstruction() argument
246 getMachineOpValue(const MCInst & MI,const MCOperand & MO,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMachineOpValue() argument
260 getRegSeqImmOpValue(const MCInst & MI,unsigned Idx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getRegSeqImmOpValue() argument
276 getRegisterSeqOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getRegisterSeqOpValue() argument
289 getImmJMPIX(const MCInst & MI,unsigned Idx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getImmJMPIX() argument
[all...] |
| H A D | CSKYMCCodeEmitter.h | 51 SmallVectorImpl<MCFixup> &Fixups, in getImmOpValue() argument
89 getImmShiftOpValue(const MCInst & MI,unsigned Idx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) getImmShiftOpValue() argument
100 getBranchSymbolOpValue(const MCInst & MI,unsigned Idx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) getBranchSymbolOpValue() argument
119 getConstpoolSymbolOpValue(const MCInst & MI,unsigned Idx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) getConstpoolSymbolOpValue() argument
134 getDataSymbolOpValue(const MCInst & MI,unsigned Idx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) getDataSymbolOpValue() argument
148 getCallSymbolOpValue(const MCInst & MI,unsigned Idx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) getCallSymbolOpValue() argument
162 getBareSymbolOpValue(const MCInst & MI,unsigned Idx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) getBareSymbolOpValue() argument
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/ |
| H A D | AVRMCCodeEmitter.cpp | 94 SmallVectorImpl<MCFixup> &Fixups, in encodeRelCondBrTarget() argument
114 SmallVectorImpl<MCFixup> &Fixups, in encodeLDSTPtrReg() argument
138 SmallVectorImpl<MCFixup> &Fixups, in encodeMemri() argument
175 SmallVectorImpl<MCFixup> &Fixups, in encodeComplement() argument
186 SmallVectorImpl<MCFixup> &Fixups, in encodeImm() argument
211 encodeCallTarget(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodeCallTarget() argument
229 getExprOpValue(const MCExpr * Expr,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getExprOpValue() argument
257 getMachineOpValue(const MCInst & MI,const MCOperand & MO,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMachineOpValue() argument
275 encodeInstruction(const MCInst & MI,SmallVectorImpl<char> & CB,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodeInstruction() argument
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/ |
| H A D | SparcMCCodeEmitter.cpp | 92 SmallVectorImpl<MCFixup> &Fixups, in encodeInstruction() argument
123 getMachineOpValue(const MCInst & MI,const MCOperand & MO,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMachineOpValue() argument
149 getSImm13OpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSImm13OpValue() argument
180 getCallTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getCallTargetOpValue() argument
207 getBranchTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValue() argument
220 getBranchPredTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchPredTargetOpValue() argument
233 getBranchOnRegTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchOnRegTargetOpValue() argument
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMCCodeEmitter.cpp | 121 SmallVectorImpl<MCFixup> &Fixups, in expandFunctionCall()
167 SmallVectorImpl<MCFixup> &Fixups, in expandTLSDESCCall()
188 SmallVectorImpl<MCFixup> &Fixups, in expandAddTPRel()
247 SmallVectorImpl<MCFixup> &Fixups, in expandLongCondBr()
307 SmallVectorImpl<MCFixup> &Fixups, in encodeInstruction()
365 SmallVectorImpl<MCFixup> &Fixups, in getMachineOpValue()
380 SmallVectorImpl<MCFixup> &Fixups, in getImmOpValueAsr1()
394 SmallVectorImpl<MCFixup> &Fixups, in getImmOpValue()
537 SmallVectorImpl<MCFixup> &Fixups, in getVMaskReg()
553 SmallVectorImpl<MCFixup> &Fixups, in getRlistOpValue()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/MCTargetDesc/ |
| H A D | LoongArchMCCodeEmitter.cpp | 83 SmallVectorImpl<MCFixup> &Fixups, in getImmOpValueAsr()
102 SmallVectorImpl<MCFixup> &Fixups, in getMachineOpValue()
118 SmallVectorImpl<MCFixup> &Fixups, in getImmOpValueSub1()
125 SmallVectorImpl<MCFixup> &Fixups, in getExprOpValue()
350 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const { in expandToVectorLDI()
376 SmallVectorImpl<MCFixup> &Fixups, in expandAddTPRel()
408 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const { in encodeInstruction()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/ |
| H A D | MSP430MCCodeEmitter.cpp | 84 SmallVectorImpl<MCFixup> &Fixups, in encodeInstruction() argument
104 getMachineOpValue(const MCInst & MI,const MCOperand & MO,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMachineOpValue() argument
122 getMemOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemOpValue() argument
154 getPCRelImmOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getPCRelImmOpValue() argument
167 getCGImmOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getCGImmOpValue() argument
186 getCCOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getCCOpValue() argument
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/ |
| H A D | VEMCCodeEmitter.cpp | 82 SmallVectorImpl<MCFixup> &Fixups, in encodeInstruction() argument
92 SmallVectorImpl<MCFixup> &Fixups, in getMachineOpValue() argument
118 getBranchTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValue() argument
130 getCCOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getCCOpValue() argument
140 getRDOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getRDOpValue() argument
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiMCCodeEmitter.cpp | 111 const MCInst &Inst, const MCOperand &MCOp, SmallVectorImpl<MCFixup> &Fixups, in getMachineOpValue() argument
175 encodeInstruction(const MCInst & Inst,SmallVectorImpl<char> & CB,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & SubtargetInfo) const encodeInstruction() argument
186 getRiMemoryOpValue(const MCInst & Inst,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & SubtargetInfo) const getRiMemoryOpValue() argument
218 getRrMemoryOpValue(const MCInst & Inst,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & SubtargetInfo) const getRrMemoryOpValue() argument
257 getSplsOpValue(const MCInst & Inst,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & SubtargetInfo) const getSplsOpValue() argument
289 getBranchTargetOpValue(const MCInst & Inst,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & SubtargetInfo) const getBranchTargetOpValue() argument
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | AMDGPUMCCodeEmitter.cpp | 364 SmallVectorImpl<MCFixup> &Fixups, in encodeInstruction()
458 SmallVectorImpl<MCFixup> &Fixups, in getSOPPBrEncoding()
474 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const { in getSMEMOffsetEncoding()
483 SmallVectorImpl<MCFixup> &Fixups, in getSDWASrcEncoding()
514 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const { in getSDWAVopcDstEncoding()
532 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const { in getAVOperandEncoding()
586 SmallVectorImpl<MCFixup> &Fixups, in getMachineOpValue()
601 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const { in getMachineOpValueT16()
648 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const { in getMachineOpValueT16Lo128()
664 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const { in getMachineOpValueCommon()
|
| H A D | AMDGPUFixupKinds.h | 16 enum Fixups { enum
|
| H A D | R600MCCodeEmitter.cpp | 88 SmallVectorImpl<MCFixup> &Fixups, in encodeInstruction()
154 SmallVectorImpl<MCFixup> &Fixups, in getMachineOpValue()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/MCTargetDesc/ |
| H A D | M68kMCCodeEmitter.cpp | 115 encodeRelocImm(const MCInst & MI,unsigned OpIdx,unsigned InsertPos,APInt & Value,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodeRelocImm() argument
142 encodePCRelImm(const MCInst & MI,unsigned OpIdx,unsigned InsertPos,APInt & Value,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodePCRelImm() argument
177 getMachineOpValue(const MCInst & MI,const MCOperand & Op,unsigned InsertPos,APInt & Value,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMachineOpValue() argument
204 encodeInstruction(const MCInst & MI,SmallVectorImpl<char> & CB,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodeInstruction() argument
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FixupVectorConstants.cpp | 350 unsigned OperandNo) { in processInstruction()
448 FixupEntry Fixups[] = { in processInstruction() local
467 FixupEntry Fixups[] = { in processInstruction() local
492 FixupEntry Fixups[] = { in processInstruction() local
519 FixupEntry Fixups[] = { in processInstruction() local
544 FixupEntry Fixups[] = { in processInstruction() local
568 FixupEntry Fixups[] = { in processInstruction() local
613 FixupEntry Fixups[] = {{(int)OpBcst32, 32, 32, rebuildSplatCst}, in processInstruction() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/ |
| H A D | BPFMCCodeEmitter.cpp | 80 getMachineOpValue(const MCInst & MI,const MCOperand & MO,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMachineOpValue() argument
112 encodeInstruction(const MCInst & MI,SmallVectorImpl<char> & CB,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodeInstruction() argument
150 getMemoryOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemoryOpValue() argument
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCodeEmitter.cpp | 369 SmallVectorImpl<MCFixup> &Fixups, in encodeInstruction() argument
400 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI, in encodeSingleInstruction() argument
577 getExprOpValue(const MCInst & MI,const MCOperand & MO,const MCExpr * ME,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getExprOpValue() argument
709 getMachineOpValue(MCInst const & MI,MCOperand const & MO,SmallVectorImpl<MCFixup> & Fixups,MCSubtargetInfo const & STI) const getMachineOpValue() argument
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCCodeEmitter.cpp | 20 encodeInstruction(const MCInst & Inst,SmallVectorImpl<char> & CB,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodeInstruction() argument
|
| /freebsd/contrib/llvm-project/llvm/lib/MCA/ |
| H A D | CodeEmitter.cpp | 23 SmallVector<llvm::MCFixup, 2> Fixups; in getOrCreateEncodingInfo() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
| H A D | WebAssemblyFixupKinds.h | 16 enum Fixups { enum
|