| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchAsmPrinter.cpp | 101 unsigned RegID = MO.getReg().id(), FirstReg; in PrintAsmOperand() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64InstPrinter.cpp | 1695 if (MCRegister FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1697 else if (MCRegister FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
1699 else if (MCRegister FirstReg = MRI.getSubReg(Reg, AArch64::zsub0)) in printVectorList() local
1701 else if (MCRegister FirstReg = MRI.getSubReg(Reg, AArch64::psub0)) in printVectorList() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FunctionLoweringInfo.cpp | 391 Register FirstReg; in CreateRegs() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 3384 MCRegister FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToGPR() local
3401 MCRegister FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToFPR() local
3453 MCRegister FirstReg = Inst.getOperand(0).getReg(); in expandLoadDoubleImmToGPR() local
3516 MCRegister FirstReg = Inst.getOperand(0).getReg(); in expandLoadDoubleImmToFPR() local
4355 MCRegister FirstReg = Inst.getOperand(0).getReg(); in expandTrunc() local
5296 MCRegister FirstReg = Inst.getOperand(0).getReg(); in expandLoadStoreDMacro() local
5343 MCRegister FirstReg = Inst.getOperand(0).getReg(); in expandStoreDM1Macro() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 494 Register FirstReg; in ScanInstruction() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 2254 Register &FirstReg, Register &SecondReg, Register &BaseReg, int &Offset, in CanFormLdStDWord()
2413 Register FirstReg, SecondReg; in RescheduleOps() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 4541 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, in copyByValRegs()
4594 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, in passByValArg()
4741 unsigned FirstReg = 0; in HandleByVal() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1891 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs]; in addVectorListOperands() local
4547 unsigned FirstReg, ElementWidth; in tryParseMatrixTileList() local
4637 MCRegister FirstReg; in tryParseVectorList() local
8408 MCRegister FirstReg; in tryParseGPRSeqPair() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1627 Register FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect() local
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| H A D | PPCISelLowering.cpp | 7066 const MCRegister FirstReg = State.AllocateReg(PPC::R9); in CC_AIX() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 3251 unsigned FirstReg = 0; in computeCalleeSaveRegisterPairs() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 4926 MCRegister FirstReg = Reg; in parseVectorList() local
|