1 /**************************************************************************
2 SPDX-License-Identifier: BSD-2-Clause
3
4 Copyright (c) 2008, Chelsio Inc.
5 All rights reserved.
6
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
12
13 2. Neither the name of the Chelsio Corporation nor the names of its
14 contributors may be used to endorse or promote products derived from
15 this software without specific prior written permission.
16
17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 POSSIBILITY OF SUCH DAMAGE.
28
29 ***************************************************************************/
30
31 #include <sys/cdefs.h>
32 #include <cxgb_include.h>
33
34 #undef msleep
35 #define msleep t3_os_sleep
36
37 /* TN1010 PHY specific registers. */
38 enum {
39 TN1010_VEND1_STAT = 1,
40 };
41
42 /* IEEE auto-negotiation 10GBASE-T registers */
43 enum {
44 ANEG_ADVER = 16,
45 ANEG_LPA = 19,
46 ANEG_10G_CTRL = 32,
47 ANEG_10G_STAT = 33
48 };
49
50 #define ADVERTISE_ENPAGE (1 << 12)
51 #define ADVERTISE_10000FULL (1 << 12)
52 #define ADVERTISE_LOOP_TIMING (1 << 0)
53
54 /* vendor specific status register fields */
55 #define F_XS_LANE_ALIGN_STAT (1 << 0)
56 #define F_PCS_BLK_LOCK (1 << 1)
57 #define F_PMD_SIGNAL_OK (1 << 2)
58 #define F_LINK_STAT (1 << 3)
59 #define F_ANEG_SPEED_1G (1 << 4)
60 #define F_ANEG_MASTER (1 << 5)
61
62 #define S_ANEG_STAT 6
63 #define M_ANEG_STAT 0x3
64 #define G_ANEG_STAT(x) (((x) >> S_ANEG_STAT) & M_ANEG_STAT)
65
66 enum { /* autonegotiation status */
67 ANEG_IN_PROGR = 0,
68 ANEG_COMPLETE = 1,
69 ANEG_FAILED = 3
70 };
71
72 /*
73 * Reset the PHY. May take up to 500ms to complete.
74 */
tn1010_reset(struct cphy * phy,int wait)75 static int tn1010_reset(struct cphy *phy, int wait)
76 {
77 int err = t3_phy_reset(phy, MDIO_DEV_PMA_PMD, wait);
78 msleep(500);
79 return err;
80 }
81
tn1010_power_down(struct cphy * phy,int enable)82 static int tn1010_power_down(struct cphy *phy, int enable)
83 {
84 return t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR,
85 BMCR_PDOWN, enable ? BMCR_PDOWN : 0);
86 }
87
tn1010_autoneg_enable(struct cphy * phy)88 static int tn1010_autoneg_enable(struct cphy *phy)
89 {
90 int err;
91
92 err = tn1010_power_down(phy, 0);
93 if (!err)
94 err = t3_mdio_change_bits(phy, MDIO_DEV_ANEG, MII_BMCR, 0,
95 BMCR_ANENABLE | BMCR_ANRESTART);
96 return err;
97 }
98
tn1010_autoneg_restart(struct cphy * phy)99 static int tn1010_autoneg_restart(struct cphy *phy)
100 {
101 int err;
102
103 err = tn1010_power_down(phy, 0);
104 if (!err)
105 err = t3_mdio_change_bits(phy, MDIO_DEV_ANEG, MII_BMCR, 0,
106 BMCR_ANRESTART);
107 return err;
108 }
109
tn1010_advertise(struct cphy * phy,unsigned int advert)110 static int tn1010_advertise(struct cphy *phy, unsigned int advert)
111 {
112 int err, val;
113
114 if (!(advert & ADVERTISED_1000baseT_Full))
115 return -EINVAL; /* PHY can't disable 1000BASE-T */
116
117 val = ADVERTISE_CSMA | ADVERTISE_ENPAGE | ADVERTISE_NPAGE;
118 if (advert & ADVERTISED_Pause)
119 val |= ADVERTISE_PAUSE_CAP;
120 if (advert & ADVERTISED_Asym_Pause)
121 val |= ADVERTISE_PAUSE_ASYM;
122 err = mdio_write(phy, MDIO_DEV_ANEG, ANEG_ADVER, val);
123 if (err)
124 return err;
125
126 val = (advert & ADVERTISED_10000baseT_Full) ? ADVERTISE_10000FULL : 0;
127 return mdio_write(phy, MDIO_DEV_ANEG, ANEG_10G_CTRL, val |
128 ADVERTISE_LOOP_TIMING);
129 }
130
tn1010_get_link_status(struct cphy * phy,int * link_state,int * speed,int * duplex,int * fc)131 static int tn1010_get_link_status(struct cphy *phy, int *link_state,
132 int *speed, int *duplex, int *fc)
133 {
134 unsigned int status, lpa, adv;
135 int err, sp = -1, pause = 0;
136
137 err = mdio_read(phy, MDIO_DEV_VEND1, TN1010_VEND1_STAT, &status);
138 if (err)
139 return err;
140
141 if (link_state)
142 *link_state = status & F_LINK_STAT ? PHY_LINK_UP :
143 PHY_LINK_DOWN;
144
145 if (G_ANEG_STAT(status) == ANEG_COMPLETE) {
146 sp = (status & F_ANEG_SPEED_1G) ? SPEED_1000 : SPEED_10000;
147
148 if (fc) {
149 err = mdio_read(phy, MDIO_DEV_ANEG, ANEG_LPA, &lpa);
150 if (!err)
151 err = mdio_read(phy, MDIO_DEV_ANEG, ANEG_ADVER,
152 &adv);
153 if (err)
154 return err;
155
156 if (lpa & adv & ADVERTISE_PAUSE_CAP)
157 pause = PAUSE_RX | PAUSE_TX;
158 else if ((lpa & ADVERTISE_PAUSE_CAP) &&
159 (lpa & ADVERTISE_PAUSE_ASYM) &&
160 (adv & ADVERTISE_PAUSE_ASYM))
161 pause = PAUSE_TX;
162 else if ((lpa & ADVERTISE_PAUSE_ASYM) &&
163 (adv & ADVERTISE_PAUSE_CAP))
164 pause = PAUSE_RX;
165 }
166 }
167 if (speed)
168 *speed = sp;
169 if (duplex)
170 *duplex = DUPLEX_FULL;
171 if (fc)
172 *fc = pause;
173 return 0;
174 }
175
tn1010_set_speed_duplex(struct cphy * phy,int speed,int duplex)176 static int tn1010_set_speed_duplex(struct cphy *phy, int speed, int duplex)
177 {
178 return -EINVAL; /* require autoneg */
179 }
180
181 #ifdef C99_NOT_SUPPORTED
182 static struct cphy_ops tn1010_ops = {
183 tn1010_reset,
184 t3_phy_lasi_intr_enable,
185 t3_phy_lasi_intr_disable,
186 t3_phy_lasi_intr_clear,
187 t3_phy_lasi_intr_handler,
188 tn1010_autoneg_enable,
189 tn1010_autoneg_restart,
190 tn1010_advertise,
191 NULL,
192 tn1010_set_speed_duplex,
193 tn1010_get_link_status,
194 tn1010_power_down,
195 };
196 #else
197 static struct cphy_ops tn1010_ops = {
198 .reset = tn1010_reset,
199 .intr_enable = t3_phy_lasi_intr_enable,
200 .intr_disable = t3_phy_lasi_intr_disable,
201 .intr_clear = t3_phy_lasi_intr_clear,
202 .intr_handler = t3_phy_lasi_intr_handler,
203 .autoneg_enable = tn1010_autoneg_enable,
204 .autoneg_restart = tn1010_autoneg_restart,
205 .advertise = tn1010_advertise,
206 .set_speed_duplex = tn1010_set_speed_duplex,
207 .get_link_status = tn1010_get_link_status,
208 .power_down = tn1010_power_down,
209 };
210 #endif
211
t3_tn1010_phy_prep(pinfo_t * pinfo,int phy_addr,const struct mdio_ops * mdio_ops)212 int t3_tn1010_phy_prep(pinfo_t *pinfo, int phy_addr,
213 const struct mdio_ops *mdio_ops)
214 {
215 cphy_init(&pinfo->phy, pinfo->adapter, pinfo, phy_addr, &tn1010_ops, mdio_ops,
216 SUPPORTED_1000baseT_Full | SUPPORTED_10000baseT_Full |
217 SUPPORTED_Autoneg | SUPPORTED_AUI | SUPPORTED_TP,
218 "1000/10GBASE-T");
219 msleep(500); /* PHY needs up to 500ms to start responding to MDIO */
220 return 0;
221 }
222