1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved. 24 */ 25 26 /* 27 * FPGA specific definitions 28 */ 29 30 #pragma ident "%Z%%M% %I% %E% SMI" /* fpga_defs.h */ 31 32 #ifndef __CHELSIO_FPGA_DEFS_H__ 33 #define __CHELSIO_FPGA_DEFS_H__ 34 35 #define FPGA_PCIX_ADDR_VERSION 0xA08 36 #define FPGA_PCIX_ADDR_STAT 0xA0C 37 38 /* FPGA master interrupt Cause/Enable bits */ 39 #define FPGA_PCIX_INTERRUPT_SGE_ERROR 0x1 40 #define FPGA_PCIX_INTERRUPT_SGE_DATA 0x2 41 #define FPGA_PCIX_INTERRUPT_TP 0x4 42 #define FPGA_PCIX_INTERRUPT_MC3 0x8 43 #define FPGA_PCIX_INTERRUPT_GMAC 0x10 44 #define FPGA_PCIX_INTERRUPT_PCIX 0x20 45 46 /* TP interrupt register addresses */ 47 #define FPGA_TP_ADDR_INTERRUPT_ENABLE 0xA10 48 #define FPGA_TP_ADDR_INTERRUPT_CAUSE 0xA14 49 #define FPGA_TP_ADDR_VERSION 0xA18 50 51 /* TP interrupt Cause/Enable bits */ 52 #define FPGA_TP_INTERRUPT_MC4 0x1 53 #define FPGA_TP_INTERRUPT_MC5 0x2 54 55 /* 56 * PM interrupt register addresses 57 */ 58 #define FPGA_MC3_REG_INTRENABLE 0xA20 59 #define FPGA_MC3_REG_INTRCAUSE 0xA24 60 #define FPGA_MC3_REG_VERSION 0xA28 61 62 /* 63 * GMAC interrupt register addresses 64 */ 65 #define FPGA_GMAC_ADDR_INTERRUPT_ENABLE 0xA30 66 #define FPGA_GMAC_ADDR_INTERRUPT_CAUSE 0xA34 67 #define FPGA_GMAC_ADDR_VERSION 0xA38 68 69 /* GMAC Cause/Enable bits */ 70 #define FPGA_GMAC_INTERRUPT_PORT0 0x1 71 #define FPGA_GMAC_INTERRUPT_PORT1 0x2 72 #define FPGA_GMAC_INTERRUPT_PORT2 0x4 73 #define FPGA_GMAC_INTERRUPT_PORT3 0x8 74 75 /* MI0 registers */ 76 #define A_MI0_CLK 0xb00 77 78 #define S_MI0_CLK_DIV 0 79 #define M_MI0_CLK_DIV 0xff 80 #define V_MI0_CLK_DIV(x) ((x) << S_MI0_CLK_DIV) 81 #define G_MI0_CLK_DIV(x) (((x) >> S_MI0_CLK_DIV) & M_MI0_CLK_DIV) 82 83 #define S_MI0_CLK_CNT 8 84 #define M_MI0_CLK_CNT 0xff 85 #define V_MI0_CLK_CNT(x) ((x) << S_MI0_CLK_CNT) 86 #define G_MI0_CLK_CNT(x) (((x) >> S_MI0_CLK_CNT) & M_MI0_CLK_CNT) 87 88 #define A_MI0_CSR 0xb04 89 90 #define S_MI0_CSR_POLL 0 91 #define V_MI0_CSR_POLL(x) ((x) << S_MI0_CSR_POLL) 92 #define F_MI0_CSR_POLL V_MI0_CSR_POLL(1U) 93 94 #define S_MI0_PREAMBLE 1 95 #define V_MI0_PREAMBLE(x) ((x) << S_MI0_PREAMBLE) 96 #define F_MI0_PREAMBLE V_MI0_PREAMBLE(1U) 97 98 #define S_MI0_INTR_ENABLE 2 99 #define V_MI0_INTR_ENABLE(x) ((x) << S_MI0_INTR_ENABLE) 100 #define F_MI0_INTR_ENABLE V_MI0_INTR_ENABLE(1U) 101 102 #define S_MI0_BUSY 3 103 #define V_MI0_BUSY(x) ((x) << S_MI0_BUSY) 104 #define F_MI0_BUSY V_MI0_BUSY(1U) 105 106 #define S_MI0_MDIO 4 107 #define V_MI0_MDIO(x) ((x) << S_MI0_MDIO) 108 #define F_MI0_MDIO V_MI0_MDIO(1U) 109 110 #define A_MI0_ADDR 0xb08 111 112 #define S_MI0_PHY_REG_ADDR 0 113 #define M_MI0_PHY_REG_ADDR 0x1f 114 #define V_MI0_PHY_REG_ADDR(x) ((x) << S_MI0_PHY_REG_ADDR) 115 #define G_MI0_PHY_REG_ADDR(x) (((x) >> S_MI0_PHY_REG_ADDR) & M_MI0_PHY_REG_ADDR) 116 117 #define S_MI0_PHY_ADDR 5 118 #define M_MI0_PHY_ADDR 0x1f 119 #define V_MI0_PHY_ADDR(x) ((x) << S_MI0_PHY_ADDR) 120 #define G_MI0_PHY_ADDR(x) (((x) >> S_MI0_PHY_ADDR) & M_MI0_PHY_ADDR) 121 122 #define A_MI0_DATA_EXT 0xb0c 123 #define A_MI0_DATA_INT 0xb10 124 125 /* GMAC registers */ 126 #define A_GMAC_MACID_LO 0x28 127 #define A_GMAC_MACID_HI 0x2c 128 #define A_GMAC_CSR 0x30 129 130 #define S_INTERFACE 0 131 #define M_INTERFACE 0x3 132 #define V_INTERFACE(x) ((x) << S_INTERFACE) 133 #define G_INTERFACE(x) (((x) >> S_INTERFACE) & M_INTERFACE) 134 135 #define S_MAC_TX_ENABLE 2 136 #define V_MAC_TX_ENABLE(x) ((x) << S_MAC_TX_ENABLE) 137 #define F_MAC_TX_ENABLE V_MAC_TX_ENABLE(1U) 138 139 #define S_MAC_RX_ENABLE 3 140 #define V_MAC_RX_ENABLE(x) ((x) << S_MAC_RX_ENABLE) 141 #define F_MAC_RX_ENABLE V_MAC_RX_ENABLE(1U) 142 143 #define S_MAC_LB_ENABLE 4 144 #define V_MAC_LB_ENABLE(x) ((x) << S_MAC_LB_ENABLE) 145 #define F_MAC_LB_ENABLE V_MAC_LB_ENABLE(1U) 146 147 #define S_MAC_SPEED 5 148 #define M_MAC_SPEED 0x3 149 #define V_MAC_SPEED(x) ((x) << S_MAC_SPEED) 150 #define G_MAC_SPEED(x) (((x) >> S_MAC_SPEED) & M_MAC_SPEED) 151 152 #define S_MAC_HD_FC_ENABLE 7 153 #define V_MAC_HD_FC_ENABLE(x) ((x) << S_MAC_HD_FC_ENABLE) 154 #define F_MAC_HD_FC_ENABLE V_MAC_HD_FC_ENABLE(1U) 155 156 #define S_MAC_HALF_DUPLEX 8 157 #define V_MAC_HALF_DUPLEX(x) ((x) << S_MAC_HALF_DUPLEX) 158 #define F_MAC_HALF_DUPLEX V_MAC_HALF_DUPLEX(1U) 159 160 #define S_MAC_PROMISC 9 161 #define V_MAC_PROMISC(x) ((x) << S_MAC_PROMISC) 162 #define F_MAC_PROMISC V_MAC_PROMISC(1U) 163 164 #define S_MAC_MC_ENABLE 10 165 #define V_MAC_MC_ENABLE(x) ((x) << S_MAC_MC_ENABLE) 166 #define F_MAC_MC_ENABLE V_MAC_MC_ENABLE(1U) 167 168 #define S_MAC_RESET 11 169 #define V_MAC_RESET(x) ((x) << S_MAC_RESET) 170 #define F_MAC_RESET V_MAC_RESET(1U) 171 172 #define S_MAC_RX_PAUSE_ENABLE 12 173 #define V_MAC_RX_PAUSE_ENABLE(x) ((x) << S_MAC_RX_PAUSE_ENABLE) 174 #define F_MAC_RX_PAUSE_ENABLE V_MAC_RX_PAUSE_ENABLE(1U) 175 176 #define S_MAC_TX_PAUSE_ENABLE 13 177 #define V_MAC_TX_PAUSE_ENABLE(x) ((x) << S_MAC_TX_PAUSE_ENABLE) 178 #define F_MAC_TX_PAUSE_ENABLE V_MAC_TX_PAUSE_ENABLE(1U) 179 180 #define S_MAC_LWM_ENABLE 14 181 #define V_MAC_LWM_ENABLE(x) ((x) << S_MAC_LWM_ENABLE) 182 #define F_MAC_LWM_ENABLE V_MAC_LWM_ENABLE(1U) 183 184 #define S_MAC_MAGIC_PKT_ENABLE 15 185 #define V_MAC_MAGIC_PKT_ENABLE(x) ((x) << S_MAC_MAGIC_PKT_ENABLE) 186 #define F_MAC_MAGIC_PKT_ENABLE V_MAC_MAGIC_PKT_ENABLE(1U) 187 188 #define S_MAC_ISL_ENABLE 16 189 #define V_MAC_ISL_ENABLE(x) ((x) << S_MAC_ISL_ENABLE) 190 #define F_MAC_ISL_ENABLE V_MAC_ISL_ENABLE(1U) 191 192 #define S_MAC_JUMBO_ENABLE 17 193 #define V_MAC_JUMBO_ENABLE(x) ((x) << S_MAC_JUMBO_ENABLE) 194 #define F_MAC_JUMBO_ENABLE V_MAC_JUMBO_ENABLE(1U) 195 196 #define S_MAC_RX_PAD_ENABLE 18 197 #define V_MAC_RX_PAD_ENABLE(x) ((x) << S_MAC_RX_PAD_ENABLE) 198 #define F_MAC_RX_PAD_ENABLE V_MAC_RX_PAD_ENABLE(1U) 199 200 #define S_MAC_RX_CRC_ENABLE 19 201 #define V_MAC_RX_CRC_ENABLE(x) ((x) << S_MAC_RX_CRC_ENABLE) 202 #define F_MAC_RX_CRC_ENABLE V_MAC_RX_CRC_ENABLE(1U) 203 204 #define A_GMAC_IFS 0x34 205 206 #define S_MAC_IFS2 0 207 #define M_MAC_IFS2 0x3f 208 #define V_MAC_IFS2(x) ((x) << S_MAC_IFS2) 209 #define G_MAC_IFS2(x) (((x) >> S_MAC_IFS2) & M_MAC_IFS2) 210 211 #define S_MAC_IFS1 8 212 #define M_MAC_IFS1 0x7f 213 #define V_MAC_IFS1(x) ((x) << S_MAC_IFS1) 214 #define G_MAC_IFS1(x) (((x) >> S_MAC_IFS1) & M_MAC_IFS1) 215 216 #define A_GMAC_JUMBO_FRAME_LEN 0x38 217 #define A_GMAC_LNK_DLY 0x3c 218 #define A_GMAC_PAUSETIME 0x40 219 #define A_GMAC_MCAST_LO 0x44 220 #define A_GMAC_MCAST_HI 0x48 221 #define A_GMAC_MCAST_MASK_LO 0x4c 222 #define A_GMAC_MCAST_MASK_HI 0x50 223 #define A_GMAC_RMT_CNT 0x54 224 #define A_GMAC_RMT_DATA 0x58 225 #define A_GMAC_BACKOFF_SEED 0x5c 226 #define A_GMAC_TXF_THRES 0x60 227 228 #define S_TXF_READ_THRESHOLD 0 229 #define M_TXF_READ_THRESHOLD 0xff 230 #define V_TXF_READ_THRESHOLD(x) ((x) << S_TXF_READ_THRESHOLD) 231 #define G_TXF_READ_THRESHOLD(x) (((x) >> S_TXF_READ_THRESHOLD) & M_TXF_READ_THRESHOLD) 232 233 #define S_TXF_WRITE_THRESHOLD 16 234 #define M_TXF_WRITE_THRESHOLD 0xff 235 #define V_TXF_WRITE_THRESHOLD(x) ((x) << S_TXF_WRITE_THRESHOLD) 236 #define G_TXF_WRITE_THRESHOLD(x) (((x) >> S_TXF_WRITE_THRESHOLD) & M_TXF_WRITE_THRESHOLD) 237 238 #define MAC_REG_BASE 0x600 239 #define MAC_REG_ADDR(idx, reg) (MAC_REG_BASE + (idx) * 128 + (reg)) 240 241 #define MAC_REG_IDLO(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_LO) 242 #define MAC_REG_IDHI(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_HI) 243 #define MAC_REG_CSR(idx) MAC_REG_ADDR(idx, A_GMAC_CSR) 244 #define MAC_REG_IFS(idx) MAC_REG_ADDR(idx, A_GMAC_IFS) 245 #define MAC_REG_LARGEFRAMELENGTH(idx) MAC_REG_ADDR(idx, A_GMAC_JUMBO_FRAME_LEN) 246 #define MAC_REG_LINKDLY(idx) MAC_REG_ADDR(idx, A_GMAC_LNK_DLY) 247 #define MAC_REG_PAUSETIME(idx) MAC_REG_ADDR(idx, A_GMAC_PAUSETIME) 248 #define MAC_REG_CASTLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_LO) 249 #define MAC_REG_MCASTHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_HI) 250 #define MAC_REG_CASTMASKLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_LO) 251 #define MAC_REG_MCASTMASKHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_HI) 252 #define MAC_REG_RMCNT(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_CNT) 253 #define MAC_REG_RMDATA(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_DATA) 254 #define MAC_REG_GMRANDBACKOFFSEED(idx) MAC_REG_ADDR(idx, A_GMAC_BACKOFF_SEED) 255 #define MAC_REG_TXFTHRESHOLDS(idx) MAC_REG_ADDR(idx, A_GMAC_TXF_THRES) 256 257 #endif 258