1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (c) 2024 AIROHA Inc
4 * Author: Lorenzo Bianconi <lorenzo@kernel.org>
5 */
6
7 #ifndef AIROHA_ETH_H
8 #define AIROHA_ETH_H
9
10 #include <linux/debugfs.h>
11 #include <linux/etherdevice.h>
12 #include <linux/iopoll.h>
13 #include <linux/kernel.h>
14 #include <linux/netdevice.h>
15 #include <linux/reset.h>
16 #include <net/dsa.h>
17
18 #define AIROHA_MAX_NUM_GDM_PORTS 4
19 #define AIROHA_MAX_NUM_QDMA 2
20 #define AIROHA_MAX_NUM_IRQ_BANKS 4
21 #define AIROHA_MAX_DSA_PORTS 7
22 #define AIROHA_MAX_NUM_RSTS 3
23 #define AIROHA_MAX_NUM_XSI_RSTS 5
24 #define AIROHA_MAX_MTU 9216
25 #define AIROHA_MAX_PACKET_SIZE 2048
26 #define AIROHA_NUM_QOS_CHANNELS 4
27 #define AIROHA_NUM_QOS_QUEUES 8
28 #define AIROHA_NUM_TX_RING 32
29 #define AIROHA_NUM_RX_RING 32
30 #define AIROHA_NUM_NETDEV_TX_RINGS (AIROHA_NUM_TX_RING + \
31 AIROHA_NUM_QOS_CHANNELS)
32 #define AIROHA_FE_MC_MAX_VLAN_TABLE 64
33 #define AIROHA_FE_MC_MAX_VLAN_PORT 16
34 #define AIROHA_NUM_TX_IRQ 2
35 #define HW_DSCP_NUM 2048
36 #define IRQ_QUEUE_LEN(_n) ((_n) ? 1024 : 2048)
37 #define TX_DSCP_NUM 1024
38 #define RX_DSCP_NUM(_n) \
39 ((_n) == 2 ? 128 : \
40 (_n) == 11 ? 128 : \
41 (_n) == 15 ? 128 : \
42 (_n) == 0 ? 1024 : 16)
43
44 #define PSE_RSV_PAGES 128
45 #define PSE_QUEUE_RSV_PAGES 64
46
47 #define QDMA_METER_IDX(_n) ((_n) & 0xff)
48 #define QDMA_METER_GROUP(_n) (((_n) >> 8) & 0x3)
49
50 #define PPE_NUM 2
51 #define PPE1_SRAM_NUM_ENTRIES (8 * 1024)
52 #define PPE_SRAM_NUM_ENTRIES (2 * PPE1_SRAM_NUM_ENTRIES)
53 #ifdef CONFIG_NET_AIROHA_FLOW_STATS
54 #define PPE1_STATS_NUM_ENTRIES (4 * 1024)
55 #else
56 #define PPE1_STATS_NUM_ENTRIES 0
57 #endif /* CONFIG_NET_AIROHA_FLOW_STATS */
58 #define PPE_STATS_NUM_ENTRIES (2 * PPE1_STATS_NUM_ENTRIES)
59 #define PPE1_SRAM_NUM_DATA_ENTRIES (PPE1_SRAM_NUM_ENTRIES - PPE1_STATS_NUM_ENTRIES)
60 #define PPE_SRAM_NUM_DATA_ENTRIES (2 * PPE1_SRAM_NUM_DATA_ENTRIES)
61 #define PPE_DRAM_NUM_ENTRIES (16 * 1024)
62 #define PPE_NUM_ENTRIES (PPE_SRAM_NUM_ENTRIES + PPE_DRAM_NUM_ENTRIES)
63 #define PPE_HASH_MASK (PPE_NUM_ENTRIES - 1)
64 #define PPE_ENTRY_SIZE 80
65 #define PPE_RAM_NUM_ENTRIES_SHIFT(_n) (__ffs((_n) >> 10))
66
67 #define MTK_HDR_LEN 4
68 #define MTK_HDR_XMIT_TAGGED_TPID_8100 1
69 #define MTK_HDR_XMIT_TAGGED_TPID_88A8 2
70
71 enum {
72 QDMA_INT_REG_IDX0,
73 QDMA_INT_REG_IDX1,
74 QDMA_INT_REG_IDX2,
75 QDMA_INT_REG_IDX3,
76 QDMA_INT_REG_IDX4,
77 QDMA_INT_REG_MAX
78 };
79
80 enum {
81 HSGMII_LAN_PCIE0_SRCPORT = 0x16,
82 HSGMII_LAN_PCIE1_SRCPORT,
83 HSGMII_LAN_ETH_SRCPORT,
84 HSGMII_LAN_USB_SRCPORT,
85 };
86
87 enum {
88 XSI_PCIE0_VIP_PORT_MASK = BIT(22),
89 XSI_PCIE1_VIP_PORT_MASK = BIT(23),
90 XSI_USB_VIP_PORT_MASK = BIT(25),
91 XSI_ETH_VIP_PORT_MASK = BIT(24),
92 };
93
94 enum {
95 DEV_STATE_INITIALIZED,
96 };
97
98 enum {
99 CDM_CRSN_QSEL_Q1 = 1,
100 CDM_CRSN_QSEL_Q5 = 5,
101 CDM_CRSN_QSEL_Q6 = 6,
102 CDM_CRSN_QSEL_Q15 = 15,
103 };
104
105 enum {
106 CRSN_08 = 0x8,
107 CRSN_21 = 0x15, /* KA */
108 CRSN_22 = 0x16, /* hit bind and force route to CPU */
109 CRSN_24 = 0x18,
110 CRSN_25 = 0x19,
111 };
112
113 enum {
114 FE_PSE_PORT_CDM1,
115 FE_PSE_PORT_GDM1,
116 FE_PSE_PORT_GDM2,
117 FE_PSE_PORT_GDM3,
118 FE_PSE_PORT_PPE1,
119 FE_PSE_PORT_CDM2,
120 FE_PSE_PORT_CDM3,
121 FE_PSE_PORT_CDM4,
122 FE_PSE_PORT_PPE2,
123 FE_PSE_PORT_GDM4,
124 FE_PSE_PORT_CDM5,
125 FE_PSE_PORT_DROP = 0xf,
126 };
127
128 enum tx_sched_mode {
129 TC_SCH_WRR8,
130 TC_SCH_SP,
131 TC_SCH_WRR7,
132 TC_SCH_WRR6,
133 TC_SCH_WRR5,
134 TC_SCH_WRR4,
135 TC_SCH_WRR3,
136 TC_SCH_WRR2,
137 };
138
139 enum trtcm_unit_type {
140 TRTCM_BYTE_UNIT,
141 TRTCM_PACKET_UNIT,
142 };
143
144 enum trtcm_param_type {
145 TRTCM_MISC_MODE, /* meter_en, pps_mode, tick_sel */
146 TRTCM_TOKEN_RATE_MODE,
147 TRTCM_BUCKETSIZE_SHIFT_MODE,
148 TRTCM_BUCKET_COUNTER_MODE,
149 };
150
151 enum trtcm_mode_type {
152 TRTCM_COMMIT_MODE,
153 TRTCM_PEAK_MODE,
154 };
155
156 enum trtcm_param {
157 TRTCM_TICK_SEL = BIT(0),
158 TRTCM_PKT_MODE = BIT(1),
159 TRTCM_METER_MODE = BIT(2),
160 };
161
162 #define MIN_TOKEN_SIZE 4096
163 #define MAX_TOKEN_SIZE_OFFSET 17
164 #define TRTCM_TOKEN_RATE_MASK GENMASK(23, 6)
165 #define TRTCM_TOKEN_RATE_FRACTION_MASK GENMASK(5, 0)
166
167 struct airoha_queue_entry {
168 union {
169 void *buf;
170 struct sk_buff *skb;
171 };
172 dma_addr_t dma_addr;
173 u16 dma_len;
174 };
175
176 struct airoha_queue {
177 struct airoha_qdma *qdma;
178
179 /* protect concurrent queue accesses */
180 spinlock_t lock;
181 struct airoha_queue_entry *entry;
182 struct airoha_qdma_desc *desc;
183 u16 head;
184 u16 tail;
185
186 int queued;
187 int ndesc;
188 int free_thr;
189 int buf_size;
190
191 struct napi_struct napi;
192 struct page_pool *page_pool;
193 struct sk_buff *skb;
194 };
195
196 struct airoha_tx_irq_queue {
197 struct airoha_qdma *qdma;
198
199 struct napi_struct napi;
200
201 int size;
202 u32 *q;
203 };
204
205 struct airoha_hw_stats {
206 /* protect concurrent hw_stats accesses */
207 spinlock_t lock;
208 struct u64_stats_sync syncp;
209
210 /* get_stats64 */
211 u64 rx_ok_pkts;
212 u64 tx_ok_pkts;
213 u64 rx_ok_bytes;
214 u64 tx_ok_bytes;
215 u64 rx_multicast;
216 u64 rx_errors;
217 u64 rx_drops;
218 u64 tx_drops;
219 u64 rx_crc_error;
220 u64 rx_over_errors;
221 /* ethtool stats */
222 u64 tx_broadcast;
223 u64 tx_multicast;
224 u64 tx_len[7];
225 u64 rx_broadcast;
226 u64 rx_fragment;
227 u64 rx_jabber;
228 u64 rx_len[7];
229 };
230
231 enum {
232 PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED = 0x0f,
233 };
234
235 enum {
236 AIROHA_FOE_STATE_INVALID,
237 AIROHA_FOE_STATE_UNBIND,
238 AIROHA_FOE_STATE_BIND,
239 AIROHA_FOE_STATE_FIN
240 };
241
242 enum {
243 PPE_PKT_TYPE_IPV4_HNAPT = 0,
244 PPE_PKT_TYPE_IPV4_ROUTE = 1,
245 PPE_PKT_TYPE_BRIDGE = 2,
246 PPE_PKT_TYPE_IPV4_DSLITE = 3,
247 PPE_PKT_TYPE_IPV6_ROUTE_3T = 4,
248 PPE_PKT_TYPE_IPV6_ROUTE_5T = 5,
249 PPE_PKT_TYPE_IPV6_6RD = 7,
250 };
251
252 #define AIROHA_FOE_MAC_SMAC_ID GENMASK(20, 16)
253 #define AIROHA_FOE_MAC_PPPOE_ID GENMASK(15, 0)
254
255 struct airoha_foe_mac_info_common {
256 u16 vlan1;
257 u16 etype;
258
259 u32 dest_mac_hi;
260
261 u16 vlan2;
262 u16 dest_mac_lo;
263
264 u32 src_mac_hi;
265 };
266
267 struct airoha_foe_mac_info {
268 struct airoha_foe_mac_info_common common;
269
270 u16 pppoe_id;
271 u16 src_mac_lo;
272
273 u32 meter;
274 };
275
276 #define AIROHA_FOE_IB1_UNBIND_PREBIND BIT(24)
277 #define AIROHA_FOE_IB1_UNBIND_PACKETS GENMASK(23, 8)
278 #define AIROHA_FOE_IB1_UNBIND_TIMESTAMP GENMASK(7, 0)
279
280 #define AIROHA_FOE_IB1_BIND_STATIC BIT(31)
281 #define AIROHA_FOE_IB1_BIND_UDP BIT(30)
282 #define AIROHA_FOE_IB1_BIND_STATE GENMASK(29, 28)
283 #define AIROHA_FOE_IB1_BIND_PACKET_TYPE GENMASK(27, 25)
284 #define AIROHA_FOE_IB1_BIND_TTL BIT(24)
285 #define AIROHA_FOE_IB1_BIND_TUNNEL_DECAP BIT(23)
286 #define AIROHA_FOE_IB1_BIND_PPPOE BIT(22)
287 #define AIROHA_FOE_IB1_BIND_VPM GENMASK(21, 20)
288 #define AIROHA_FOE_IB1_BIND_VLAN_LAYER GENMASK(19, 16)
289 #define AIROHA_FOE_IB1_BIND_KEEPALIVE BIT(15)
290 #define AIROHA_FOE_IB1_BIND_TIMESTAMP GENMASK(14, 0)
291
292 #define AIROHA_FOE_IB2_DSCP GENMASK(31, 24)
293 #define AIROHA_FOE_IB2_PORT_AG GENMASK(23, 13)
294 #define AIROHA_FOE_IB2_PCP BIT(12)
295 #define AIROHA_FOE_IB2_MULTICAST BIT(11)
296 #define AIROHA_FOE_IB2_FAST_PATH BIT(10)
297 #define AIROHA_FOE_IB2_PSE_QOS BIT(9)
298 #define AIROHA_FOE_IB2_PSE_PORT GENMASK(8, 5)
299 #define AIROHA_FOE_IB2_NBQ GENMASK(4, 0)
300
301 #define AIROHA_FOE_ACTDP GENMASK(31, 24)
302 #define AIROHA_FOE_SHAPER_ID GENMASK(23, 16)
303 #define AIROHA_FOE_CHANNEL GENMASK(15, 11)
304 #define AIROHA_FOE_QID GENMASK(10, 8)
305 #define AIROHA_FOE_DPI BIT(7)
306 #define AIROHA_FOE_TUNNEL BIT(6)
307 #define AIROHA_FOE_TUNNEL_ID GENMASK(5, 0)
308
309 #define AIROHA_FOE_TUNNEL_MTU GENMASK(31, 16)
310 #define AIROHA_FOE_ACNT_GRP3 GENMASK(15, 9)
311 #define AIROHA_FOE_METER_GRP3 GENMASK(8, 5)
312 #define AIROHA_FOE_METER_GRP2 GENMASK(4, 0)
313
314 struct airoha_foe_bridge {
315 u32 dest_mac_hi;
316
317 u16 src_mac_hi;
318 u16 dest_mac_lo;
319
320 u32 src_mac_lo;
321
322 u32 ib2;
323
324 u32 rsv[5];
325
326 u32 data;
327
328 struct airoha_foe_mac_info l2;
329 };
330
331 struct airoha_foe_ipv4_tuple {
332 u32 src_ip;
333 u32 dest_ip;
334 union {
335 struct {
336 u16 dest_port;
337 u16 src_port;
338 };
339 struct {
340 u8 protocol;
341 u8 _pad[3]; /* fill with 0xa5a5a5 */
342 };
343 u32 ports;
344 };
345 };
346
347 struct airoha_foe_ipv4 {
348 struct airoha_foe_ipv4_tuple orig_tuple;
349
350 u32 ib2;
351
352 struct airoha_foe_ipv4_tuple new_tuple;
353
354 u32 rsv[2];
355
356 u32 data;
357
358 struct airoha_foe_mac_info l2;
359 };
360
361 struct airoha_foe_ipv4_dslite {
362 struct airoha_foe_ipv4_tuple ip4;
363
364 u32 ib2;
365
366 u8 flow_label[3];
367 u8 priority;
368
369 u32 rsv[4];
370
371 u32 data;
372
373 struct airoha_foe_mac_info l2;
374 };
375
376 struct airoha_foe_ipv6 {
377 u32 src_ip[4];
378 u32 dest_ip[4];
379
380 union {
381 struct {
382 u16 dest_port;
383 u16 src_port;
384 };
385 struct {
386 u8 protocol;
387 u8 pad[3];
388 };
389 u32 ports;
390 };
391
392 u32 data;
393
394 u32 ib2;
395
396 struct airoha_foe_mac_info_common l2;
397
398 u32 meter;
399 };
400
401 struct airoha_foe_entry {
402 union {
403 struct {
404 u32 ib1;
405 union {
406 struct airoha_foe_bridge bridge;
407 struct airoha_foe_ipv4 ipv4;
408 struct airoha_foe_ipv4_dslite dslite;
409 struct airoha_foe_ipv6 ipv6;
410 DECLARE_FLEX_ARRAY(u32, d);
411 };
412 };
413 u8 data[PPE_ENTRY_SIZE];
414 };
415 };
416
417 struct airoha_foe_stats {
418 u32 bytes;
419 u32 packets;
420 };
421
422 struct airoha_foe_stats64 {
423 u64 bytes;
424 u64 packets;
425 };
426
427 struct airoha_flow_data {
428 struct ethhdr eth;
429
430 union {
431 struct {
432 __be32 src_addr;
433 __be32 dst_addr;
434 } v4;
435
436 struct {
437 struct in6_addr src_addr;
438 struct in6_addr dst_addr;
439 } v6;
440 };
441
442 __be16 src_port;
443 __be16 dst_port;
444
445 struct {
446 struct {
447 u16 id;
448 __be16 proto;
449 } hdr[2];
450 u8 num;
451 } vlan;
452 struct {
453 u16 sid;
454 u8 num;
455 } pppoe;
456 };
457
458 enum airoha_flow_entry_type {
459 FLOW_TYPE_L4,
460 FLOW_TYPE_L2,
461 FLOW_TYPE_L2_SUBFLOW,
462 };
463
464 struct airoha_flow_table_entry {
465 union {
466 struct hlist_node list; /* PPE L3 flow entry */
467 struct {
468 struct rhash_head l2_node; /* L2 flow entry */
469 struct hlist_head l2_flows; /* PPE L2 subflows list */
470 };
471 };
472
473 struct airoha_foe_entry data;
474 struct hlist_node l2_subflow_node; /* PPE L2 subflow entry */
475 u32 hash;
476
477 struct airoha_foe_stats64 stats;
478 enum airoha_flow_entry_type type;
479
480 struct rhash_head node;
481 unsigned long cookie;
482 };
483
484 /* RX queue to IRQ mapping: BIT(q) in IRQ(n) */
485 #define RX_IRQ0_BANK_PIN_MASK 0x839f
486 #define RX_IRQ1_BANK_PIN_MASK 0x7fe00000
487 #define RX_IRQ2_BANK_PIN_MASK 0x20
488 #define RX_IRQ3_BANK_PIN_MASK 0x40
489 #define RX_IRQ_BANK_PIN_MASK(_n) \
490 (((_n) == 3) ? RX_IRQ3_BANK_PIN_MASK : \
491 ((_n) == 2) ? RX_IRQ2_BANK_PIN_MASK : \
492 ((_n) == 1) ? RX_IRQ1_BANK_PIN_MASK : \
493 RX_IRQ0_BANK_PIN_MASK)
494
495 struct airoha_irq_bank {
496 struct airoha_qdma *qdma;
497
498 /* protect concurrent irqmask accesses */
499 spinlock_t irq_lock;
500 u32 irqmask[QDMA_INT_REG_MAX];
501 int irq;
502 };
503
504 struct airoha_qdma {
505 struct airoha_eth *eth;
506 void __iomem *regs;
507
508 atomic_t users;
509
510 struct airoha_irq_bank irq_banks[AIROHA_MAX_NUM_IRQ_BANKS];
511
512 struct airoha_tx_irq_queue q_tx_irq[AIROHA_NUM_TX_IRQ];
513
514 struct airoha_queue q_tx[AIROHA_NUM_TX_RING];
515 struct airoha_queue q_rx[AIROHA_NUM_RX_RING];
516 };
517
518 struct airoha_gdm_port {
519 struct airoha_qdma *qdma;
520 struct net_device *dev;
521 int id;
522
523 struct airoha_hw_stats stats;
524
525 DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS);
526
527 /* qos stats counters */
528 u64 cpu_tx_packets;
529 u64 fwd_tx_packets;
530
531 struct metadata_dst *dsa_meta[AIROHA_MAX_DSA_PORTS];
532 };
533
534 #define AIROHA_RXD4_PPE_CPU_REASON GENMASK(20, 16)
535 #define AIROHA_RXD4_FOE_ENTRY GENMASK(15, 0)
536
537 struct airoha_ppe {
538 struct airoha_eth *eth;
539
540 void *foe;
541 dma_addr_t foe_dma;
542
543 struct rhashtable l2_flows;
544
545 struct hlist_head *foe_flow;
546 u16 foe_check_time[PPE_NUM_ENTRIES];
547
548 struct airoha_foe_stats *foe_stats;
549 dma_addr_t foe_stats_dma;
550
551 struct dentry *debugfs_dir;
552 };
553
554 struct airoha_eth {
555 struct device *dev;
556
557 unsigned long state;
558 void __iomem *fe_regs;
559
560 struct airoha_npu __rcu *npu;
561
562 struct airoha_ppe *ppe;
563 struct rhashtable flow_table;
564
565 struct reset_control_bulk_data rsts[AIROHA_MAX_NUM_RSTS];
566 struct reset_control_bulk_data xsi_rsts[AIROHA_MAX_NUM_XSI_RSTS];
567
568 struct net_device *napi_dev;
569
570 struct airoha_qdma qdma[AIROHA_MAX_NUM_QDMA];
571 struct airoha_gdm_port *ports[AIROHA_MAX_NUM_GDM_PORTS];
572 };
573
574 u32 airoha_rr(void __iomem *base, u32 offset);
575 void airoha_wr(void __iomem *base, u32 offset, u32 val);
576 u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val);
577
578 #define airoha_fe_rr(eth, offset) \
579 airoha_rr((eth)->fe_regs, (offset))
580 #define airoha_fe_wr(eth, offset, val) \
581 airoha_wr((eth)->fe_regs, (offset), (val))
582 #define airoha_fe_rmw(eth, offset, mask, val) \
583 airoha_rmw((eth)->fe_regs, (offset), (mask), (val))
584 #define airoha_fe_set(eth, offset, val) \
585 airoha_rmw((eth)->fe_regs, (offset), 0, (val))
586 #define airoha_fe_clear(eth, offset, val) \
587 airoha_rmw((eth)->fe_regs, (offset), (val), 0)
588
589 #define airoha_qdma_rr(qdma, offset) \
590 airoha_rr((qdma)->regs, (offset))
591 #define airoha_qdma_wr(qdma, offset, val) \
592 airoha_wr((qdma)->regs, (offset), (val))
593 #define airoha_qdma_rmw(qdma, offset, mask, val) \
594 airoha_rmw((qdma)->regs, (offset), (mask), (val))
595 #define airoha_qdma_set(qdma, offset, val) \
596 airoha_rmw((qdma)->regs, (offset), 0, (val))
597 #define airoha_qdma_clear(qdma, offset, val) \
598 airoha_rmw((qdma)->regs, (offset), (val), 0)
599
airhoa_is_lan_gdm_port(struct airoha_gdm_port * port)600 static inline bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port)
601 {
602 /* GDM1 port on EN7581 SoC is connected to the lan dsa switch.
603 * GDM{2,3,4} can be used as wan port connected to an external
604 * phy module.
605 */
606 return port->id == 1;
607 }
608
609 bool airoha_is_valid_gdm_port(struct airoha_eth *eth,
610 struct airoha_gdm_port *port);
611
612 void airoha_ppe_check_skb(struct airoha_ppe *ppe, struct sk_buff *skb,
613 u16 hash);
614 int airoha_ppe_setup_tc_block_cb(struct net_device *dev, void *type_data);
615 int airoha_ppe_init(struct airoha_eth *eth);
616 void airoha_ppe_deinit(struct airoha_eth *eth);
617 void airoha_ppe_init_upd_mem(struct airoha_gdm_port *port);
618 struct airoha_foe_entry *airoha_ppe_foe_get_entry(struct airoha_ppe *ppe,
619 u32 hash);
620 void airoha_ppe_foe_entry_get_stats(struct airoha_ppe *ppe, u32 hash,
621 struct airoha_foe_stats64 *stats);
622
623 #ifdef CONFIG_DEBUG_FS
624 int airoha_ppe_debugfs_init(struct airoha_ppe *ppe);
625 #else
airoha_ppe_debugfs_init(struct airoha_ppe * ppe)626 static inline int airoha_ppe_debugfs_init(struct airoha_ppe *ppe)
627 {
628 return 0;
629 }
630 #endif
631
632 #endif /* AIROHA_ETH_H */
633