1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_FFLP_H 27 #define _SYS_NXGE_NXGE_FFLP_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <npi_fflp.h> 34 35 #define MAX_PARTITION 8 36 37 typedef struct _fflp_errlog { 38 uint32_t vlan; 39 uint32_t tcam; 40 uint32_t hash_pio[MAX_PARTITION]; 41 uint32_t hash_lookup1; 42 uint32_t hash_lookup2; 43 } fflp_errlog_t, *p_fflp_errlog_t; 44 45 typedef struct _fflp_stats { 46 uint32_t tcam_entries; 47 uint32_t fcram_entries; 48 uint32_t tcam_parity_err; 49 uint32_t tcam_ecc_err; 50 uint32_t vlan_parity_err; 51 uint32_t hash_lookup_err; 52 uint32_t hash_pio_err[MAX_PARTITION]; 53 fflp_errlog_t errlog; 54 } nxge_fflp_stats_t, *p_nxge_fflp_stats_t; 55 56 /* 57 * The FCRAM (hash table) cosnists of 1 meg cells 58 * each 64 byte wide. Each cell can hold either of: 59 * 2 IPV4 Exact match entry (each 32 bytes) 60 * 1 IPV6 Exact match entry (each 56 bytes) and 61 * 1 Optimistic match entry (each 8 bytes) 62 * 8 Optimistic match entries (each 8 bytes) 63 * In the case IPV4 Exact match, half of the cell 64 * (the first or the second 32 bytes) could be used 65 * to hold 4 Optimistic matches 66 */ 67 68 #define FCRAM_CELL_EMPTY 0x00 69 #define FCRAM_CELL_IPV4_IPV4 0x01 70 #define FCRAM_CELL_IPV4_OPT 0x02 71 #define FCRAM_CELL_OPT_IPV4 0x04 72 #define FCRAM_CELL_IPV6_OPT 0x08 73 #define FCRAM_CELL_OPT_OPT 0x10 74 75 76 #define FCRAM_SUBAREA0_OCCUPIED 0x01 77 #define FCRAM_SUBAREA1_OCCUPIED 0x02 78 #define FCRAM_SUBAREA2_OCCUPIED 0x04 79 #define FCRAM_SUBAREA3_OCCUPIED 0x08 80 81 #define FCRAM_SUBAREA4_OCCUPIED 0x10 82 #define FCRAM_SUBAREA5_OCCUPIED 0x20 83 #define FCRAM_SUBAREA6_OCCUPIED 0x40 84 #define FCRAM_SUBAREA7_OCCUPIED 0x20 85 86 #define FCRAM_IPV4_SUBAREA0_OCCUPIED \ 87 (FCRAM_SUBAREA0_OCCUPIED | FCRAM_SUBAREA1_OCCUPIED | \ 88 FCRAM_SUBAREA2_OCCUPIED | FCRAM_SUBAREA3_OCCUPIED) 89 90 #define FCRAM_IPV4_SUBAREA4_OCCUPIED \ 91 (FCRAM_SUBAREA4_OCCUPIED | FCRAM_SUBAREA5_OCCUPIED | \ 92 FCRAM_SUBAREA6_OCCUPIED | FCRAM_SUBAREA7_OCCUPIED) 93 94 95 #define FCRAM_IPV6_SUBAREA0_OCCUPIED \ 96 (FCRAM_SUBAREA0_OCCUPIED | FCRAM_SUBAREA1_OCCUPIED | \ 97 FCRAM_SUBAREA2_OCCUPIED | FCRAM_SUBAREA3_OCCUPIED | \ 98 FCRAM_SUBAREA4_OCCUPIED | FCRAM_SUBAREA5_OCCUPIED | \ 99 FCRAM_SUBAREA6_OCCUPIED) 100 101 /* 102 * The current occupancy state of each FCRAM cell isy 103 * described by the fcram_cell_t data structure. 104 * The "type" field denotes the type of entry (or combination) 105 * the cell holds (FCRAM_CELL_EMPTY ...... FCRAM_CELL_OPT_OPT) 106 * The "occupied" field indicates if individual 8 bytes (subareas) 107 * with in the cell are occupied 108 */ 109 110 typedef struct _fcram_cell { 111 uint32_t type:8; 112 uint32_t occupied:8; 113 uint32_t shadow_loc:16; 114 } fcram_cell_t, *p_fcram_cell_t; 115 116 typedef struct _fcram_parition { 117 uint8_t id; 118 uint8_t base; 119 uint8_t mask; 120 uint8_t reloc; 121 uint32_t flags; 122 #define HASH_PARTITION_ENABLED 1 123 uint32_t offset; 124 uint32_t size; 125 } fcram_parition_t, *p_fcram_partition_t; 126 127 128 typedef struct _tcam_flow_spec { 129 tcam_entry_t tce; 130 uint64_t flags; 131 uint64_t user_info; 132 uint8_t valid; 133 } tcam_flow_spec_t, *p_tcam_flow_spec_t; 134 135 136 /* 137 * Used for configuration. 138 * ndd as well nxge.conf use the following definitions 139 */ 140 141 #define NXGE_CLASS_CONFIG_PARAMS 20 142 /* Used for ip class flow key and tcam key config */ 143 144 #define NXGE_CLASS_TCAM_LOOKUP 0x0001 145 #define NXGE_CLASS_TCAM_USE_SRC_ADDR 0x0002 146 #define NXGE_CLASS_FLOW_USE_PORTNUM 0x0010 147 #define NXGE_CLASS_FLOW_USE_L2DA 0x0020 148 #define NXGE_CLASS_FLOW_USE_VLAN 0x0040 149 #define NXGE_CLASS_FLOW_USE_PROTO 0x0080 150 #define NXGE_CLASS_FLOW_USE_IPSRC 0x0100 151 #define NXGE_CLASS_FLOW_USE_IPDST 0x0200 152 #define NXGE_CLASS_FLOW_USE_SRC_PORT 0x0400 153 #define NXGE_CLASS_FLOW_USE_DST_PORT 0x0800 154 #define NXGE_CLASS_DISCARD 0x80000000 155 156 /* these are used for quick configs */ 157 #define NXGE_CLASS_FLOW_WEB_SERVER NXGE_CLASS_FLOW_USE_IPSRC | \ 158 NXGE_CLASS_FLOW_USE_SRC_PORT 159 160 #define NXGE_CLASS_FLOW_GEN_SERVER NXGE_CLASS_FLOW_USE_IPSRC | \ 161 NXGE_CLASS_FLOW_USE_IPDST | \ 162 NXGE_CLASS_FLOW_USE_SRC_PORT | \ 163 NXGE_CLASS_FLOW_USE_DST_PORT | \ 164 NXGE_CLASS_FLOW_USE_PROTO | \ 165 NXGE_CLASS_FLOW_USE_L2DA | \ 166 NXGE_CLASS_FLOW_USE_VLAN 167 168 /* 169 * used for use classes 170 */ 171 172 173 /* Ethernet Classes */ 174 #define NXGE_CLASS_CFG_ETHER_TYPE_MASK 0x0000FFFF 175 #define NXGE_CLASS_CFG_ETHER_ENABLE_MASK 0x40000000 176 177 /* IP Classes */ 178 #define NXGE_CLASS_CFG_IP_TOS_MASK 0x000000FF 179 #define NXGE_CLASS_CFG_IP_TOS_SHIFT 0 180 #define NXGE_CLASS_CFG_IP_TOS_MASK_MASK 0x0000FF00 181 #define NXGE_CLASS_CFG_IP_TOS_MASK_SHIFT 8 182 #define NXGE_CLASS_CFG_IP_PROTO_MASK 0x00FFFF00 183 #define NXGE_CLASS_CFG_IP_PROTO_SHIFT 16 184 185 #define NXGE_CLASS_CFG_IP_IPV6_MASK 0x01000000 186 #define NXGE_CLASS_CFG_IP_PARAM_MASK NXGE_CLASS_CFG_IP_TOS_MASK | \ 187 NXGE_CLASS_CFG_IP_TOS_MASK_MASK | \ 188 NXGE_CLASS_CFG_IP_PROTO_MASK | \ 189 NXGE_CLASS_CFG_IP_IPV6_MASK 190 191 #define NXGE_CLASS_CFG_IP_ENABLE_MASK 0x40000000 192 193 typedef struct _vlan_rdcgrp_map { 194 uint32_t rsrvd:8; 195 uint32_t vid:16; 196 uint32_t rdc_grp:8; 197 } vlan_rdcgrp_map_t, *p_vlan_rdcgrp_map_t; 198 199 #define NXGE_INIT_VLAN_RDCG_TBL 32 200 201 typedef struct _nxge_classify { 202 nxge_os_mutex_t tcam_lock; 203 nxge_os_mutex_t fcram_lock; 204 nxge_os_mutex_t hash_lock[MAX_PARTITION]; 205 uint32_t tcam_size; 206 uint32_t tcam_entry_cnt; 207 uint32_t state; 208 #define NXGE_FFLP_HW_RESET 0x1 209 #define NXGE_FFLP_HW_INIT 0x2 210 #define NXGE_FFLP_SW_INIT 0x4 211 #define NXGE_FFLP_FCRAM_PART 0x80000000 212 p_nxge_fflp_stats_t fflp_stats; 213 214 tcam_flow_spec_t *tcam_entries; 215 uint8_t tcam_top; 216 uint8_t tcam_location; 217 uint64_t tcam_l2_prog_cls[NXGE_L2_PROG_CLS]; 218 uint64_t tcam_l3_prog_cls[NXGE_L3_PROG_CLS]; 219 uint64_t tcam_key[12]; 220 uint64_t flow_key[12]; 221 uint16_t tcam_l3_prog_cls_refcnt[NXGE_L3_PROG_CLS]; 222 uint8_t tcam_l3_prog_cls_pid[NXGE_L3_PROG_CLS]; 223 #define NXGE_FLOW_NO_SUPPORT 0x0 224 #define NXGE_FLOW_USE_TCAM 0x1 225 #define NXGE_FLOW_USE_FCRAM 0x2 226 #define NXGE_FLOW_USE_TCAM_FCRAM 0x3 227 228 #define NXGE_FLOW_COMPUTE_H1 0x10 229 #define NXGE_FLOW_COMPUTE_H2 0x20 230 uint8_t fragment_bug; 231 uint8_t fragment_bug_location; 232 fcram_cell_t *hash_table; /* allocated for Neptune only */ 233 fcram_parition_t partition[MAX_PARTITION]; 234 } nxge_classify_t, *p_nxge_classify_t; 235 236 #ifdef __cplusplus 237 } 238 #endif 239 240 #endif /* _SYS_NXGE_NXGE_FFLP_H */ 241