1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) Meta Platforms, Inc. and affiliates. */ 3 4 #ifndef _FBNIC_CSR_H_ 5 #define _FBNIC_CSR_H_ 6 7 #include <linux/bitops.h> 8 9 #define CSR_BIT(nr) (1u << (nr)) 10 #define CSR_GENMASK(h, l) GENMASK(h, l) 11 12 #define DESC_BIT(nr) BIT_ULL(nr) 13 #define DESC_GENMASK(h, l) GENMASK_ULL(h, l) 14 15 #define FW_VER_CODE(_major, _minor, _patch, _build) ( \ 16 FIELD_PREP(FBNIC_FW_CAP_RESP_VERSION_MAJOR, _major) | \ 17 FIELD_PREP(FBNIC_FW_CAP_RESP_VERSION_MINOR, _minor) | \ 18 FIELD_PREP(FBNIC_FW_CAP_RESP_VERSION_PATCH, _patch) | \ 19 FIELD_PREP(FBNIC_FW_CAP_RESP_VERSION_BUILD, _build)) 20 21 /* Defines the minimum firmware version required by the driver */ 22 #define MIN_FW_VER_CODE FW_VER_CODE(0, 10, 6, 0) 23 24 /* Defines the minimum firmware version required for firmware logs */ 25 #define MIN_FW_VER_CODE_LOG FW_VER_CODE(0, 12, 9, 0) 26 27 /* Driver can request that firmware sends all cached logs in bulk. This 28 * feature was enabled on older firmware however firmware has a bug 29 * which attempted to send 30 messages per mbx message which caused an 30 * overflow flooding the mailbox. This results in a kernel warning 31 * related to corrupt mailbox messages. 32 * 33 * If firmware is new enough only request sending historical logs when 34 * the log buffer is empty to prevent duplicate logs. 35 */ 36 #define MIN_FW_VER_CODE_HIST FW_VER_CODE(25, 5, 7, 0) 37 38 #define PCI_DEVICE_ID_META_FBNIC_ASIC 0x0013 39 40 #define FBNIC_CLOCK_FREQ (600 * (1000 * 1000)) 41 42 /* Transmit Work Descriptor Format */ 43 /* Length, Type, Offset Masks and Shifts */ 44 #define FBNIC_TWD_L2_HLEN_MASK DESC_GENMASK(5, 0) 45 46 #define FBNIC_TWD_L3_TYPE_MASK DESC_GENMASK(7, 6) 47 enum { 48 FBNIC_TWD_L3_TYPE_OTHER = 0, 49 FBNIC_TWD_L3_TYPE_IPV4 = 1, 50 FBNIC_TWD_L3_TYPE_IPV6 = 2, 51 FBNIC_TWD_L3_TYPE_V6V6 = 3, 52 }; 53 54 #define FBNIC_TWD_L3_OHLEN_MASK DESC_GENMASK(15, 8) 55 #define FBNIC_TWD_L3_IHLEN_MASK DESC_GENMASK(23, 16) 56 57 enum { 58 FBNIC_TWD_L4_TYPE_OTHER = 0, 59 FBNIC_TWD_L4_TYPE_TCP = 1, 60 FBNIC_TWD_L4_TYPE_UDP = 2, 61 }; 62 63 #define FBNIC_TWD_CSUM_OFFSET_MASK DESC_GENMASK(27, 24) 64 #define FBNIC_TWD_L4_HLEN_MASK DESC_GENMASK(31, 28) 65 66 /* Flags and Type */ 67 #define FBNIC_TWD_L4_TYPE_MASK DESC_GENMASK(33, 32) 68 #define FBNIC_TWD_FLAG_REQ_TS DESC_BIT(34) 69 #define FBNIC_TWD_FLAG_REQ_LSO DESC_BIT(35) 70 #define FBNIC_TWD_FLAG_REQ_CSO DESC_BIT(36) 71 #define FBNIC_TWD_FLAG_REQ_COMPLETION DESC_BIT(37) 72 #define FBNIC_TWD_FLAG_DEST_MAC DESC_BIT(43) 73 #define FBNIC_TWD_FLAG_DEST_BMC DESC_BIT(44) 74 #define FBNIC_TWD_FLAG_DEST_FW DESC_BIT(45) 75 #define FBNIC_TWD_TYPE_MASK DESC_GENMASK(47, 46) 76 enum { 77 FBNIC_TWD_TYPE_META = 0, 78 FBNIC_TWD_TYPE_OPT_META = 1, 79 FBNIC_TWD_TYPE_AL = 2, 80 FBNIC_TWD_TYPE_LAST_AL = 3, 81 }; 82 83 /* MSS and Completion Req */ 84 #define FBNIC_TWD_MSS_MASK DESC_GENMASK(61, 48) 85 86 #define FBNIC_TWD_TS_MASK DESC_GENMASK(39, 0) 87 #define FBNIC_TWD_ADDR_MASK DESC_GENMASK(45, 0) 88 #define FBNIC_TWD_LEN_MASK DESC_GENMASK(63, 48) 89 90 /* Tx Completion Descriptor Format */ 91 #define FBNIC_TCD_TYPE0_HEAD0_MASK DESC_GENMASK(15, 0) 92 #define FBNIC_TCD_TYPE0_HEAD1_MASK DESC_GENMASK(31, 16) 93 94 #define FBNIC_TCD_TYPE1_TS_MASK DESC_GENMASK(39, 0) 95 96 #define FBNIC_TCD_STATUS_MASK DESC_GENMASK(59, 48) 97 #define FBNIC_TCD_STATUS_TS_INVALID DESC_BIT(48) 98 #define FBNIC_TCD_STATUS_ILLEGAL_TS_REQ DESC_BIT(49) 99 #define FBNIC_TCD_TWQ1 DESC_BIT(60) 100 #define FBNIC_TCD_TYPE_MASK DESC_GENMASK(62, 61) 101 enum { 102 FBNIC_TCD_TYPE_0 = 0, 103 FBNIC_TCD_TYPE_1 = 1, 104 }; 105 106 #define FBNIC_TCD_DONE DESC_BIT(63) 107 108 /* Rx Buffer Descriptor Format 109 * 110 * The layout of this can vary depending on the page size of the system. 111 * 112 * If the page size is 4K then the layout will simply consist of ID for 113 * the 16 most significant bits, and the lower 46 are essentially the page 114 * address with the lowest 12 bits being reserved 0 due to the fact that 115 * a page will be aligned. 116 * 117 * If the page size is larger than 4K then the lower n bits of the ID and 118 * page address will be reserved for the fragment ID. This fragment will 119 * be 4K in size and will be used to index both the DMA address and the ID 120 * by the same amount. 121 */ 122 #define FBNIC_BD_DESC_ADDR_MASK DESC_GENMASK(45, 12) 123 #define FBNIC_BD_DESC_ID_MASK DESC_GENMASK(63, 48) 124 #define FBNIC_BD_FRAG_SIZE \ 125 (FBNIC_BD_DESC_ADDR_MASK & ~(FBNIC_BD_DESC_ADDR_MASK - 1)) 126 #define FBNIC_BD_FRAG_COUNT \ 127 (PAGE_SIZE / FBNIC_BD_FRAG_SIZE) 128 #define FBNIC_BD_FRAG_ADDR_MASK \ 129 (FBNIC_BD_DESC_ADDR_MASK & \ 130 ~(FBNIC_BD_DESC_ADDR_MASK * FBNIC_BD_FRAG_COUNT)) 131 #define FBNIC_BD_FRAG_ID_MASK \ 132 (FBNIC_BD_DESC_ID_MASK & \ 133 ~(FBNIC_BD_DESC_ID_MASK * FBNIC_BD_FRAG_COUNT)) 134 #define FBNIC_BD_PAGE_ADDR_MASK \ 135 (FBNIC_BD_DESC_ADDR_MASK & ~FBNIC_BD_FRAG_ADDR_MASK) 136 #define FBNIC_BD_PAGE_ID_MASK \ 137 (FBNIC_BD_DESC_ID_MASK & ~FBNIC_BD_FRAG_ID_MASK) 138 139 /* Rx Completion Queue Descriptors */ 140 #define FBNIC_RCD_TYPE_MASK DESC_GENMASK(62, 61) 141 enum { 142 FBNIC_RCD_TYPE_HDR_AL = 0, 143 FBNIC_RCD_TYPE_PAY_AL = 1, 144 FBNIC_RCD_TYPE_OPT_META = 2, 145 FBNIC_RCD_TYPE_META = 3, 146 }; 147 148 #define FBNIC_RCD_DONE DESC_BIT(63) 149 150 /* Address/Length Completion Descriptors */ 151 #define FBNIC_RCD_AL_BUFF_ID_MASK DESC_GENMASK(15, 0) 152 #define FBNIC_RCD_AL_BUFF_FRAG_MASK (FBNIC_BD_FRAG_COUNT - 1) 153 #define FBNIC_RCD_AL_BUFF_PAGE_MASK \ 154 (FBNIC_RCD_AL_BUFF_ID_MASK & ~FBNIC_RCD_AL_BUFF_FRAG_MASK) 155 #define FBNIC_RCD_AL_BUFF_LEN_MASK DESC_GENMASK(28, 16) 156 #define FBNIC_RCD_AL_BUFF_OFF_MASK DESC_GENMASK(43, 32) 157 #define FBNIC_RCD_AL_PAGE_FIN DESC_BIT(60) 158 159 /* Header AL specific values */ 160 #define FBNIC_RCD_HDR_AL_OVERFLOW DESC_BIT(53) 161 #define FBNIC_RCD_HDR_AL_DMA_HINT_MASK DESC_GENMASK(59, 54) 162 enum { 163 FBNIC_RCD_HDR_AL_DMA_HINT_NONE = 0, 164 FBNIC_RCD_HDR_AL_DMA_HINT_L2 = 1, 165 FBNIC_RCD_HDR_AL_DMA_HINT_L3 = 2, 166 FBNIC_RCD_HDR_AL_DMA_HINT_L4 = 4, 167 }; 168 169 /* Optional Metadata Completion Descriptors */ 170 #define FBNIC_RCD_OPT_META_TS_MASK DESC_GENMASK(39, 0) 171 #define FBNIC_RCD_OPT_META_ACTION_MASK DESC_GENMASK(45, 40) 172 #define FBNIC_RCD_OPT_META_ACTION DESC_BIT(57) 173 #define FBNIC_RCD_OPT_META_TS DESC_BIT(58) 174 #define FBNIC_RCD_OPT_META_TYPE_MASK DESC_GENMASK(60, 59) 175 176 /* Metadata Completion Descriptors */ 177 #define FBNIC_RCD_META_RSS_HASH_MASK DESC_GENMASK(31, 0) 178 #define FBNIC_RCD_META_L2_CSUM_MASK DESC_GENMASK(47, 32) 179 #define FBNIC_RCD_META_L3_TYPE_MASK DESC_GENMASK(49, 48) 180 enum { 181 FBNIC_RCD_META_L3_TYPE_OTHER = 0, 182 FBNIC_RCD_META_L3_TYPE_IPV4 = 1, 183 FBNIC_RCD_META_L3_TYPE_IPV6 = 2, 184 FBNIC_RCD_META_L3_TYPE_V6V6 = 3, 185 }; 186 187 #define FBNIC_RCD_META_L4_TYPE_MASK DESC_GENMASK(51, 50) 188 enum { 189 FBNIC_RCD_META_L4_TYPE_OTHER = 0, 190 FBNIC_RCD_META_L4_TYPE_TCP = 1, 191 FBNIC_RCD_META_L4_TYPE_UDP = 2, 192 }; 193 194 #define FBNIC_RCD_META_L4_CSUM_UNNECESSARY DESC_BIT(52) 195 #define FBNIC_RCD_META_ERR_MAC_EOP DESC_BIT(53) 196 #define FBNIC_RCD_META_ERR_TRUNCATED_FRAME DESC_BIT(54) 197 #define FBNIC_RCD_META_ERR_PARSER DESC_BIT(55) 198 #define FBNIC_RCD_META_UNCORRECTABLE_ERR_MASK \ 199 (FBNIC_RCD_META_ERR_MAC_EOP | FBNIC_RCD_META_ERR_TRUNCATED_FRAME) 200 #define FBNIC_RCD_META_ECN DESC_BIT(60) 201 202 /* Register Definitions 203 * 204 * The registers are laid as indexes into an le32 array. As such the actual 205 * address is 4 times the index value. Below each register is defined as 3 206 * fields, name, index, and Address. 207 * 208 * Name Index Address 209 *************************************************************************/ 210 /* Interrupt Registers */ 211 #define FBNIC_CSR_START_INTR 0x00000 /* CSR section delimiter */ 212 #define FBNIC_INTR_STATUS(n) (0x00000 + (n)) /* 0x00000 + 4*n */ 213 #define FBNIC_INTR_STATUS_CNT 8 214 #define FBNIC_INTR_MASK(n) (0x00008 + (n)) /* 0x00020 + 4*n */ 215 #define FBNIC_INTR_MASK_CNT 8 216 #define FBNIC_INTR_SET(n) (0x00010 + (n)) /* 0x00040 + 4*n */ 217 #define FBNIC_INTR_SET_CNT 8 218 #define FBNIC_INTR_CLEAR(n) (0x00018 + (n)) /* 0x00060 + 4*n */ 219 #define FBNIC_INTR_CLEAR_CNT 8 220 #define FBNIC_INTR_SW_STATUS(n) (0x00020 + (n)) /* 0x00080 + 4*n */ 221 #define FBNIC_INTR_SW_STATUS_CNT 8 222 #define FBNIC_INTR_SW_AC_MODE(n) (0x00028 + (n)) /* 0x000a0 + 4*n */ 223 #define FBNIC_INTR_SW_AC_MODE_CNT 8 224 #define FBNIC_INTR_MASK_SET(n) (0x00030 + (n)) /* 0x000c0 + 4*n */ 225 #define FBNIC_INTR_MASK_SET_CNT 8 226 #define FBNIC_INTR_MASK_CLEAR(n) (0x00038 + (n)) /* 0x000e0 + 4*n */ 227 #define FBNIC_INTR_MASK_CLEAR_CNT 8 228 #define FBNIC_MAX_MSIX_VECS 256U 229 #define FBNIC_INTR_MSIX_CTRL(n) (0x00040 + (n)) /* 0x00100 + 4*n */ 230 #define FBNIC_INTR_MSIX_CTRL_VECTOR_MASK CSR_GENMASK(7, 0) 231 #define FBNIC_INTR_MSIX_CTRL_ENABLE CSR_BIT(31) 232 enum { 233 FBNIC_INTR_MSIX_CTRL_PCS_IDX = 34, 234 }; 235 236 #define FBNIC_CSR_END_INTR 0x0005f /* CSR section delimiter */ 237 238 /* Interrupt MSIX Registers */ 239 #define FBNIC_CSR_START_INTR_CQ 0x00400 /* CSR section delimiter */ 240 #define FBNIC_INTR_CQ_REARM(n) \ 241 (0x00400 + 4 * (n)) /* 0x01000 + 16*n */ 242 #define FBNIC_INTR_CQ_REARM_CNT 256 243 #define FBNIC_INTR_CQ_REARM_RCQ_TIMEOUT CSR_GENMASK(13, 0) 244 #define FBNIC_INTR_CQ_REARM_RCQ_TIMEOUT_UPD_EN CSR_BIT(14) 245 #define FBNIC_INTR_CQ_REARM_TCQ_TIMEOUT CSR_GENMASK(28, 15) 246 #define FBNIC_INTR_CQ_REARM_TCQ_TIMEOUT_UPD_EN CSR_BIT(29) 247 #define FBNIC_INTR_CQ_REARM_INTR_RELOAD CSR_BIT(30) 248 #define FBNIC_INTR_CQ_REARM_INTR_UNMASK CSR_BIT(31) 249 250 #define FBNIC_INTR_RCQ_TIMEOUT(n) \ 251 (0x00401 + 4 * (n)) /* 0x01004 + 16*n */ 252 #define FBNIC_INTR_RCQ_TIMEOUT_CNT 256 253 #define FBNIC_INTR_TCQ_TIMEOUT(n) \ 254 (0x00402 + 4 * (n)) /* 0x01008 + 16*n */ 255 #define FBNIC_INTR_TCQ_TIMEOUT_CNT 256 256 #define FBNIC_CSR_END_INTR_CQ 0x007fe /* CSR section delimiter */ 257 258 /* Global QM Tx registers */ 259 #define FBNIC_CSR_START_QM_TX 0x00800 /* CSR section delimiter */ 260 #define FBNIC_QM_TWQ_IDLE(n) (0x00800 + (n)) /* 0x02000 + 4*n */ 261 #define FBNIC_QM_TWQ_IDLE_CNT 8 262 #define FBNIC_QM_TWQ_DEFAULT_META_L 0x00818 /* 0x02060 */ 263 #define FBNIC_QM_TWQ_DEFAULT_META_H 0x00819 /* 0x02064 */ 264 265 #define FBNIC_QM_TQS_CTL0 0x0081b /* 0x0206c */ 266 #define FBNIC_QM_TQS_CTL0_LSO_TS_MASK CSR_BIT(0) 267 enum { 268 FBNIC_QM_TQS_CTL0_LSO_TS_FIRST = 0, 269 FBNIC_QM_TQS_CTL0_LSO_TS_LAST = 1, 270 }; 271 272 #define FBNIC_QM_TQS_CTL0_PREFETCH_THRESH CSR_GENMASK(7, 1) 273 enum { 274 FBNIC_QM_TQS_CTL0_PREFETCH_THRESH_MIN = 16, 275 }; 276 277 #define FBNIC_QM_TQS_CTL1 0x0081c /* 0x02070 */ 278 #define FBNIC_QM_TQS_CTL1_MC_MAX_CREDITS CSR_GENMASK(7, 0) 279 #define FBNIC_QM_TQS_CTL1_BULK_MAX_CREDITS CSR_GENMASK(15, 8) 280 #define FBNIC_QM_TQS_MTU_CTL0 0x0081d /* 0x02074 */ 281 #define FBNIC_QM_TQS_MTU_CTL1 0x0081e /* 0x02078 */ 282 #define FBNIC_QM_TQS_MTU_CTL1_BULK CSR_GENMASK(13, 0) 283 #define FBNIC_QM_TCQ_IDLE(n) (0x00821 + (n)) /* 0x02084 + 4*n */ 284 #define FBNIC_QM_TCQ_IDLE_CNT 4 285 #define FBNIC_QM_TCQ_CTL0 0x0082d /* 0x020b4 */ 286 #define FBNIC_QM_TCQ_CTL0_COAL_WAIT CSR_GENMASK(15, 0) 287 #define FBNIC_QM_TCQ_CTL0_TICK_CYCLES CSR_GENMASK(26, 16) 288 #define FBNIC_QM_TQS_IDLE(n) (0x00830 + (n)) /* 0x020c0 + 4*n */ 289 #define FBNIC_QM_TQS_IDLE_CNT 8 290 #define FBNIC_QM_TQS_EDT_TS_RANGE 0x00849 /* 0x2124 */ 291 #define FBNIC_QM_TDE_IDLE(n) (0x00853 + (n)) /* 0x0214c + 4*n */ 292 #define FBNIC_QM_TDE_IDLE_CNT 8 293 #define FBNIC_QM_TNI_TDF_CTL 0x0086c /* 0x021b0 */ 294 #define FBNIC_QM_TNI_TDF_CTL_MRRS CSR_GENMASK(1, 0) 295 #define FBNIC_QM_TNI_TDF_CTL_CLS CSR_GENMASK(3, 2) 296 #define FBNIC_QM_TNI_TDF_CTL_MAX_OT CSR_GENMASK(11, 4) 297 #define FBNIC_QM_TNI_TDF_CTL_MAX_OB CSR_GENMASK(23, 12) 298 #define FBNIC_QM_TNI_TDE_CTL 0x0086d /* 0x021b4 */ 299 #define FBNIC_QM_TNI_TDE_CTL_MRRS CSR_GENMASK(1, 0) 300 #define FBNIC_QM_TNI_TDE_CTL_CLS CSR_GENMASK(3, 2) 301 #define FBNIC_QM_TNI_TDE_CTL_MAX_OT CSR_GENMASK(11, 4) 302 #define FBNIC_QM_TNI_TDE_CTL_MAX_OB CSR_GENMASK(24, 12) 303 #define FBNIC_QM_TNI_TDE_CTL_MRRS_1K CSR_BIT(25) 304 #define FBNIC_QM_TNI_TCM_CTL 0x0086e /* 0x021b8 */ 305 #define FBNIC_QM_TNI_TCM_CTL_MPS CSR_GENMASK(1, 0) 306 #define FBNIC_QM_TNI_TCM_CTL_CLS CSR_GENMASK(3, 2) 307 #define FBNIC_QM_TNI_TCM_CTL_MAX_OT CSR_GENMASK(11, 4) 308 #define FBNIC_QM_TNI_TCM_CTL_MAX_OB CSR_GENMASK(23, 12) 309 #define FBNIC_CSR_END_QM_TX 0x00873 /* CSR section delimiter */ 310 311 /* Global QM Rx registers */ 312 #define FBNIC_CSR_START_QM_RX 0x00c00 /* CSR section delimiter */ 313 #define FBNIC_QM_RCQ_IDLE(n) (0x00c00 + (n)) /* 0x03000 + 4*n */ 314 #define FBNIC_QM_RCQ_IDLE_CNT 4 315 #define FBNIC_QM_RCQ_CTL0 0x00c0c /* 0x03030 */ 316 #define FBNIC_QM_RCQ_CTL0_COAL_WAIT CSR_GENMASK(15, 0) 317 #define FBNIC_QM_RCQ_CTL0_TICK_CYCLES CSR_GENMASK(26, 16) 318 #define FBNIC_QM_HPQ_IDLE(n) (0x00c0f + (n)) /* 0x0303c + 4*n */ 319 #define FBNIC_QM_HPQ_IDLE_CNT 4 320 #define FBNIC_QM_PPQ_IDLE(n) (0x00c13 + (n)) /* 0x0304c + 4*n */ 321 #define FBNIC_QM_PPQ_IDLE_CNT 4 322 #define FBNIC_QM_RNI_RBP_CTL 0x00c2d /* 0x030b4 */ 323 #define FBNIC_QM_RNI_RBP_CTL_MRRS CSR_GENMASK(1, 0) 324 #define FBNIC_QM_RNI_RBP_CTL_CLS CSR_GENMASK(3, 2) 325 #define FBNIC_QM_RNI_RBP_CTL_MAX_OT CSR_GENMASK(11, 4) 326 #define FBNIC_QM_RNI_RBP_CTL_MAX_OB CSR_GENMASK(23, 12) 327 #define FBNIC_QM_RNI_RDE_CTL 0x00c2e /* 0x030b8 */ 328 #define FBNIC_QM_RNI_RDE_CTL_MPS CSR_GENMASK(1, 0) 329 #define FBNIC_QM_RNI_RDE_CTL_CLS CSR_GENMASK(3, 2) 330 #define FBNIC_QM_RNI_RDE_CTL_MAX_OT CSR_GENMASK(11, 4) 331 #define FBNIC_QM_RNI_RDE_CTL_MAX_OB CSR_GENMASK(23, 12) 332 #define FBNIC_QM_RNI_RCM_CTL 0x00c2f /* 0x030bc */ 333 #define FBNIC_QM_RNI_RCM_CTL_MPS CSR_GENMASK(1, 0) 334 #define FBNIC_QM_RNI_RCM_CTL_CLS CSR_GENMASK(3, 2) 335 #define FBNIC_QM_RNI_RCM_CTL_MAX_OT CSR_GENMASK(11, 4) 336 #define FBNIC_QM_RNI_RCM_CTL_MAX_OB CSR_GENMASK(23, 12) 337 #define FBNIC_CSR_END_QM_RX 0x00c34 /* CSR section delimiter */ 338 339 /* TCE registers */ 340 #define FBNIC_CSR_START_TCE 0x04000 /* CSR section delimiter */ 341 #define FBNIC_TCE_REG_BASE 0x04000 /* 0x10000 */ 342 343 #define FBNIC_TCE_LSO_CTRL 0x04000 /* 0x10000 */ 344 #define FBNIC_TCE_LSO_CTRL_TCPF_CLR_1ST CSR_GENMASK(8, 0) 345 #define FBNIC_TCE_LSO_CTRL_TCPF_CLR_MID CSR_GENMASK(17, 9) 346 #define FBNIC_TCE_LSO_CTRL_TCPF_CLR_END CSR_GENMASK(26, 18) 347 #define FBNIC_TCE_LSO_CTRL_IPID_MODE_INC CSR_BIT(27) 348 349 #define FBNIC_TCE_CSO_CTRL 0x04001 /* 0x10004 */ 350 #define FBNIC_TCE_CSO_CTRL_TCP_ZERO_CSUM CSR_BIT(0) 351 352 #define FBNIC_TCE_TXB_CTRL 0x04002 /* 0x10008 */ 353 #define FBNIC_TCE_TXB_CTRL_LOAD CSR_BIT(0) 354 #define FBNIC_TCE_TXB_CTRL_TCAM_ENABLE CSR_BIT(1) 355 #define FBNIC_TCE_TXB_CTRL_DISABLE CSR_BIT(2) 356 357 #define FBNIC_TCE_TXB_ENQ_WRR_CTRL 0x04003 /* 0x1000c */ 358 #define FBNIC_TCE_TXB_ENQ_WRR_CTRL_WEIGHT0 CSR_GENMASK(7, 0) 359 #define FBNIC_TCE_TXB_ENQ_WRR_CTRL_WEIGHT1 CSR_GENMASK(15, 8) 360 #define FBNIC_TCE_TXB_ENQ_WRR_CTRL_WEIGHT2 CSR_GENMASK(23, 16) 361 362 #define FBNIC_TCE_TXB_TEI_Q0_CTRL 0x04004 /* 0x10010 */ 363 #define FBNIC_TCE_TXB_TEI_Q1_CTRL 0x04005 /* 0x10014 */ 364 #define FBNIC_TCE_TXB_MC_Q_CTRL 0x04006 /* 0x10018 */ 365 #define FBNIC_TCE_TXB_RX_TEI_Q_CTRL 0x04007 /* 0x1001c */ 366 #define FBNIC_TCE_TXB_RX_BMC_Q_CTRL 0x04008 /* 0x10020 */ 367 #define FBNIC_TCE_TXB_Q_CTRL_START CSR_GENMASK(10, 0) 368 #define FBNIC_TCE_TXB_Q_CTRL_SIZE CSR_GENMASK(22, 11) 369 370 #define FBNIC_TCE_TXB_TEI_DWRR_CTRL 0x04009 /* 0x10024 */ 371 #define FBNIC_TCE_TXB_TEI_DWRR_CTRL_QUANTUM0 CSR_GENMASK(7, 0) 372 #define FBNIC_TCE_TXB_TEI_DWRR_CTRL_QUANTUM1 CSR_GENMASK(15, 8) 373 #define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL 0x0400a /* 0x10028 */ 374 #define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_QUANTUM0 CSR_GENMASK(7, 0) 375 #define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_QUANTUM1 CSR_GENMASK(15, 8) 376 #define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_QUANTUM2 CSR_GENMASK(23, 16) 377 378 #define FBNIC_TCE_TXB_CLDR_CFG 0x0400b /* 0x1002c */ 379 #define FBNIC_TCE_TXB_CLDR_CFG_NUM_SLOT CSR_GENMASK(5, 0) 380 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG(n) (0x0400c + (n)) /* 0x10030 + 4*n */ 381 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_CNT 16 382 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_0 CSR_GENMASK(1, 0) 383 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_1 CSR_GENMASK(3, 2) 384 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_2 CSR_GENMASK(5, 4) 385 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_3 CSR_GENMASK(7, 6) 386 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_0 CSR_GENMASK(9, 8) 387 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_1 CSR_GENMASK(11, 10) 388 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_2 CSR_GENMASK(13, 12) 389 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_3 CSR_GENMASK(15, 14) 390 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_0 CSR_GENMASK(17, 16) 391 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_1 CSR_GENMASK(19, 18) 392 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_2 CSR_GENMASK(21, 20) 393 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_3 CSR_GENMASK(23, 22) 394 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_0 CSR_GENMASK(25, 24) 395 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_1 CSR_GENMASK(27, 26) 396 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_2 CSR_GENMASK(29, 28) 397 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_3 CSR_GENMASK(31, 30) 398 399 #define FBNIC_TCE_BMC_MAX_PKTSZ 0x0403a /* 0x100e8 */ 400 #define FBNIC_TCE_BMC_MAX_PKTSZ_TX CSR_GENMASK(13, 0) 401 #define FBNIC_TCE_BMC_MAX_PKTSZ_RX CSR_GENMASK(27, 14) 402 #define FBNIC_TCE_MC_MAX_PKTSZ 0x0403b /* 0x100ec */ 403 #define FBNIC_TCE_MC_MAX_PKTSZ_TMI CSR_GENMASK(13, 0) 404 405 #define FBNIC_TCE_SOP_PROT_CTRL 0x0403c /* 0x100f0 */ 406 #define FBNIC_TCE_SOP_PROT_CTRL_TBI CSR_GENMASK(7, 0) 407 #define FBNIC_TCE_SOP_PROT_CTRL_TTI_FRM CSR_GENMASK(14, 8) 408 #define FBNIC_TCE_SOP_PROT_CTRL_TTI_CM CSR_GENMASK(18, 15) 409 410 #define FBNIC_TCE_DROP_CTRL 0x0403d /* 0x100f4 */ 411 #define FBNIC_TCE_DROP_CTRL_TTI_CM_DROP_EN CSR_BIT(0) 412 #define FBNIC_TCE_DROP_CTRL_TTI_FRM_DROP_EN CSR_BIT(1) 413 #define FBNIC_TCE_DROP_CTRL_TTI_TBI_DROP_EN CSR_BIT(2) 414 415 #define FBNIC_TCE_TTI_CM_DROP_PKTS 0x0403e /* 0x100f8 */ 416 #define FBNIC_TCE_TTI_CM_DROP_BYTE_L 0x0403f /* 0x100fc */ 417 #define FBNIC_TCE_TTI_CM_DROP_BYTE_H 0x04040 /* 0x10100 */ 418 #define FBNIC_TCE_TTI_FRAME_DROP_PKTS 0x04041 /* 0x10104 */ 419 #define FBNIC_TCE_TTI_FRAME_DROP_BYTE_L 0x04042 /* 0x10108 */ 420 #define FBNIC_TCE_TTI_FRAME_DROP_BYTE_H 0x04043 /* 0x1010c */ 421 #define FBNIC_TCE_TBI_DROP_PKTS 0x04044 /* 0x10110 */ 422 #define FBNIC_TCE_TBI_DROP_BYTE_L 0x04045 /* 0x10114 */ 423 424 #define FBNIC_TCE_TCAM_IDX2DEST_MAP 0x0404A /* 0x10128 */ 425 #define FBNIC_TCE_TCAM_IDX2DEST_MAP_DEST_ID_0 CSR_GENMASK(3, 0) 426 enum { 427 FBNIC_TCE_TCAM_DEST_MAC = 1, 428 FBNIC_TCE_TCAM_DEST_BMC = 2, 429 FBNIC_TCE_TCAM_DEST_FW = 4, 430 }; 431 432 #define FBNIC_TCE_TXB_TX_BMC_Q_CTRL 0x0404B /* 0x1012c */ 433 #define FBNIC_TCE_TXB_BMC_DWRR_CTRL 0x0404C /* 0x10130 */ 434 #define FBNIC_TCE_TXB_BMC_DWRR_CTRL_QUANTUM0 CSR_GENMASK(7, 0) 435 #define FBNIC_TCE_TXB_BMC_DWRR_CTRL_QUANTUM1 CSR_GENMASK(15, 8) 436 #define FBNIC_TCE_TXB_TEI_DWRR_CTRL_EXT 0x0404D /* 0x10134 */ 437 #define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_EXT \ 438 0x0404E /* 0x10138 */ 439 #define FBNIC_TCE_TXB_BMC_DWRR_CTRL_EXT 0x0404F /* 0x1013c */ 440 #define FBNIC_CSR_END_TCE 0x04050 /* CSR section delimiter */ 441 442 /* TCE RAM registers */ 443 #define FBNIC_CSR_START_TCE_RAM 0x04200 /* CSR section delimiter */ 444 #define FBNIC_TCE_RAM_TCAM(m, n) \ 445 (0x04200 + 0x8 * (n) + (m)) /* 0x10800 + 32*n + 4*m */ 446 #define FBNIC_TCE_RAM_TCAM_MASK CSR_GENMASK(15, 0) 447 #define FBNIC_TCE_RAM_TCAM_VALUE CSR_GENMASK(31, 16) 448 #define FBNIC_TCE_RAM_TCAM3(n) (0x04218 + (n)) /* 0x010860 + 4*n */ 449 #define FBNIC_TCE_RAM_TCAM3_DEST_MASK CSR_GENMASK(5, 3) 450 #define FBNIC_TCE_RAM_TCAM3_MCQ_MASK CSR_BIT(7) 451 #define FBNIC_TCE_RAM_TCAM3_VALIDATE CSR_BIT(31) 452 #define FBNIC_CSR_END_TCE_RAM 0x0421F /* CSR section delimiter */ 453 454 /* TMI registers */ 455 #define FBNIC_CSR_START_TMI 0x04400 /* CSR section delimiter */ 456 #define FBNIC_TMI_SOP_PROT_CTRL 0x04400 /* 0x11000 */ 457 #define FBNIC_TMI_DROP_CTRL 0x04401 /* 0x11004 */ 458 #define FBNIC_TMI_DROP_CTRL_EN CSR_BIT(0) 459 #define FBNIC_TMI_DROP_PKTS 0x04402 /* 0x11008 */ 460 #define FBNIC_TMI_DROP_BYTE_L 0x04403 /* 0x1100c */ 461 #define FBNIC_TMI_ILLEGAL_PTP_REQS 0x04409 /* 0x11024 */ 462 #define FBNIC_TMI_GOOD_PTP_TS 0x0440a /* 0x11028 */ 463 #define FBNIC_TMI_BAD_PTP_TS 0x0440b /* 0x1102c */ 464 #define FBNIC_TMI_STAT_TX_PACKET_1519_2047_BYTES_L \ 465 0x04433 /* 0x110cc */ 466 #define FBNIC_TMI_STAT_TX_PACKET_1519_2047_BYTES_H \ 467 0x04434 /* 0x110d0 */ 468 #define FBNIC_TMI_STAT_TX_PACKET_2048_4095_BYTES_L \ 469 0x04435 /* 0x110d4 */ 470 #define FBNIC_TMI_STAT_TX_PACKET_2048_4095_BYTES_H \ 471 0x04436 /* 0x110d8 */ 472 #define FBNIC_TMI_STAT_TX_PACKET_4096_8191_BYTES_L \ 473 0x04437 /* 0x110dc */ 474 #define FBNIC_TMI_STAT_TX_PACKET_4096_8191_BYTES_H \ 475 0x04438 /* 0x110e0 */ 476 #define FBNIC_TMI_STAT_TX_PACKET_8192_9216_BYTES_L \ 477 0x04439 /* 0x110e4 */ 478 #define FBNIC_TMI_STAT_TX_PACKET_8192_9216_BYTES_H \ 479 0x0443a /* 0x110e8 */ 480 #define FBNIC_TMI_STAT_TX_PACKET_9217_MAX_BYTES_L \ 481 0x0443b /* 0x110ec */ 482 #define FBNIC_TMI_STAT_TX_PACKET_9217_MAX_BYTES_H \ 483 0x0443c /* 0x110f0 */ 484 #define FBNIC_CSR_END_TMI 0x0443f /* CSR section delimiter */ 485 486 /* Precision Time Protocol Registers */ 487 #define FBNIC_CSR_START_PTP 0x04800 /* CSR section delimiter */ 488 #define FBNIC_PTP_REG_BASE 0x04800 /* 0x12000 */ 489 490 #define FBNIC_PTP_CTRL 0x04800 /* 0x12000 */ 491 #define FBNIC_PTP_CTRL_EN CSR_BIT(0) 492 #define FBNIC_PTP_CTRL_MONO_EN CSR_BIT(4) 493 #define FBNIC_PTP_CTRL_TQS_OUT_EN CSR_BIT(8) 494 #define FBNIC_PTP_CTRL_MAC_OUT_IVAL CSR_GENMASK(16, 12) 495 #define FBNIC_PTP_CTRL_TICK_IVAL CSR_GENMASK(23, 20) 496 497 #define FBNIC_PTP_ADJUST 0x04801 /* 0x12004 */ 498 #define FBNIC_PTP_ADJUST_INIT CSR_BIT(0) 499 #define FBNIC_PTP_ADJUST_SUB_NUDGE CSR_BIT(8) 500 #define FBNIC_PTP_ADJUST_ADD_NUDGE CSR_BIT(16) 501 #define FBNIC_PTP_ADJUST_ADDEND_SET CSR_BIT(24) 502 503 #define FBNIC_PTP_INIT_HI 0x04802 /* 0x12008 */ 504 #define FBNIC_PTP_INIT_LO 0x04803 /* 0x1200c */ 505 506 #define FBNIC_PTP_NUDGE_NS 0x04804 /* 0x12010 */ 507 #define FBNIC_PTP_NUDGE_SUBNS 0x04805 /* 0x12014 */ 508 509 #define FBNIC_PTP_ADD_VAL_NS 0x04806 /* 0x12018 */ 510 #define FBNIC_PTP_ADD_VAL_NS_MASK CSR_GENMASK(15, 0) 511 #define FBNIC_PTP_ADD_VAL_SUBNS 0x04807 /* 0x1201c */ 512 513 #define FBNIC_PTP_CTR_VAL_HI 0x04808 /* 0x12020 */ 514 #define FBNIC_PTP_CTR_VAL_LO 0x04809 /* 0x12024 */ 515 516 #define FBNIC_PTP_MONO_PTP_CTR_HI 0x0480a /* 0x12028 */ 517 #define FBNIC_PTP_MONO_PTP_CTR_LO 0x0480b /* 0x1202c */ 518 519 #define FBNIC_PTP_CDC_FIFO_STATUS 0x0480c /* 0x12030 */ 520 #define FBNIC_PTP_SPARE 0x0480d /* 0x12034 */ 521 #define FBNIC_CSR_END_PTP 0x0480d /* CSR section delimiter */ 522 523 /* Rx Buffer Registers */ 524 #define FBNIC_CSR_START_RXB 0x08000 /* CSR section delimiter */ 525 enum { 526 FBNIC_RXB_FIFO_MC = 0, 527 /* Unused */ 528 /* Unused */ 529 FBNIC_RXB_FIFO_NET_TO_BMC = 3, 530 FBNIC_RXB_FIFO_HOST = 4, 531 /* Unused */ 532 FBNIC_RXB_FIFO_BMC_TO_HOST = 6, 533 /* Unused */ 534 FBNIC_RXB_FIFO_INDICES = 8 535 }; 536 537 enum { 538 FBNIC_RXB_INTF_NET = 0, 539 FBNIC_RXB_INTF_RBT = 1, 540 /* Unused */ 541 /* Unused */ 542 FBNIC_RXB_INTF_INDICES = 4 543 }; 544 545 #define FBNIC_RXB_CT_SIZE(n) (0x08000 + (n)) /* 0x20000 + 4*n */ 546 #define FBNIC_RXB_CT_SIZE_CNT 8 547 #define FBNIC_RXB_CT_SIZE_HEADER CSR_GENMASK(5, 0) 548 #define FBNIC_RXB_CT_SIZE_PAYLOAD CSR_GENMASK(11, 6) 549 #define FBNIC_RXB_CT_SIZE_ENABLE CSR_BIT(12) 550 #define FBNIC_RXB_PAUSE_DROP_CTRL 0x08008 /* 0x20020 */ 551 #define FBNIC_RXB_PAUSE_DROP_CTRL_DROP_ENABLE CSR_GENMASK(7, 0) 552 #define FBNIC_RXB_PAUSE_DROP_CTRL_PAUSE_ENABLE CSR_GENMASK(15, 8) 553 #define FBNIC_RXB_PAUSE_DROP_CTRL_ECN_ENABLE CSR_GENMASK(23, 16) 554 #define FBNIC_RXB_PAUSE_DROP_CTRL_PS_ENABLE CSR_GENMASK(27, 24) 555 #define FBNIC_RXB_PAUSE_THLD(n) (0x08009 + (n)) /* 0x20024 + 4*n */ 556 #define FBNIC_RXB_PAUSE_THLD_CNT 8 557 #define FBNIC_RXB_PAUSE_THLD_ON CSR_GENMASK(12, 0) 558 #define FBNIC_RXB_PAUSE_THLD_OFF CSR_GENMASK(25, 13) 559 #define FBNIC_RXB_DROP_THLD(n) (0x08011 + (n)) /* 0x20044 + 4*n */ 560 #define FBNIC_RXB_DROP_THLD_CNT 8 561 #define FBNIC_RXB_DROP_THLD_ON CSR_GENMASK(12, 0) 562 #define FBNIC_RXB_DROP_THLD_OFF CSR_GENMASK(25, 13) 563 #define FBNIC_RXB_ECN_THLD(n) (0x0801e + (n)) /* 0x20078 + 4*n */ 564 #define FBNIC_RXB_ECN_THLD_CNT 8 565 #define FBNIC_RXB_ECN_THLD_ON CSR_GENMASK(12, 0) 566 #define FBNIC_RXB_ECN_THLD_OFF CSR_GENMASK(25, 13) 567 #define FBNIC_RXB_PBUF_CFG(n) (0x08027 + (n)) /* 0x2009c + 4*n */ 568 #define FBNIC_RXB_PBUF_CFG_CNT 8 569 #define FBNIC_RXB_PBUF_BASE_ADDR CSR_GENMASK(12, 0) 570 #define FBNIC_RXB_PBUF_SIZE CSR_GENMASK(21, 13) 571 #define FBNIC_RXB_DWRR_RDE_WEIGHT0 0x0802f /* 0x200bc */ 572 #define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM0 CSR_GENMASK(7, 0) 573 #define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM1 CSR_GENMASK(15, 8) 574 #define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM2 CSR_GENMASK(23, 16) 575 #define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM3 CSR_GENMASK(31, 24) 576 #define FBNIC_RXB_DWRR_RDE_WEIGHT1 0x08030 /* 0x200c0 */ 577 #define FBNIC_RXB_DWRR_RDE_WEIGHT1_QUANTUM4 CSR_GENMASK(7, 0) 578 #define FBNIC_RXB_DWRR_BMC_WEIGHT 0x08031 /* 0x200c4 */ 579 #define FBNIC_RXB_CLDR_PRIO_CFG(n) (0x8034 + (n)) /* 0x200d0 + 4*n */ 580 #define FBNIC_RXB_CLDR_PRIO_CFG_CNT 16 581 #define FBNIC_RXB_ENDIAN_FCS 0x08044 /* 0x20110 */ 582 enum { 583 /* Unused */ 584 /* Unused */ 585 FBNIC_RXB_DEQUEUE_BMC = 2, 586 FBNIC_RXB_DEQUEUE_HOST = 3, 587 FBNIC_RXB_DEQUEUE_INDICES = 4 588 }; 589 590 #define FBNIC_RXB_PBUF_CREDIT(n) (0x08047 + (n)) /* 0x2011C + 4*n */ 591 #define FBNIC_RXB_PBUF_CREDIT_CNT 8 592 #define FBNIC_RXB_PBUF_CREDIT_MASK CSR_GENMASK(13, 0) 593 #define FBNIC_RXB_INTF_CREDIT 0x0804f /* 0x2013C */ 594 #define FBNIC_RXB_INTF_CREDIT_MASK0 CSR_GENMASK(3, 0) 595 #define FBNIC_RXB_INTF_CREDIT_MASK1 CSR_GENMASK(7, 4) 596 #define FBNIC_RXB_INTF_CREDIT_MASK2 CSR_GENMASK(11, 8) 597 #define FBNIC_RXB_INTF_CREDIT_MASK3 CSR_GENMASK(15, 12) 598 599 #define FBNIC_RXB_PAUSE_EVENT_CNT(n) (0x08053 + (n)) /* 0x2014c + 4*n */ 600 #define FBNIC_RXB_DROP_FRMS_STS(n) (0x08057 + (n)) /* 0x2015c + 4*n */ 601 #define FBNIC_RXB_DROP_BYTES_STS_L(n) \ 602 (0x08080 + 2 * (n)) /* 0x20200 + 8*n */ 603 #define FBNIC_RXB_DROP_BYTES_STS_H(n) \ 604 (0x08081 + 2 * (n)) /* 0x20204 + 8*n */ 605 #define FBNIC_RXB_TRUN_FRMS_STS(n) (0x08091 + (n)) /* 0x20244 + 4*n */ 606 #define FBNIC_RXB_TRUN_BYTES_STS_L(n) \ 607 (0x080c0 + 2 * (n)) /* 0x20300 + 8*n */ 608 #define FBNIC_RXB_TRUN_BYTES_STS_H(n) \ 609 (0x080c1 + 2 * (n)) /* 0x20304 + 8*n */ 610 #define FBNIC_RXB_TRANS_PAUSE_STS(n) (0x080d1 + (n)) /* 0x20344 + 4*n */ 611 #define FBNIC_RXB_TRANS_DROP_STS(n) (0x080d9 + (n)) /* 0x20364 + 4*n */ 612 #define FBNIC_RXB_TRANS_ECN_STS(n) (0x080e1 + (n)) /* 0x20384 + 4*n */ 613 enum { 614 FBNIC_RXB_ENQUEUE_NET = 0, 615 FBNIC_RXB_ENQUEUE_BMC = 1, 616 /* Unused */ 617 /* Unused */ 618 FBNIC_RXB_ENQUEUE_INDICES = 4 619 }; 620 621 #define FBNIC_RXB_DRBO_FRM_CNT_SRC(n) (0x080f9 + (n)) /* 0x203e4 + 4*n */ 622 #define FBNIC_RXB_DRBO_BYTE_CNT_SRC_L(n) \ 623 (0x080fd + (n)) /* 0x203f4 + 4*n */ 624 #define FBNIC_RXB_DRBO_BYTE_CNT_SRC_H(n) \ 625 (0x08101 + (n)) /* 0x20404 + 4*n */ 626 #define FBNIC_RXB_INTF_FRM_CNT_DST(n) (0x08105 + (n)) /* 0x20414 + 4*n */ 627 #define FBNIC_RXB_INTF_BYTE_CNT_DST_L(n) \ 628 (0x08109 + (n)) /* 0x20424 + 4*n */ 629 #define FBNIC_RXB_INTF_BYTE_CNT_DST_H(n) \ 630 (0x0810d + (n)) /* 0x20434 + 4*n */ 631 #define FBNIC_RXB_PBUF_FRM_CNT_DST(n) (0x08111 + (n)) /* 0x20444 + 4*n */ 632 #define FBNIC_RXB_PBUF_BYTE_CNT_DST_L(n) \ 633 (0x08115 + (n)) /* 0x20454 + 4*n */ 634 #define FBNIC_RXB_PBUF_BYTE_CNT_DST_H(n) \ 635 (0x08119 + (n)) /* 0x20464 + 4*n */ 636 637 #define FBNIC_RXB_PBUF_FIFO_LEVEL(n) (0x0811d + (n)) /* 0x20474 + 4*n */ 638 639 #define FBNIC_RXB_INTEGRITY_ERR(n) (0x0812f + (n)) /* 0x204bc + 4*n */ 640 #define FBNIC_RXB_MAC_ERR(n) (0x08133 + (n)) /* 0x204cc + 4*n */ 641 #define FBNIC_RXB_PARSER_ERR(n) (0x08137 + (n)) /* 0x204dc + 4*n */ 642 #define FBNIC_RXB_FRM_ERR(n) (0x0813b + (n)) /* 0x204ec + 4*n */ 643 644 #define FBNIC_RXB_DWRR_RDE_WEIGHT0_EXT 0x08143 /* 0x2050c */ 645 #define FBNIC_RXB_DWRR_RDE_WEIGHT1_EXT 0x08144 /* 0x20510 */ 646 #define FBNIC_CSR_END_RXB 0x081b1 /* CSR section delimiter */ 647 648 /* Rx Parser and Classifier Registers */ 649 #define FBNIC_CSR_START_RPC 0x08400 /* CSR section delimiter */ 650 #define FBNIC_RPC_RMI_CONFIG 0x08400 /* 0x21000 */ 651 #define FBNIC_RPC_RMI_CONFIG_OH_BYTES CSR_GENMASK(4, 0) 652 #define FBNIC_RPC_RMI_CONFIG_FCS_PRESENT CSR_BIT(8) 653 #define FBNIC_RPC_RMI_CONFIG_ENABLE CSR_BIT(12) 654 #define FBNIC_RPC_RMI_CONFIG_MTU CSR_GENMASK(31, 16) 655 656 #define FBNIC_RPC_ACT_TBL0_DEFAULT 0x0840a /* 0x21028 */ 657 #define FBNIC_RPC_ACT_TBL0_DROP CSR_BIT(0) 658 #define FBNIC_RPC_ACT_TBL0_DEST_MASK CSR_GENMASK(3, 1) 659 enum { 660 FBNIC_RPC_ACT_TBL0_DEST_HOST = 1, 661 FBNIC_RPC_ACT_TBL0_DEST_BMC = 2, 662 FBNIC_RPC_ACT_TBL0_DEST_EI = 4, 663 }; 664 665 #define FBNIC_RPC_ACT_TBL0_Q_SEL CSR_BIT(4) 666 #define FBNIC_RPC_ACT_TBL0_Q_ID CSR_GENMASK(15, 8) 667 #define FBNIC_RPC_ACT_TBL0_DMA_HINT CSR_GENMASK(24, 16) 668 #define FBNIC_RPC_ACT_TBL0_TS_ENA CSR_BIT(28) 669 #define FBNIC_RPC_ACT_TBL0_ACT_TBL_IDX CSR_BIT(29) 670 #define FBNIC_RPC_ACT_TBL0_RSS_CTXT_ID CSR_BIT(30) 671 672 #define FBNIC_RPC_ACT_TBL1_DEFAULT 0x0840b /* 0x2102c */ 673 #define FBNIC_RPC_ACT_TBL1_RSS_ENA_MASK CSR_GENMASK(15, 0) 674 enum { 675 FBNIC_RPC_ACT_TBL1_RSS_ENA_IP_SRC = 1, 676 FBNIC_RPC_ACT_TBL1_RSS_ENA_IP_DST = 2, 677 FBNIC_RPC_ACT_TBL1_RSS_ENA_L4_SRC = 4, 678 FBNIC_RPC_ACT_TBL1_RSS_ENA_L4_DST = 8, 679 FBNIC_RPC_ACT_TBL1_RSS_ENA_L2_DA = 16, 680 FBNIC_RPC_ACT_TBL1_RSS_ENA_L4_RSS_BYTE = 32, 681 FBNIC_RPC_ACT_TBL1_RSS_ENA_IV6_FL_LBL = 64, 682 FBNIC_RPC_ACT_TBL1_RSS_ENA_OV6_FL_LBL = 128, 683 FBNIC_RPC_ACT_TBL1_RSS_ENA_DSCP = 256, 684 FBNIC_RPC_ACT_TBL1_RSS_ENA_L3_PROT = 512, 685 FBNIC_RPC_ACT_TBL1_RSS_ENA_L4_PROT = 1024, 686 }; 687 688 #define FBNIC_RPC_RSS_KEY(n) (0x0840c + (n)) /* 0x21030 + 4*n */ 689 #define FBNIC_RPC_RSS_KEY_BIT_LEN 425 690 #define FBNIC_RPC_RSS_KEY_BYTE_LEN \ 691 DIV_ROUND_UP(FBNIC_RPC_RSS_KEY_BIT_LEN, 8) 692 #define FBNIC_RPC_RSS_KEY_DWORD_LEN \ 693 DIV_ROUND_UP(FBNIC_RPC_RSS_KEY_BIT_LEN, 32) 694 #define FBNIC_RPC_RSS_KEY_LAST_IDX \ 695 (FBNIC_RPC_RSS_KEY_DWORD_LEN - 1) 696 #define FBNIC_RPC_RSS_KEY_LAST_MASK \ 697 CSR_GENMASK(31, \ 698 FBNIC_RPC_RSS_KEY_DWORD_LEN * 32 - \ 699 FBNIC_RPC_RSS_KEY_BIT_LEN) 700 701 #define FBNIC_RPC_CNTR_TCP_OPT_ERR 0x0849e /* 0x21278 */ 702 #define FBNIC_RPC_CNTR_UNKN_ETYPE 0x0849f /* 0x2127c */ 703 #define FBNIC_RPC_CNTR_IPV4_FRAG 0x084a0 /* 0x21280 */ 704 #define FBNIC_RPC_CNTR_IPV6_FRAG 0x084a1 /* 0x21284 */ 705 #define FBNIC_RPC_CNTR_IPV4_ESP 0x084a2 /* 0x21288 */ 706 #define FBNIC_RPC_CNTR_IPV6_ESP 0x084a3 /* 0x2128c */ 707 #define FBNIC_RPC_CNTR_UNKN_EXT_HDR 0x084a4 /* 0x21290 */ 708 #define FBNIC_RPC_CNTR_OUT_OF_HDR_ERR 0x084a5 /* 0x21294 */ 709 #define FBNIC_RPC_CNTR_OVR_SIZE_ERR 0x084a6 /* 0x21298 */ 710 711 #define FBNIC_RPC_TCAM_MACDA_VALIDATE 0x0852d /* 0x214b4 */ 712 #define FBNIC_RPC_STAT_RX_PACKET_1519_2047_BYTES_L \ 713 0x0855f /* 0x2157c */ 714 #define FBNIC_RPC_STAT_RX_PACKET_1519_2047_BYTES_H \ 715 0x08560 /* 0x21580 */ 716 #define FBNIC_RPC_STAT_RX_PACKET_2048_4095_BYTES_L \ 717 0x08561 /* 0x21584 */ 718 #define FBNIC_RPC_STAT_RX_PACKET_2048_4095_BYTES_H \ 719 0x08562 /* 0x21588 */ 720 #define FBNIC_RPC_STAT_RX_PACKET_4096_8191_BYTES_L \ 721 0x08563 /* 0x2158c */ 722 #define FBNIC_RPC_STAT_RX_PACKET_4096_8191_BYTES_H \ 723 0x08564 /* 0x21590 */ 724 #define FBNIC_RPC_STAT_RX_PACKET_8192_9216_BYTES_L \ 725 0x08565 /* 0x21594 */ 726 #define FBNIC_RPC_STAT_RX_PACKET_8192_9216_BYTES_H \ 727 0x08566 /* 0x21598 */ 728 #define FBNIC_RPC_STAT_RX_PACKET_9217_MAX_BYTES_L \ 729 0x08567 /* 0x2159c */ 730 #define FBNIC_RPC_STAT_RX_PACKET_9217_MAX_BYTES_H \ 731 0x08568 /* 0x215a0 */ 732 #define FBNIC_CSR_END_RPC 0x0856b /* CSR section delimiter */ 733 734 /* RPC RAM Registers */ 735 736 #define FBNIC_CSR_START_RPC_RAM 0x08800 /* CSR section delimiter */ 737 #define FBNIC_RPC_ACT_TBL0(n) (0x08800 + (n)) /* 0x22000 + 4*n */ 738 #define FBNIC_RPC_ACT_TBL1(n) (0x08840 + (n)) /* 0x22100 + 4*n */ 739 #define FBNIC_RPC_ACT_TBL_NUM_ENTRIES 64 740 741 /* TCAM Tables */ 742 #define FBNIC_RPC_TCAM_VALIDATE CSR_BIT(31) 743 744 /* 64 Action TCAM Entries, 12 registers 745 * 3 mixed, src port, dst port, 6 L4 words, and Validate 746 */ 747 #define FBNIC_RPC_TCAM_ACT(m, n) \ 748 (0x08880 + 0x40 * (n) + (m)) /* 0x22200 + 256*n + 4*m */ 749 750 #define FBNIC_RPC_TCAM_ACT_VALUE CSR_GENMASK(15, 0) 751 #define FBNIC_RPC_TCAM_ACT_MASK CSR_GENMASK(31, 16) 752 753 #define FBNIC_RPC_TCAM_MACDA(m, n) \ 754 (0x08b80 + 0x20 * (n) + (m)) /* 0x022e00 + 128*n + 4*m */ 755 #define FBNIC_RPC_TCAM_MACDA_VALUE CSR_GENMASK(15, 0) 756 #define FBNIC_RPC_TCAM_MACDA_MASK CSR_GENMASK(31, 16) 757 758 #define FBNIC_RPC_TCAM_OUTER_IPSRC(m, n)\ 759 (0x08c00 + 0x08 * (n) + (m)) /* 0x023000 + 32*n + 4*m */ 760 #define FBNIC_RPC_TCAM_IP_ADDR_VALUE CSR_GENMASK(15, 0) 761 #define FBNIC_RPC_TCAM_IP_ADDR_MASK CSR_GENMASK(31, 16) 762 763 #define FBNIC_RPC_TCAM_OUTER_IPDST(m, n)\ 764 (0x08c48 + 0x08 * (n) + (m)) /* 0x023120 + 32*n + 4*m */ 765 #define FBNIC_RPC_TCAM_IPSRC(m, n)\ 766 (0x08c90 + 0x08 * (n) + (m)) /* 0x023240 + 32*n + 4*m */ 767 #define FBNIC_RPC_TCAM_IPDST(m, n)\ 768 (0x08cd8 + 0x08 * (n) + (m)) /* 0x023360 + 32*n + 4*m */ 769 770 #define FBNIC_RPC_RSS_TBL(n, m) \ 771 (0x08d20 + 0x100 * (n) + (m)) /* 0x023480 + 1024*n + 4*m */ 772 #define FBNIC_RPC_RSS_TBL_COUNT 2 773 #define FBNIC_RPC_RSS_TBL_SIZE 256 774 #define FBNIC_CSR_END_RPC_RAM 0x08f1f /* CSR section delimiter */ 775 776 /* Fab Registers */ 777 #define FBNIC_CSR_START_FAB 0x0C000 /* CSR section delimiter */ 778 #define FBNIC_FAB_AXI4_AR_SPACER_2_CFG 0x0C005 /* 0x30014 */ 779 #define FBNIC_FAB_AXI4_AR_SPACER_MASK CSR_BIT(16) 780 #define FBNIC_FAB_AXI4_AR_SPACER_THREADSHOLD CSR_GENMASK(15, 0) 781 #define FBNIC_CSR_END_FAB 0x0C020 /* CSR section delimiter */ 782 783 /* Master Registers */ 784 #define FBNIC_CSR_START_MASTER 0x0C400 /* CSR section delimiter */ 785 #define FBNIC_MASTER_SPARE_0 0x0C41B /* 0x3106c */ 786 #define FBNIC_CSR_END_MASTER 0x0C452 /* CSR section delimiter */ 787 788 /* MAC PCS registers */ 789 #define FBNIC_CSR_START_PCS 0x10000 /* CSR section delimiter */ 790 #define FBNIC_CSR_END_PCS 0x10668 /* CSR section delimiter */ 791 792 #define FBNIC_CSR_START_RSFEC 0x10800 /* CSR section delimiter */ 793 #define FBNIC_CSR_END_RSFEC 0x108c8 /* CSR section delimiter */ 794 795 /* MAC MAC registers (ASIC only) */ 796 #define FBNIC_CSR_START_MAC_MAC 0x11000 /* CSR section delimiter */ 797 #define FBNIC_MAC_COMMAND_CONFIG 0x11002 /* 0x44008 */ 798 #define FBNIC_MAC_COMMAND_CONFIG_RX_PAUSE_DIS CSR_BIT(29) 799 #define FBNIC_MAC_COMMAND_CONFIG_TX_PAUSE_DIS CSR_BIT(28) 800 #define FBNIC_MAC_COMMAND_CONFIG_FLT_HDL_DIS CSR_BIT(27) 801 #define FBNIC_MAC_COMMAND_CONFIG_TX_PAD_EN CSR_BIT(11) 802 #define FBNIC_MAC_COMMAND_CONFIG_LOOPBACK_EN CSR_BIT(10) 803 #define FBNIC_MAC_COMMAND_CONFIG_PROMISC_EN CSR_BIT(4) 804 #define FBNIC_MAC_COMMAND_CONFIG_RX_ENA CSR_BIT(1) 805 #define FBNIC_MAC_COMMAND_CONFIG_TX_ENA CSR_BIT(0) 806 #define FBNIC_MAC_CL01_PAUSE_QUANTA 0x11015 /* 0x44054 */ 807 #define FBNIC_MAC_CL01_QUANTA_THRESH 0x11019 /* 0x44064 */ 808 #define FBNIC_CSR_END_MAC_MAC 0x11028 /* CSR section delimiter */ 809 810 /* Signals from MAC, AN, PCS, and LED CSR registers (ASIC only) */ 811 #define FBNIC_CSR_START_SIG 0x11800 /* CSR section delimiter */ 812 #define FBNIC_SIG_MAC_IN0 0x11800 /* 0x46000 */ 813 #define FBNIC_SIG_MAC_IN0_RESET_FF_TX_CLK CSR_BIT(14) 814 #define FBNIC_SIG_MAC_IN0_RESET_FF_RX_CLK CSR_BIT(13) 815 #define FBNIC_SIG_MAC_IN0_RESET_TX_CLK CSR_BIT(12) 816 #define FBNIC_SIG_MAC_IN0_RESET_RX_CLK CSR_BIT(11) 817 #define FBNIC_SIG_MAC_IN0_TX_CRC CSR_BIT(8) 818 #define FBNIC_SIG_MAC_IN0_CFG_MODE128 CSR_BIT(10) 819 #define FBNIC_SIG_PCS_OUT0 0x11808 /* 0x46020 */ 820 #define FBNIC_SIG_PCS_OUT0_LINK CSR_BIT(27) 821 #define FBNIC_SIG_PCS_OUT0_BLOCK_LOCK CSR_GENMASK(24, 5) 822 #define FBNIC_SIG_PCS_OUT0_AMPS_LOCK CSR_GENMASK(4, 1) 823 #define FBNIC_SIG_PCS_OUT1 0x11809 /* 0x46024 */ 824 #define FBNIC_SIG_PCS_OUT1_FCFEC_LOCK CSR_GENMASK(11, 8) 825 #define FBNIC_SIG_PCS_INTR_STS 0x11814 /* 0x46050 */ 826 #define FBNIC_SIG_PCS_INTR_LINK_DOWN CSR_BIT(1) 827 #define FBNIC_SIG_PCS_INTR_LINK_UP CSR_BIT(0) 828 #define FBNIC_SIG_PCS_INTR_MASK 0x11816 /* 0x46058 */ 829 #define FBNIC_CSR_END_SIG 0x1184e /* CSR section delimiter */ 830 831 #define FBNIC_CSR_START_MAC_STAT 0x11a00 832 #define FBNIC_MAC_STAT_RX_BYTE_COUNT_L 0x11a08 /* 0x46820 */ 833 #define FBNIC_MAC_STAT_RX_BYTE_COUNT_H 0x11a09 /* 0x46824 */ 834 #define FBNIC_MAC_STAT_RX_ALIGN_ERROR_L 0x11a0a /* 0x46828 */ 835 #define FBNIC_MAC_STAT_RX_ALIGN_ERROR_H 0x11a0b /* 0x4682c */ 836 #define FBNIC_MAC_STAT_RX_TOOLONG_L 0x11a0e /* 0x46838 */ 837 #define FBNIC_MAC_STAT_RX_TOOLONG_H 0x11a0f /* 0x4683c */ 838 #define FBNIC_MAC_STAT_RX_RECEIVED_OK_L 0x11a12 /* 0x46848 */ 839 #define FBNIC_MAC_STAT_RX_RECEIVED_OK_H 0x11a13 /* 0x4684c */ 840 #define FBNIC_MAC_STAT_RX_PACKET_BAD_FCS_L \ 841 0x11a14 /* 0x46850 */ 842 #define FBNIC_MAC_STAT_RX_PACKET_BAD_FCS_H \ 843 0x11a15 /* 0x46854 */ 844 #define FBNIC_MAC_STAT_RX_IFINERRORS_L 0x11a18 /* 0x46860 */ 845 #define FBNIC_MAC_STAT_RX_IFINERRORS_H 0x11a19 /* 0x46864 */ 846 #define FBNIC_MAC_STAT_RX_MULTICAST_L 0x11a1c /* 0x46870 */ 847 #define FBNIC_MAC_STAT_RX_MULTICAST_H 0x11a1d /* 0x46874 */ 848 #define FBNIC_MAC_STAT_RX_BROADCAST_L 0x11a1e /* 0x46878 */ 849 #define FBNIC_MAC_STAT_RX_BROADCAST_H 0x11a1f /* 0x4687c */ 850 #define FBNIC_MAC_STAT_RX_UNDERSIZE_L 0x11a24 /* 0x46890 */ 851 #define FBNIC_MAC_STAT_RX_UNDERSIZE_H 0x11a25 /* 0x46894 */ 852 #define FBNIC_MAC_STAT_RX_PACKET_64_BYTES_L \ 853 0x11a26 /* 0x46898 */ 854 #define FBNIC_MAC_STAT_RX_PACKET_64_BYTES_H \ 855 0x11a27 /* 0x4689c */ 856 #define FBNIC_MAC_STAT_RX_PACKET_65_127_BYTES_L \ 857 0x11a28 /* 0x468a0 */ 858 #define FBNIC_MAC_STAT_RX_PACKET_65_127_BYTES_H \ 859 0x11a29 /* 0x468a4 */ 860 #define FBNIC_MAC_STAT_RX_PACKET_128_255_BYTES_L \ 861 0x11a2a /* 0x468a8 */ 862 #define FBNIC_MAC_STAT_RX_PACKET_128_255_BYTES_H \ 863 0x11a2b /* 0x468ac */ 864 #define FBNIC_MAC_STAT_RX_PACKET_256_511_BYTES_L \ 865 0x11a2c /* 0x468b0 */ 866 #define FBNIC_MAC_STAT_RX_PACKET_256_511_BYTES_H \ 867 0x11a2d /* 0x468b4 */ 868 #define FBNIC_MAC_STAT_RX_PACKET_512_1023_BYTES_L \ 869 0x11a2e /* 0x468b8 */ 870 #define FBNIC_MAC_STAT_RX_PACKET_512_1023_BYTES_H \ 871 0x11a2f /* 0x468bc */ 872 #define FBNIC_MAC_STAT_RX_PACKET_1024_1518_BYTES_L \ 873 0x11a30 /* 0x468c0 */ 874 #define FBNIC_MAC_STAT_RX_PACKET_1024_1518_BYTES_H \ 875 0x11a31 /* 0x468c4 */ 876 #define FBNIC_MAC_STAT_RX_PACKET_1519_MAX_BYTES_L \ 877 0x11a32 /* 0x468c8 */ 878 #define FBNIC_MAC_STAT_RX_PACKET_1519_MAX_BYTES_H \ 879 0x11a33 /* 0x468cc */ 880 #define FBNIC_MAC_STAT_RX_OVERSIZE_L 0x11a34 /* 0x468d0 */ 881 #define FBNIC_MAC_STAT_RX_OVERSSIZE_H 0x11a35 /* 0x468d4 */ 882 #define FBNIC_MAC_STAT_RX_JABBER_L 0x11a36 /* 0x468d8 */ 883 #define FBNIC_MAC_STAT_RX_JABBER_H 0x11a37 /* 0x468dc */ 884 #define FBNIC_MAC_STAT_RX_FRAGMENT_L 0x11a38 /* 0x468e0 */ 885 #define FBNIC_MAC_STAT_RX_FRAGMENT_H 0x11a39 /* 0x468e4 */ 886 #define FBNIC_MAC_STAT_RX_CONTROL_FRAMES_L \ 887 0x11a3c /* 0x468f0 */ 888 #define FBNIC_MAC_STAT_RX_CONTROL_FRAMES_H \ 889 0x11a3d /* 0x468f4 */ 890 #define FBNIC_MAC_STAT_TX_BYTE_COUNT_L 0x11a3e /* 0x468f8 */ 891 #define FBNIC_MAC_STAT_TX_BYTE_COUNT_H 0x11a3f /* 0x468fc */ 892 #define FBNIC_MAC_STAT_TX_TRANSMITTED_OK_L \ 893 0x11a42 /* 0x46908 */ 894 #define FBNIC_MAC_STAT_TX_TRANSMITTED_OK_H \ 895 0x11a43 /* 0x4690c */ 896 #define FBNIC_MAC_STAT_TX_IFOUTERRORS_L 0x11a46 /* 0x46918 */ 897 #define FBNIC_MAC_STAT_TX_IFOUTERRORS_H 0x11a47 /* 0x4691c */ 898 #define FBNIC_MAC_STAT_TX_MULTICAST_L 0x11a4a /* 0x46928 */ 899 #define FBNIC_MAC_STAT_TX_MULTICAST_H 0x11a4b /* 0x4692c */ 900 #define FBNIC_MAC_STAT_TX_BROADCAST_L 0x11a4c /* 0x46930 */ 901 #define FBNIC_MAC_STAT_TX_BROADCAST_H 0x11a4d /* 0x46934 */ 902 #define FBNIC_MAC_STAT_TX_PACKET_64_BYTES_L \ 903 0x11a4e /* 0x46938 */ 904 #define FBNIC_MAC_STAT_TX_PACKET_64_BYTES_H \ 905 0x11a4f /* 0x4693c */ 906 #define FBNIC_MAC_STAT_TX_PACKET_65_127_BYTES_L \ 907 0x11a50 /* 0x46940 */ 908 #define FBNIC_MAC_STAT_TX_PACKET_65_127_BYTES_H \ 909 0x11a51 /* 0x46944 */ 910 #define FBNIC_MAC_STAT_TX_PACKET_128_255_BYTES_L \ 911 0x11a52 /* 0x46948 */ 912 #define FBNIC_MAC_STAT_TX_PACKET_128_255_BYTES_H \ 913 0x11a53 /* 0x4694c */ 914 #define FBNIC_MAC_STAT_TX_PACKET_256_511_BYTES_L \ 915 0x11a54 /* 0x46950 */ 916 #define FBNIC_MAC_STAT_TX_PACKET_256_511_BYTES_H \ 917 0x11a55 /* 0x46954 */ 918 #define FBNIC_MAC_STAT_TX_PACKET_512_1023_BYTES_L \ 919 0x11a56 /* 0x46958 */ 920 #define FBNIC_MAC_STAT_TX_PACKET_512_1023_BYTES_H \ 921 0x11a57 /* 0x4695c */ 922 #define FBNIC_MAC_STAT_TX_PACKET_1024_1518_BYTES_L \ 923 0x11a58 /* 0x46960 */ 924 #define FBNIC_MAC_STAT_TX_PACKET_1024_1518_BYTES_H \ 925 0x11a59 /* 0x46964 */ 926 #define FBNIC_MAC_STAT_TX_PACKET_1519_MAX_BYTES_L \ 927 0x11a5a /* 0x46968 */ 928 #define FBNIC_MAC_STAT_TX_PACKET_1519_MAX_BYTES_H \ 929 0x11a5b /* 0x4696c */ 930 #define FBNIC_MAC_STAT_TX_CONTROL_FRAMES_L \ 931 0x11a5e /* 0x46978 */ 932 #define FBNIC_MAC_STAT_TX_CONTROL_FRAMES_H \ 933 0x11a5f /* 0x4697c */ 934 935 /* PCIE Comphy Registers */ 936 #define FBNIC_CSR_START_PCIE_SS_COMPHY 0x2442e /* CSR section delimiter */ 937 #define FBNIC_CSR_END_PCIE_SS_COMPHY 0x279d7 /* CSR section delimiter */ 938 939 /* PUL User Registers */ 940 #define FBNIC_CSR_START_PUL_USER 0x31000 /* CSR section delimiter */ 941 #define FBNIC_PUL_OB_TLP_HDR_AW_CFG 0x3103d /* 0xc40f4 */ 942 #define FBNIC_PUL_OB_TLP_HDR_AW_CFG_FLUSH CSR_BIT(19) 943 #define FBNIC_PUL_OB_TLP_HDR_AW_CFG_BME CSR_BIT(18) 944 #define FBNIC_PUL_OB_TLP_HDR_AR_CFG 0x3103e /* 0xc40f8 */ 945 #define FBNIC_PUL_OB_TLP_HDR_AR_CFG_FLUSH CSR_BIT(19) 946 #define FBNIC_PUL_OB_TLP_HDR_AR_CFG_BME CSR_BIT(18) 947 #define FBNIC_PUL_USER_OB_RD_TLP_CNT_31_0 \ 948 0x3106e /* 0xc41b8 */ 949 #define FBNIC_PUL_USER_OB_RD_DWORD_CNT_31_0 \ 950 0x31070 /* 0xc41c0 */ 951 #define FBNIC_PUL_USER_OB_RD_DWORD_CNT_63_32 \ 952 0x31071 /* 0xc41c4 */ 953 #define FBNIC_PUL_USER_OB_WR_TLP_CNT_31_0 \ 954 0x31072 /* 0xc41c8 */ 955 #define FBNIC_PUL_USER_OB_WR_TLP_CNT_63_32 \ 956 0x31073 /* 0xc41cc */ 957 #define FBNIC_PUL_USER_OB_WR_DWORD_CNT_31_0 \ 958 0x31074 /* 0xc41d0 */ 959 #define FBNIC_PUL_USER_OB_WR_DWORD_CNT_63_32 \ 960 0x31075 /* 0xc41d4 */ 961 #define FBNIC_PUL_USER_OB_CPL_TLP_CNT_31_0 \ 962 0x31076 /* 0xc41d8 */ 963 #define FBNIC_PUL_USER_OB_CPL_TLP_CNT_63_32 \ 964 0x31077 /* 0xc41dc */ 965 #define FBNIC_PUL_USER_OB_CPL_DWORD_CNT_31_0 \ 966 0x31078 /* 0xc41e0 */ 967 #define FBNIC_PUL_USER_OB_CPL_DWORD_CNT_63_32 \ 968 0x31079 /* 0xc41e4 */ 969 #define FBNIC_PUL_USER_OB_RD_DBG_CNT_CPL_CRED_31_0 \ 970 0x3107a /* 0xc41e8 */ 971 #define FBNIC_PUL_USER_OB_RD_DBG_CNT_CPL_CRED_63_32 \ 972 0x3107b /* 0xc41ec */ 973 #define FBNIC_PUL_USER_OB_RD_DBG_CNT_TAG_31_0 \ 974 0x3107c /* 0xc41f0 */ 975 #define FBNIC_PUL_USER_OB_RD_DBG_CNT_TAG_63_32 \ 976 0x3107d /* 0xc41f4 */ 977 #define FBNIC_PUL_USER_OB_RD_DBG_CNT_NP_CRED_31_0 \ 978 0x3107e /* 0xc41f8 */ 979 #define FBNIC_PUL_USER_OB_RD_DBG_CNT_NP_CRED_63_32 \ 980 0x3107f /* 0xc41fc */ 981 #define FBNIC_CSR_END_PUL_USER 0x310ea /* CSR section delimiter */ 982 983 /* Queue Registers 984 * 985 * The queue register offsets are specific for a given queue grouping. So to 986 * find the actual register offset it is necessary to combine FBNIC_QUEUE(n) 987 * with the register to get the actual register offset like so: 988 * FBNIC_QUEUE_TWQ0_CTL(n) == FBNIC_QUEUE(n) + FBNIC_QUEUE_TWQ0_CTL 989 */ 990 #define FBNIC_CSR_START_QUEUE 0x40000 /* CSR section delimiter */ 991 #define FBNIC_QUEUE_STRIDE 0x400 /* 0x1000 */ 992 #define FBNIC_QUEUE(n)\ 993 (0x40000 + FBNIC_QUEUE_STRIDE * (n)) /* 0x100000 + 4096*n */ 994 995 #define FBNIC_QUEUE_TWQ0_CTL 0x000 /* 0x000 */ 996 #define FBNIC_QUEUE_TWQ1_CTL 0x001 /* 0x004 */ 997 #define FBNIC_QUEUE_TWQ_CTL_RESET CSR_BIT(0) 998 #define FBNIC_QUEUE_TWQ_CTL_ENABLE CSR_BIT(1) 999 #define FBNIC_QUEUE_TWQ0_TAIL 0x002 /* 0x008 */ 1000 #define FBNIC_QUEUE_TWQ1_TAIL 0x003 /* 0x00c */ 1001 1002 #define FBNIC_QUEUE_TWQ0_SIZE 0x00a /* 0x028 */ 1003 #define FBNIC_QUEUE_TWQ1_SIZE 0x00b /* 0x02c */ 1004 #define FBNIC_QUEUE_TWQ_SIZE_MASK CSR_GENMASK(3, 0) 1005 1006 #define FBNIC_QUEUE_TWQ0_BAL 0x020 /* 0x080 */ 1007 #define FBNIC_QUEUE_BAL_MASK CSR_GENMASK(31, 7) 1008 #define FBNIC_QUEUE_TWQ0_BAH 0x021 /* 0x084 */ 1009 #define FBNIC_QUEUE_TWQ1_BAL 0x022 /* 0x088 */ 1010 #define FBNIC_QUEUE_TWQ1_BAH 0x023 /* 0x08c */ 1011 1012 /* Tx Work Queue Statistics Registers */ 1013 #define FBNIC_QUEUE_TWQ0_PKT_CNT 0x062 /* 0x188 */ 1014 #define FBNIC_QUEUE_TWQ0_ERR_CNT 0x063 /* 0x18c */ 1015 #define FBNIC_QUEUE_TWQ1_PKT_CNT 0x072 /* 0x1c8 */ 1016 #define FBNIC_QUEUE_TWQ1_ERR_CNT 0x073 /* 0x1cc */ 1017 1018 /* Tx Completion Queue Registers */ 1019 #define FBNIC_QUEUE_TCQ_CTL 0x080 /* 0x200 */ 1020 #define FBNIC_QUEUE_TCQ_CTL_RESET CSR_BIT(0) 1021 #define FBNIC_QUEUE_TCQ_CTL_ENABLE CSR_BIT(1) 1022 1023 #define FBNIC_QUEUE_TCQ_HEAD 0x081 /* 0x204 */ 1024 1025 #define FBNIC_QUEUE_TCQ_SIZE 0x084 /* 0x210 */ 1026 #define FBNIC_QUEUE_TCQ_SIZE_MASK CSR_GENMASK(3, 0) 1027 1028 #define FBNIC_QUEUE_TCQ_BAL 0x0a0 /* 0x280 */ 1029 #define FBNIC_QUEUE_TCQ_BAH 0x0a1 /* 0x284 */ 1030 1031 /* Tx Interrupt Manager Registers */ 1032 #define FBNIC_QUEUE_TIM_CTL 0x0c0 /* 0x300 */ 1033 #define FBNIC_QUEUE_TIM_CTL_MSIX_MASK CSR_GENMASK(7, 0) 1034 1035 #define FBNIC_QUEUE_TIM_THRESHOLD 0x0c1 /* 0x304 */ 1036 #define FBNIC_QUEUE_TIM_THRESHOLD_TWD_MASK CSR_GENMASK(14, 0) 1037 1038 #define FBNIC_QUEUE_TIM_CLEAR 0x0c2 /* 0x308 */ 1039 #define FBNIC_QUEUE_TIM_CLEAR_MASK CSR_BIT(0) 1040 #define FBNIC_QUEUE_TIM_SET 0x0c3 /* 0x30c */ 1041 #define FBNIC_QUEUE_TIM_SET_MASK CSR_BIT(0) 1042 #define FBNIC_QUEUE_TIM_MASK 0x0c4 /* 0x310 */ 1043 #define FBNIC_QUEUE_TIM_MASK_MASK CSR_BIT(0) 1044 1045 #define FBNIC_QUEUE_TIM_TIMER 0x0c5 /* 0x314 */ 1046 1047 #define FBNIC_QUEUE_TIM_COUNTS 0x0c6 /* 0x318 */ 1048 #define FBNIC_QUEUE_TIM_COUNTS_CNT1_MASK CSR_GENMASK(30, 16) 1049 #define FBNIC_QUEUE_TIM_COUNTS_CNT0_MASK CSR_GENMASK(14, 0) 1050 1051 /* Rx Completion Queue Registers */ 1052 #define FBNIC_QUEUE_RCQ_CTL 0x200 /* 0x800 */ 1053 #define FBNIC_QUEUE_RCQ_CTL_RESET CSR_BIT(0) 1054 #define FBNIC_QUEUE_RCQ_CTL_ENABLE CSR_BIT(1) 1055 1056 #define FBNIC_QUEUE_RCQ_HEAD 0x201 /* 0x804 */ 1057 1058 #define FBNIC_QUEUE_RCQ_SIZE 0x204 /* 0x810 */ 1059 #define FBNIC_QUEUE_RCQ_SIZE_MASK CSR_GENMASK(3, 0) 1060 1061 #define FBNIC_QUEUE_RCQ_BAL 0x220 /* 0x880 */ 1062 #define FBNIC_QUEUE_RCQ_BAH 0x221 /* 0x884 */ 1063 1064 /* Rx Buffer Descriptor Queue Registers */ 1065 #define FBNIC_QUEUE_BDQ_CTL 0x240 /* 0x900 */ 1066 #define FBNIC_QUEUE_BDQ_CTL_RESET CSR_BIT(0) 1067 #define FBNIC_QUEUE_BDQ_CTL_ENABLE CSR_BIT(1) 1068 #define FBNIC_QUEUE_BDQ_CTL_PPQ_ENABLE CSR_BIT(30) 1069 1070 #define FBNIC_QUEUE_BDQ_HPQ_TAIL 0x241 /* 0x904 */ 1071 #define FBNIC_QUEUE_BDQ_PPQ_TAIL 0x242 /* 0x908 */ 1072 1073 #define FBNIC_QUEUE_BDQ_HPQ_SIZE 0x247 /* 0x91c */ 1074 #define FBNIC_QUEUE_BDQ_PPQ_SIZE 0x248 /* 0x920 */ 1075 #define FBNIC_QUEUE_BDQ_SIZE_MASK CSR_GENMASK(3, 0) 1076 1077 #define FBNIC_QUEUE_BDQ_HPQ_BAL 0x260 /* 0x980 */ 1078 #define FBNIC_QUEUE_BDQ_HPQ_BAH 0x261 /* 0x984 */ 1079 #define FBNIC_QUEUE_BDQ_PPQ_BAL 0x262 /* 0x988 */ 1080 #define FBNIC_QUEUE_BDQ_PPQ_BAH 0x263 /* 0x98c */ 1081 1082 /* Rx DMA Engine Configuration */ 1083 #define FBNIC_QUEUE_RDE_CTL0 0x2a0 /* 0xa80 */ 1084 #define FBNIC_QUEUE_RDE_CTL0_EN_HDR_SPLIT CSR_BIT(31) 1085 #define FBNIC_QUEUE_RDE_CTL0_DROP_MODE_MASK CSR_GENMASK(30, 29) 1086 enum { 1087 FBNIC_QUEUE_RDE_CTL0_DROP_IMMEDIATE = 0, 1088 FBNIC_QUEUE_RDE_CTL0_DROP_WAIT = 1, 1089 FBNIC_QUEUE_RDE_CTL0_DROP_NEVER = 2, 1090 }; 1091 1092 #define FBNIC_QUEUE_RDE_CTL0_MIN_HROOM_MASK CSR_GENMASK(28, 20) 1093 #define FBNIC_QUEUE_RDE_CTL0_MIN_TROOM_MASK CSR_GENMASK(19, 11) 1094 1095 #define FBNIC_QUEUE_RDE_CTL1 0x2a1 /* 0xa84 */ 1096 #define FBNIC_QUEUE_RDE_CTL1_MAX_HDR_MASK CSR_GENMASK(24, 12) 1097 #define FBNIC_QUEUE_RDE_CTL1_PAYLD_OFF_MASK CSR_GENMASK(11, 9) 1098 #define FBNIC_QUEUE_RDE_CTL1_PAYLD_PG_CL_MASK CSR_GENMASK(8, 6) 1099 #define FBNIC_QUEUE_RDE_CTL1_PADLEN_MASK CSR_GENMASK(5, 2) 1100 #define FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_MASK CSR_GENMASK(1, 0) 1101 enum { 1102 FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_NONE = 0, 1103 FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_ALL = 1, 1104 FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_RSS = 2, 1105 }; 1106 1107 /* Rx Per CQ Statistics Counters */ 1108 #define FBNIC_QUEUE_RDE_PKT_CNT 0x2a2 /* 0xa88 */ 1109 #define FBNIC_QUEUE_RDE_PKT_ERR_CNT 0x2a3 /* 0xa8c */ 1110 #define FBNIC_QUEUE_RDE_CQ_DROP_CNT 0x2a4 /* 0xa90 */ 1111 #define FBNIC_QUEUE_RDE_BDQ_DROP_CNT 0x2a5 /* 0xa94 */ 1112 1113 /* Rx Interrupt Manager Registers */ 1114 #define FBNIC_QUEUE_RIM_CTL 0x2c0 /* 0xb00 */ 1115 #define FBNIC_QUEUE_RIM_CTL_MSIX_MASK CSR_GENMASK(7, 0) 1116 1117 #define FBNIC_QUEUE_RIM_THRESHOLD 0x2c1 /* 0xb04 */ 1118 #define FBNIC_QUEUE_RIM_THRESHOLD_RCD_MASK CSR_GENMASK(14, 0) 1119 1120 #define FBNIC_QUEUE_RIM_CLEAR 0x2c2 /* 0xb08 */ 1121 #define FBNIC_QUEUE_RIM_CLEAR_MASK CSR_BIT(0) 1122 #define FBNIC_QUEUE_RIM_SET 0x2c3 /* 0xb0c */ 1123 #define FBNIC_QUEUE_RIM_SET_MASK CSR_BIT(0) 1124 #define FBNIC_QUEUE_RIM_MASK 0x2c4 /* 0xb10 */ 1125 #define FBNIC_QUEUE_RIM_MASK_MASK CSR_BIT(0) 1126 1127 #define FBNIC_QUEUE_RIM_COAL_STATUS 0x2c5 /* 0xb14 */ 1128 #define FBNIC_QUEUE_RIM_RCD_COUNT_MASK CSR_GENMASK(30, 16) 1129 #define FBNIC_QUEUE_RIM_TIMER_MASK CSR_GENMASK(13, 0) 1130 #define FBNIC_MAX_QUEUES 128 1131 #define FBNIC_CSR_END_QUEUE (0x40000 + 0x400 * FBNIC_MAX_QUEUES - 1) 1132 1133 /* BAR 4 CSRs */ 1134 1135 /* The IPC mailbox consists of 32 mailboxes, with each mailbox consisting 1136 * of 32 4 byte registers. We will use 2 registers per descriptor so the 1137 * length of the mailbox is reduced to 16. 1138 * 1139 * Currently we use an offset of 0x6000 on BAR4 for the mailbox so we just 1140 * have to do the math and determine the offset based on the mailbox 1141 * direction and index inside that mailbox. 1142 */ 1143 #define FBNIC_IPC_MBX_DESC_LEN 16 1144 #define FBNIC_IPC_MBX(mbx_idx, desc_idx) \ 1145 ((((mbx_idx) * FBNIC_IPC_MBX_DESC_LEN + (desc_idx)) * 2) + 0x6000) 1146 1147 /* Use first register in mailbox to flush writes */ 1148 #define FBNIC_FW_ZERO_REG FBNIC_IPC_MBX(0, 0) 1149 1150 enum { 1151 FBNIC_IPC_MBX_RX_IDX, 1152 FBNIC_IPC_MBX_TX_IDX, 1153 FBNIC_IPC_MBX_INDICES, 1154 }; 1155 1156 #define FBNIC_IPC_MBX_DESC_LEN_MASK DESC_GENMASK(63, 48) 1157 #define FBNIC_IPC_MBX_DESC_EOM DESC_BIT(46) 1158 #define FBNIC_IPC_MBX_DESC_ADDR_MASK DESC_GENMASK(45, 3) 1159 #define FBNIC_IPC_MBX_DESC_FW_CMPL DESC_BIT(1) 1160 #define FBNIC_IPC_MBX_DESC_HOST_CMPL DESC_BIT(0) 1161 1162 #endif /* _FBNIC_CSR_H_ */ 1163