xref: /linux/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c (revision 7dc340540363a008cee1e160e8f2a4f034f196d4)
1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include "amdgpu.h"
30 #include "amdgpu_gfx.h"
31 #include "amdgpu_psp.h"
32 #include "nv.h"
33 #include "nvd.h"
34 
35 #include "gc/gc_10_1_0_offset.h"
36 #include "gc/gc_10_1_0_sh_mask.h"
37 #include "smuio/smuio_11_0_0_offset.h"
38 #include "smuio/smuio_11_0_0_sh_mask.h"
39 #include "navi10_enum.h"
40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
41 
42 #include "soc15.h"
43 #include "soc15_common.h"
44 #include "clearstate_gfx10.h"
45 #include "v10_structs.h"
46 #include "gfx_v10_0.h"
47 #include "gfx_v10_0_cleaner_shader.h"
48 #include "nbio_v2_3.h"
49 
50 /*
51  * Navi10 has two graphic rings to share each graphic pipe.
52  * 1. Primary ring
53  * 2. Async ring
54  */
55 #define GFX10_NUM_GFX_RINGS_NV1X	1
56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid	2
57 #define GFX10_MEC_HPD_SIZE	2048
58 
59 #define F32_CE_PROGRAM_RAM_SIZE		65536
60 #define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L
61 
62 #define mmCGTT_GS_NGG_CLK_CTRL	0x5087
63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX	1
64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
68 
69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
71 
72 #define mmCGTS_TCC_DISABLE_gc_10_3                 0x5006
73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX        1
74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3            0x5007
75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX   1
76 
77 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
79 #define mmRLC_SAFE_MODE_Sienna_Cichlid			0x4ca0
80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX		1
81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid		0x4ca1
82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX	1
83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid			0x11ec
84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX		0
85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid		0x0fc1
86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX	0
87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid		0x0fc2
88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX	0
89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid			0x0fc3
90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX	0
91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid		0x0fc4
92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX	0
93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid		0x0fc5
94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX	0
95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid		0x0fc6
96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX	0
97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT	0x1a
98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK	0x04000000L
99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK	0x00000FFCL
100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT	0x2
101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK	0x00000FFCL
102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid			0x1580
103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX	0
104 
105 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish                0x0105
106 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX       1
107 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish                0x0106
108 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX       1
109 
110 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
111 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
112 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
113 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
114 
115 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6                0x002d
116 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX       1
117 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6                0x002e
118 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX       1
119 
120 #define mmSPI_CONFIG_CNTL_1_Vangogh		 0x2441
121 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX	 1
122 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
123 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
124 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
125 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
126 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
127 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
128 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
129 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
130 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
131 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
132 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
133 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
134 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
135 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
136 #define mmGCR_GENERAL_CNTL_Vangogh               0x1580
137 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
138 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh   0x0000FFFFL
139 
140 #define mmCP_HYP_PFP_UCODE_ADDR			0x5814
141 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX	1
142 #define mmCP_HYP_PFP_UCODE_DATA			0x5815
143 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX	1
144 #define mmCP_HYP_CE_UCODE_ADDR			0x5818
145 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX		1
146 #define mmCP_HYP_CE_UCODE_DATA			0x5819
147 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX		1
148 #define mmCP_HYP_ME_UCODE_ADDR			0x5816
149 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX		1
150 #define mmCP_HYP_ME_UCODE_DATA			0x5817
151 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX		1
152 
153 #define mmCPG_PSP_DEBUG				0x5c10
154 #define mmCPG_PSP_DEBUG_BASE_IDX		1
155 #define mmCPC_PSP_DEBUG				0x5c11
156 #define mmCPC_PSP_DEBUG_BASE_IDX		1
157 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK	0x00000008L
158 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK	0x00000008L
159 
160 //CC_GC_SA_UNIT_DISABLE
161 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
162 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
163 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT	0x8
164 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK		0x0000FF00L
165 //GC_USER_SA_UNIT_DISABLE
166 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
167 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
168 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT	0x8
169 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK	0x0000FF00L
170 //PA_SC_ENHANCE_3
171 #define mmPA_SC_ENHANCE_3                       0x1085
172 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
173 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
174 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
175 
176 #define mmCGTT_SPI_CS_CLK_CTRL			0x507c
177 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
178 
179 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid		0x16f3
180 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX	0
181 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
182 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX	0
183 
184 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
185 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
186 
187 #define mmRLC_SPARE_INT_0_Sienna_Cichlid               0x4ca5
188 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX      1
189 
190 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
191 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
192 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
193 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
194 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
195 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
196 
197 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
198 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
199 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
200 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
201 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
202 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
203 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
204 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
205 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
206 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
207 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
208 
209 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
210 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
211 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
212 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
213 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
214 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
215 
216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
217 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
218 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
219 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
220 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
221 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
222 
223 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
224 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
225 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
226 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
227 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
228 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
229 
230 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
231 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
232 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
233 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
234 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
235 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
236 
237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
238 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
239 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
240 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
241 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
242 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
243 
244 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
245 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
246 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
247 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
248 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
249 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
250 
251 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
252 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
253 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
254 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
255 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
256 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
257 
258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin");
259 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin");
260 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin");
261 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
262 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
263 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
264 
265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");
266 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");
267 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");
268 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");
269 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");
270 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");
271 
272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
273 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
274 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
275 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
276 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
277 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
278 
279 static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {
280 	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
281 	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
282 	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),
283 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
284 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
285 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
286 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
287 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
288 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),
289 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),
290 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2),
291 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2),
292 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),
293 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),
294 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0),
295 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
296 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
297 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
298 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
299 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
300 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
301 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
302 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),
303 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),
304 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),
305 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
306 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
307 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),
308 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),
309 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),
310 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),
311 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),
312 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),
313 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),
314 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),
315 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),
316 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),
317 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),
318 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),
319 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),
320 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),
321 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),
322 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),
323 	SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),
324 	SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),
325 	SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),
326 	SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),
327 	SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),
328 	SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),
329 	SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2),
330 	SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),
331 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),
332 	SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),
333 	SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS),
334 	SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS),
335 	SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS),
336 	SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS),
337 	SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),
338 	SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL),
339 	SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS),
340 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),
341 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),
342 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL),
343 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),
344 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),
345 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),
346 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
347 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR),
348 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),
349 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),
350 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),
351 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),
352 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),
353 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),
354 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),
355 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),
356 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3),
357 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4),
358 	SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),
359 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),
360 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
361 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2),
362 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS),
363 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS),
364 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
365 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
366 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A),
367 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B),
368 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR),
369 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST),
370 	/* cp header registers */
371 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
372 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
373 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP),
374 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
375 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
376 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP),
377 	/* SE status registers */
378 	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),
379 	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),
380 	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),
381 	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
382 };
383 
384 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_10[] = {
385 	/* compute registers */
386 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID),
387 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE),
388 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY),
389 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY),
390 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM),
391 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE),
392 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI),
393 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR),
394 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
395 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
396 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
397 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL),
398 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR),
399 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI),
400 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR),
401 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL),
402 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST),
403 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR),
404 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI),
405 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL),
406 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR),
407 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR),
408 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS),
409 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO),
410 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI),
411 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL),
412 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET),
413 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE),
414 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET),
415 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE),
416 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE),
417 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR),
418 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM),
419 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
420 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
421 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
422 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
423 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET),
424 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS)
425 };
426 
427 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = {
428 	/* gfx queue registers */
429 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_ACTIVE),
430 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY),
431 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE),
432 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE_HI),
433 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_OFFSET),
434 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CSMD_RPTR),
435 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR),
436 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR_HI),
437 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_DEQUEUE_REQUEST),
438 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_MAPPED),
439 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUE_MGR_CONTROL),
440 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0),
441 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_STATUS0),
442 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO),
443 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI),
444 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_OFFSET),
445 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_CSMD_RPTR),
446 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR),
447 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_HI),
448 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR),
449 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI),
450 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO),
451 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI)
452 };
453 
454 static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
455 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
465 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
466 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
467 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
468 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
469 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
470 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
471 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
472 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
473 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
474 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
475 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
476 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
477 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
478 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
479 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
480 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
481 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
482 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
483 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
484 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
485 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
486 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
487 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
488 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
489 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
490 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
491 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
492 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
493 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
494 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
495 };
496 
497 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = {
498 	/* Pending on emulation bring up */
499 };
500 
501 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = {
502 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
503 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
504 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
505 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
506 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
507 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
508 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
509 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
510 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
511 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
512 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
513 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
514 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
515 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
516 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
517 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
518 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
519 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
520 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
541 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
542 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
543 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
544 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
550 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
551 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
552 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
554 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
555 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
556 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
563 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
564 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
565 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
566 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
578 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
579 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
580 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
581 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
587 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
588 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
589 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
595 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
596 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
597 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
606 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
607 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
608 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
609 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
612 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
613 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
614 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
617 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
618 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
619 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
620 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
637 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
638 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
639 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
640 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
641 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
642 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
643 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
644 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
645 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
646 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
647 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
648 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
649 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
650 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
651 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
652 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
653 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
654 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
655 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
656 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
657 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
658 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
659 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
660 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
661 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
662 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
663 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
664 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
665 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
666 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
667 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
668 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
669 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
670 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
671 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
672 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
673 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
674 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
675 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
676 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
677 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
678 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
679 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
680 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
681 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
682 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
683 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
684 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
685 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
686 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
687 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
688 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
689 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
690 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
691 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
692 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
693 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
694 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
695 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
696 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
697 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
698 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
699 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
700 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
701 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
702 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
703 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
704 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
705 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
706 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
707 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
708 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
709 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
710 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
711 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
712 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
713 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
714 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
715 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
716 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
717 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
718 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
719 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
720 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
721 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
722 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
723 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
724 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
725 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
726 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
727 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
728 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
729 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
730 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
731 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
732 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
733 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
734 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
735 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
736 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
737 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
738 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
739 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
740 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
741 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
742 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
743 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
744 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
745 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
746 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
747 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
748 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
749 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
750 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
751 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
752 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
753 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
754 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
755 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
756 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
757 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
758 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
759 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
760 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
761 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
762 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
763 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
764 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
765 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
766 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
767 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
768 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
769 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
770 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
771 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
772 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
773 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
774 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
775 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
776 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
777 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
778 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
779 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
780 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
781 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
782 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
783 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
784 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
785 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
786 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
787 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
788 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
789 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
790 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
791 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
792 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
793 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
794 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
795 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
796 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
797 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
798 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
799 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
800 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
801 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
802 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
803 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
804 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
805 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
806 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
807 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
808 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
809 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
810 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
811 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
812 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
813 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
814 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
815 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
816 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
817 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
818 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
819 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
820 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
821 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
822 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
823 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
824 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
825 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
826 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
827 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
828 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
829 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
830 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
831 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
832 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
833 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
834 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
835 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
836 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
837 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
838 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
839 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
840 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
841 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
842 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
843 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
844 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
845 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
846 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
847 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
848 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
849 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
850 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
851 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
852 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
853 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
854 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
855 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
856 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
857 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
858 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
859 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
860 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
861 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
862 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
863 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
864 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
865 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
866 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
867 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
868 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
869 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
870 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
871 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
872 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
873 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
874 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
875 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
876 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
877 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
878 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
879 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
880 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
881 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
882 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
883 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
884 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
885 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
886 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
887 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
888 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
889 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
890 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
891 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
892 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
893 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
894 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
895 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
896 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
897 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
898 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
899 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
900 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
901 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
902 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
903 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
904 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
905 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
906 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
907 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
908 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
909 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
910 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
911 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
912 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
913 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
914 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
915 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
916 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
917 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
918 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
919 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
920 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
921 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
922 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
923 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
924 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
925 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
926 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
927 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
928 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
929 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
930 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
931 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
932 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
933 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
934 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
935 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
936 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
937 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
938 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
939 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
940 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
941 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
942 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
943 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
944 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
945 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
946 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
947 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
948 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
949 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
950 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
951 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
952 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
953 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
954 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
955 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
956 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
957 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
958 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
959 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
960 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
961 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
962 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
963 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
964 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
965 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
966 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
967 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
968 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
969 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
970 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
971 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
972 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
973 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
974 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
975 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
976 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
977 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
978 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
979 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
980 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
981 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
982 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
983 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
984 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
985 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
986 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
987 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
988 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
989 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
990 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
991 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
992 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
993 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
994 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
995 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
996 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
997 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
998 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
999 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1000 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1001 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1002 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1003 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1004 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1005 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1006 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1007 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1008 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1009 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1010 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1011 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1012 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1013 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1014 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1015 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1016 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1017 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1018 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1019 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1020 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1021 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1022 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1023 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1024 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1025 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1026 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1027 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1028 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1029 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1030 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1031 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1032 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1033 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1034 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1035 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1036 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1037 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1038 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1039 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1040 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1041 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1042 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1043 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1044 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1045 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1046 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1047 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1048 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1049 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1050 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1051 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1052 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1053 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1054 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1055 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1056 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1057 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1058 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1059 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1060 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1061 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1062 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1063 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1064 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1065 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1066 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1067 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1068 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1069 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1070 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1071 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1072 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1073 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1074 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1075 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1076 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1077 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1078 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1079 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1080 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1081 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1082 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1083 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1084 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1085 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1086 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1087 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1088 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1089 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1090 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1091 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1092 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1093 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1094 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1095 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1096 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1097 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1098 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1099 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1100 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1101 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1102 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1103 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1104 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1105 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1106 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1107 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1108 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1109 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1110 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1111 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1112 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1113 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1114 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1115 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1116 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1117 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1118 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1119 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1120 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1121 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1122 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1123 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1124 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1125 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1126 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1127 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1128 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1129 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1130 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1131 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1132 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1133 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1134 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1135 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1136 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1137 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1138 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1139 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1140 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1141 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1142 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1143 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1144 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1145 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1146 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1147 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1148 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1149 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1150 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1151 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1152 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1153 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1154 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1155 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1156 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1157 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1158 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1159 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1160 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
1161 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1162 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1163 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1164 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
1165 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1166 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1167 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1168 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1169 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1170 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1171 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1172 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1173 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1174 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1175 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1176 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1177 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1178 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1179 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1180 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1181 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1182 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1183 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1184 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1188 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1189 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1190 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1191 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1192 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1193 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1194 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1195 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1196 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1197 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1198 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1199 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1200 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1201 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1202 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1203 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1204 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1205 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1206 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1207 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1208 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1209 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1210 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1211 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1212 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1213 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1214 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1215 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1216 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1217 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1218 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1219 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1220 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1221 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1222 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1223 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1224 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1225 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1226 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1227 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1228 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1229 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1230 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1231 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1232 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1233 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1234 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1235 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1236 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1237 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1238 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1239 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1240 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1241 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1242 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1243 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1244 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1245 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1246 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1247 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1248 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1249 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1250 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1251 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1252 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1253 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1254 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1255 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1256 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1257 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1258 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1259 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1260 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1261 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1262 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1263 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1264 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1265 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1266 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1267 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1268 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1269 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1270 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1271 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1272 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1273 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1274 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1275 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1276 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1277 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1278 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1279 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1280 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1281 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1282 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1283 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1284 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1285 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1286 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1287 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1288 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1289 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1290 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1291 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1292 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1293 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1294 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1295 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1296 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1297 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1298 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1299 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1300 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1301 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1302 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1303 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1304 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1305 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1306 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1307 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1308 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1309 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1310 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1311 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1312 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1313 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1314 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1315 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1316 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1317 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1318 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1319 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1320 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1321 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1322 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1323 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1324 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1325 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1326 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1327 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1328 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1329 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1330 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1331 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1332 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1333 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1334 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1335 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1336 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1337 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1338 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1339 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1340 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1341 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1342 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1343 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1344 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1345 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1346 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1347 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1348 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1349 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1350 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1351 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1352 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1353 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1354 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1355 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1356 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1357 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1358 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1359 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1360 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1361 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1362 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1363 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1364 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1365 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1366 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1367 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1368 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1369 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1370 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1371 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1372 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1373 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1374 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1375 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1376 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1377 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1378 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1379 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1380 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1381 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1382 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1383 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1384 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1385 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1386 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1387 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1388 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1389 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1390 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1391 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1392 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1393 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1394 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1395 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1396 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1397 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1398 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1399 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1400 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1401 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1402 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1403 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1404 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1405 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1406 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1407 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1408 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1409 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1410 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1411 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1412 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1413 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1414 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1415 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1416 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1417 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1418 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1419 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1420 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1421 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1422 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1423 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1424 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1425 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1426 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1427 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1428 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1429 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1430 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1431 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1432 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1433 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1434 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1435 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1436 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1437 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1438 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1439 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1440 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1441 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1442 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1443 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1444 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1445 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1446 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1447 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1448 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1449 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1450 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1451 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1452 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1453 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1454 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1455 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1465 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1466 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1467 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1468 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1469 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1470 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1471 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1472 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1473 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1474 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1475 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1476 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1477 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1478 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1479 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1481 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1483 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1484 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1485 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1486 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1487 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1489 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1491 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1492 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1493 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1494 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1495 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1497 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1499 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1500 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1501 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1502 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1503 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1505 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1507 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1508 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1509 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1510 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1511 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1513 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1515 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1517 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1519 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1541 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1543 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1550 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1551 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1554 };
1555 
1556 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = {
1557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1563 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1564 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1565 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1566 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1578 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1579 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1580 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1581 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1587 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1588 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1589 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1595 };
1596 
1597 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = {
1598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1606 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1607 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1608 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1609 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1612 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1613 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1614 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1617 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1618 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1619 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1620 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1637 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1638 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1639 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1640 };
1641 
1642 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = {
1643 	/* Pending on emulation bring up */
1644 };
1645 
1646 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = {
1647 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1648 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1649 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1650 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1651 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1652 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1653 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1654 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1655 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1656 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1657 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1658 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1659 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1660 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1661 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1662 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1663 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1664 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1665 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1666 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1667 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1668 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1669 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1670 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1671 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1672 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1673 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1674 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1675 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1676 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1677 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1678 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1679 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1680 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1681 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1682 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1683 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1684 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1685 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1686 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1687 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1688 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1689 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1690 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1691 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1692 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1693 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1694 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1695 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1696 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1697 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1698 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1699 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1700 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1701 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1702 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1703 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1704 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1705 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1706 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1707 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1708 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1709 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1710 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1711 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1712 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1713 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1714 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1715 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1716 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1717 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1718 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1719 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1720 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1721 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1722 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1723 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1724 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1725 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1726 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1727 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1728 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1729 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1730 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1731 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1732 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1733 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1734 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1735 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1736 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1737 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1738 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1739 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1740 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1741 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1742 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1743 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1744 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1745 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1746 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1747 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1748 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1749 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1750 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1751 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1752 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1753 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1754 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1755 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1756 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1757 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1758 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1759 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1760 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1761 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1762 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1763 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1764 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1765 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1766 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1767 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1768 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1769 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1770 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1771 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1772 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1773 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1774 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1775 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1776 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1777 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1778 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1779 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1780 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1781 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1782 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1783 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1784 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1785 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1786 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1787 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1788 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1789 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1790 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1791 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1792 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1793 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1794 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1795 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1796 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1797 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1798 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1799 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1800 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1801 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1802 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1803 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1804 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1805 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1806 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1807 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1808 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1809 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1810 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1811 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1812 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1813 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1814 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1815 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1816 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1817 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1818 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1819 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1820 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1821 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1822 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1823 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1824 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1825 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1826 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1827 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1828 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1829 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1830 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1831 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1832 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1833 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1834 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1835 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1836 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1837 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1838 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1839 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1840 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1841 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1842 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1843 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1844 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1845 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1846 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1847 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1848 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1849 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1850 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1851 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1852 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1853 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1854 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1855 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1856 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1857 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1858 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1859 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1860 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1861 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1862 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1863 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1864 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1865 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1866 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1867 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1868 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1869 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1870 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1871 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1872 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1873 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1874 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1875 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1876 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1877 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1878 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1879 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1880 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1881 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1882 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1883 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1884 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1885 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1886 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1887 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1888 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1889 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1890 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1891 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1892 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1893 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1894 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1895 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1896 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1897 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1898 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1899 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1900 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1901 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1902 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1903 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1904 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1905 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1906 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1907 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1908 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1909 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1910 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1911 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1912 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1913 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1914 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1915 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1916 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1917 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1918 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1919 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1920 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1921 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1922 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1923 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1924 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1925 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1926 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1927 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1928 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1929 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1930 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1931 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1932 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1933 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1934 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1935 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1936 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1937 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1938 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1939 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1940 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1941 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1942 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1943 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1944 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1945 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1946 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1947 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1948 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1949 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1950 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1951 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1952 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1953 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1954 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1955 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1956 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1957 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1958 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1959 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1960 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1961 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1962 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1963 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1964 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1965 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1966 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1967 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1968 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1969 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1970 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1971 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1972 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1973 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1974 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1975 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1976 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1977 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1978 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1979 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1980 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1981 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1982 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1983 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1984 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1985 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1986 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1987 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1988 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1989 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1990 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1991 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1992 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1993 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1994 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1995 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1996 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1997 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1998 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1999 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2000 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2001 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2002 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2003 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2004 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2005 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2006 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2007 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2008 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2009 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
2010 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2011 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2012 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2013 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2014 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2015 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2016 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2017 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2018 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2019 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2020 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2021 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2022 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2023 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2024 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2025 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2026 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2027 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2028 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2029 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2030 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2031 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2032 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2033 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2034 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2035 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2036 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2037 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2038 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2039 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2040 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2041 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2042 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2043 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2044 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2045 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2046 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2047 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2048 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2049 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2050 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2051 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2052 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2053 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2054 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2055 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2056 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2057 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2058 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2059 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2060 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2061 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2062 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2063 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2064 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2065 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2066 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2067 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2068 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2069 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2070 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2071 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2072 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2073 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2074 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2075 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2076 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2077 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2078 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2079 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2080 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2081 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2082 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2083 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2084 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2085 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2086 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2087 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2088 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2089 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2090 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2091 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2092 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2093 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2094 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2095 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2096 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2097 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2098 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2099 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2100 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2101 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2102 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2103 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2104 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2106 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2108 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2109 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2110 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2112 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2113 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2114 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2115 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2116 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2118 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2120 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2122 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2124 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2126 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2128 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2130 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2132 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2134 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2136 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2138 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2140 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2142 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2144 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2146 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2148 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2150 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2152 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2154 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2156 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2158 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2160 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2161 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2162 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2163 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2164 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2166 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2168 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
2170 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2172 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2174 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2176 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2178 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2180 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2182 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2184 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2188 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2190 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2192 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2194 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2196 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2198 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2200 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2202 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2204 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2206 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2208 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2210 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2212 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2214 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2216 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2218 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2220 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2222 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2224 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2226 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2228 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2230 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2232 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2234 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2236 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2238 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2240 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2242 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2244 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2246 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2248 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2250 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2252 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2254 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2256 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2258 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2259 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2260 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2262 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2263 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2264 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2265 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2266 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2267 };
2268 
2269 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = {
2270 	/* Pending on emulation bring up */
2271 };
2272 
2273 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = {
2274 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2275 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2276 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2277 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2278 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2279 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2280 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2281 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2282 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2283 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2284 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2285 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2286 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2287 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2288 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2289 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2290 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2291 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2292 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2293 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2294 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2295 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2296 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2297 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2298 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2299 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2300 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2301 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2302 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2303 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2304 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2305 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2306 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2307 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2308 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2309 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2310 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2311 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2312 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2313 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2314 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2315 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2316 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2317 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2318 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2319 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2320 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2321 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2322 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2323 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2324 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2325 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2326 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2327 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2328 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2329 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2330 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2331 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2332 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2333 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2334 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2335 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2336 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2337 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2338 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2339 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2340 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2341 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2342 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2343 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2344 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2345 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2346 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2347 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2348 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2349 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2350 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2351 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2352 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2353 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2354 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2355 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2356 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2357 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2358 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2359 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2360 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2361 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2362 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2363 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2364 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2365 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2366 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2367 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2368 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2369 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2370 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2371 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2372 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2373 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2374 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2375 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2376 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2377 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2378 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2379 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2380 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2381 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2382 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2383 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2384 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2385 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2386 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2387 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2388 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2389 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2390 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2391 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2392 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2393 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2394 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2395 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2396 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2397 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2398 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2399 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2400 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2401 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2402 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2403 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2404 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2405 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2406 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2407 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2408 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2409 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2410 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2411 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2412 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2413 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2414 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2415 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2416 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2417 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2418 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2419 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2420 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2421 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2422 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2423 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2424 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2425 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2426 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2427 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2428 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2429 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2430 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2431 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2432 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2433 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2434 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2435 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2436 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2437 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2438 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2439 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2440 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2441 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2442 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2443 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2444 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2445 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2446 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2447 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2448 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2449 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2450 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2451 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2452 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2453 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2454 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2455 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2465 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2466 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2467 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2468 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2469 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2470 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2471 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2472 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2473 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2474 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2475 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2476 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2477 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2478 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2479 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2480 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2481 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2482 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2483 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2484 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2485 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2486 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2487 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2488 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2489 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2490 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2491 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2492 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2493 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2494 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2495 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2496 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2497 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2498 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2499 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2500 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2501 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2502 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2503 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2504 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2505 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2506 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2507 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2508 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2509 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2510 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2511 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2512 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2513 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2514 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2515 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2516 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2517 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2518 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2519 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2520 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2541 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2542 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2543 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2544 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2550 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2551 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2552 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2554 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2555 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2556 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2563 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2564 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2565 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2566 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2578 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2579 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2580 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2581 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2587 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2588 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2589 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2595 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2596 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2597 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2606 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2607 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2608 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2609 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2612 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2613 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2614 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2617 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2618 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2619 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2620 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2637 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2638 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2639 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2640 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2641 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2642 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2643 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2644 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2645 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2646 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2647 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2648 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2649 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2650 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2651 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2652 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2653 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2654 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2655 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2656 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2657 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2658 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2659 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2660 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2661 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2662 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2663 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2664 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2665 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2666 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2667 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2668 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2669 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2670 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2671 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2672 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2673 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2674 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2675 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2676 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2677 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2678 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2679 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2680 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2681 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2682 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2683 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2684 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2685 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2686 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2687 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2688 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2689 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2690 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2691 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2692 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2693 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2694 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2695 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2696 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2697 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2698 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2699 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2700 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2701 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2702 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2703 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2704 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2705 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2706 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2707 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2708 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2709 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2710 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2711 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2712 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2713 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2714 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2715 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2716 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2717 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2718 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2719 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2720 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2721 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2722 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2723 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2724 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2725 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2726 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2727 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2728 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2729 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2730 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2731 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2732 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2733 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2734 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2735 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2736 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2737 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2738 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2739 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2740 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2741 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2742 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2743 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2744 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2745 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2746 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2747 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2748 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2749 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2750 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2751 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2752 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2753 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2754 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2755 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2756 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2757 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2758 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2759 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2760 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2761 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2762 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2763 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2764 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2765 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2766 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2767 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2768 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2769 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2770 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2771 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2772 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2773 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2774 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2775 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2776 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2777 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2778 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2779 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2780 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2781 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2782 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2783 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2784 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2785 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2786 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2787 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2788 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2789 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2790 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2791 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2792 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2793 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2794 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2795 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2796 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2797 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2798 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2799 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2800 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2801 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2802 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2803 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2804 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2805 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2806 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2807 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2808 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2809 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2810 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2811 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2812 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2813 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2814 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2815 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2816 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2817 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2818 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2819 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2820 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2821 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2822 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2823 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2824 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2825 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2826 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2827 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2828 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2829 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2830 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2831 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2832 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2833 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2834 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2835 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2836 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2837 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2838 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2839 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2840 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2841 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2842 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2843 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2844 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2845 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2846 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2847 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2848 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2849 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2850 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2851 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2852 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2853 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2854 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2855 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2856 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2857 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2858 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2859 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2860 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2861 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2862 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2863 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2864 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2865 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2866 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2867 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2868 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2869 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2870 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2871 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2872 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2873 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2874 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2875 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2876 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2877 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2878 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2879 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2880 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2881 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2882 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2883 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2884 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2885 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2886 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2887 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2888 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2889 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2890 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2891 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2892 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2893 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2894 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2895 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2896 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2897 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2898 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2899 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2900 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2901 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2902 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2903 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2904 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2905 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2906 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2907 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2908 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2909 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2910 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2911 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2912 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2913 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2914 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2915 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2916 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2917 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2918 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2919 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2920 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2921 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2922 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2923 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2924 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2925 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2926 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2927 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2928 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2929 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2930 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2931 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2932 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2933 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2934 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2935 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2936 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2937 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2938 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2939 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2940 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2941 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2942 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2943 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2944 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2945 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2946 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2947 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2948 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2949 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2950 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2951 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2952 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2953 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2954 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2955 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2956 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2957 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2958 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2959 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2960 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2961 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2962 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2963 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2964 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2965 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2966 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2967 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2968 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2969 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2970 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2971 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2972 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2973 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2974 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2975 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2976 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2977 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2978 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2979 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2980 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2981 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2982 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2983 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2984 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2985 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2986 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2987 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2988 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2989 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2990 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2991 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2992 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2993 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2994 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2995 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2996 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2997 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2998 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2999 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3000 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
3001 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3002 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3003 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3004 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
3005 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3006 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
3007 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3008 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
3009 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3010 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
3011 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3012 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
3013 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3014 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
3015 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3016 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
3017 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3018 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
3019 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3020 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
3021 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3022 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3023 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3024 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
3025 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3026 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3027 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3028 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
3029 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3030 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3031 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3032 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
3033 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3034 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3035 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3036 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
3037 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3038 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
3039 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3040 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
3041 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3042 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
3043 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3044 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
3045 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3046 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3047 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3048 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
3049 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3050 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3051 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3052 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
3053 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3054 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3055 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3056 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
3057 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3058 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3059 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3060 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
3061 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3062 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3063 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3064 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
3065 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3066 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3067 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3068 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
3069 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3070 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3071 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3072 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
3073 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3074 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3075 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3076 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
3077 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3078 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3079 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3080 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
3081 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3082 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3083 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3084 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3085 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3086 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3087 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3088 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3089 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3090 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3091 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3092 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3093 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3094 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3095 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3096 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3097 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3098 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3099 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3100 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3101 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3102 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3103 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3104 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3105 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3106 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3107 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3108 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3109 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3110 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3111 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3112 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3113 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3114 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3115 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3116 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3117 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3118 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3119 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3120 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3121 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3122 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3123 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3124 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3125 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3126 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3127 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3128 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3129 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3130 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3131 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3132 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3133 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3134 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3135 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3136 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3137 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3138 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3139 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3140 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3141 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3142 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3143 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3144 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3145 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3146 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3147 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3148 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3149 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3150 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3151 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3152 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3153 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3154 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3155 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3156 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3157 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3158 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3159 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3160 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3161 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3162 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3163 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3164 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3165 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3166 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3167 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3168 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3169 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3170 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3171 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3172 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3173 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3174 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3175 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3176 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3177 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3178 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3179 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3180 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3181 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3182 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3183 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3184 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3188 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3189 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3190 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3191 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3192 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3193 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3194 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3195 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3196 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3197 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3198 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3199 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3200 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3201 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3202 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3203 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3204 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3205 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3206 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3207 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3208 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3209 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3210 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3211 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3212 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3213 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3214 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3215 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3216 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3217 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3218 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3219 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3220 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3221 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3222 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3223 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3224 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3225 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3226 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3227 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3228 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3229 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3230 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3231 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3232 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3233 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3234 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3235 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3236 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3237 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3238 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3239 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3240 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3241 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3242 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3243 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3244 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3245 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3246 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3247 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3248 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3249 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3250 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3251 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3252 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3253 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3254 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3255 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3256 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3257 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3258 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3259 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3260 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3261 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3262 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3263 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3264 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3265 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3266 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3267 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3268 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3269 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3270 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3271 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3272 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3273 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3274 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3275 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3276 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3277 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3278 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3279 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3280 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3281 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3282 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3283 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3284 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3285 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3286 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3287 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3288 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3289 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3290 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3291 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3292 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3293 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3294 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3295 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3296 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3297 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3298 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3299 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3300 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3301 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3302 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3303 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3304 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3305 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3306 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3307 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3308 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3309 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3310 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3311 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3312 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3313 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3314 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3315 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3316 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3317 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3318 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3319 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3320 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3321 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3322 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3323 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3324 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3325 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3326 };
3327 
3328 static const struct soc15_reg_golden golden_settings_gc_10_3[] = {
3329 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3330 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3331 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3332 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3333 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3334 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3335 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3336 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3337 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3338 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3339 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3340 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3341 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3342 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3343 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3344 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3345 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3346 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3347 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3348 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3349 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3350 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3351 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3352 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3353 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3354 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3355 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3356 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3357 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3358 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3359 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3360 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3361 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3362 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3363 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3364 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3365 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3366 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3367 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3368 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3369 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3370 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3371 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3372 };
3373 
3374 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = {
3375 	/* Pending on emulation bring up */
3376 };
3377 
3378 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = {
3379 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3380 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3381 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3382 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3383 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3384 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3385 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3386 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3387 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3388 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3389 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3390 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3391 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3392 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3393 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3394 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3395 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3396 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3397 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3398 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3399 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3400 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3401 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3402 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3403 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3404 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3405 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3406 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3407 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3408 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3409 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3410 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3411 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3412 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3413 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3414 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3415 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3416 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3417 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3418 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3419 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3420 
3421 	/* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3422 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3423 };
3424 
3425 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = {
3426 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3427 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3428 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3429 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3430 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3431 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3432 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3433 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3434 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3435 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3436 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3437 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3438 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3439 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3440 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3441 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3442 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3443 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3444 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3445 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3446 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3447 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3448 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3449 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3450 
3451 	/* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3452 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3453 };
3454 
3455 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = {
3456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
3462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3465 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3466 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3467 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3468 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3469 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3470 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3471 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3472 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3473 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3474 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3475 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3476 };
3477 
3478 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = {
3479 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3480 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3481 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3482 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3483 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3484 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3485 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3486 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3487 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3488 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3489 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3490 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3491 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3492 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3493 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3494 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3495 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3496 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3497 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3498 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3499 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3500 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3501 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3502 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3503 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3504 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3505 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3506 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3507 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3508 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3509 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3510 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3511 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3512 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3513 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3514 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3515 };
3516 
3517 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3518 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3519 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
3520 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
3521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3541 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3542 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3543 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3544 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3550 };
3551 
3552 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {
3553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000),
3554 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e),
3555 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
3556 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100),
3557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000),
3558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014),
3559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8),
3561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003),
3562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
3563 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
3564 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3565 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
3566 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210),
3567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
3568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500),
3569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff),
3570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8),
3572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130),
3573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130),
3574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
3577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f),
3578 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188),
3579 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009),
3580 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02),
3581 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000),
3582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101),
3583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
3584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
3585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),
3586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
3587 };
3588 
3589 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = {
3590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),
3592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3595 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),
3596 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3597 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),
3598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3606 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3607 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3608 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3609 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3612 };
3613 
3614 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
3615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3617 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3618 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3619 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3620 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),
3621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),
3631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3637 };
3638 
3639 #define DEFAULT_SH_MEM_CONFIG \
3640 	((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3641 	 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3642 	 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3643 	 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3644 
3645 /* TODO: pending on golden setting value of gb address config */
3646 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044
3647 
3648 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3649 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3650 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3651 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3652 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev);
3653 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3654 				 struct amdgpu_cu_info *cu_info);
3655 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3656 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3657 				   u32 sh_num, u32 instance, int xcc_id);
3658 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3659 
3660 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3661 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3662 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3663 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3664 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3665 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3666 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3667 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3668 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3669 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3670 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
3671 					   uint16_t pasid, uint32_t flush_type,
3672 					   bool all_hub, uint8_t dst_sel);
3673 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
3674 					       unsigned int vmid);
3675 
3676 static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
3677 					  enum amd_powergating_state state);
3678 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3679 {
3680 	struct amdgpu_device *adev = kiq_ring->adev;
3681 	u64 shader_mc_addr;
3682 
3683 	/* Cleaner shader MC address */
3684 	shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8;
3685 
3686 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3687 	amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3688 			  PACKET3_SET_RESOURCES_QUEUE_TYPE(0));	/* vmid_mask:0 queue_type:0 (KIQ) */
3689 	amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask));	/* queue mask lo */
3690 	amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask));	/* queue mask hi */
3691 	amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */
3692 	amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */
3693 	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */
3694 	amdgpu_ring_write(kiq_ring, 0);	/* gds heap base:0, gds heap size:0 */
3695 }
3696 
3697 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3698 				 struct amdgpu_ring *ring)
3699 {
3700 	uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3701 	uint64_t wptr_addr = ring->wptr_gpu_addr;
3702 	uint32_t eng_sel = 0;
3703 
3704 	switch (ring->funcs->type) {
3705 	case AMDGPU_RING_TYPE_COMPUTE:
3706 		eng_sel = 0;
3707 		break;
3708 	case AMDGPU_RING_TYPE_GFX:
3709 		eng_sel = 4;
3710 		break;
3711 	case AMDGPU_RING_TYPE_MES:
3712 		eng_sel = 5;
3713 		break;
3714 	default:
3715 		WARN_ON(1);
3716 	}
3717 
3718 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3719 	/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3720 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3721 			  PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3722 			  PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3723 			  PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3724 			  PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3725 			  PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3726 			  PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3727 			  PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3728 			  PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3729 			  PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3730 	amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3731 	amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3732 	amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3733 	amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3734 	amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3735 }
3736 
3737 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3738 				   struct amdgpu_ring *ring,
3739 				   enum amdgpu_unmap_queues_action action,
3740 				   u64 gpu_addr, u64 seq)
3741 {
3742 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3743 
3744 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3745 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3746 			  PACKET3_UNMAP_QUEUES_ACTION(action) |
3747 			  PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3748 			  PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3749 			  PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3750 	amdgpu_ring_write(kiq_ring,
3751 		  PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3752 
3753 	if (action == PREEMPT_QUEUES_NO_UNMAP) {
3754 		amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3755 		amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3756 		amdgpu_ring_write(kiq_ring, seq);
3757 	} else {
3758 		amdgpu_ring_write(kiq_ring, 0);
3759 		amdgpu_ring_write(kiq_ring, 0);
3760 		amdgpu_ring_write(kiq_ring, 0);
3761 	}
3762 }
3763 
3764 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3765 				   struct amdgpu_ring *ring,
3766 				   u64 addr,
3767 				   u64 seq)
3768 {
3769 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3770 
3771 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3772 	amdgpu_ring_write(kiq_ring,
3773 			  PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3774 			  PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3775 			  PACKET3_QUERY_STATUS_COMMAND(2));
3776 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3777 			  PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3778 			  PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3779 	amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3780 	amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3781 	amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3782 	amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3783 }
3784 
3785 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3786 				uint16_t pasid, uint32_t flush_type,
3787 				bool all_hub)
3788 {
3789 	gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
3790 }
3791 
3792 static void gfx_v10_0_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type,
3793 					uint32_t me_id, uint32_t pipe_id, uint32_t queue_id,
3794 					uint32_t xcc_id, uint32_t vmid)
3795 {
3796 	struct amdgpu_device *adev = kiq_ring->adev;
3797 	unsigned i;
3798 	uint32_t tmp;
3799 
3800 	/* enter save mode */
3801 	amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id);
3802 	mutex_lock(&adev->srbm_mutex);
3803 	nv_grbm_select(adev, me_id, pipe_id, queue_id, 0);
3804 
3805 	if (queue_type == AMDGPU_RING_TYPE_COMPUTE) {
3806 		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 0x2);
3807 		WREG32_SOC15(GC, 0, mmSPI_COMPUTE_QUEUE_RESET, 0x1);
3808 		/* wait till dequeue take effects */
3809 		for (i = 0; i < adev->usec_timeout; i++) {
3810 			if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3811 				break;
3812 			udelay(1);
3813 		}
3814 		if (i >= adev->usec_timeout)
3815 			dev_err(adev->dev, "fail to wait on hqd deactive\n");
3816 	} else if (queue_type == AMDGPU_RING_TYPE_GFX) {
3817 		WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
3818 			     (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
3819 		tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);
3820 		if (pipe_id == 0)
3821 			tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id);
3822 		else
3823 			tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id);
3824 		WREG32_SOC15(GC, 0, mmCP_VMID_RESET, tmp);
3825 
3826 		/* wait till dequeue take effects */
3827 		for (i = 0; i < adev->usec_timeout; i++) {
3828 			if (!(RREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE) & 1))
3829 				break;
3830 			udelay(1);
3831 		}
3832 		if (i >= adev->usec_timeout)
3833 			dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n");
3834 	} else {
3835 		dev_err(adev->dev, "reset queue_type(%d) not supported\n", queue_type);
3836 	}
3837 
3838 	nv_grbm_select(adev, 0, 0, 0, 0);
3839 	mutex_unlock(&adev->srbm_mutex);
3840 	/* exit safe mode */
3841 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
3842 }
3843 
3844 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3845 	.kiq_set_resources = gfx10_kiq_set_resources,
3846 	.kiq_map_queues = gfx10_kiq_map_queues,
3847 	.kiq_unmap_queues = gfx10_kiq_unmap_queues,
3848 	.kiq_query_status = gfx10_kiq_query_status,
3849 	.kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3850 	.kiq_reset_hw_queue = gfx_v10_0_kiq_reset_hw_queue,
3851 	.set_resources_size = 8,
3852 	.map_queues_size = 7,
3853 	.unmap_queues_size = 6,
3854 	.query_status_size = 7,
3855 	.invalidate_tlbs_size = 2,
3856 };
3857 
3858 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3859 {
3860 	adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs;
3861 }
3862 
3863 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3864 {
3865 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3866 	case IP_VERSION(10, 1, 10):
3867 		soc15_program_register_sequence(adev,
3868 						golden_settings_gc_rlc_spm_10_0_nv10,
3869 						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3870 		break;
3871 	case IP_VERSION(10, 1, 1):
3872 		soc15_program_register_sequence(adev,
3873 						golden_settings_gc_rlc_spm_10_1_nv14,
3874 						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3875 		break;
3876 	case IP_VERSION(10, 1, 2):
3877 		soc15_program_register_sequence(adev,
3878 						golden_settings_gc_rlc_spm_10_1_2_nv12,
3879 						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3880 		break;
3881 	default:
3882 		break;
3883 	}
3884 }
3885 
3886 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3887 {
3888 	if (amdgpu_sriov_vf(adev))
3889 		return;
3890 
3891 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3892 	case IP_VERSION(10, 1, 10):
3893 		soc15_program_register_sequence(adev,
3894 						golden_settings_gc_10_1,
3895 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3896 		soc15_program_register_sequence(adev,
3897 						golden_settings_gc_10_0_nv10,
3898 						(const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3899 		break;
3900 	case IP_VERSION(10, 1, 1):
3901 		soc15_program_register_sequence(adev,
3902 						golden_settings_gc_10_1_1,
3903 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3904 		soc15_program_register_sequence(adev,
3905 						golden_settings_gc_10_1_nv14,
3906 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3907 		break;
3908 	case IP_VERSION(10, 1, 2):
3909 		soc15_program_register_sequence(adev,
3910 						golden_settings_gc_10_1_2,
3911 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3912 		soc15_program_register_sequence(adev,
3913 						golden_settings_gc_10_1_2_nv12,
3914 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3915 		break;
3916 	case IP_VERSION(10, 3, 0):
3917 		soc15_program_register_sequence(adev,
3918 						golden_settings_gc_10_3,
3919 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3920 		soc15_program_register_sequence(adev,
3921 						golden_settings_gc_10_3_sienna_cichlid,
3922 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3923 		break;
3924 	case IP_VERSION(10, 3, 2):
3925 		soc15_program_register_sequence(adev,
3926 						golden_settings_gc_10_3_2,
3927 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3928 		break;
3929 	case IP_VERSION(10, 3, 1):
3930 		soc15_program_register_sequence(adev,
3931 						golden_settings_gc_10_3_vangogh,
3932 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3933 		break;
3934 	case IP_VERSION(10, 3, 3):
3935 		soc15_program_register_sequence(adev,
3936 						golden_settings_gc_10_3_3,
3937 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
3938 		break;
3939 	case IP_VERSION(10, 3, 4):
3940 		soc15_program_register_sequence(adev,
3941 						golden_settings_gc_10_3_4,
3942 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3943 		break;
3944 	case IP_VERSION(10, 3, 5):
3945 		soc15_program_register_sequence(adev,
3946 						golden_settings_gc_10_3_5,
3947 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
3948 		break;
3949 	case IP_VERSION(10, 1, 3):
3950 	case IP_VERSION(10, 1, 4):
3951 		soc15_program_register_sequence(adev,
3952 						golden_settings_gc_10_0_cyan_skillfish,
3953 						(const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
3954 		break;
3955 	case IP_VERSION(10, 3, 6):
3956 		soc15_program_register_sequence(adev,
3957 						golden_settings_gc_10_3_6,
3958 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));
3959 		break;
3960 	case IP_VERSION(10, 3, 7):
3961 		soc15_program_register_sequence(adev,
3962 						golden_settings_gc_10_3_7,
3963 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));
3964 		break;
3965 	default:
3966 		break;
3967 	}
3968 	gfx_v10_0_init_spm_golden_registers(adev);
3969 }
3970 
3971 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3972 				       bool wc, uint32_t reg, uint32_t val)
3973 {
3974 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3975 	amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3976 			  WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3977 	amdgpu_ring_write(ring, reg);
3978 	amdgpu_ring_write(ring, 0);
3979 	amdgpu_ring_write(ring, val);
3980 }
3981 
3982 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3983 				  int mem_space, int opt, uint32_t addr0,
3984 				  uint32_t addr1, uint32_t ref, uint32_t mask,
3985 				  uint32_t inv)
3986 {
3987 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3988 	amdgpu_ring_write(ring,
3989 			  /* memory (1) or register (0) */
3990 			  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3991 			   WAIT_REG_MEM_OPERATION(opt) | /* wait */
3992 			   WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3993 			   WAIT_REG_MEM_ENGINE(eng_sel)));
3994 
3995 	if (mem_space)
3996 		BUG_ON(addr0 & 0x3); /* Dword align */
3997 	amdgpu_ring_write(ring, addr0);
3998 	amdgpu_ring_write(ring, addr1);
3999 	amdgpu_ring_write(ring, ref);
4000 	amdgpu_ring_write(ring, mask);
4001 	amdgpu_ring_write(ring, inv); /* poll interval */
4002 }
4003 
4004 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
4005 {
4006 	struct amdgpu_device *adev = ring->adev;
4007 	uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
4008 	uint32_t tmp = 0;
4009 	unsigned int i;
4010 	int r;
4011 
4012 	WREG32(scratch, 0xCAFEDEAD);
4013 	r = amdgpu_ring_alloc(ring, 3);
4014 	if (r) {
4015 		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
4016 			  ring->idx, r);
4017 		return r;
4018 	}
4019 
4020 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
4021 	amdgpu_ring_write(ring, scratch -
4022 			  PACKET3_SET_UCONFIG_REG_START);
4023 	amdgpu_ring_write(ring, 0xDEADBEEF);
4024 	amdgpu_ring_commit(ring);
4025 
4026 	for (i = 0; i < adev->usec_timeout; i++) {
4027 		tmp = RREG32(scratch);
4028 		if (tmp == 0xDEADBEEF)
4029 			break;
4030 		if (amdgpu_emu_mode == 1)
4031 			msleep(1);
4032 		else
4033 			udelay(1);
4034 	}
4035 
4036 	if (i >= adev->usec_timeout)
4037 		r = -ETIMEDOUT;
4038 
4039 	return r;
4040 }
4041 
4042 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
4043 {
4044 	struct amdgpu_device *adev = ring->adev;
4045 	struct amdgpu_ib ib;
4046 	struct dma_fence *f = NULL;
4047 	unsigned int index;
4048 	uint64_t gpu_addr;
4049 	volatile uint32_t *cpu_ptr;
4050 	long r;
4051 
4052 	memset(&ib, 0, sizeof(ib));
4053 
4054 	r = amdgpu_device_wb_get(adev, &index);
4055 	if (r)
4056 		return r;
4057 
4058 	gpu_addr = adev->wb.gpu_addr + (index * 4);
4059 	adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
4060 	cpu_ptr = &adev->wb.wb[index];
4061 
4062 	r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
4063 	if (r) {
4064 		DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
4065 		goto err1;
4066 	}
4067 
4068 	ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
4069 	ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
4070 	ib.ptr[2] = lower_32_bits(gpu_addr);
4071 	ib.ptr[3] = upper_32_bits(gpu_addr);
4072 	ib.ptr[4] = 0xDEADBEEF;
4073 	ib.length_dw = 5;
4074 
4075 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
4076 	if (r)
4077 		goto err2;
4078 
4079 	r = dma_fence_wait_timeout(f, false, timeout);
4080 	if (r == 0) {
4081 		r = -ETIMEDOUT;
4082 		goto err2;
4083 	} else if (r < 0) {
4084 		goto err2;
4085 	}
4086 
4087 	if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
4088 		r = 0;
4089 	else
4090 		r = -EINVAL;
4091 err2:
4092 	amdgpu_ib_free(&ib, NULL);
4093 	dma_fence_put(f);
4094 err1:
4095 	amdgpu_device_wb_free(adev, index);
4096 	return r;
4097 }
4098 
4099 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
4100 {
4101 	amdgpu_ucode_release(&adev->gfx.pfp_fw);
4102 	amdgpu_ucode_release(&adev->gfx.me_fw);
4103 	amdgpu_ucode_release(&adev->gfx.ce_fw);
4104 	amdgpu_ucode_release(&adev->gfx.rlc_fw);
4105 	amdgpu_ucode_release(&adev->gfx.mec_fw);
4106 	amdgpu_ucode_release(&adev->gfx.mec2_fw);
4107 
4108 	kfree(adev->gfx.rlc.register_list_format);
4109 }
4110 
4111 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
4112 {
4113 	adev->gfx.cp_fw_write_wait = false;
4114 
4115 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4116 	case IP_VERSION(10, 1, 10):
4117 	case IP_VERSION(10, 1, 2):
4118 	case IP_VERSION(10, 1, 1):
4119 	case IP_VERSION(10, 1, 3):
4120 	case IP_VERSION(10, 1, 4):
4121 		if ((adev->gfx.me_fw_version >= 0x00000046) &&
4122 		    (adev->gfx.me_feature_version >= 27) &&
4123 		    (adev->gfx.pfp_fw_version >= 0x00000068) &&
4124 		    (adev->gfx.pfp_feature_version >= 27) &&
4125 		    (adev->gfx.mec_fw_version >= 0x0000005b) &&
4126 		    (adev->gfx.mec_feature_version >= 27))
4127 			adev->gfx.cp_fw_write_wait = true;
4128 		break;
4129 	case IP_VERSION(10, 3, 0):
4130 	case IP_VERSION(10, 3, 2):
4131 	case IP_VERSION(10, 3, 1):
4132 	case IP_VERSION(10, 3, 4):
4133 	case IP_VERSION(10, 3, 5):
4134 	case IP_VERSION(10, 3, 6):
4135 	case IP_VERSION(10, 3, 3):
4136 	case IP_VERSION(10, 3, 7):
4137 		adev->gfx.cp_fw_write_wait = true;
4138 		break;
4139 	default:
4140 		break;
4141 	}
4142 
4143 	if (!adev->gfx.cp_fw_write_wait)
4144 		DRM_WARN_ONCE("CP firmware version too old, please update!");
4145 }
4146 
4147 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
4148 {
4149 	bool ret = false;
4150 
4151 	switch (adev->pdev->revision) {
4152 	case 0xc2:
4153 	case 0xc3:
4154 		ret = true;
4155 		break;
4156 	default:
4157 		ret = false;
4158 		break;
4159 	}
4160 
4161 	return ret;
4162 }
4163 
4164 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
4165 {
4166 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4167 	case IP_VERSION(10, 1, 10):
4168 		if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
4169 			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
4170 		break;
4171 	default:
4172 		break;
4173 	}
4174 }
4175 
4176 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
4177 {
4178 	char fw_name[53];
4179 	char ucode_prefix[30];
4180 	const char *wks = "";
4181 	int err;
4182 	const struct rlc_firmware_header_v2_0 *rlc_hdr;
4183 	uint16_t version_major;
4184 	uint16_t version_minor;
4185 
4186 	DRM_DEBUG("\n");
4187 
4188 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) &&
4189 	    (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00)))
4190 		wks = "_wks";
4191 	amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
4192 
4193 	err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
4194 				   AMDGPU_UCODE_REQUIRED,
4195 				   "amdgpu/%s_pfp%s.bin", ucode_prefix, wks);
4196 	if (err)
4197 		goto out;
4198 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
4199 
4200 	err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
4201 				   AMDGPU_UCODE_REQUIRED,
4202 				   "amdgpu/%s_me%s.bin", ucode_prefix, wks);
4203 	if (err)
4204 		goto out;
4205 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
4206 
4207 	err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,
4208 				   AMDGPU_UCODE_REQUIRED,
4209 				   "amdgpu/%s_ce%s.bin", ucode_prefix, wks);
4210 	if (err)
4211 		goto out;
4212 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE);
4213 
4214 	if (!amdgpu_sriov_vf(adev)) {
4215 		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);
4216 		err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4217 		if (err)
4218 			goto out;
4219 
4220 		/* don't validate this firmware. There are apparently firmwares
4221 		 * in the wild with incorrect size in the header
4222 		 */
4223 		rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4224 		version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4225 		version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4226 		err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
4227 		if (err)
4228 			goto out;
4229 	}
4230 
4231 	err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
4232 				   AMDGPU_UCODE_REQUIRED,
4233 				   "amdgpu/%s_mec%s.bin", ucode_prefix, wks);
4234 	if (err)
4235 		goto out;
4236 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
4237 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
4238 
4239 	err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw,
4240 				   AMDGPU_UCODE_REQUIRED,
4241 				   "amdgpu/%s_mec2%s.bin", ucode_prefix, wks);
4242 	if (!err) {
4243 		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
4244 		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);
4245 	} else {
4246 		err = 0;
4247 		adev->gfx.mec2_fw = NULL;
4248 	}
4249 
4250 	gfx_v10_0_check_fw_write_wait(adev);
4251 out:
4252 	if (err) {
4253 		amdgpu_ucode_release(&adev->gfx.pfp_fw);
4254 		amdgpu_ucode_release(&adev->gfx.me_fw);
4255 		amdgpu_ucode_release(&adev->gfx.ce_fw);
4256 		amdgpu_ucode_release(&adev->gfx.rlc_fw);
4257 		amdgpu_ucode_release(&adev->gfx.mec_fw);
4258 		amdgpu_ucode_release(&adev->gfx.mec2_fw);
4259 	}
4260 
4261 	gfx_v10_0_check_gfxoff_flag(adev);
4262 
4263 	return err;
4264 }
4265 
4266 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4267 {
4268 	u32 count = 0;
4269 	const struct cs_section_def *sect = NULL;
4270 	const struct cs_extent_def *ext = NULL;
4271 
4272 	/* begin clear state */
4273 	count += 2;
4274 	/* context control state */
4275 	count += 3;
4276 
4277 	for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4278 		for (ext = sect->section; ext->extent != NULL; ++ext) {
4279 			if (sect->id == SECT_CONTEXT)
4280 				count += 2 + ext->reg_count;
4281 			else
4282 				return 0;
4283 		}
4284 	}
4285 
4286 	/* set PA_SC_TILE_STEERING_OVERRIDE */
4287 	count += 3;
4288 	/* end clear state */
4289 	count += 2;
4290 	/* clear state */
4291 	count += 2;
4292 
4293 	return count;
4294 }
4295 
4296 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4297 				    volatile u32 *buffer)
4298 {
4299 	u32 count = 0, i;
4300 	const struct cs_section_def *sect = NULL;
4301 	const struct cs_extent_def *ext = NULL;
4302 	int ctx_reg_offset;
4303 
4304 	if (adev->gfx.rlc.cs_data == NULL)
4305 		return;
4306 	if (buffer == NULL)
4307 		return;
4308 
4309 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4310 	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4311 
4312 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4313 	buffer[count++] = cpu_to_le32(0x80000000);
4314 	buffer[count++] = cpu_to_le32(0x80000000);
4315 
4316 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4317 		for (ext = sect->section; ext->extent != NULL; ++ext) {
4318 			if (sect->id == SECT_CONTEXT) {
4319 				buffer[count++] =
4320 					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4321 				buffer[count++] = cpu_to_le32(ext->reg_index -
4322 						PACKET3_SET_CONTEXT_REG_START);
4323 				for (i = 0; i < ext->reg_count; i++)
4324 					buffer[count++] = cpu_to_le32(ext->extent[i]);
4325 			} else {
4326 				return;
4327 			}
4328 		}
4329 	}
4330 
4331 	ctx_reg_offset =
4332 		SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4333 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4334 	buffer[count++] = cpu_to_le32(ctx_reg_offset);
4335 	buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4336 
4337 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4338 	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4339 
4340 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4341 	buffer[count++] = cpu_to_le32(0);
4342 }
4343 
4344 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4345 {
4346 	/* clear state block */
4347 	amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4348 			&adev->gfx.rlc.clear_state_gpu_addr,
4349 			(void **)&adev->gfx.rlc.cs_ptr);
4350 
4351 	/* jump table block */
4352 	amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4353 			&adev->gfx.rlc.cp_table_gpu_addr,
4354 			(void **)&adev->gfx.rlc.cp_table_ptr);
4355 }
4356 
4357 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
4358 {
4359 	struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
4360 
4361 	reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
4362 	reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
4363 	reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
4364 	reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
4365 	reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
4366 	reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
4367 	reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
4368 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4369 	case IP_VERSION(10, 3, 0):
4370 		reg_access_ctrl->spare_int =
4371 			SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);
4372 		break;
4373 	default:
4374 		reg_access_ctrl->spare_int =
4375 			SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
4376 		break;
4377 	}
4378 	adev->gfx.rlc.rlcg_reg_access_supported = true;
4379 }
4380 
4381 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4382 {
4383 	const struct cs_section_def *cs_data;
4384 	int r;
4385 
4386 	adev->gfx.rlc.cs_data = gfx10_cs_data;
4387 
4388 	cs_data = adev->gfx.rlc.cs_data;
4389 
4390 	if (cs_data) {
4391 		/* init clear state block */
4392 		r = amdgpu_gfx_rlc_init_csb(adev);
4393 		if (r)
4394 			return r;
4395 	}
4396 
4397 	return 0;
4398 }
4399 
4400 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4401 {
4402 	amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4403 	amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4404 }
4405 
4406 static void gfx_v10_0_me_init(struct amdgpu_device *adev)
4407 {
4408 	bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4409 
4410 	amdgpu_gfx_graphics_queue_acquire(adev);
4411 }
4412 
4413 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4414 {
4415 	int r;
4416 	u32 *hpd;
4417 	const __le32 *fw_data = NULL;
4418 	unsigned int fw_size;
4419 	u32 *fw = NULL;
4420 	size_t mec_hpd_size;
4421 
4422 	const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4423 
4424 	bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4425 
4426 	/* take ownership of the relevant compute queues */
4427 	amdgpu_gfx_compute_queue_acquire(adev);
4428 	mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4429 
4430 	if (mec_hpd_size) {
4431 		r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4432 					      AMDGPU_GEM_DOMAIN_GTT,
4433 					      &adev->gfx.mec.hpd_eop_obj,
4434 					      &adev->gfx.mec.hpd_eop_gpu_addr,
4435 					      (void **)&hpd);
4436 		if (r) {
4437 			dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4438 			gfx_v10_0_mec_fini(adev);
4439 			return r;
4440 		}
4441 
4442 		memset(hpd, 0, mec_hpd_size);
4443 
4444 		amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4445 		amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4446 	}
4447 
4448 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4449 		mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4450 
4451 		fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4452 			 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4453 		fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4454 
4455 		r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4456 					      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4457 					      &adev->gfx.mec.mec_fw_obj,
4458 					      &adev->gfx.mec.mec_fw_gpu_addr,
4459 					      (void **)&fw);
4460 		if (r) {
4461 			dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4462 			gfx_v10_0_mec_fini(adev);
4463 			return r;
4464 		}
4465 
4466 		memcpy(fw, fw_data, fw_size);
4467 
4468 		amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4469 		amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4470 	}
4471 
4472 	return 0;
4473 }
4474 
4475 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4476 {
4477 	WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4478 		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4479 		(address << SQ_IND_INDEX__INDEX__SHIFT));
4480 	return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4481 }
4482 
4483 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4484 			   uint32_t thread, uint32_t regno,
4485 			   uint32_t num, uint32_t *out)
4486 {
4487 	WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4488 		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4489 		(regno << SQ_IND_INDEX__INDEX__SHIFT) |
4490 		(thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4491 		(SQ_IND_INDEX__AUTO_INCR_MASK));
4492 	while (num--)
4493 		*(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4494 }
4495 
4496 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4497 {
4498 	/* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4499 	 * field when performing a select_se_sh so it should be
4500 	 * zero here
4501 	 */
4502 	WARN_ON(simd != 0);
4503 
4504 	/* type 2 wave data */
4505 	dst[(*no_fields)++] = 2;
4506 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4507 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4508 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4509 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4510 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4511 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4512 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4513 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4514 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4515 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4516 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4517 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4518 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4519 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4520 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4521 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
4522 }
4523 
4524 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4525 				     uint32_t wave, uint32_t start,
4526 				     uint32_t size, uint32_t *dst)
4527 {
4528 	WARN_ON(simd != 0);
4529 
4530 	wave_read_regs(
4531 		adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4532 		dst);
4533 }
4534 
4535 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4536 				      uint32_t wave, uint32_t thread,
4537 				      uint32_t start, uint32_t size,
4538 				      uint32_t *dst)
4539 {
4540 	wave_read_regs(
4541 		adev, wave, thread,
4542 		start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4543 }
4544 
4545 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4546 				       u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
4547 {
4548 	nv_grbm_select(adev, me, pipe, q, vm);
4549 }
4550 
4551 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4552 					  bool enable)
4553 {
4554 	uint32_t data, def;
4555 
4556 	data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4557 
4558 	if (enable)
4559 		data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4560 	else
4561 		data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4562 
4563 	if (data != def)
4564 		WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4565 }
4566 
4567 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4568 	.get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4569 	.select_se_sh = &gfx_v10_0_select_se_sh,
4570 	.read_wave_data = &gfx_v10_0_read_wave_data,
4571 	.read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4572 	.read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4573 	.select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4574 	.init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4575 	.update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4576 };
4577 
4578 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4579 {
4580 	u32 gb_addr_config;
4581 
4582 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4583 	case IP_VERSION(10, 1, 10):
4584 	case IP_VERSION(10, 1, 1):
4585 	case IP_VERSION(10, 1, 2):
4586 		adev->gfx.config.max_hw_contexts = 8;
4587 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4588 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4589 		adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4590 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4591 		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4592 		break;
4593 	case IP_VERSION(10, 3, 0):
4594 	case IP_VERSION(10, 3, 2):
4595 	case IP_VERSION(10, 3, 1):
4596 	case IP_VERSION(10, 3, 4):
4597 	case IP_VERSION(10, 3, 5):
4598 	case IP_VERSION(10, 3, 6):
4599 	case IP_VERSION(10, 3, 3):
4600 	case IP_VERSION(10, 3, 7):
4601 		adev->gfx.config.max_hw_contexts = 8;
4602 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4603 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4604 		adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4605 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4606 		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4607 		adev->gfx.config.gb_addr_config_fields.num_pkrs =
4608 			1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4609 		break;
4610 	case IP_VERSION(10, 1, 3):
4611 	case IP_VERSION(10, 1, 4):
4612 		adev->gfx.config.max_hw_contexts = 8;
4613 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4614 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4615 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4616 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4617 		gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN;
4618 		break;
4619 	default:
4620 		BUG();
4621 		break;
4622 	}
4623 
4624 	adev->gfx.config.gb_addr_config = gb_addr_config;
4625 
4626 	adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4627 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4628 				      GB_ADDR_CONFIG, NUM_PIPES);
4629 
4630 	adev->gfx.config.max_tile_pipes =
4631 		adev->gfx.config.gb_addr_config_fields.num_pipes;
4632 
4633 	adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4634 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4635 				      GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4636 	adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4637 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4638 				      GB_ADDR_CONFIG, NUM_RB_PER_SE);
4639 	adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4640 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4641 				      GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4642 	adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4643 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4644 				      GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4645 }
4646 
4647 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4648 				   int me, int pipe, int queue)
4649 {
4650 	struct amdgpu_ring *ring;
4651 	unsigned int irq_type;
4652 	unsigned int hw_prio;
4653 
4654 	ring = &adev->gfx.gfx_ring[ring_id];
4655 
4656 	ring->me = me;
4657 	ring->pipe = pipe;
4658 	ring->queue = queue;
4659 
4660 	ring->ring_obj = NULL;
4661 	ring->use_doorbell = true;
4662 
4663 	if (!ring_id)
4664 		ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4665 	else
4666 		ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4667 	ring->vm_hub = AMDGPU_GFXHUB(0);
4668 	sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4669 
4670 	irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4671 	hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
4672 			AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4673 	return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4674 				hw_prio, NULL);
4675 }
4676 
4677 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4678 				       int mec, int pipe, int queue)
4679 {
4680 	unsigned int irq_type;
4681 	struct amdgpu_ring *ring;
4682 	unsigned int hw_prio;
4683 
4684 	ring = &adev->gfx.compute_ring[ring_id];
4685 
4686 	/* mec0 is me1 */
4687 	ring->me = mec + 1;
4688 	ring->pipe = pipe;
4689 	ring->queue = queue;
4690 
4691 	ring->ring_obj = NULL;
4692 	ring->use_doorbell = true;
4693 	ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4694 	ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4695 				+ (ring_id * GFX10_MEC_HPD_SIZE);
4696 	ring->vm_hub = AMDGPU_GFXHUB(0);
4697 	sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4698 
4699 	irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4700 		+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4701 		+ ring->pipe;
4702 	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4703 			AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
4704 	/* type-2 packets are deprecated on MEC, use type-3 instead */
4705 	return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4706 			     hw_prio, NULL);
4707 }
4708 
4709 static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev)
4710 {
4711 	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
4712 	uint32_t *ptr;
4713 	uint32_t inst;
4714 
4715 	ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
4716 	if (!ptr) {
4717 		DRM_ERROR("Failed to allocate memory for GFX IP Dump\n");
4718 		adev->gfx.ip_dump_core = NULL;
4719 	} else {
4720 		adev->gfx.ip_dump_core = ptr;
4721 	}
4722 
4723 	/* Allocate memory for compute queue registers for all the instances */
4724 	reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
4725 	inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
4726 		adev->gfx.mec.num_queue_per_pipe;
4727 
4728 	ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
4729 	if (!ptr) {
4730 		DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n");
4731 		adev->gfx.ip_dump_compute_queues = NULL;
4732 	} else {
4733 		adev->gfx.ip_dump_compute_queues = ptr;
4734 	}
4735 
4736 	/* Allocate memory for gfx queue registers for all the instances */
4737 	reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
4738 	inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
4739 		adev->gfx.me.num_queue_per_pipe;
4740 
4741 	ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
4742 	if (!ptr) {
4743 		DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n");
4744 		adev->gfx.ip_dump_gfx_queues = NULL;
4745 	} else {
4746 		adev->gfx.ip_dump_gfx_queues = ptr;
4747 	}
4748 }
4749 
4750 static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block)
4751 {
4752 	int i, j, k, r, ring_id = 0;
4753 	int xcc_id = 0;
4754 	struct amdgpu_device *adev = ip_block->adev;
4755 
4756 	INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler);
4757 
4758 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4759 	case IP_VERSION(10, 1, 10):
4760 	case IP_VERSION(10, 1, 1):
4761 	case IP_VERSION(10, 1, 2):
4762 	case IP_VERSION(10, 1, 3):
4763 	case IP_VERSION(10, 1, 4):
4764 		adev->gfx.me.num_me = 1;
4765 		adev->gfx.me.num_pipe_per_me = 1;
4766 		adev->gfx.me.num_queue_per_pipe = 1;
4767 		adev->gfx.mec.num_mec = 2;
4768 		adev->gfx.mec.num_pipe_per_mec = 4;
4769 		adev->gfx.mec.num_queue_per_pipe = 8;
4770 		break;
4771 	case IP_VERSION(10, 3, 0):
4772 	case IP_VERSION(10, 3, 2):
4773 	case IP_VERSION(10, 3, 1):
4774 	case IP_VERSION(10, 3, 4):
4775 	case IP_VERSION(10, 3, 5):
4776 	case IP_VERSION(10, 3, 6):
4777 	case IP_VERSION(10, 3, 3):
4778 	case IP_VERSION(10, 3, 7):
4779 		adev->gfx.me.num_me = 1;
4780 		adev->gfx.me.num_pipe_per_me = 2;
4781 		adev->gfx.me.num_queue_per_pipe = 1;
4782 		adev->gfx.mec.num_mec = 2;
4783 		adev->gfx.mec.num_pipe_per_mec = 4;
4784 		adev->gfx.mec.num_queue_per_pipe = 4;
4785 		break;
4786 	default:
4787 		adev->gfx.me.num_me = 1;
4788 		adev->gfx.me.num_pipe_per_me = 1;
4789 		adev->gfx.me.num_queue_per_pipe = 1;
4790 		adev->gfx.mec.num_mec = 1;
4791 		adev->gfx.mec.num_pipe_per_mec = 4;
4792 		adev->gfx.mec.num_queue_per_pipe = 8;
4793 		break;
4794 	}
4795 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4796 	case IP_VERSION(10, 1, 10):
4797 	case IP_VERSION(10, 1, 1):
4798 	case IP_VERSION(10, 1, 2):
4799 		adev->gfx.cleaner_shader_ptr = gfx_10_1_10_cleaner_shader_hex;
4800 		adev->gfx.cleaner_shader_size = sizeof(gfx_10_1_10_cleaner_shader_hex);
4801 		if (adev->gfx.me_fw_version >= 101 &&
4802 		    adev->gfx.pfp_fw_version  >= 158 &&
4803 		    adev->gfx.mec_fw_version >= 152) {
4804 			adev->gfx.enable_cleaner_shader = true;
4805 			r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size);
4806 			if (r) {
4807 				adev->gfx.enable_cleaner_shader = false;
4808 				dev_err(adev->dev, "Failed to initialize cleaner shader\n");
4809 			}
4810 		}
4811 		break;
4812 	case IP_VERSION(10, 3, 0):
4813 	case IP_VERSION(10, 3, 2):
4814 	case IP_VERSION(10, 3, 4):
4815 	case IP_VERSION(10, 3, 5):
4816 		adev->gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex;
4817 		adev->gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex);
4818 		if (adev->gfx.me_fw_version >= 64 &&
4819 		    adev->gfx.pfp_fw_version >= 100 &&
4820 		    adev->gfx.mec_fw_version >= 122) {
4821 			adev->gfx.enable_cleaner_shader = true;
4822 			r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size);
4823 			if (r) {
4824 				adev->gfx.enable_cleaner_shader = false;
4825 				dev_err(adev->dev, "Failed to initialize cleaner shader\n");
4826 			}
4827 		}
4828 		break;
4829 	default:
4830 		adev->gfx.enable_cleaner_shader = false;
4831 		break;
4832 	}
4833 
4834 	/* KIQ event */
4835 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4836 			      GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4837 			      &adev->gfx.kiq[0].irq);
4838 	if (r)
4839 		return r;
4840 
4841 	/* EOP Event */
4842 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4843 			      GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4844 			      &adev->gfx.eop_irq);
4845 	if (r)
4846 		return r;
4847 
4848 	/* Bad opcode Event */
4849 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4850 			      GFX_10_1__SRCID__CP_BAD_OPCODE_ERROR,
4851 			      &adev->gfx.bad_op_irq);
4852 	if (r)
4853 		return r;
4854 
4855 	/* Privileged reg */
4856 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4857 			      &adev->gfx.priv_reg_irq);
4858 	if (r)
4859 		return r;
4860 
4861 	/* Privileged inst */
4862 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4863 			      &adev->gfx.priv_inst_irq);
4864 	if (r)
4865 		return r;
4866 
4867 	adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4868 
4869 	gfx_v10_0_me_init(adev);
4870 
4871 	if (adev->gfx.rlc.funcs) {
4872 		if (adev->gfx.rlc.funcs->init) {
4873 			r = adev->gfx.rlc.funcs->init(adev);
4874 			if (r) {
4875 				dev_err(adev->dev, "Failed to init rlc BOs!\n");
4876 				return r;
4877 			}
4878 		}
4879 	}
4880 
4881 	r = gfx_v10_0_mec_init(adev);
4882 	if (r) {
4883 		DRM_ERROR("Failed to init MEC BOs!\n");
4884 		return r;
4885 	}
4886 
4887 	/* set up the gfx ring */
4888 	for (i = 0; i < adev->gfx.me.num_me; i++) {
4889 		for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4890 			for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4891 				if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4892 					continue;
4893 
4894 				r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4895 							    i, k, j);
4896 				if (r)
4897 					return r;
4898 				ring_id++;
4899 			}
4900 		}
4901 	}
4902 
4903 	ring_id = 0;
4904 	/* set up the compute queues - allocate horizontally across pipes */
4905 	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4906 		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4907 			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4908 				if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
4909 								     k, j))
4910 					continue;
4911 
4912 				r = gfx_v10_0_compute_ring_init(adev, ring_id,
4913 								i, k, j);
4914 				if (r)
4915 					return r;
4916 
4917 				ring_id++;
4918 			}
4919 		}
4920 	}
4921 	/* TODO: Add queue reset mask when FW fully supports it */
4922 	adev->gfx.gfx_supported_reset =
4923 		amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]);
4924 	adev->gfx.compute_supported_reset =
4925 		amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]);
4926 
4927 	r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0);
4928 	if (r) {
4929 		DRM_ERROR("Failed to init KIQ BOs!\n");
4930 		return r;
4931 	}
4932 
4933 	r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);
4934 	if (r)
4935 		return r;
4936 
4937 	r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0);
4938 	if (r)
4939 		return r;
4940 
4941 	/* allocate visible FB for rlc auto-loading fw */
4942 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4943 		r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4944 		if (r)
4945 			return r;
4946 	}
4947 
4948 	adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4949 
4950 	gfx_v10_0_gpu_early_init(adev);
4951 
4952 	gfx_v10_0_alloc_ip_dump(adev);
4953 
4954 	r = amdgpu_gfx_sysfs_init(adev);
4955 	if (r)
4956 		return r;
4957 
4958 	return 0;
4959 }
4960 
4961 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4962 {
4963 	amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4964 			      &adev->gfx.pfp.pfp_fw_gpu_addr,
4965 			      (void **)&adev->gfx.pfp.pfp_fw_ptr);
4966 }
4967 
4968 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4969 {
4970 	amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4971 			      &adev->gfx.ce.ce_fw_gpu_addr,
4972 			      (void **)&adev->gfx.ce.ce_fw_ptr);
4973 }
4974 
4975 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4976 {
4977 	amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4978 			      &adev->gfx.me.me_fw_gpu_addr,
4979 			      (void **)&adev->gfx.me.me_fw_ptr);
4980 }
4981 
4982 static int gfx_v10_0_sw_fini(struct amdgpu_ip_block *ip_block)
4983 {
4984 	int i;
4985 	struct amdgpu_device *adev = ip_block->adev;
4986 
4987 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4988 		amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4989 	for (i = 0; i < adev->gfx.num_compute_rings; i++)
4990 		amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4991 
4992 	amdgpu_gfx_mqd_sw_fini(adev, 0);
4993 
4994 	amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
4995 	amdgpu_gfx_kiq_fini(adev, 0);
4996 
4997 	amdgpu_gfx_cleaner_shader_sw_fini(adev);
4998 
4999 	gfx_v10_0_pfp_fini(adev);
5000 	gfx_v10_0_ce_fini(adev);
5001 	gfx_v10_0_me_fini(adev);
5002 	gfx_v10_0_rlc_fini(adev);
5003 	gfx_v10_0_mec_fini(adev);
5004 
5005 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
5006 		gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
5007 
5008 	gfx_v10_0_free_microcode(adev);
5009 	amdgpu_gfx_sysfs_fini(adev);
5010 
5011 	kfree(adev->gfx.ip_dump_core);
5012 	kfree(adev->gfx.ip_dump_compute_queues);
5013 	kfree(adev->gfx.ip_dump_gfx_queues);
5014 
5015 	return 0;
5016 }
5017 
5018 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
5019 				   u32 sh_num, u32 instance, int xcc_id)
5020 {
5021 	u32 data;
5022 
5023 	if (instance == 0xffffffff)
5024 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
5025 				     INSTANCE_BROADCAST_WRITES, 1);
5026 	else
5027 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
5028 				     instance);
5029 
5030 	if (se_num == 0xffffffff)
5031 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
5032 				     1);
5033 	else
5034 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
5035 
5036 	if (sh_num == 0xffffffff)
5037 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
5038 				     1);
5039 	else
5040 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
5041 
5042 	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
5043 }
5044 
5045 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
5046 {
5047 	u32 data, mask;
5048 
5049 	data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
5050 	data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
5051 
5052 	data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
5053 	data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
5054 
5055 	mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
5056 					 adev->gfx.config.max_sh_per_se);
5057 
5058 	return (~data) & mask;
5059 }
5060 
5061 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
5062 {
5063 	int i, j;
5064 	u32 data;
5065 	u32 active_rbs = 0;
5066 	u32 bitmap;
5067 	u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
5068 					adev->gfx.config.max_sh_per_se;
5069 
5070 	mutex_lock(&adev->grbm_idx_mutex);
5071 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5072 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5073 			bitmap = i * adev->gfx.config.max_sh_per_se + j;
5074 			if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==
5075 			      IP_VERSION(10, 3, 0)) ||
5076 			     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
5077 			      IP_VERSION(10, 3, 3)) ||
5078 			     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
5079 			      IP_VERSION(10, 3, 6))) &&
5080 			    ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
5081 				continue;
5082 			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
5083 			data = gfx_v10_0_get_rb_active_bitmap(adev);
5084 			active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
5085 					       rb_bitmap_width_per_sh);
5086 		}
5087 	}
5088 	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
5089 	mutex_unlock(&adev->grbm_idx_mutex);
5090 
5091 	adev->gfx.config.backend_enable_mask = active_rbs;
5092 	adev->gfx.config.num_rbs = hweight32(active_rbs);
5093 }
5094 
5095 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
5096 {
5097 	uint32_t num_sc;
5098 	uint32_t enabled_rb_per_sh;
5099 	uint32_t active_rb_bitmap;
5100 	uint32_t num_rb_per_sc;
5101 	uint32_t num_packer_per_sc;
5102 	uint32_t pa_sc_tile_steering_override;
5103 
5104 	/* for ASICs that integrates GFX v10.3
5105 	 * pa_sc_tile_steering_override should be set to 0
5106 	 */
5107 	if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0))
5108 		return 0;
5109 
5110 	/* init num_sc */
5111 	num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
5112 			adev->gfx.config.num_sc_per_sh;
5113 	/* init num_rb_per_sc */
5114 	active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
5115 	enabled_rb_per_sh = hweight32(active_rb_bitmap);
5116 	num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
5117 	/* init num_packer_per_sc */
5118 	num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
5119 
5120 	pa_sc_tile_steering_override = 0;
5121 	pa_sc_tile_steering_override |=
5122 		(order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
5123 		PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
5124 	pa_sc_tile_steering_override |=
5125 		(order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
5126 		PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
5127 	pa_sc_tile_steering_override |=
5128 		(order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
5129 		PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
5130 
5131 	return pa_sc_tile_steering_override;
5132 }
5133 
5134 #define DEFAULT_SH_MEM_BASES	(0x6000)
5135 
5136 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev,
5137 				uint32_t first_vmid,
5138 				uint32_t last_vmid)
5139 {
5140 	uint32_t data;
5141 	uint32_t trap_config_vmid_mask = 0;
5142 	int i;
5143 
5144 	/* Calculate trap config vmid mask */
5145 	for (i = first_vmid; i < last_vmid; i++)
5146 		trap_config_vmid_mask |= (1 << i);
5147 
5148 	data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG,
5149 			VMID_SEL, trap_config_vmid_mask);
5150 	data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
5151 			TRAP_EN, 1);
5152 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
5153 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
5154 
5155 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
5156 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
5157 }
5158 
5159 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
5160 {
5161 	int i;
5162 	uint32_t sh_mem_bases;
5163 
5164 	/*
5165 	 * Configure apertures:
5166 	 * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
5167 	 * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
5168 	 * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
5169 	 */
5170 	sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
5171 
5172 	mutex_lock(&adev->srbm_mutex);
5173 	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5174 		nv_grbm_select(adev, 0, 0, 0, i);
5175 		/* CP and shaders */
5176 		WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5177 		WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
5178 	}
5179 	nv_grbm_select(adev, 0, 0, 0, 0);
5180 	mutex_unlock(&adev->srbm_mutex);
5181 
5182 	/*
5183 	 * Initialize all compute VMIDs to have no GDS, GWS, or OA
5184 	 * access. These should be enabled by FW for target VMIDs.
5185 	 */
5186 	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5187 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
5188 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
5189 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
5190 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
5191 	}
5192 
5193 	gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid,
5194 					AMDGPU_NUM_VMID);
5195 }
5196 
5197 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
5198 {
5199 	int vmid;
5200 
5201 	/*
5202 	 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
5203 	 * access. Compute VMIDs should be enabled by FW for target VMIDs,
5204 	 * the driver can enable them for graphics. VMID0 should maintain
5205 	 * access so that HWS firmware can save/restore entries.
5206 	 */
5207 	for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
5208 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
5209 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
5210 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
5211 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
5212 	}
5213 }
5214 
5215 
5216 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
5217 {
5218 	int i, j, k;
5219 	int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
5220 	u32 tmp, wgp_active_bitmap = 0;
5221 	u32 gcrd_targets_disable_tcp = 0;
5222 	u32 utcl_invreq_disable = 0;
5223 	/*
5224 	 * GCRD_TARGETS_DISABLE field contains
5225 	 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
5226 	 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
5227 	 */
5228 	u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
5229 		2 * max_wgp_per_sh + /* TCP */
5230 		max_wgp_per_sh + /* SQC */
5231 		4); /* GL1C */
5232 	/*
5233 	 * UTCL1_UTCL0_INVREQ_DISABLE field contains
5234 	 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
5235 	 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
5236 	 */
5237 	u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
5238 		2 * max_wgp_per_sh + /* TCP */
5239 		2 * max_wgp_per_sh + /* SQC */
5240 		4 + /* RMI */
5241 		1); /* SQG */
5242 
5243 	mutex_lock(&adev->grbm_idx_mutex);
5244 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5245 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5246 			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
5247 			wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5248 			/*
5249 			 * Set corresponding TCP bits for the inactive WGPs in
5250 			 * GCRD_SA_TARGETS_DISABLE
5251 			 */
5252 			gcrd_targets_disable_tcp = 0;
5253 			/* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
5254 			utcl_invreq_disable = 0;
5255 
5256 			for (k = 0; k < max_wgp_per_sh; k++) {
5257 				if (!(wgp_active_bitmap & (1 << k))) {
5258 					gcrd_targets_disable_tcp |= 3 << (2 * k);
5259 					gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
5260 					utcl_invreq_disable |= (3 << (2 * k)) |
5261 						(3 << (2 * (max_wgp_per_sh + k)));
5262 				}
5263 			}
5264 
5265 			tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5266 			/* only override TCP & SQC bits */
5267 			tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
5268 			tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5269 			WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5270 
5271 			tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5272 			/* only override TCP & SQC bits */
5273 			tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
5274 			tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5275 			WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5276 		}
5277 	}
5278 
5279 	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
5280 	mutex_unlock(&adev->grbm_idx_mutex);
5281 }
5282 
5283 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5284 {
5285 	/* TCCs are global (not instanced). */
5286 	uint32_t tcc_disable;
5287 
5288 	if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) {
5289 		tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
5290 			      RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
5291 	} else {
5292 		tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
5293 			      RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
5294 	}
5295 
5296 	adev->gfx.config.tcc_disabled_mask =
5297 		REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
5298 		(REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
5299 }
5300 
5301 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5302 {
5303 	u32 tmp;
5304 	int i;
5305 
5306 	if (!amdgpu_sriov_vf(adev))
5307 		WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
5308 
5309 	gfx_v10_0_setup_rb(adev);
5310 	gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5311 	gfx_v10_0_get_tcc_info(adev);
5312 	adev->gfx.config.pa_sc_tile_steering_override =
5313 		gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5314 
5315 	/* XXX SH_MEM regs */
5316 	/* where to put LDS, scratch, GPUVM in FSA64 space */
5317 	mutex_lock(&adev->srbm_mutex);
5318 	for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
5319 		nv_grbm_select(adev, 0, 0, 0, i);
5320 		/* CP and shaders */
5321 		WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5322 		if (i != 0) {
5323 			tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5324 				(adev->gmc.private_aperture_start >> 48));
5325 			tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5326 				(adev->gmc.shared_aperture_start >> 48));
5327 			WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5328 		}
5329 	}
5330 	nv_grbm_select(adev, 0, 0, 0, 0);
5331 
5332 	mutex_unlock(&adev->srbm_mutex);
5333 
5334 	gfx_v10_0_init_compute_vmid(adev);
5335 	gfx_v10_0_init_gds_vmid(adev);
5336 
5337 }
5338 
5339 static u32 gfx_v10_0_get_cpg_int_cntl(struct amdgpu_device *adev,
5340 				      int me, int pipe)
5341 {
5342 	if (me != 0)
5343 		return 0;
5344 
5345 	switch (pipe) {
5346 	case 0:
5347 		return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
5348 	case 1:
5349 		return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
5350 	default:
5351 		return 0;
5352 	}
5353 }
5354 
5355 static u32 gfx_v10_0_get_cpc_int_cntl(struct amdgpu_device *adev,
5356 				      int me, int pipe)
5357 {
5358 	/*
5359 	 * amdgpu controls only the first MEC. That's why this function only
5360 	 * handles the setting of interrupts for this specific MEC. All other
5361 	 * pipes' interrupts are set by amdkfd.
5362 	 */
5363 	if (me != 1)
5364 		return 0;
5365 
5366 	switch (pipe) {
5367 	case 0:
5368 		return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
5369 	case 1:
5370 		return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
5371 	case 2:
5372 		return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
5373 	case 3:
5374 		return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
5375 	default:
5376 		return 0;
5377 	}
5378 }
5379 
5380 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5381 					       bool enable)
5382 {
5383 	u32 tmp, cp_int_cntl_reg;
5384 	int i, j;
5385 
5386 	if (amdgpu_sriov_vf(adev))
5387 		return;
5388 
5389 	for (i = 0; i < adev->gfx.me.num_me; i++) {
5390 		for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
5391 			cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
5392 
5393 			if (cp_int_cntl_reg) {
5394 				tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
5395 				tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5396 						    enable ? 1 : 0);
5397 				tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5398 						    enable ? 1 : 0);
5399 				tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5400 						    enable ? 1 : 0);
5401 				tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5402 						    enable ? 1 : 0);
5403 				WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);
5404 			}
5405 		}
5406 	}
5407 }
5408 
5409 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5410 {
5411 	adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5412 
5413 	/* csib */
5414 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {
5415 		WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5416 				adev->gfx.rlc.clear_state_gpu_addr >> 32);
5417 		WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5418 				adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5419 		WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5420 	} else {
5421 		WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5422 				adev->gfx.rlc.clear_state_gpu_addr >> 32);
5423 		WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5424 				adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5425 		WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5426 	}
5427 	return 0;
5428 }
5429 
5430 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5431 {
5432 	u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5433 
5434 	tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5435 	WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5436 }
5437 
5438 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5439 {
5440 	WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5441 	udelay(50);
5442 	WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5443 	udelay(50);
5444 }
5445 
5446 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5447 					     bool enable)
5448 {
5449 	uint32_t rlc_pg_cntl;
5450 
5451 	rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5452 
5453 	if (!enable) {
5454 		/* RLC_PG_CNTL[23] = 0 (default)
5455 		 * RLC will wait for handshake acks with SMU
5456 		 * GFXOFF will be enabled
5457 		 * RLC_PG_CNTL[23] = 1
5458 		 * RLC will not issue any message to SMU
5459 		 * hence no handshake between SMU & RLC
5460 		 * GFXOFF will be disabled
5461 		 */
5462 		rlc_pg_cntl |= 0x800000;
5463 	} else
5464 		rlc_pg_cntl &= ~0x800000;
5465 	WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5466 }
5467 
5468 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5469 {
5470 	/*
5471 	 * TODO: enable rlc & smu handshake until smu
5472 	 * and gfxoff feature works as expected
5473 	 */
5474 	if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5475 		gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5476 
5477 	WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5478 	udelay(50);
5479 }
5480 
5481 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5482 {
5483 	uint32_t tmp;
5484 
5485 	/* enable Save Restore Machine */
5486 	tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5487 	tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5488 	tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5489 	WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5490 }
5491 
5492 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5493 {
5494 	const struct rlc_firmware_header_v2_0 *hdr;
5495 	const __le32 *fw_data;
5496 	unsigned int i, fw_size;
5497 
5498 	if (!adev->gfx.rlc_fw)
5499 		return -EINVAL;
5500 
5501 	hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5502 	amdgpu_ucode_print_rlc_hdr(&hdr->header);
5503 
5504 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5505 			   le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5506 	fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5507 
5508 	WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5509 		     RLCG_UCODE_LOADING_START_ADDRESS);
5510 
5511 	for (i = 0; i < fw_size; i++)
5512 		WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5513 			     le32_to_cpup(fw_data++));
5514 
5515 	WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5516 
5517 	return 0;
5518 }
5519 
5520 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5521 {
5522 	int r;
5523 
5524 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
5525 		adev->psp.autoload_supported) {
5526 
5527 		r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5528 		if (r)
5529 			return r;
5530 
5531 		gfx_v10_0_init_csb(adev);
5532 
5533 		gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
5534 
5535 		if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5536 			gfx_v10_0_rlc_enable_srm(adev);
5537 	} else {
5538 		if (amdgpu_sriov_vf(adev)) {
5539 			gfx_v10_0_init_csb(adev);
5540 			return 0;
5541 		}
5542 
5543 		adev->gfx.rlc.funcs->stop(adev);
5544 
5545 		/* disable CG */
5546 		WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5547 
5548 		/* disable PG */
5549 		WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5550 
5551 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5552 			/* legacy rlc firmware loading */
5553 			r = gfx_v10_0_rlc_load_microcode(adev);
5554 			if (r)
5555 				return r;
5556 		} else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5557 			/* rlc backdoor autoload firmware */
5558 			r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5559 			if (r)
5560 				return r;
5561 		}
5562 
5563 		gfx_v10_0_init_csb(adev);
5564 
5565 		gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
5566 
5567 		adev->gfx.rlc.funcs->start(adev);
5568 
5569 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5570 			r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5571 			if (r)
5572 				return r;
5573 		}
5574 	}
5575 
5576 	return 0;
5577 }
5578 
5579 static struct {
5580 	FIRMWARE_ID	id;
5581 	unsigned int	offset;
5582 	unsigned int	size;
5583 } rlc_autoload_info[FIRMWARE_ID_MAX];
5584 
5585 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5586 {
5587 	int ret;
5588 	RLC_TABLE_OF_CONTENT *rlc_toc;
5589 
5590 	ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE,
5591 					AMDGPU_GEM_DOMAIN_GTT,
5592 					&adev->gfx.rlc.rlc_toc_bo,
5593 					&adev->gfx.rlc.rlc_toc_gpu_addr,
5594 					(void **)&adev->gfx.rlc.rlc_toc_buf);
5595 	if (ret) {
5596 		dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5597 		return ret;
5598 	}
5599 
5600 	/* Copy toc from psp sos fw to rlc toc buffer */
5601 	memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);
5602 
5603 	rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5604 	while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5605 		(rlc_toc->id < FIRMWARE_ID_MAX)) {
5606 		if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5607 		    (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5608 			/* Offset needs 4KB alignment */
5609 			rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5610 		}
5611 
5612 		rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5613 		rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5614 		rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5615 
5616 		rlc_toc++;
5617 	}
5618 
5619 	return 0;
5620 }
5621 
5622 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5623 {
5624 	uint32_t total_size = 0;
5625 	FIRMWARE_ID id;
5626 	int ret;
5627 
5628 	ret = gfx_v10_0_parse_rlc_toc(adev);
5629 	if (ret) {
5630 		dev_err(adev->dev, "failed to parse rlc toc\n");
5631 		return 0;
5632 	}
5633 
5634 	for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5635 		total_size += rlc_autoload_info[id].size;
5636 
5637 	/* In case the offset in rlc toc ucode is aligned */
5638 	if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5639 		total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5640 				rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5641 
5642 	return total_size;
5643 }
5644 
5645 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5646 {
5647 	int r;
5648 	uint32_t total_size;
5649 
5650 	total_size = gfx_v10_0_calc_toc_total_size(adev);
5651 
5652 	r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5653 				      AMDGPU_GEM_DOMAIN_GTT,
5654 				      &adev->gfx.rlc.rlc_autoload_bo,
5655 				      &adev->gfx.rlc.rlc_autoload_gpu_addr,
5656 				      (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5657 	if (r) {
5658 		dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5659 		return r;
5660 	}
5661 
5662 	return 0;
5663 }
5664 
5665 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5666 {
5667 	amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5668 			      &adev->gfx.rlc.rlc_toc_gpu_addr,
5669 			      (void **)&adev->gfx.rlc.rlc_toc_buf);
5670 	amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5671 			      &adev->gfx.rlc.rlc_autoload_gpu_addr,
5672 			      (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5673 }
5674 
5675 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5676 						       FIRMWARE_ID id,
5677 						       const void *fw_data,
5678 						       uint32_t fw_size)
5679 {
5680 	uint32_t toc_offset;
5681 	uint32_t toc_fw_size;
5682 	char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5683 
5684 	if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5685 		return;
5686 
5687 	toc_offset = rlc_autoload_info[id].offset;
5688 	toc_fw_size = rlc_autoload_info[id].size;
5689 
5690 	if (fw_size == 0)
5691 		fw_size = toc_fw_size;
5692 
5693 	if (fw_size > toc_fw_size)
5694 		fw_size = toc_fw_size;
5695 
5696 	memcpy(ptr + toc_offset, fw_data, fw_size);
5697 
5698 	if (fw_size < toc_fw_size)
5699 		memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5700 }
5701 
5702 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5703 {
5704 	void *data;
5705 	uint32_t size;
5706 
5707 	data = adev->gfx.rlc.rlc_toc_buf;
5708 	size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5709 
5710 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5711 						   FIRMWARE_ID_RLC_TOC,
5712 						   data, size);
5713 }
5714 
5715 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5716 {
5717 	const __le32 *fw_data;
5718 	uint32_t fw_size;
5719 	const struct gfx_firmware_header_v1_0 *cp_hdr;
5720 	const struct rlc_firmware_header_v2_0 *rlc_hdr;
5721 
5722 	/* pfp ucode */
5723 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5724 		adev->gfx.pfp_fw->data;
5725 	fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5726 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5727 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5728 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5729 						   FIRMWARE_ID_CP_PFP,
5730 						   fw_data, fw_size);
5731 
5732 	/* ce ucode */
5733 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5734 		adev->gfx.ce_fw->data;
5735 	fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5736 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5737 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5738 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5739 						   FIRMWARE_ID_CP_CE,
5740 						   fw_data, fw_size);
5741 
5742 	/* me ucode */
5743 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5744 		adev->gfx.me_fw->data;
5745 	fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5746 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5747 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5748 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5749 						   FIRMWARE_ID_CP_ME,
5750 						   fw_data, fw_size);
5751 
5752 	/* rlc ucode */
5753 	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5754 		adev->gfx.rlc_fw->data;
5755 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5756 		le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5757 	fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5758 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5759 						   FIRMWARE_ID_RLC_G_UCODE,
5760 						   fw_data, fw_size);
5761 
5762 	/* mec1 ucode */
5763 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5764 		adev->gfx.mec_fw->data;
5765 	fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5766 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5767 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5768 		cp_hdr->jt_size * 4;
5769 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5770 						   FIRMWARE_ID_CP_MEC,
5771 						   fw_data, fw_size);
5772 	/* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5773 }
5774 
5775 /* Temporarily put sdma part here */
5776 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5777 {
5778 	const __le32 *fw_data;
5779 	uint32_t fw_size;
5780 	const struct sdma_firmware_header_v1_0 *sdma_hdr;
5781 	int i;
5782 
5783 	for (i = 0; i < adev->sdma.num_instances; i++) {
5784 		sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5785 			adev->sdma.instance[i].fw->data;
5786 		fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5787 			le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5788 		fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5789 
5790 		if (i == 0) {
5791 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5792 				FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5793 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5794 				FIRMWARE_ID_SDMA0_JT,
5795 				(uint32_t *)fw_data +
5796 				sdma_hdr->jt_offset,
5797 				sdma_hdr->jt_size * 4);
5798 		} else if (i == 1) {
5799 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5800 				FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5801 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5802 				FIRMWARE_ID_SDMA1_JT,
5803 				(uint32_t *)fw_data +
5804 				sdma_hdr->jt_offset,
5805 				sdma_hdr->jt_size * 4);
5806 		}
5807 	}
5808 }
5809 
5810 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5811 {
5812 	uint32_t rlc_g_offset, rlc_g_size, tmp;
5813 	uint64_t gpu_addr;
5814 
5815 	gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5816 	gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5817 	gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5818 
5819 	rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5820 	rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5821 	gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5822 
5823 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5824 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5825 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5826 
5827 	tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5828 	if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5829 		   RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5830 		DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5831 		return -EINVAL;
5832 	}
5833 
5834 	tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5835 	if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5836 		DRM_ERROR("RLC ROM should halt itself\n");
5837 		return -EINVAL;
5838 	}
5839 
5840 	return 0;
5841 }
5842 
5843 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5844 {
5845 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5846 	uint32_t tmp;
5847 	int i;
5848 	uint64_t addr;
5849 
5850 	/* Trigger an invalidation of the L1 instruction caches */
5851 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5852 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5853 	WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5854 
5855 	/* Wait for invalidation complete */
5856 	for (i = 0; i < usec_timeout; i++) {
5857 		tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5858 		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5859 			INVALIDATE_CACHE_COMPLETE))
5860 			break;
5861 		udelay(1);
5862 	}
5863 
5864 	if (i >= usec_timeout) {
5865 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5866 		return -EINVAL;
5867 	}
5868 
5869 	/* Program me ucode address into intruction cache address register */
5870 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5871 		rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5872 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5873 			lower_32_bits(addr) & 0xFFFFF000);
5874 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5875 			upper_32_bits(addr));
5876 
5877 	return 0;
5878 }
5879 
5880 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5881 {
5882 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5883 	uint32_t tmp;
5884 	int i;
5885 	uint64_t addr;
5886 
5887 	/* Trigger an invalidation of the L1 instruction caches */
5888 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5889 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5890 	WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5891 
5892 	/* Wait for invalidation complete */
5893 	for (i = 0; i < usec_timeout; i++) {
5894 		tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5895 		if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5896 			INVALIDATE_CACHE_COMPLETE))
5897 			break;
5898 		udelay(1);
5899 	}
5900 
5901 	if (i >= usec_timeout) {
5902 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5903 		return -EINVAL;
5904 	}
5905 
5906 	/* Program ce ucode address into intruction cache address register */
5907 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5908 		rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5909 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5910 			lower_32_bits(addr) & 0xFFFFF000);
5911 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5912 			upper_32_bits(addr));
5913 
5914 	return 0;
5915 }
5916 
5917 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5918 {
5919 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5920 	uint32_t tmp;
5921 	int i;
5922 	uint64_t addr;
5923 
5924 	/* Trigger an invalidation of the L1 instruction caches */
5925 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5926 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5927 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5928 
5929 	/* Wait for invalidation complete */
5930 	for (i = 0; i < usec_timeout; i++) {
5931 		tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5932 		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5933 			INVALIDATE_CACHE_COMPLETE))
5934 			break;
5935 		udelay(1);
5936 	}
5937 
5938 	if (i >= usec_timeout) {
5939 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5940 		return -EINVAL;
5941 	}
5942 
5943 	/* Program pfp ucode address into intruction cache address register */
5944 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5945 		rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5946 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5947 			lower_32_bits(addr) & 0xFFFFF000);
5948 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5949 			upper_32_bits(addr));
5950 
5951 	return 0;
5952 }
5953 
5954 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5955 {
5956 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5957 	uint32_t tmp;
5958 	int i;
5959 	uint64_t addr;
5960 
5961 	/* Trigger an invalidation of the L1 instruction caches */
5962 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5963 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5964 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5965 
5966 	/* Wait for invalidation complete */
5967 	for (i = 0; i < usec_timeout; i++) {
5968 		tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5969 		if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5970 			INVALIDATE_CACHE_COMPLETE))
5971 			break;
5972 		udelay(1);
5973 	}
5974 
5975 	if (i >= usec_timeout) {
5976 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5977 		return -EINVAL;
5978 	}
5979 
5980 	/* Program mec1 ucode address into intruction cache address register */
5981 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5982 		rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5983 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5984 			lower_32_bits(addr) & 0xFFFFF000);
5985 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5986 			upper_32_bits(addr));
5987 
5988 	return 0;
5989 }
5990 
5991 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5992 {
5993 	uint32_t cp_status;
5994 	uint32_t bootload_status;
5995 	int i, r;
5996 
5997 	for (i = 0; i < adev->usec_timeout; i++) {
5998 		cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5999 		bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
6000 		if ((cp_status == 0) &&
6001 		    (REG_GET_FIELD(bootload_status,
6002 			RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
6003 			break;
6004 		}
6005 		udelay(1);
6006 	}
6007 
6008 	if (i >= adev->usec_timeout) {
6009 		dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
6010 		return -ETIMEDOUT;
6011 	}
6012 
6013 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
6014 		r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
6015 		if (r)
6016 			return r;
6017 
6018 		r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
6019 		if (r)
6020 			return r;
6021 
6022 		r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
6023 		if (r)
6024 			return r;
6025 
6026 		r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
6027 		if (r)
6028 			return r;
6029 	}
6030 
6031 	return 0;
6032 }
6033 
6034 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
6035 {
6036 	int i;
6037 	u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
6038 
6039 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
6040 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
6041 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
6042 
6043 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))
6044 		WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
6045 	else
6046 		WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
6047 
6048 	if (amdgpu_in_reset(adev) && !enable)
6049 		return 0;
6050 
6051 	for (i = 0; i < adev->usec_timeout; i++) {
6052 		if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
6053 			break;
6054 		udelay(1);
6055 	}
6056 
6057 	if (i >= adev->usec_timeout)
6058 		DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
6059 
6060 	return 0;
6061 }
6062 
6063 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
6064 {
6065 	int r;
6066 	const struct gfx_firmware_header_v1_0 *pfp_hdr;
6067 	const __le32 *fw_data;
6068 	unsigned int i, fw_size;
6069 	uint32_t tmp;
6070 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
6071 
6072 	pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
6073 		adev->gfx.pfp_fw->data;
6074 
6075 	amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
6076 
6077 	fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
6078 		le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
6079 	fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
6080 
6081 	r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
6082 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6083 				      &adev->gfx.pfp.pfp_fw_obj,
6084 				      &adev->gfx.pfp.pfp_fw_gpu_addr,
6085 				      (void **)&adev->gfx.pfp.pfp_fw_ptr);
6086 	if (r) {
6087 		dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
6088 		gfx_v10_0_pfp_fini(adev);
6089 		return r;
6090 	}
6091 
6092 	memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
6093 
6094 	amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
6095 	amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
6096 
6097 	/* Trigger an invalidation of the L1 instruction caches */
6098 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
6099 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6100 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
6101 
6102 	/* Wait for invalidation complete */
6103 	for (i = 0; i < usec_timeout; i++) {
6104 		tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
6105 		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
6106 			INVALIDATE_CACHE_COMPLETE))
6107 			break;
6108 		udelay(1);
6109 	}
6110 
6111 	if (i >= usec_timeout) {
6112 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
6113 		return -EINVAL;
6114 	}
6115 
6116 	if (amdgpu_emu_mode == 1)
6117 		adev->hdp.funcs->flush_hdp(adev, NULL);
6118 
6119 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
6120 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
6121 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
6122 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
6123 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6124 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
6125 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
6126 		adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
6127 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
6128 		upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
6129 
6130 	WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
6131 
6132 	for (i = 0; i < pfp_hdr->jt_size; i++)
6133 		WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
6134 			     le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
6135 
6136 	WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
6137 
6138 	return 0;
6139 }
6140 
6141 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
6142 {
6143 	int r;
6144 	const struct gfx_firmware_header_v1_0 *ce_hdr;
6145 	const __le32 *fw_data;
6146 	unsigned int i, fw_size;
6147 	uint32_t tmp;
6148 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
6149 
6150 	ce_hdr = (const struct gfx_firmware_header_v1_0 *)
6151 		adev->gfx.ce_fw->data;
6152 
6153 	amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
6154 
6155 	fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
6156 		le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
6157 	fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
6158 
6159 	r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
6160 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6161 				      &adev->gfx.ce.ce_fw_obj,
6162 				      &adev->gfx.ce.ce_fw_gpu_addr,
6163 				      (void **)&adev->gfx.ce.ce_fw_ptr);
6164 	if (r) {
6165 		dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
6166 		gfx_v10_0_ce_fini(adev);
6167 		return r;
6168 	}
6169 
6170 	memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
6171 
6172 	amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
6173 	amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
6174 
6175 	/* Trigger an invalidation of the L1 instruction caches */
6176 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6177 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6178 	WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
6179 
6180 	/* Wait for invalidation complete */
6181 	for (i = 0; i < usec_timeout; i++) {
6182 		tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6183 		if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
6184 			INVALIDATE_CACHE_COMPLETE))
6185 			break;
6186 		udelay(1);
6187 	}
6188 
6189 	if (i >= usec_timeout) {
6190 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
6191 		return -EINVAL;
6192 	}
6193 
6194 	if (amdgpu_emu_mode == 1)
6195 		adev->hdp.funcs->flush_hdp(adev, NULL);
6196 
6197 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
6198 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
6199 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
6200 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
6201 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6202 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
6203 		adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
6204 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
6205 		upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
6206 
6207 	WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
6208 
6209 	for (i = 0; i < ce_hdr->jt_size; i++)
6210 		WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
6211 			     le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
6212 
6213 	WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
6214 
6215 	return 0;
6216 }
6217 
6218 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
6219 {
6220 	int r;
6221 	const struct gfx_firmware_header_v1_0 *me_hdr;
6222 	const __le32 *fw_data;
6223 	unsigned int i, fw_size;
6224 	uint32_t tmp;
6225 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
6226 
6227 	me_hdr = (const struct gfx_firmware_header_v1_0 *)
6228 		adev->gfx.me_fw->data;
6229 
6230 	amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
6231 
6232 	fw_data = (const __le32 *)(adev->gfx.me_fw->data +
6233 		le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
6234 	fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
6235 
6236 	r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
6237 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6238 				      &adev->gfx.me.me_fw_obj,
6239 				      &adev->gfx.me.me_fw_gpu_addr,
6240 				      (void **)&adev->gfx.me.me_fw_ptr);
6241 	if (r) {
6242 		dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
6243 		gfx_v10_0_me_fini(adev);
6244 		return r;
6245 	}
6246 
6247 	memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
6248 
6249 	amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
6250 	amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
6251 
6252 	/* Trigger an invalidation of the L1 instruction caches */
6253 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6254 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6255 	WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
6256 
6257 	/* Wait for invalidation complete */
6258 	for (i = 0; i < usec_timeout; i++) {
6259 		tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6260 		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
6261 			INVALIDATE_CACHE_COMPLETE))
6262 			break;
6263 		udelay(1);
6264 	}
6265 
6266 	if (i >= usec_timeout) {
6267 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
6268 		return -EINVAL;
6269 	}
6270 
6271 	if (amdgpu_emu_mode == 1)
6272 		adev->hdp.funcs->flush_hdp(adev, NULL);
6273 
6274 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
6275 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
6276 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
6277 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
6278 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6279 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
6280 		adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
6281 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
6282 		upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
6283 
6284 	WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
6285 
6286 	for (i = 0; i < me_hdr->jt_size; i++)
6287 		WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
6288 			     le32_to_cpup(fw_data + me_hdr->jt_offset + i));
6289 
6290 	WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
6291 
6292 	return 0;
6293 }
6294 
6295 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
6296 {
6297 	int r;
6298 
6299 	if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
6300 		return -EINVAL;
6301 
6302 	gfx_v10_0_cp_gfx_enable(adev, false);
6303 
6304 	r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
6305 	if (r) {
6306 		dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
6307 		return r;
6308 	}
6309 
6310 	r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
6311 	if (r) {
6312 		dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
6313 		return r;
6314 	}
6315 
6316 	r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6317 	if (r) {
6318 		dev_err(adev->dev, "(%d) failed to load me fw\n", r);
6319 		return r;
6320 	}
6321 
6322 	return 0;
6323 }
6324 
6325 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6326 {
6327 	struct amdgpu_ring *ring;
6328 	const struct cs_section_def *sect = NULL;
6329 	const struct cs_extent_def *ext = NULL;
6330 	int r, i;
6331 	int ctx_reg_offset;
6332 
6333 	/* init the CP */
6334 	WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
6335 		     adev->gfx.config.max_hw_contexts - 1);
6336 	WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
6337 
6338 	gfx_v10_0_cp_gfx_enable(adev, true);
6339 
6340 	ring = &adev->gfx.gfx_ring[0];
6341 	r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6342 	if (r) {
6343 		DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6344 		return r;
6345 	}
6346 
6347 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6348 	amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6349 
6350 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6351 	amdgpu_ring_write(ring, 0x80000000);
6352 	amdgpu_ring_write(ring, 0x80000000);
6353 
6354 	for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
6355 		for (ext = sect->section; ext->extent != NULL; ++ext) {
6356 			if (sect->id == SECT_CONTEXT) {
6357 				amdgpu_ring_write(ring,
6358 						  PACKET3(PACKET3_SET_CONTEXT_REG,
6359 							  ext->reg_count));
6360 				amdgpu_ring_write(ring, ext->reg_index -
6361 						  PACKET3_SET_CONTEXT_REG_START);
6362 				for (i = 0; i < ext->reg_count; i++)
6363 					amdgpu_ring_write(ring, ext->extent[i]);
6364 			}
6365 		}
6366 	}
6367 
6368 	ctx_reg_offset =
6369 		SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6370 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6371 	amdgpu_ring_write(ring, ctx_reg_offset);
6372 	amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6373 
6374 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6375 	amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6376 
6377 	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6378 	amdgpu_ring_write(ring, 0);
6379 
6380 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6381 	amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6382 	amdgpu_ring_write(ring, 0x8000);
6383 	amdgpu_ring_write(ring, 0x8000);
6384 
6385 	amdgpu_ring_commit(ring);
6386 
6387 	/* submit cs packet to copy state 0 to next available state */
6388 	if (adev->gfx.num_gfx_rings > 1) {
6389 		/* maximum supported gfx ring is 2 */
6390 		ring = &adev->gfx.gfx_ring[1];
6391 		r = amdgpu_ring_alloc(ring, 2);
6392 		if (r) {
6393 			DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6394 			return r;
6395 		}
6396 
6397 		amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6398 		amdgpu_ring_write(ring, 0);
6399 
6400 		amdgpu_ring_commit(ring);
6401 	}
6402 	return 0;
6403 }
6404 
6405 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6406 					 CP_PIPE_ID pipe)
6407 {
6408 	u32 tmp;
6409 
6410 	tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6411 	tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6412 
6413 	WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6414 }
6415 
6416 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6417 					  struct amdgpu_ring *ring)
6418 {
6419 	u32 tmp;
6420 
6421 	if (!amdgpu_async_gfx_ring) {
6422 		tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6423 		if (ring->use_doorbell) {
6424 			tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6425 						DOORBELL_OFFSET, ring->doorbell_index);
6426 			tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6427 						DOORBELL_EN, 1);
6428 		} else {
6429 			tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6430 						DOORBELL_EN, 0);
6431 		}
6432 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6433 	}
6434 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6435 	case IP_VERSION(10, 3, 0):
6436 	case IP_VERSION(10, 3, 2):
6437 	case IP_VERSION(10, 3, 1):
6438 	case IP_VERSION(10, 3, 4):
6439 	case IP_VERSION(10, 3, 5):
6440 	case IP_VERSION(10, 3, 6):
6441 	case IP_VERSION(10, 3, 3):
6442 	case IP_VERSION(10, 3, 7):
6443 		tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6444 				    DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6445 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6446 
6447 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6448 			     CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6449 		break;
6450 	default:
6451 		tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6452 				    DOORBELL_RANGE_LOWER, ring->doorbell_index);
6453 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6454 
6455 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6456 			     CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6457 		break;
6458 	}
6459 }
6460 
6461 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6462 {
6463 	struct amdgpu_ring *ring;
6464 	u32 tmp;
6465 	u32 rb_bufsz;
6466 	u64 rb_addr, rptr_addr, wptr_gpu_addr;
6467 
6468 	/* Set the write pointer delay */
6469 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6470 
6471 	/* set the RB to use vmid 0 */
6472 	WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6473 
6474 	/* Init gfx ring 0 for pipe 0 */
6475 	mutex_lock(&adev->srbm_mutex);
6476 	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6477 
6478 	/* Set ring buffer size */
6479 	ring = &adev->gfx.gfx_ring[0];
6480 	rb_bufsz = order_base_2(ring->ring_size / 8);
6481 	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6482 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6483 #ifdef __BIG_ENDIAN
6484 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6485 #endif
6486 	WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6487 
6488 	/* Initialize the ring buffer's write pointers */
6489 	ring->wptr = 0;
6490 	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6491 	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6492 
6493 	/* set the wb address whether it's enabled or not */
6494 	rptr_addr = ring->rptr_gpu_addr;
6495 	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6496 	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6497 		     CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6498 
6499 	wptr_gpu_addr = ring->wptr_gpu_addr;
6500 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6501 		     lower_32_bits(wptr_gpu_addr));
6502 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6503 		     upper_32_bits(wptr_gpu_addr));
6504 
6505 	mdelay(1);
6506 	WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6507 
6508 	rb_addr = ring->gpu_addr >> 8;
6509 	WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6510 	WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6511 
6512 	WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6513 
6514 	gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6515 	mutex_unlock(&adev->srbm_mutex);
6516 
6517 	/* Init gfx ring 1 for pipe 1 */
6518 	if (adev->gfx.num_gfx_rings > 1) {
6519 		mutex_lock(&adev->srbm_mutex);
6520 		gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6521 		/* maximum supported gfx ring is 2 */
6522 		ring = &adev->gfx.gfx_ring[1];
6523 		rb_bufsz = order_base_2(ring->ring_size / 8);
6524 		tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6525 		tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6526 		WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6527 		/* Initialize the ring buffer's write pointers */
6528 		ring->wptr = 0;
6529 		WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6530 		WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6531 		/* Set the wb address whether it's enabled or not */
6532 		rptr_addr = ring->rptr_gpu_addr;
6533 		WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6534 		WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6535 			     CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6536 		wptr_gpu_addr = ring->wptr_gpu_addr;
6537 		WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6538 			     lower_32_bits(wptr_gpu_addr));
6539 		WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6540 			     upper_32_bits(wptr_gpu_addr));
6541 
6542 		mdelay(1);
6543 		WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6544 
6545 		rb_addr = ring->gpu_addr >> 8;
6546 		WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6547 		WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6548 		WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6549 
6550 		gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6551 		mutex_unlock(&adev->srbm_mutex);
6552 	}
6553 	/* Switch to pipe 0 */
6554 	mutex_lock(&adev->srbm_mutex);
6555 	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6556 	mutex_unlock(&adev->srbm_mutex);
6557 
6558 	/* start the ring */
6559 	gfx_v10_0_cp_gfx_start(adev);
6560 
6561 	return 0;
6562 }
6563 
6564 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6565 {
6566 	if (enable) {
6567 		switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6568 		case IP_VERSION(10, 3, 0):
6569 		case IP_VERSION(10, 3, 2):
6570 		case IP_VERSION(10, 3, 1):
6571 		case IP_VERSION(10, 3, 4):
6572 		case IP_VERSION(10, 3, 5):
6573 		case IP_VERSION(10, 3, 6):
6574 		case IP_VERSION(10, 3, 3):
6575 		case IP_VERSION(10, 3, 7):
6576 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6577 			break;
6578 		default:
6579 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6580 			break;
6581 		}
6582 	} else {
6583 		switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6584 		case IP_VERSION(10, 3, 0):
6585 		case IP_VERSION(10, 3, 2):
6586 		case IP_VERSION(10, 3, 1):
6587 		case IP_VERSION(10, 3, 4):
6588 		case IP_VERSION(10, 3, 5):
6589 		case IP_VERSION(10, 3, 6):
6590 		case IP_VERSION(10, 3, 3):
6591 		case IP_VERSION(10, 3, 7):
6592 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6593 				     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6594 				      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6595 			break;
6596 		default:
6597 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6598 				     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6599 				      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6600 			break;
6601 		}
6602 		adev->gfx.kiq[0].ring.sched.ready = false;
6603 	}
6604 	udelay(50);
6605 }
6606 
6607 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6608 {
6609 	const struct gfx_firmware_header_v1_0 *mec_hdr;
6610 	const __le32 *fw_data;
6611 	unsigned int i;
6612 	u32 tmp;
6613 	u32 usec_timeout = 50000; /* Wait for 50 ms */
6614 
6615 	if (!adev->gfx.mec_fw)
6616 		return -EINVAL;
6617 
6618 	gfx_v10_0_cp_compute_enable(adev, false);
6619 
6620 	mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6621 	amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6622 
6623 	fw_data = (const __le32 *)
6624 		(adev->gfx.mec_fw->data +
6625 		 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6626 
6627 	/* Trigger an invalidation of the L1 instruction caches */
6628 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6629 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6630 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6631 
6632 	/* Wait for invalidation complete */
6633 	for (i = 0; i < usec_timeout; i++) {
6634 		tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6635 		if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6636 				       INVALIDATE_CACHE_COMPLETE))
6637 			break;
6638 		udelay(1);
6639 	}
6640 
6641 	if (i >= usec_timeout) {
6642 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
6643 		return -EINVAL;
6644 	}
6645 
6646 	if (amdgpu_emu_mode == 1)
6647 		adev->hdp.funcs->flush_hdp(adev, NULL);
6648 
6649 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6650 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6651 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6652 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6653 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6654 
6655 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6656 		     0xFFFFF000);
6657 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6658 		     upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6659 
6660 	/* MEC1 */
6661 	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6662 
6663 	for (i = 0; i < mec_hdr->jt_size; i++)
6664 		WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6665 			     le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6666 
6667 	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6668 
6669 	/*
6670 	 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6671 	 * different microcode than MEC1.
6672 	 */
6673 
6674 	return 0;
6675 }
6676 
6677 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6678 {
6679 	uint32_t tmp;
6680 	struct amdgpu_device *adev = ring->adev;
6681 
6682 	/* tell RLC which is KIQ queue */
6683 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6684 	case IP_VERSION(10, 3, 0):
6685 	case IP_VERSION(10, 3, 2):
6686 	case IP_VERSION(10, 3, 1):
6687 	case IP_VERSION(10, 3, 4):
6688 	case IP_VERSION(10, 3, 5):
6689 	case IP_VERSION(10, 3, 6):
6690 	case IP_VERSION(10, 3, 3):
6691 	case IP_VERSION(10, 3, 7):
6692 		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6693 		tmp &= 0xffffff00;
6694 		tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6695 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp | 0x80);
6696 		break;
6697 	default:
6698 		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6699 		tmp &= 0xffffff00;
6700 		tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6701 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp | 0x80);
6702 		break;
6703 	}
6704 }
6705 
6706 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev,
6707 					   struct v10_gfx_mqd *mqd,
6708 					   struct amdgpu_mqd_prop *prop)
6709 {
6710 	bool priority = 0;
6711 	u32 tmp;
6712 
6713 	/* set up default queue priority level
6714 	 * 0x0 = low priority, 0x1 = high priority
6715 	 */
6716 	if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)
6717 		priority = 1;
6718 
6719 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6720 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
6721 	mqd->cp_gfx_hqd_queue_priority = tmp;
6722 }
6723 
6724 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
6725 				  struct amdgpu_mqd_prop *prop)
6726 {
6727 	struct v10_gfx_mqd *mqd = m;
6728 	uint64_t hqd_gpu_addr, wb_gpu_addr;
6729 	uint32_t tmp;
6730 	uint32_t rb_bufsz;
6731 
6732 	/* set up gfx hqd wptr */
6733 	mqd->cp_gfx_hqd_wptr = 0;
6734 	mqd->cp_gfx_hqd_wptr_hi = 0;
6735 
6736 	/* set the pointer to the MQD */
6737 	mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
6738 	mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6739 
6740 	/* set up mqd control */
6741 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6742 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6743 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6744 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6745 	mqd->cp_gfx_mqd_control = tmp;
6746 
6747 	/* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6748 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6749 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6750 	mqd->cp_gfx_hqd_vmid = 0;
6751 
6752 	/* set up gfx queue priority */
6753 	gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop);
6754 
6755 	/* set up time quantum */
6756 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6757 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6758 	mqd->cp_gfx_hqd_quantum = tmp;
6759 
6760 	/* set up gfx hqd base. this is similar as CP_RB_BASE */
6761 	hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6762 	mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6763 	mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6764 
6765 	/* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6766 	wb_gpu_addr = prop->rptr_gpu_addr;
6767 	mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6768 	mqd->cp_gfx_hqd_rptr_addr_hi =
6769 		upper_32_bits(wb_gpu_addr) & 0xffff;
6770 
6771 	/* set up rb_wptr_poll addr */
6772 	wb_gpu_addr = prop->wptr_gpu_addr;
6773 	mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6774 	mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6775 
6776 	/* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6777 	rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
6778 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6779 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6780 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6781 #ifdef __BIG_ENDIAN
6782 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6783 #endif
6784 	mqd->cp_gfx_hqd_cntl = tmp;
6785 
6786 	/* set up cp_doorbell_control */
6787 	tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6788 	if (prop->use_doorbell) {
6789 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6790 				    DOORBELL_OFFSET, prop->doorbell_index);
6791 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6792 				    DOORBELL_EN, 1);
6793 	} else
6794 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6795 				    DOORBELL_EN, 0);
6796 	mqd->cp_rb_doorbell_control = tmp;
6797 
6798 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6799 	mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6800 
6801 	/* active the queue */
6802 	mqd->cp_gfx_hqd_active = 1;
6803 
6804 	return 0;
6805 }
6806 
6807 static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)
6808 {
6809 	struct amdgpu_device *adev = ring->adev;
6810 	struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6811 	int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6812 
6813 	if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) {
6814 		memset((void *)mqd, 0, sizeof(*mqd));
6815 		mutex_lock(&adev->srbm_mutex);
6816 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6817 		amdgpu_ring_init_mqd(ring);
6818 
6819 		/*
6820 		 * if there are 2 gfx rings, set the lower doorbell
6821 		 * range of the first ring, otherwise the range of
6822 		 * the second ring will override the first ring
6823 		 */
6824 		if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6825 			gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6826 
6827 		nv_grbm_select(adev, 0, 0, 0, 0);
6828 		mutex_unlock(&adev->srbm_mutex);
6829 		if (adev->gfx.me.mqd_backup[mqd_idx])
6830 			memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6831 	} else {
6832 		mutex_lock(&adev->srbm_mutex);
6833 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6834 		if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6835 			gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6836 
6837 		nv_grbm_select(adev, 0, 0, 0, 0);
6838 		mutex_unlock(&adev->srbm_mutex);
6839 		/* restore mqd with the backup copy */
6840 		if (adev->gfx.me.mqd_backup[mqd_idx])
6841 			memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6842 		/* reset the ring */
6843 		ring->wptr = 0;
6844 		*ring->wptr_cpu_addr = 0;
6845 		amdgpu_ring_clear_ring(ring);
6846 	}
6847 
6848 	return 0;
6849 }
6850 
6851 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6852 {
6853 	int r, i;
6854 	struct amdgpu_ring *ring;
6855 
6856 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6857 		ring = &adev->gfx.gfx_ring[i];
6858 
6859 		r = amdgpu_bo_reserve(ring->mqd_obj, false);
6860 		if (unlikely(r != 0))
6861 			return r;
6862 
6863 		r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6864 		if (!r) {
6865 			r = gfx_v10_0_kgq_init_queue(ring, false);
6866 			amdgpu_bo_kunmap(ring->mqd_obj);
6867 			ring->mqd_ptr = NULL;
6868 		}
6869 		amdgpu_bo_unreserve(ring->mqd_obj);
6870 		if (r)
6871 			return r;
6872 	}
6873 
6874 	r = amdgpu_gfx_enable_kgq(adev, 0);
6875 	if (r)
6876 		return r;
6877 
6878 	return gfx_v10_0_cp_gfx_start(adev);
6879 }
6880 
6881 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
6882 				      struct amdgpu_mqd_prop *prop)
6883 {
6884 	struct v10_compute_mqd *mqd = m;
6885 	uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6886 	uint32_t tmp;
6887 
6888 	mqd->header = 0xC0310800;
6889 	mqd->compute_pipelinestat_enable = 0x00000001;
6890 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6891 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6892 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6893 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6894 	mqd->compute_misc_reserved = 0x00000003;
6895 
6896 	eop_base_addr = prop->eop_gpu_addr >> 8;
6897 	mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6898 	mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6899 
6900 	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6901 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6902 	tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6903 			(order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6904 
6905 	mqd->cp_hqd_eop_control = tmp;
6906 
6907 	/* enable doorbell? */
6908 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6909 
6910 	if (prop->use_doorbell) {
6911 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6912 				    DOORBELL_OFFSET, prop->doorbell_index);
6913 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6914 				    DOORBELL_EN, 1);
6915 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6916 				    DOORBELL_SOURCE, 0);
6917 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6918 				    DOORBELL_HIT, 0);
6919 	} else {
6920 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6921 				    DOORBELL_EN, 0);
6922 	}
6923 
6924 	mqd->cp_hqd_pq_doorbell_control = tmp;
6925 
6926 	/* disable the queue if it's active */
6927 	mqd->cp_hqd_dequeue_request = 0;
6928 	mqd->cp_hqd_pq_rptr = 0;
6929 	mqd->cp_hqd_pq_wptr_lo = 0;
6930 	mqd->cp_hqd_pq_wptr_hi = 0;
6931 
6932 	/* set the pointer to the MQD */
6933 	mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
6934 	mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6935 
6936 	/* set MQD vmid to 0 */
6937 	tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6938 	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6939 	mqd->cp_mqd_control = tmp;
6940 
6941 	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6942 	hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6943 	mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6944 	mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6945 
6946 	/* set up the HQD, this is similar to CP_RB0_CNTL */
6947 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6948 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6949 			    (order_base_2(prop->queue_size / 4) - 1));
6950 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6951 			    (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
6952 #ifdef __BIG_ENDIAN
6953 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6954 #endif
6955 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
6956 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,
6957 			    prop->allow_tunneling);
6958 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6959 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6960 	mqd->cp_hqd_pq_control = tmp;
6961 
6962 	/* set the wb address whether it's enabled or not */
6963 	wb_gpu_addr = prop->rptr_gpu_addr;
6964 	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6965 	mqd->cp_hqd_pq_rptr_report_addr_hi =
6966 		upper_32_bits(wb_gpu_addr) & 0xffff;
6967 
6968 	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6969 	wb_gpu_addr = prop->wptr_gpu_addr;
6970 	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6971 	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6972 
6973 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6974 	mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6975 
6976 	/* set the vmid for the queue */
6977 	mqd->cp_hqd_vmid = 0;
6978 
6979 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6980 	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6981 	mqd->cp_hqd_persistent_state = tmp;
6982 
6983 	/* set MIN_IB_AVAIL_SIZE */
6984 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6985 	tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6986 	mqd->cp_hqd_ib_control = tmp;
6987 
6988 	/* set static priority for a compute queue/ring */
6989 	mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
6990 	mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
6991 
6992 	mqd->cp_hqd_active = prop->hqd_active;
6993 
6994 	return 0;
6995 }
6996 
6997 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6998 {
6999 	struct amdgpu_device *adev = ring->adev;
7000 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
7001 	int j;
7002 
7003 	/* inactivate the queue */
7004 	if (amdgpu_sriov_vf(adev))
7005 		WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
7006 
7007 	/* disable wptr polling */
7008 	WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
7009 
7010 	/* disable the queue if it's active */
7011 	if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
7012 		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
7013 		for (j = 0; j < adev->usec_timeout; j++) {
7014 			if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
7015 				break;
7016 			udelay(1);
7017 		}
7018 		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
7019 		       mqd->cp_hqd_dequeue_request);
7020 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
7021 		       mqd->cp_hqd_pq_rptr);
7022 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
7023 		       mqd->cp_hqd_pq_wptr_lo);
7024 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
7025 		       mqd->cp_hqd_pq_wptr_hi);
7026 	}
7027 
7028 	/* disable doorbells */
7029 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
7030 
7031 	/* write the EOP addr */
7032 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
7033 	       mqd->cp_hqd_eop_base_addr_lo);
7034 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
7035 	       mqd->cp_hqd_eop_base_addr_hi);
7036 
7037 	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
7038 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
7039 	       mqd->cp_hqd_eop_control);
7040 
7041 	/* set the pointer to the MQD */
7042 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
7043 	       mqd->cp_mqd_base_addr_lo);
7044 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
7045 	       mqd->cp_mqd_base_addr_hi);
7046 
7047 	/* set MQD vmid to 0 */
7048 	WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
7049 	       mqd->cp_mqd_control);
7050 
7051 	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
7052 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
7053 	       mqd->cp_hqd_pq_base_lo);
7054 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
7055 	       mqd->cp_hqd_pq_base_hi);
7056 
7057 	/* set up the HQD, this is similar to CP_RB0_CNTL */
7058 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
7059 	       mqd->cp_hqd_pq_control);
7060 
7061 	/* set the wb address whether it's enabled or not */
7062 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
7063 		mqd->cp_hqd_pq_rptr_report_addr_lo);
7064 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
7065 		mqd->cp_hqd_pq_rptr_report_addr_hi);
7066 
7067 	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
7068 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
7069 	       mqd->cp_hqd_pq_wptr_poll_addr_lo);
7070 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
7071 	       mqd->cp_hqd_pq_wptr_poll_addr_hi);
7072 
7073 	/* enable the doorbell if requested */
7074 	if (ring->use_doorbell) {
7075 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
7076 			(adev->doorbell_index.kiq * 2) << 2);
7077 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
7078 			(adev->doorbell_index.userqueue_end * 2) << 2);
7079 	}
7080 
7081 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
7082 	       mqd->cp_hqd_pq_doorbell_control);
7083 
7084 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
7085 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
7086 	       mqd->cp_hqd_pq_wptr_lo);
7087 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
7088 	       mqd->cp_hqd_pq_wptr_hi);
7089 
7090 	/* set the vmid for the queue */
7091 	WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
7092 
7093 	WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
7094 	       mqd->cp_hqd_persistent_state);
7095 
7096 	/* activate the queue */
7097 	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
7098 	       mqd->cp_hqd_active);
7099 
7100 	if (ring->use_doorbell)
7101 		WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
7102 
7103 	return 0;
7104 }
7105 
7106 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
7107 {
7108 	struct amdgpu_device *adev = ring->adev;
7109 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
7110 
7111 	gfx_v10_0_kiq_setting(ring);
7112 
7113 	if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7114 		/* reset MQD to a clean status */
7115 		if (adev->gfx.kiq[0].mqd_backup)
7116 			memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd));
7117 
7118 		/* reset ring buffer */
7119 		ring->wptr = 0;
7120 		amdgpu_ring_clear_ring(ring);
7121 
7122 		mutex_lock(&adev->srbm_mutex);
7123 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7124 		gfx_v10_0_kiq_init_register(ring);
7125 		nv_grbm_select(adev, 0, 0, 0, 0);
7126 		mutex_unlock(&adev->srbm_mutex);
7127 	} else {
7128 		memset((void *)mqd, 0, sizeof(*mqd));
7129 		if (amdgpu_sriov_vf(adev) && adev->in_suspend)
7130 			amdgpu_ring_clear_ring(ring);
7131 		mutex_lock(&adev->srbm_mutex);
7132 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7133 		amdgpu_ring_init_mqd(ring);
7134 		gfx_v10_0_kiq_init_register(ring);
7135 		nv_grbm_select(adev, 0, 0, 0, 0);
7136 		mutex_unlock(&adev->srbm_mutex);
7137 
7138 		if (adev->gfx.kiq[0].mqd_backup)
7139 			memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd));
7140 	}
7141 
7142 	return 0;
7143 }
7144 
7145 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring, bool restore)
7146 {
7147 	struct amdgpu_device *adev = ring->adev;
7148 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
7149 	int mqd_idx = ring - &adev->gfx.compute_ring[0];
7150 
7151 	if (!restore && !amdgpu_in_reset(adev) && !adev->in_suspend) {
7152 		memset((void *)mqd, 0, sizeof(*mqd));
7153 		mutex_lock(&adev->srbm_mutex);
7154 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7155 		amdgpu_ring_init_mqd(ring);
7156 		nv_grbm_select(adev, 0, 0, 0, 0);
7157 		mutex_unlock(&adev->srbm_mutex);
7158 
7159 		if (adev->gfx.mec.mqd_backup[mqd_idx])
7160 			memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7161 	} else {
7162 		/* restore MQD to a clean status */
7163 		if (adev->gfx.mec.mqd_backup[mqd_idx])
7164 			memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7165 		/* reset ring buffer */
7166 		ring->wptr = 0;
7167 		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
7168 		amdgpu_ring_clear_ring(ring);
7169 	}
7170 
7171 	return 0;
7172 }
7173 
7174 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
7175 {
7176 	struct amdgpu_ring *ring;
7177 	int r;
7178 
7179 	ring = &adev->gfx.kiq[0].ring;
7180 
7181 	r = amdgpu_bo_reserve(ring->mqd_obj, false);
7182 	if (unlikely(r != 0))
7183 		return r;
7184 
7185 	r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7186 	if (unlikely(r != 0)) {
7187 		amdgpu_bo_unreserve(ring->mqd_obj);
7188 		return r;
7189 	}
7190 
7191 	gfx_v10_0_kiq_init_queue(ring);
7192 	amdgpu_bo_kunmap(ring->mqd_obj);
7193 	ring->mqd_ptr = NULL;
7194 	amdgpu_bo_unreserve(ring->mqd_obj);
7195 	return 0;
7196 }
7197 
7198 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
7199 {
7200 	struct amdgpu_ring *ring = NULL;
7201 	int r = 0, i;
7202 
7203 	gfx_v10_0_cp_compute_enable(adev, true);
7204 
7205 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7206 		ring = &adev->gfx.compute_ring[i];
7207 
7208 		r = amdgpu_bo_reserve(ring->mqd_obj, false);
7209 		if (unlikely(r != 0))
7210 			goto done;
7211 		r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7212 		if (!r) {
7213 			r = gfx_v10_0_kcq_init_queue(ring, false);
7214 			amdgpu_bo_kunmap(ring->mqd_obj);
7215 			ring->mqd_ptr = NULL;
7216 		}
7217 		amdgpu_bo_unreserve(ring->mqd_obj);
7218 		if (r)
7219 			goto done;
7220 	}
7221 
7222 	r = amdgpu_gfx_enable_kcq(adev, 0);
7223 done:
7224 	return r;
7225 }
7226 
7227 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
7228 {
7229 	int r, i;
7230 	struct amdgpu_ring *ring;
7231 
7232 	if (!(adev->flags & AMD_IS_APU))
7233 		gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7234 
7235 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7236 		/* legacy firmware loading */
7237 		r = gfx_v10_0_cp_gfx_load_microcode(adev);
7238 		if (r)
7239 			return r;
7240 
7241 		r = gfx_v10_0_cp_compute_load_microcode(adev);
7242 		if (r)
7243 			return r;
7244 	}
7245 
7246 	r = gfx_v10_0_kiq_resume(adev);
7247 	if (r)
7248 		return r;
7249 
7250 	r = gfx_v10_0_kcq_resume(adev);
7251 	if (r)
7252 		return r;
7253 
7254 	if (!amdgpu_async_gfx_ring) {
7255 		r = gfx_v10_0_cp_gfx_resume(adev);
7256 		if (r)
7257 			return r;
7258 	} else {
7259 		r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7260 		if (r)
7261 			return r;
7262 	}
7263 
7264 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7265 		ring = &adev->gfx.gfx_ring[i];
7266 		r = amdgpu_ring_test_helper(ring);
7267 		if (r)
7268 			return r;
7269 	}
7270 
7271 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7272 		ring = &adev->gfx.compute_ring[i];
7273 		r = amdgpu_ring_test_helper(ring);
7274 		if (r)
7275 			return r;
7276 	}
7277 
7278 	return 0;
7279 }
7280 
7281 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
7282 {
7283 	gfx_v10_0_cp_gfx_enable(adev, enable);
7284 	gfx_v10_0_cp_compute_enable(adev, enable);
7285 }
7286 
7287 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7288 {
7289 	uint32_t data, pattern = 0xDEADBEEF;
7290 
7291 	/*
7292 	 * check if mmVGT_ESGS_RING_SIZE_UMD
7293 	 * has been remapped to mmVGT_ESGS_RING_SIZE
7294 	 */
7295 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7296 	case IP_VERSION(10, 3, 0):
7297 	case IP_VERSION(10, 3, 2):
7298 	case IP_VERSION(10, 3, 4):
7299 	case IP_VERSION(10, 3, 5):
7300 		data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
7301 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
7302 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7303 
7304 		if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7305 			WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7306 			return true;
7307 		}
7308 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7309 		break;
7310 	case IP_VERSION(10, 3, 1):
7311 	case IP_VERSION(10, 3, 3):
7312 	case IP_VERSION(10, 3, 6):
7313 	case IP_VERSION(10, 3, 7):
7314 		return true;
7315 	default:
7316 		data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7317 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7318 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7319 
7320 		if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7321 			WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7322 			return true;
7323 		}
7324 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7325 		break;
7326 	}
7327 
7328 	return false;
7329 }
7330 
7331 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7332 {
7333 	uint32_t data;
7334 
7335 	if (amdgpu_sriov_vf(adev))
7336 		return;
7337 
7338 	/*
7339 	 * Initialize cam_index to 0
7340 	 * index will auto-inc after each data writing
7341 	 */
7342 	WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7343 
7344 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7345 	case IP_VERSION(10, 3, 0):
7346 	case IP_VERSION(10, 3, 2):
7347 	case IP_VERSION(10, 3, 1):
7348 	case IP_VERSION(10, 3, 4):
7349 	case IP_VERSION(10, 3, 5):
7350 	case IP_VERSION(10, 3, 6):
7351 	case IP_VERSION(10, 3, 3):
7352 	case IP_VERSION(10, 3, 7):
7353 		/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7354 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7355 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7356 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7357 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7358 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7359 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7360 
7361 		/* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7362 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7363 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7364 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7365 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7366 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7367 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7368 
7369 		/* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7370 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7371 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7372 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7373 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7374 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7375 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7376 
7377 		/* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7378 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7379 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7380 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7381 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7382 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7383 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7384 
7385 		/* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7386 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7387 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7388 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7389 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7390 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7391 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7392 
7393 		/* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7394 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7395 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7396 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7397 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7398 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7399 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7400 
7401 		/* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7402 		data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7403 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7404 		       (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7405 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7406 		break;
7407 	default:
7408 		/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7409 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7410 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7411 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7412 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7413 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7414 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7415 
7416 		/* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7417 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7418 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7419 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7420 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7421 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7422 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7423 
7424 		/* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7425 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7426 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7427 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7428 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7429 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7430 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7431 
7432 		/* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7433 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7434 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7435 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7436 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7437 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7438 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7439 
7440 		/* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7441 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7442 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7443 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7444 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7445 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7446 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7447 
7448 		/* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7449 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7450 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7451 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7452 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7453 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7454 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7455 
7456 		/* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7457 		data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7458 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7459 		       (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7460 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7461 		break;
7462 	}
7463 
7464 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7465 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7466 }
7467 
7468 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7469 {
7470 	uint32_t data;
7471 
7472 	data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7473 	data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7474 	WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7475 
7476 	data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7477 	data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7478 	WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7479 }
7480 
7481 static int gfx_v10_0_hw_init(struct amdgpu_ip_block *ip_block)
7482 {
7483 	int r;
7484 	struct amdgpu_device *adev = ip_block->adev;
7485 
7486 	if (!amdgpu_emu_mode)
7487 		gfx_v10_0_init_golden_registers(adev);
7488 
7489 	amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size,
7490 				       adev->gfx.cleaner_shader_ptr);
7491 
7492 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7493 		/**
7494 		 * For gfx 10, rlc firmware loading relies on smu firmware is
7495 		 * loaded firstly, so in direct type, it has to load smc ucode
7496 		 * here before rlc.
7497 		 */
7498 		r = amdgpu_pm_load_smu_firmware(adev, NULL);
7499 		if (r)
7500 			return r;
7501 		gfx_v10_0_disable_gpa_mode(adev);
7502 	}
7503 
7504 	/* if GRBM CAM not remapped, set up the remapping */
7505 	if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7506 		gfx_v10_0_setup_grbm_cam_remapping(adev);
7507 
7508 	gfx_v10_0_constants_init(adev);
7509 
7510 	r = gfx_v10_0_rlc_resume(adev);
7511 	if (r)
7512 		return r;
7513 
7514 	/*
7515 	 * init golden registers and rlc resume may override some registers,
7516 	 * reconfig them here
7517 	 */
7518 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 10) ||
7519 	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) ||
7520 	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))
7521 		gfx_v10_0_tcp_harvest(adev);
7522 
7523 	r = gfx_v10_0_cp_resume(adev);
7524 	if (r)
7525 		return r;
7526 
7527 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))
7528 		gfx_v10_3_program_pbb_mode(adev);
7529 
7530 	if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0) && !amdgpu_sriov_vf(adev))
7531 		gfx_v10_3_set_power_brake_sequence(adev);
7532 
7533 	return r;
7534 }
7535 
7536 static int gfx_v10_0_hw_fini(struct amdgpu_ip_block *ip_block)
7537 {
7538 	struct amdgpu_device *adev = ip_block->adev;
7539 
7540 	cancel_delayed_work_sync(&adev->gfx.idle_work);
7541 
7542 	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7543 	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7544 	amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);
7545 
7546 	/* WA added for Vangogh asic fixing the SMU suspend failure
7547 	 * It needs to set power gating again during gfxoff control
7548 	 * otherwise the gfxoff disallowing will be failed to set.
7549 	 */
7550 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1))
7551 		gfx_v10_0_set_powergating_state(ip_block, AMD_PG_STATE_UNGATE);
7552 
7553 	if (!adev->no_hw_access) {
7554 		if (amdgpu_async_gfx_ring) {
7555 			if (amdgpu_gfx_disable_kgq(adev, 0))
7556 				DRM_ERROR("KGQ disable failed\n");
7557 		}
7558 
7559 		if (amdgpu_gfx_disable_kcq(adev, 0))
7560 			DRM_ERROR("KCQ disable failed\n");
7561 	}
7562 
7563 	if (amdgpu_sriov_vf(adev)) {
7564 		gfx_v10_0_cp_gfx_enable(adev, false);
7565 		/* Remove the steps of clearing KIQ position.
7566 		 * It causes GFX hang when another Win guest is rendering.
7567 		 */
7568 		return 0;
7569 	}
7570 	gfx_v10_0_cp_enable(adev, false);
7571 	gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7572 
7573 	return 0;
7574 }
7575 
7576 static int gfx_v10_0_suspend(struct amdgpu_ip_block *ip_block)
7577 {
7578 	return gfx_v10_0_hw_fini(ip_block);
7579 }
7580 
7581 static int gfx_v10_0_resume(struct amdgpu_ip_block *ip_block)
7582 {
7583 	return gfx_v10_0_hw_init(ip_block);
7584 }
7585 
7586 static bool gfx_v10_0_is_idle(struct amdgpu_ip_block *ip_block)
7587 {
7588 	struct amdgpu_device *adev = ip_block->adev;
7589 
7590 	if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7591 				GRBM_STATUS, GUI_ACTIVE))
7592 		return false;
7593 	else
7594 		return true;
7595 }
7596 
7597 static int gfx_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
7598 {
7599 	unsigned int i;
7600 	u32 tmp;
7601 	struct amdgpu_device *adev = ip_block->adev;
7602 
7603 	for (i = 0; i < adev->usec_timeout; i++) {
7604 		/* read MC_STATUS */
7605 		tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7606 			GRBM_STATUS__GUI_ACTIVE_MASK;
7607 
7608 		if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7609 			return 0;
7610 		udelay(1);
7611 	}
7612 	return -ETIMEDOUT;
7613 }
7614 
7615 static int gfx_v10_0_soft_reset(struct amdgpu_ip_block *ip_block)
7616 {
7617 	u32 grbm_soft_reset = 0;
7618 	u32 tmp;
7619 	struct amdgpu_device *adev = ip_block->adev;
7620 
7621 	/* GRBM_STATUS */
7622 	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7623 	if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7624 		   GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7625 		   GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7626 		   GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7627 		   GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7628 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7629 						GRBM_SOFT_RESET, SOFT_RESET_CP,
7630 						1);
7631 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7632 						GRBM_SOFT_RESET, SOFT_RESET_GFX,
7633 						1);
7634 	}
7635 
7636 	if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7637 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7638 						GRBM_SOFT_RESET, SOFT_RESET_CP,
7639 						1);
7640 	}
7641 
7642 	/* GRBM_STATUS2 */
7643 	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7644 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7645 	case IP_VERSION(10, 3, 0):
7646 	case IP_VERSION(10, 3, 2):
7647 	case IP_VERSION(10, 3, 1):
7648 	case IP_VERSION(10, 3, 4):
7649 	case IP_VERSION(10, 3, 5):
7650 	case IP_VERSION(10, 3, 6):
7651 	case IP_VERSION(10, 3, 3):
7652 		if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7653 			grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7654 							GRBM_SOFT_RESET,
7655 							SOFT_RESET_RLC,
7656 							1);
7657 		break;
7658 	default:
7659 		if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7660 			grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7661 							GRBM_SOFT_RESET,
7662 							SOFT_RESET_RLC,
7663 							1);
7664 		break;
7665 	}
7666 
7667 	if (grbm_soft_reset) {
7668 		/* stop the rlc */
7669 		gfx_v10_0_rlc_stop(adev);
7670 
7671 		/* Disable GFX parsing/prefetching */
7672 		gfx_v10_0_cp_gfx_enable(adev, false);
7673 
7674 		/* Disable MEC parsing/prefetching */
7675 		gfx_v10_0_cp_compute_enable(adev, false);
7676 
7677 		if (grbm_soft_reset) {
7678 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7679 			tmp |= grbm_soft_reset;
7680 			dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7681 			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7682 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7683 
7684 			udelay(50);
7685 
7686 			tmp &= ~grbm_soft_reset;
7687 			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7688 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7689 		}
7690 
7691 		/* Wait a little for things to settle down */
7692 		udelay(50);
7693 	}
7694 	return 0;
7695 }
7696 
7697 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7698 {
7699 	uint64_t clock, clock_lo, clock_hi, hi_check;
7700 
7701 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7702 	case IP_VERSION(10, 1, 3):
7703 	case IP_VERSION(10, 1, 4):
7704 		preempt_disable();
7705 		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
7706 		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
7707 		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
7708 		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7709 		 * roughly every 42 seconds.
7710 		 */
7711 		if (hi_check != clock_hi) {
7712 			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
7713 			clock_hi = hi_check;
7714 		}
7715 		preempt_enable();
7716 		clock = clock_lo | (clock_hi << 32ULL);
7717 		break;
7718 	case IP_VERSION(10, 3, 1):
7719 	case IP_VERSION(10, 3, 3):
7720 	case IP_VERSION(10, 3, 7):
7721 		preempt_disable();
7722 		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7723 		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7724 		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7725 		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7726 		 * roughly every 42 seconds.
7727 		 */
7728 		if (hi_check != clock_hi) {
7729 			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7730 			clock_hi = hi_check;
7731 		}
7732 		preempt_enable();
7733 		clock = clock_lo | (clock_hi << 32ULL);
7734 		break;
7735 	case IP_VERSION(10, 3, 6):
7736 		preempt_disable();
7737 		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7738 		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7739 		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7740 		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7741 		 * roughly every 42 seconds.
7742 		 */
7743 		if (hi_check != clock_hi) {
7744 			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7745 			clock_hi = hi_check;
7746 		}
7747 		preempt_enable();
7748 		clock = clock_lo | (clock_hi << 32ULL);
7749 		break;
7750 	default:
7751 		preempt_disable();
7752 		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7753 		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7754 		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7755 		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7756 		 * roughly every 42 seconds.
7757 		 */
7758 		if (hi_check != clock_hi) {
7759 			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7760 			clock_hi = hi_check;
7761 		}
7762 		preempt_enable();
7763 		clock = clock_lo | (clock_hi << 32ULL);
7764 		break;
7765 	}
7766 	return clock;
7767 }
7768 
7769 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7770 					   uint32_t vmid,
7771 					   uint32_t gds_base, uint32_t gds_size,
7772 					   uint32_t gws_base, uint32_t gws_size,
7773 					   uint32_t oa_base, uint32_t oa_size)
7774 {
7775 	struct amdgpu_device *adev = ring->adev;
7776 
7777 	/* GDS Base */
7778 	gfx_v10_0_write_data_to_reg(ring, 0, false,
7779 				    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7780 				    gds_base);
7781 
7782 	/* GDS Size */
7783 	gfx_v10_0_write_data_to_reg(ring, 0, false,
7784 				    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7785 				    gds_size);
7786 
7787 	/* GWS */
7788 	gfx_v10_0_write_data_to_reg(ring, 0, false,
7789 				    SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7790 				    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7791 
7792 	/* OA */
7793 	gfx_v10_0_write_data_to_reg(ring, 0, false,
7794 				    SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7795 				    (1 << (oa_size + oa_base)) - (1 << oa_base));
7796 }
7797 
7798 static int gfx_v10_0_early_init(struct amdgpu_ip_block *ip_block)
7799 {
7800 	struct amdgpu_device *adev = ip_block->adev;
7801 
7802 	adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
7803 
7804 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7805 	case IP_VERSION(10, 1, 10):
7806 	case IP_VERSION(10, 1, 1):
7807 	case IP_VERSION(10, 1, 2):
7808 	case IP_VERSION(10, 1, 3):
7809 	case IP_VERSION(10, 1, 4):
7810 		adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7811 		break;
7812 	case IP_VERSION(10, 3, 0):
7813 	case IP_VERSION(10, 3, 2):
7814 	case IP_VERSION(10, 3, 1):
7815 	case IP_VERSION(10, 3, 4):
7816 	case IP_VERSION(10, 3, 5):
7817 	case IP_VERSION(10, 3, 6):
7818 	case IP_VERSION(10, 3, 3):
7819 	case IP_VERSION(10, 3, 7):
7820 		adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7821 		break;
7822 	default:
7823 		break;
7824 	}
7825 
7826 	adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7827 					  AMDGPU_MAX_COMPUTE_RINGS);
7828 
7829 	gfx_v10_0_set_kiq_pm4_funcs(adev);
7830 	gfx_v10_0_set_ring_funcs(adev);
7831 	gfx_v10_0_set_irq_funcs(adev);
7832 	gfx_v10_0_set_gds_init(adev);
7833 	gfx_v10_0_set_rlc_funcs(adev);
7834 	gfx_v10_0_set_mqd_funcs(adev);
7835 
7836 	/* init rlcg reg access ctrl */
7837 	gfx_v10_0_init_rlcg_reg_access_ctrl(adev);
7838 
7839 	return gfx_v10_0_init_microcode(adev);
7840 }
7841 
7842 static int gfx_v10_0_late_init(struct amdgpu_ip_block *ip_block)
7843 {
7844 	struct amdgpu_device *adev = ip_block->adev;
7845 	int r;
7846 
7847 	r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7848 	if (r)
7849 		return r;
7850 
7851 	r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7852 	if (r)
7853 		return r;
7854 
7855 	r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0);
7856 	if (r)
7857 		return r;
7858 
7859 	return 0;
7860 }
7861 
7862 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7863 {
7864 	uint32_t rlc_cntl;
7865 
7866 	/* if RLC is not enabled, do nothing */
7867 	rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7868 	return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7869 }
7870 
7871 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
7872 {
7873 	uint32_t data;
7874 	unsigned int i;
7875 
7876 	data = RLC_SAFE_MODE__CMD_MASK;
7877 	data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7878 
7879 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7880 	case IP_VERSION(10, 3, 0):
7881 	case IP_VERSION(10, 3, 2):
7882 	case IP_VERSION(10, 3, 1):
7883 	case IP_VERSION(10, 3, 4):
7884 	case IP_VERSION(10, 3, 5):
7885 	case IP_VERSION(10, 3, 6):
7886 	case IP_VERSION(10, 3, 3):
7887 	case IP_VERSION(10, 3, 7):
7888 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7889 
7890 		/* wait for RLC_SAFE_MODE */
7891 		for (i = 0; i < adev->usec_timeout; i++) {
7892 			if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7893 					   RLC_SAFE_MODE, CMD))
7894 				break;
7895 			udelay(1);
7896 		}
7897 		break;
7898 	default:
7899 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7900 
7901 		/* wait for RLC_SAFE_MODE */
7902 		for (i = 0; i < adev->usec_timeout; i++) {
7903 			if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7904 					   RLC_SAFE_MODE, CMD))
7905 				break;
7906 			udelay(1);
7907 		}
7908 		break;
7909 	}
7910 }
7911 
7912 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
7913 {
7914 	uint32_t data;
7915 
7916 	data = RLC_SAFE_MODE__CMD_MASK;
7917 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7918 	case IP_VERSION(10, 3, 0):
7919 	case IP_VERSION(10, 3, 2):
7920 	case IP_VERSION(10, 3, 1):
7921 	case IP_VERSION(10, 3, 4):
7922 	case IP_VERSION(10, 3, 5):
7923 	case IP_VERSION(10, 3, 6):
7924 	case IP_VERSION(10, 3, 3):
7925 	case IP_VERSION(10, 3, 7):
7926 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7927 		break;
7928 	default:
7929 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7930 		break;
7931 	}
7932 }
7933 
7934 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7935 						      bool enable)
7936 {
7937 	uint32_t data, def;
7938 
7939 	if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
7940 		return;
7941 
7942 	/* It is disabled by HW by default */
7943 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7944 		/* 0 - Disable some blocks' MGCG */
7945 		WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7946 		WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7947 		WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7948 		WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7949 
7950 		/* 1 - RLC_CGTT_MGCG_OVERRIDE */
7951 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7952 		data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7953 			  RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7954 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7955 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7956 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7957 			  RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7958 
7959 		if (def != data)
7960 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7961 
7962 		/* MGLS is a global flag to control all MGLS in GFX */
7963 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7964 			/* 2 - RLC memory Light sleep */
7965 			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7966 				def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7967 				data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7968 				if (def != data)
7969 					WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7970 			}
7971 			/* 3 - CP memory Light sleep */
7972 			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7973 				def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7974 				data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7975 				if (def != data)
7976 					WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7977 			}
7978 		}
7979 	} else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7980 		/* 1 - MGCG_OVERRIDE */
7981 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7982 		data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7983 			 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7984 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7985 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7986 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7987 			 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7988 		if (def != data)
7989 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7990 
7991 		/* 2 - disable MGLS in CP */
7992 		data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7993 		if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7994 			data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7995 			WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7996 		}
7997 
7998 		/* 3 - disable MGLS in RLC */
7999 		data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
8000 		if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
8001 			data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
8002 			WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
8003 		}
8004 
8005 	}
8006 }
8007 
8008 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
8009 					   bool enable)
8010 {
8011 	uint32_t data, def;
8012 
8013 	if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
8014 		return;
8015 
8016 	/* Enable 3D CGCG/CGLS */
8017 	if (enable) {
8018 		/* write cmd to clear cgcg/cgls ov */
8019 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8020 
8021 		/* unset CGCG override */
8022 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8023 			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
8024 
8025 		/* update CGCG and CGLS override bits */
8026 		if (def != data)
8027 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8028 
8029 		/* enable 3Dcgcg FSM(0x0000363f) */
8030 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
8031 		data = 0;
8032 
8033 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8034 			data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
8035 				RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
8036 
8037 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
8038 			data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
8039 				RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
8040 
8041 		if (def != data)
8042 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
8043 
8044 		/* set IDLE_POLL_COUNT(0x00900100) */
8045 		def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
8046 		data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
8047 			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
8048 		if (def != data)
8049 			WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8050 	} else {
8051 		/* Disable CGCG/CGLS */
8052 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
8053 
8054 		/* disable cgcg, cgls should be disabled */
8055 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8056 			data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
8057 
8058 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
8059 			data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
8060 
8061 		/* disable cgcg and cgls in FSM */
8062 		if (def != data)
8063 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
8064 	}
8065 }
8066 
8067 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
8068 						      bool enable)
8069 {
8070 	uint32_t def, data;
8071 
8072 	if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
8073 		return;
8074 
8075 	if (enable) {
8076 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8077 
8078 		/* unset CGCG override */
8079 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8080 			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
8081 
8082 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8083 			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
8084 
8085 		/* update CGCG and CGLS override bits */
8086 		if (def != data)
8087 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8088 
8089 		/* enable cgcg FSM(0x0000363F) */
8090 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8091 		data = 0;
8092 
8093 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8094 			data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
8095 				RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8096 
8097 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8098 			data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
8099 				RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8100 
8101 		if (def != data)
8102 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8103 
8104 		/* set IDLE_POLL_COUNT(0x00900100) */
8105 		def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
8106 		data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
8107 			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
8108 		if (def != data)
8109 			WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8110 	} else {
8111 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8112 
8113 		/* reset CGCG/CGLS bits */
8114 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8115 			data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8116 
8117 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8118 			data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8119 
8120 		/* disable cgcg and cgls in FSM */
8121 		if (def != data)
8122 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8123 	}
8124 }
8125 
8126 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
8127 						      bool enable)
8128 {
8129 	uint32_t def, data;
8130 
8131 	if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
8132 		return;
8133 
8134 	if (enable) {
8135 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8136 		/* unset FGCG override */
8137 		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8138 		/* update FGCG override bits */
8139 		if (def != data)
8140 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8141 
8142 		def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8143 		/* unset RLC SRAM CLK GATER override */
8144 		data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8145 		/* update RLC SRAM CLK GATER override bits */
8146 		if (def != data)
8147 			WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8148 	} else {
8149 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8150 		/* reset FGCG bits */
8151 		data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8152 		/* disable FGCG*/
8153 		if (def != data)
8154 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8155 
8156 		def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8157 		/* reset RLC SRAM CLK GATER bits */
8158 		data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8159 		/* disable RLC SRAM CLK*/
8160 		if (def != data)
8161 			WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8162 	}
8163 }
8164 
8165 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
8166 {
8167 	uint32_t reg_data = 0;
8168 	uint32_t reg_idx = 0;
8169 	uint32_t i;
8170 
8171 	const uint32_t tcp_ctrl_regs[] = {
8172 		mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8173 		mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8174 		mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8175 		mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8176 		mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8177 		mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8178 		mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8179 		mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8180 		mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8181 		mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8182 		mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,
8183 		mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,
8184 		mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8185 		mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8186 		mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8187 		mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8188 		mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8189 		mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8190 		mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8191 		mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8192 		mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8193 		mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8194 		mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,
8195 		mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG
8196 	};
8197 
8198 	const uint32_t tcp_ctrl_regs_nv12[] = {
8199 		mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8200 		mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8201 		mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8202 		mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8203 		mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8204 		mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8205 		mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8206 		mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8207 		mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8208 		mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8209 		mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8210 		mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8211 		mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8212 		mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8213 		mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8214 		mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8215 		mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8216 		mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8217 		mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8218 		mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8219 	};
8220 
8221 	const uint32_t sm_ctlr_regs[] = {
8222 		mmCGTS_SA0_QUAD0_SM_CTRL_REG,
8223 		mmCGTS_SA0_QUAD1_SM_CTRL_REG,
8224 		mmCGTS_SA1_QUAD0_SM_CTRL_REG,
8225 		mmCGTS_SA1_QUAD1_SM_CTRL_REG
8226 	};
8227 
8228 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {
8229 		for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
8230 			reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8231 				  tcp_ctrl_regs_nv12[i];
8232 			reg_data = RREG32(reg_idx);
8233 			reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8234 			WREG32(reg_idx, reg_data);
8235 		}
8236 	} else {
8237 		for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {
8238 			reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8239 				  tcp_ctrl_regs[i];
8240 			reg_data = RREG32(reg_idx);
8241 			reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8242 			WREG32(reg_idx, reg_data);
8243 		}
8244 	}
8245 
8246 	for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {
8247 		reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +
8248 			  sm_ctlr_regs[i];
8249 		reg_data = RREG32(reg_idx);
8250 		reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;
8251 		reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;
8252 		WREG32(reg_idx, reg_data);
8253 	}
8254 }
8255 
8256 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
8257 					    bool enable)
8258 {
8259 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
8260 
8261 	if (enable) {
8262 		/* enable FGCG firstly*/
8263 		gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8264 		/* CGCG/CGLS should be enabled after MGCG/MGLS
8265 		 * ===  MGCG + MGLS ===
8266 		 */
8267 		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8268 		/* ===  CGCG /CGLS for GFX 3D Only === */
8269 		gfx_v10_0_update_3d_clock_gating(adev, enable);
8270 		/* ===  CGCG + CGLS === */
8271 		gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8272 
8273 		if ((amdgpu_ip_version(adev, GC_HWIP, 0) ==
8274 		     IP_VERSION(10, 1, 10)) ||
8275 		    (amdgpu_ip_version(adev, GC_HWIP, 0) ==
8276 		     IP_VERSION(10, 1, 1)) ||
8277 		    (amdgpu_ip_version(adev, GC_HWIP, 0) ==
8278 		     IP_VERSION(10, 1, 2)))
8279 			gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
8280 	} else {
8281 		/* CGCG/CGLS should be disabled before MGCG/MGLS
8282 		 * ===  CGCG + CGLS ===
8283 		 */
8284 		gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8285 		/* ===  CGCG /CGLS for GFX 3D Only === */
8286 		gfx_v10_0_update_3d_clock_gating(adev, enable);
8287 		/* ===  MGCG + MGLS === */
8288 		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8289 		/* disable fgcg at last*/
8290 		gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8291 	}
8292 
8293 	if (adev->cg_flags &
8294 	    (AMD_CG_SUPPORT_GFX_MGCG |
8295 	     AMD_CG_SUPPORT_GFX_CGLS |
8296 	     AMD_CG_SUPPORT_GFX_CGCG |
8297 	     AMD_CG_SUPPORT_GFX_3D_CGCG |
8298 	     AMD_CG_SUPPORT_GFX_3D_CGLS))
8299 		gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
8300 
8301 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
8302 
8303 	return 0;
8304 }
8305 
8306 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
8307 					       unsigned int vmid)
8308 {
8309 	u32 reg, pre_data, data;
8310 
8311 	reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
8312 	/* not for *_SOC15 */
8313 	if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev))
8314 		pre_data = RREG32_NO_KIQ(reg);
8315 	else
8316 		pre_data = RREG32(reg);
8317 
8318 	data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK);
8319 	data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
8320 
8321 	if (pre_data != data) {
8322 		if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) {
8323 			WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
8324 		} else
8325 			WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
8326 	}
8327 }
8328 
8329 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid)
8330 {
8331 	amdgpu_gfx_off_ctrl(adev, false);
8332 
8333 	gfx_v10_0_update_spm_vmid_internal(adev, vmid);
8334 
8335 	amdgpu_gfx_off_ctrl(adev, true);
8336 }
8337 
8338 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
8339 					uint32_t offset,
8340 					struct soc15_reg_rlcg *entries, int arr_size)
8341 {
8342 	int i;
8343 	uint32_t reg;
8344 
8345 	if (!entries)
8346 		return false;
8347 
8348 	for (i = 0; i < arr_size; i++) {
8349 		const struct soc15_reg_rlcg *entry;
8350 
8351 		entry = &entries[i];
8352 		reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
8353 		if (offset == reg)
8354 			return true;
8355 	}
8356 
8357 	return false;
8358 }
8359 
8360 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
8361 {
8362 	return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
8363 }
8364 
8365 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
8366 {
8367 	u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
8368 
8369 	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
8370 		data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8371 	else
8372 		data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8373 
8374 	WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
8375 
8376 	/*
8377 	 * CGPG enablement required and the register to program the hysteresis value
8378 	 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
8379 	 * in refclk count. Note that RLC FW is modified to take 16 bits from
8380 	 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
8381 	 *
8382 	 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
8383 	 * of CGPG enablement starting point.
8384 	 * Power/performance team will optimize it and might give a new value later.
8385 	 */
8386 	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
8387 		switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8388 		case IP_VERSION(10, 3, 1):
8389 		case IP_VERSION(10, 3, 3):
8390 		case IP_VERSION(10, 3, 6):
8391 		case IP_VERSION(10, 3, 7):
8392 			data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8393 			WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8394 			break;
8395 		default:
8396 			break;
8397 		}
8398 	}
8399 }
8400 
8401 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
8402 {
8403 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
8404 
8405 	gfx_v10_cntl_power_gating(adev, enable);
8406 
8407 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
8408 }
8409 
8410 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8411 	.is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8412 	.set_safe_mode = gfx_v10_0_set_safe_mode,
8413 	.unset_safe_mode = gfx_v10_0_unset_safe_mode,
8414 	.init = gfx_v10_0_rlc_init,
8415 	.get_csb_size = gfx_v10_0_get_csb_size,
8416 	.get_csb_buffer = gfx_v10_0_get_csb_buffer,
8417 	.resume = gfx_v10_0_rlc_resume,
8418 	.stop = gfx_v10_0_rlc_stop,
8419 	.reset = gfx_v10_0_rlc_reset,
8420 	.start = gfx_v10_0_rlc_start,
8421 	.update_spm_vmid = gfx_v10_0_update_spm_vmid,
8422 };
8423 
8424 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8425 	.is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8426 	.set_safe_mode = gfx_v10_0_set_safe_mode,
8427 	.unset_safe_mode = gfx_v10_0_unset_safe_mode,
8428 	.init = gfx_v10_0_rlc_init,
8429 	.get_csb_size = gfx_v10_0_get_csb_size,
8430 	.get_csb_buffer = gfx_v10_0_get_csb_buffer,
8431 	.resume = gfx_v10_0_rlc_resume,
8432 	.stop = gfx_v10_0_rlc_stop,
8433 	.reset = gfx_v10_0_rlc_reset,
8434 	.start = gfx_v10_0_rlc_start,
8435 	.update_spm_vmid = gfx_v10_0_update_spm_vmid,
8436 	.is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8437 };
8438 
8439 static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
8440 					  enum amd_powergating_state state)
8441 {
8442 	struct amdgpu_device *adev = ip_block->adev;
8443 	bool enable = (state == AMD_PG_STATE_GATE);
8444 
8445 	if (amdgpu_sriov_vf(adev))
8446 		return 0;
8447 
8448 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8449 	case IP_VERSION(10, 1, 10):
8450 	case IP_VERSION(10, 1, 1):
8451 	case IP_VERSION(10, 1, 2):
8452 	case IP_VERSION(10, 3, 0):
8453 	case IP_VERSION(10, 3, 2):
8454 	case IP_VERSION(10, 3, 4):
8455 	case IP_VERSION(10, 3, 5):
8456 		amdgpu_gfx_off_ctrl(adev, enable);
8457 		break;
8458 	case IP_VERSION(10, 3, 1):
8459 	case IP_VERSION(10, 3, 3):
8460 	case IP_VERSION(10, 3, 6):
8461 	case IP_VERSION(10, 3, 7):
8462 		if (!enable)
8463 			amdgpu_gfx_off_ctrl(adev, false);
8464 
8465 		gfx_v10_cntl_pg(adev, enable);
8466 
8467 		if (enable)
8468 			amdgpu_gfx_off_ctrl(adev, true);
8469 
8470 		break;
8471 	default:
8472 		break;
8473 	}
8474 	return 0;
8475 }
8476 
8477 static int gfx_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
8478 					  enum amd_clockgating_state state)
8479 {
8480 	struct amdgpu_device *adev = ip_block->adev;
8481 
8482 	if (amdgpu_sriov_vf(adev))
8483 		return 0;
8484 
8485 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8486 	case IP_VERSION(10, 1, 10):
8487 	case IP_VERSION(10, 1, 1):
8488 	case IP_VERSION(10, 1, 2):
8489 	case IP_VERSION(10, 3, 0):
8490 	case IP_VERSION(10, 3, 2):
8491 	case IP_VERSION(10, 3, 1):
8492 	case IP_VERSION(10, 3, 4):
8493 	case IP_VERSION(10, 3, 5):
8494 	case IP_VERSION(10, 3, 6):
8495 	case IP_VERSION(10, 3, 3):
8496 	case IP_VERSION(10, 3, 7):
8497 		gfx_v10_0_update_gfx_clock_gating(adev,
8498 						 state == AMD_CG_STATE_GATE);
8499 		break;
8500 	default:
8501 		break;
8502 	}
8503 	return 0;
8504 }
8505 
8506 static void gfx_v10_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
8507 {
8508 	struct amdgpu_device *adev = ip_block->adev;
8509 	int data;
8510 
8511 	/* AMD_CG_SUPPORT_GFX_FGCG */
8512 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8513 	if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8514 		*flags |= AMD_CG_SUPPORT_GFX_FGCG;
8515 
8516 	/* AMD_CG_SUPPORT_GFX_MGCG */
8517 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8518 	if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8519 		*flags |= AMD_CG_SUPPORT_GFX_MGCG;
8520 
8521 	/* AMD_CG_SUPPORT_GFX_CGCG */
8522 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8523 	if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8524 		*flags |= AMD_CG_SUPPORT_GFX_CGCG;
8525 
8526 	/* AMD_CG_SUPPORT_GFX_CGLS */
8527 	if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8528 		*flags |= AMD_CG_SUPPORT_GFX_CGLS;
8529 
8530 	/* AMD_CG_SUPPORT_GFX_RLC_LS */
8531 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8532 	if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8533 		*flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8534 
8535 	/* AMD_CG_SUPPORT_GFX_CP_LS */
8536 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8537 	if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8538 		*flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8539 
8540 	/* AMD_CG_SUPPORT_GFX_3D_CGCG */
8541 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8542 	if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8543 		*flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8544 
8545 	/* AMD_CG_SUPPORT_GFX_3D_CGLS */
8546 	if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8547 		*flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8548 }
8549 
8550 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8551 {
8552 	/* gfx10 is 32bit rptr*/
8553 	return *(uint32_t *)ring->rptr_cpu_addr;
8554 }
8555 
8556 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8557 {
8558 	struct amdgpu_device *adev = ring->adev;
8559 	u64 wptr;
8560 
8561 	/* XXX check if swapping is necessary on BE */
8562 	if (ring->use_doorbell) {
8563 		wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8564 	} else {
8565 		wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8566 		wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8567 	}
8568 
8569 	return wptr;
8570 }
8571 
8572 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8573 {
8574 	struct amdgpu_device *adev = ring->adev;
8575 
8576 	if (ring->use_doorbell) {
8577 		/* XXX check if swapping is necessary on BE */
8578 		atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8579 			     ring->wptr);
8580 		WDOORBELL64(ring->doorbell_index, ring->wptr);
8581 	} else {
8582 		WREG32_SOC15(GC, 0, mmCP_RB0_WPTR,
8583 			     lower_32_bits(ring->wptr));
8584 		WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI,
8585 			     upper_32_bits(ring->wptr));
8586 	}
8587 }
8588 
8589 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8590 {
8591 	/* gfx10 hardware is 32bit rptr */
8592 	return *(uint32_t *)ring->rptr_cpu_addr;
8593 }
8594 
8595 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8596 {
8597 	u64 wptr;
8598 
8599 	/* XXX check if swapping is necessary on BE */
8600 	if (ring->use_doorbell)
8601 		wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8602 	else
8603 		BUG();
8604 	return wptr;
8605 }
8606 
8607 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8608 {
8609 	struct amdgpu_device *adev = ring->adev;
8610 
8611 	if (ring->use_doorbell) {
8612 		atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8613 			     ring->wptr);
8614 		WDOORBELL64(ring->doorbell_index, ring->wptr);
8615 	} else {
8616 		BUG(); /* only DOORBELL method supported on gfx10 now */
8617 	}
8618 }
8619 
8620 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8621 {
8622 	struct amdgpu_device *adev = ring->adev;
8623 	u32 ref_and_mask, reg_mem_engine;
8624 	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8625 
8626 	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8627 		switch (ring->me) {
8628 		case 1:
8629 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8630 			break;
8631 		case 2:
8632 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8633 			break;
8634 		default:
8635 			return;
8636 		}
8637 		reg_mem_engine = 0;
8638 	} else {
8639 		ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe;
8640 		reg_mem_engine = 1; /* pfp */
8641 	}
8642 
8643 	gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8644 			       adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8645 			       adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8646 			       ref_and_mask, ref_and_mask, 0x20);
8647 }
8648 
8649 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8650 				       struct amdgpu_job *job,
8651 				       struct amdgpu_ib *ib,
8652 				       uint32_t flags)
8653 {
8654 	unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8655 	u32 header, control = 0;
8656 
8657 	if (ib->flags & AMDGPU_IB_FLAG_CE)
8658 		header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8659 	else
8660 		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8661 
8662 	control |= ib->length_dw | (vmid << 24);
8663 
8664 	if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8665 		control |= INDIRECT_BUFFER_PRE_ENB(1);
8666 
8667 		if (flags & AMDGPU_IB_PREEMPTED)
8668 			control |= INDIRECT_BUFFER_PRE_RESUME(1);
8669 
8670 		if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8671 			gfx_v10_0_ring_emit_de_meta(ring,
8672 				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8673 	}
8674 
8675 	amdgpu_ring_write(ring, header);
8676 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8677 	amdgpu_ring_write(ring,
8678 #ifdef __BIG_ENDIAN
8679 		(2 << 0) |
8680 #endif
8681 		lower_32_bits(ib->gpu_addr));
8682 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8683 	amdgpu_ring_write(ring, control);
8684 }
8685 
8686 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8687 					   struct amdgpu_job *job,
8688 					   struct amdgpu_ib *ib,
8689 					   uint32_t flags)
8690 {
8691 	unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8692 	u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8693 
8694 	/* Currently, there is a high possibility to get wave ID mismatch
8695 	 * between ME and GDS, leading to a hw deadlock, because ME generates
8696 	 * different wave IDs than the GDS expects. This situation happens
8697 	 * randomly when at least 5 compute pipes use GDS ordered append.
8698 	 * The wave IDs generated by ME are also wrong after suspend/resume.
8699 	 * Those are probably bugs somewhere else in the kernel driver.
8700 	 *
8701 	 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8702 	 * GDS to 0 for this ring (me/pipe).
8703 	 */
8704 	if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8705 		amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8706 		amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8707 		amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8708 	}
8709 
8710 	amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8711 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8712 	amdgpu_ring_write(ring,
8713 #ifdef __BIG_ENDIAN
8714 				(2 << 0) |
8715 #endif
8716 				lower_32_bits(ib->gpu_addr));
8717 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8718 	amdgpu_ring_write(ring, control);
8719 }
8720 
8721 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8722 				     u64 seq, unsigned int flags)
8723 {
8724 	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8725 	bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8726 
8727 	/* RELEASE_MEM - flush caches, send int */
8728 	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8729 	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8730 				 PACKET3_RELEASE_MEM_GCR_GL2_WB |
8731 				 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8732 				 PACKET3_RELEASE_MEM_GCR_GLM_WB |
8733 				 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8734 				 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8735 				 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8736 	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8737 				 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8738 
8739 	/*
8740 	 * the address should be Qword aligned if 64bit write, Dword
8741 	 * aligned if only send 32bit data low (discard data high)
8742 	 */
8743 	if (write64bit)
8744 		BUG_ON(addr & 0x7);
8745 	else
8746 		BUG_ON(addr & 0x3);
8747 	amdgpu_ring_write(ring, lower_32_bits(addr));
8748 	amdgpu_ring_write(ring, upper_32_bits(addr));
8749 	amdgpu_ring_write(ring, lower_32_bits(seq));
8750 	amdgpu_ring_write(ring, upper_32_bits(seq));
8751 	amdgpu_ring_write(ring, 0);
8752 }
8753 
8754 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8755 {
8756 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8757 	uint32_t seq = ring->fence_drv.sync_seq;
8758 	uint64_t addr = ring->fence_drv.gpu_addr;
8759 
8760 	gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8761 			       upper_32_bits(addr), seq, 0xffffffff, 4);
8762 }
8763 
8764 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
8765 				   uint16_t pasid, uint32_t flush_type,
8766 				   bool all_hub, uint8_t dst_sel)
8767 {
8768 	amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
8769 	amdgpu_ring_write(ring,
8770 			  PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
8771 			  PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
8772 			  PACKET3_INVALIDATE_TLBS_PASID(pasid) |
8773 			  PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
8774 }
8775 
8776 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8777 					 unsigned int vmid, uint64_t pd_addr)
8778 {
8779 	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8780 
8781 	/* compute doesn't have PFP */
8782 	if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8783 		/* sync PFP to ME, otherwise we might get invalid PFP reads */
8784 		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8785 		amdgpu_ring_write(ring, 0x0);
8786 	}
8787 }
8788 
8789 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8790 					  u64 seq, unsigned int flags)
8791 {
8792 	struct amdgpu_device *adev = ring->adev;
8793 
8794 	/* we only allocate 32bit for each seq wb address */
8795 	BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8796 
8797 	/* write fence seq to the "addr" */
8798 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8799 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8800 				 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8801 	amdgpu_ring_write(ring, lower_32_bits(addr));
8802 	amdgpu_ring_write(ring, upper_32_bits(addr));
8803 	amdgpu_ring_write(ring, lower_32_bits(seq));
8804 
8805 	if (flags & AMDGPU_FENCE_FLAG_INT) {
8806 		/* set register to trigger INT */
8807 		amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8808 		amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8809 					 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8810 		amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8811 		amdgpu_ring_write(ring, 0);
8812 		amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8813 	}
8814 }
8815 
8816 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8817 {
8818 	amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8819 	amdgpu_ring_write(ring, 0);
8820 }
8821 
8822 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8823 					 uint32_t flags)
8824 {
8825 	uint32_t dw2 = 0;
8826 
8827 	if (ring->adev->gfx.mcbp)
8828 		gfx_v10_0_ring_emit_ce_meta(ring,
8829 				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8830 
8831 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8832 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8833 		/* set load_global_config & load_global_uconfig */
8834 		dw2 |= 0x8001;
8835 		/* set load_cs_sh_regs */
8836 		dw2 |= 0x01000000;
8837 		/* set load_per_context_state & load_gfx_sh_regs for GFX */
8838 		dw2 |= 0x10002;
8839 
8840 		/* set load_ce_ram if preamble presented */
8841 		if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8842 			dw2 |= 0x10000000;
8843 	} else {
8844 		/* still load_ce_ram if this is the first time preamble presented
8845 		 * although there is no context switch happens.
8846 		 */
8847 		if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8848 			dw2 |= 0x10000000;
8849 	}
8850 
8851 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8852 	amdgpu_ring_write(ring, dw2);
8853 	amdgpu_ring_write(ring, 0);
8854 }
8855 
8856 static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring,
8857 						       uint64_t addr)
8858 {
8859 	unsigned int ret;
8860 
8861 	amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8862 	amdgpu_ring_write(ring, lower_32_bits(addr));
8863 	amdgpu_ring_write(ring, upper_32_bits(addr));
8864 	/* discard following DWs if *cond_exec_gpu_addr==0 */
8865 	amdgpu_ring_write(ring, 0);
8866 	ret = ring->wptr & ring->buf_mask;
8867 	/* patch dummy value later */
8868 	amdgpu_ring_write(ring, 0);
8869 
8870 	return ret;
8871 }
8872 
8873 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8874 {
8875 	int i, r = 0;
8876 	struct amdgpu_device *adev = ring->adev;
8877 	struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
8878 	struct amdgpu_ring *kiq_ring = &kiq->ring;
8879 	unsigned long flags;
8880 
8881 	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8882 		return -EINVAL;
8883 
8884 	spin_lock_irqsave(&kiq->ring_lock, flags);
8885 
8886 	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8887 		spin_unlock_irqrestore(&kiq->ring_lock, flags);
8888 		return -ENOMEM;
8889 	}
8890 
8891 	/* assert preemption condition */
8892 	amdgpu_ring_set_preempt_cond_exec(ring, false);
8893 
8894 	/* assert IB preemption, emit the trailing fence */
8895 	kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8896 				   ring->trail_fence_gpu_addr,
8897 				   ++ring->trail_seq);
8898 	amdgpu_ring_commit(kiq_ring);
8899 
8900 	spin_unlock_irqrestore(&kiq->ring_lock, flags);
8901 
8902 	/* poll the trailing fence */
8903 	for (i = 0; i < adev->usec_timeout; i++) {
8904 		if (ring->trail_seq ==
8905 		    le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8906 			break;
8907 		udelay(1);
8908 	}
8909 
8910 	if (i >= adev->usec_timeout) {
8911 		r = -EINVAL;
8912 		DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8913 	}
8914 
8915 	/* deassert preemption condition */
8916 	amdgpu_ring_set_preempt_cond_exec(ring, true);
8917 	return r;
8918 }
8919 
8920 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8921 {
8922 	struct amdgpu_device *adev = ring->adev;
8923 	struct v10_ce_ib_state ce_payload = {0};
8924 	uint64_t offset, ce_payload_gpu_addr;
8925 	void *ce_payload_cpu_addr;
8926 	int cnt;
8927 
8928 	cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8929 
8930 	offset = offsetof(struct v10_gfx_meta_data, ce_payload);
8931 	ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8932 	ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8933 
8934 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8935 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8936 				 WRITE_DATA_DST_SEL(8) |
8937 				 WR_CONFIRM) |
8938 				 WRITE_DATA_CACHE_POLICY(0));
8939 	amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
8940 	amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));
8941 
8942 	if (resume)
8943 		amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,
8944 					   sizeof(ce_payload) >> 2);
8945 	else
8946 		amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8947 					   sizeof(ce_payload) >> 2);
8948 }
8949 
8950 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8951 {
8952 	struct amdgpu_device *adev = ring->adev;
8953 	struct v10_de_ib_state de_payload = {0};
8954 	uint64_t offset, gds_addr, de_payload_gpu_addr;
8955 	void *de_payload_cpu_addr;
8956 	int cnt;
8957 
8958 	offset = offsetof(struct v10_gfx_meta_data, de_payload);
8959 	de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8960 	de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8961 
8962 	gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
8963 			 AMDGPU_CSA_SIZE - adev->gds.gds_size,
8964 			 PAGE_SIZE);
8965 
8966 	de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8967 	de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8968 
8969 	cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8970 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8971 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8972 				 WRITE_DATA_DST_SEL(8) |
8973 				 WR_CONFIRM) |
8974 				 WRITE_DATA_CACHE_POLICY(0));
8975 	amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
8976 	amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
8977 
8978 	if (resume)
8979 		amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
8980 					   sizeof(de_payload) >> 2);
8981 	else
8982 		amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8983 					   sizeof(de_payload) >> 2);
8984 }
8985 
8986 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8987 				    bool secure)
8988 {
8989 	uint32_t v = secure ? FRAME_TMZ : 0;
8990 
8991 	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8992 	amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8993 }
8994 
8995 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8996 				     uint32_t reg_val_offs)
8997 {
8998 	struct amdgpu_device *adev = ring->adev;
8999 
9000 	amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
9001 	amdgpu_ring_write(ring, 0 |	/* src: register*/
9002 				(5 << 8) |	/* dst: memory */
9003 				(1 << 20));	/* write confirm */
9004 	amdgpu_ring_write(ring, reg);
9005 	amdgpu_ring_write(ring, 0);
9006 	amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
9007 				reg_val_offs * 4));
9008 	amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
9009 				reg_val_offs * 4));
9010 }
9011 
9012 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
9013 				   uint32_t val)
9014 {
9015 	uint32_t cmd = 0;
9016 
9017 	switch (ring->funcs->type) {
9018 	case AMDGPU_RING_TYPE_GFX:
9019 		cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
9020 		break;
9021 	case AMDGPU_RING_TYPE_KIQ:
9022 		cmd = (1 << 16); /* no inc addr */
9023 		break;
9024 	default:
9025 		cmd = WR_CONFIRM;
9026 		break;
9027 	}
9028 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
9029 	amdgpu_ring_write(ring, cmd);
9030 	amdgpu_ring_write(ring, reg);
9031 	amdgpu_ring_write(ring, 0);
9032 	amdgpu_ring_write(ring, val);
9033 }
9034 
9035 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
9036 					uint32_t val, uint32_t mask)
9037 {
9038 	gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
9039 }
9040 
9041 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
9042 						   uint32_t reg0, uint32_t reg1,
9043 						   uint32_t ref, uint32_t mask)
9044 {
9045 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
9046 	struct amdgpu_device *adev = ring->adev;
9047 	bool fw_version_ok = false;
9048 
9049 	fw_version_ok = adev->gfx.cp_fw_write_wait;
9050 
9051 	if (fw_version_ok)
9052 		gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
9053 				       ref, mask, 0x20);
9054 	else
9055 		amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
9056 							   ref, mask);
9057 }
9058 
9059 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
9060 					 unsigned int vmid)
9061 {
9062 	struct amdgpu_device *adev = ring->adev;
9063 	uint32_t value = 0;
9064 
9065 	value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
9066 	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
9067 	value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
9068 	value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
9069 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
9070 	WREG32_SOC15(GC, 0, mmSQ_CMD, value);
9071 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
9072 }
9073 
9074 static void
9075 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
9076 				      uint32_t me, uint32_t pipe,
9077 				      enum amdgpu_interrupt_state state)
9078 {
9079 	uint32_t cp_int_cntl, cp_int_cntl_reg;
9080 
9081 	if (!me) {
9082 		switch (pipe) {
9083 		case 0:
9084 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
9085 			break;
9086 		case 1:
9087 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
9088 			break;
9089 		default:
9090 			DRM_DEBUG("invalid pipe %d\n", pipe);
9091 			return;
9092 		}
9093 	} else {
9094 		DRM_DEBUG("invalid me %d\n", me);
9095 		return;
9096 	}
9097 
9098 	switch (state) {
9099 	case AMDGPU_IRQ_STATE_DISABLE:
9100 		cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9101 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9102 					    TIME_STAMP_INT_ENABLE, 0);
9103 		WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9104 		break;
9105 	case AMDGPU_IRQ_STATE_ENABLE:
9106 		cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9107 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9108 					    TIME_STAMP_INT_ENABLE, 1);
9109 		WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9110 		break;
9111 	default:
9112 		break;
9113 	}
9114 }
9115 
9116 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
9117 						     int me, int pipe,
9118 						     enum amdgpu_interrupt_state state)
9119 {
9120 	u32 mec_int_cntl, mec_int_cntl_reg;
9121 
9122 	/*
9123 	 * amdgpu controls only the first MEC. That's why this function only
9124 	 * handles the setting of interrupts for this specific MEC. All other
9125 	 * pipes' interrupts are set by amdkfd.
9126 	 */
9127 
9128 	if (me == 1) {
9129 		switch (pipe) {
9130 		case 0:
9131 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9132 			break;
9133 		case 1:
9134 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
9135 			break;
9136 		case 2:
9137 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
9138 			break;
9139 		case 3:
9140 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
9141 			break;
9142 		default:
9143 			DRM_DEBUG("invalid pipe %d\n", pipe);
9144 			return;
9145 		}
9146 	} else {
9147 		DRM_DEBUG("invalid me %d\n", me);
9148 		return;
9149 	}
9150 
9151 	switch (state) {
9152 	case AMDGPU_IRQ_STATE_DISABLE:
9153 		mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9154 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9155 					     TIME_STAMP_INT_ENABLE, 0);
9156 		WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9157 		break;
9158 	case AMDGPU_IRQ_STATE_ENABLE:
9159 		mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9160 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9161 					     TIME_STAMP_INT_ENABLE, 1);
9162 		WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9163 		break;
9164 	default:
9165 		break;
9166 	}
9167 }
9168 
9169 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
9170 					    struct amdgpu_irq_src *src,
9171 					    unsigned int type,
9172 					    enum amdgpu_interrupt_state state)
9173 {
9174 	switch (type) {
9175 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
9176 		gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
9177 		break;
9178 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
9179 		gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
9180 		break;
9181 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
9182 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
9183 		break;
9184 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
9185 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
9186 		break;
9187 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
9188 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
9189 		break;
9190 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
9191 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
9192 		break;
9193 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
9194 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
9195 		break;
9196 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
9197 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
9198 		break;
9199 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
9200 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
9201 		break;
9202 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
9203 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
9204 		break;
9205 	default:
9206 		break;
9207 	}
9208 	return 0;
9209 }
9210 
9211 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
9212 			     struct amdgpu_irq_src *source,
9213 			     struct amdgpu_iv_entry *entry)
9214 {
9215 	int i;
9216 	u8 me_id, pipe_id, queue_id;
9217 	struct amdgpu_ring *ring;
9218 
9219 	DRM_DEBUG("IH: CP EOP\n");
9220 
9221 	me_id = (entry->ring_id & 0x0c) >> 2;
9222 	pipe_id = (entry->ring_id & 0x03) >> 0;
9223 	queue_id = (entry->ring_id & 0x70) >> 4;
9224 
9225 	switch (me_id) {
9226 	case 0:
9227 		if (pipe_id == 0)
9228 			amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
9229 		else
9230 			amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
9231 		break;
9232 	case 1:
9233 	case 2:
9234 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9235 			ring = &adev->gfx.compute_ring[i];
9236 			/* Per-queue interrupt is supported for MEC starting from VI.
9237 			 * The interrupt can only be enabled/disabled per pipe instead
9238 			 * of per queue.
9239 			 */
9240 			if ((ring->me == me_id) &&
9241 			    (ring->pipe == pipe_id) &&
9242 			    (ring->queue == queue_id))
9243 				amdgpu_fence_process(ring);
9244 		}
9245 		break;
9246 	}
9247 
9248 	return 0;
9249 }
9250 
9251 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
9252 					      struct amdgpu_irq_src *source,
9253 					      unsigned int type,
9254 					      enum amdgpu_interrupt_state state)
9255 {
9256 	u32 cp_int_cntl_reg, cp_int_cntl;
9257 	int i, j;
9258 
9259 	switch (state) {
9260 	case AMDGPU_IRQ_STATE_DISABLE:
9261 	case AMDGPU_IRQ_STATE_ENABLE:
9262 		for (i = 0; i < adev->gfx.me.num_me; i++) {
9263 			for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9264 				cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
9265 
9266 				if (cp_int_cntl_reg) {
9267 					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9268 					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9269 								    PRIV_REG_INT_ENABLE,
9270 								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9271 					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9272 				}
9273 			}
9274 		}
9275 		for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9276 			for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9277 				/* MECs start at 1 */
9278 				cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j);
9279 
9280 				if (cp_int_cntl_reg) {
9281 					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9282 					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9283 								    PRIV_REG_INT_ENABLE,
9284 								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9285 					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9286 				}
9287 			}
9288 		}
9289 		break;
9290 	default:
9291 		break;
9292 	}
9293 
9294 	return 0;
9295 }
9296 
9297 static int gfx_v10_0_set_bad_op_fault_state(struct amdgpu_device *adev,
9298 					    struct amdgpu_irq_src *source,
9299 					    unsigned type,
9300 					    enum amdgpu_interrupt_state state)
9301 {
9302 	u32 cp_int_cntl_reg, cp_int_cntl;
9303 	int i, j;
9304 
9305 	switch (state) {
9306 	case AMDGPU_IRQ_STATE_DISABLE:
9307 	case AMDGPU_IRQ_STATE_ENABLE:
9308 		for (i = 0; i < adev->gfx.me.num_me; i++) {
9309 			for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9310 				cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
9311 
9312 				if (cp_int_cntl_reg) {
9313 					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9314 					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9315 								    OPCODE_ERROR_INT_ENABLE,
9316 								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9317 					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9318 				}
9319 			}
9320 		}
9321 		for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9322 			for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9323 				/* MECs start at 1 */
9324 				cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j);
9325 
9326 				if (cp_int_cntl_reg) {
9327 					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9328 					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9329 								    OPCODE_ERROR_INT_ENABLE,
9330 								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9331 					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9332 				}
9333 			}
9334 		}
9335 		break;
9336 	default:
9337 		break;
9338 	}
9339 	return 0;
9340 }
9341 
9342 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
9343 					       struct amdgpu_irq_src *source,
9344 					       unsigned int type,
9345 					       enum amdgpu_interrupt_state state)
9346 {
9347 	u32 cp_int_cntl_reg, cp_int_cntl;
9348 	int i, j;
9349 
9350 	switch (state) {
9351 	case AMDGPU_IRQ_STATE_DISABLE:
9352 	case AMDGPU_IRQ_STATE_ENABLE:
9353 		for (i = 0; i < adev->gfx.me.num_me; i++) {
9354 			for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9355 				cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
9356 
9357 				if (cp_int_cntl_reg) {
9358 					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9359 					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9360 								    PRIV_INSTR_INT_ENABLE,
9361 								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9362 					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9363 				}
9364 			}
9365 		}
9366 		break;
9367 	default:
9368 		break;
9369 	}
9370 
9371 	return 0;
9372 }
9373 
9374 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
9375 					struct amdgpu_iv_entry *entry)
9376 {
9377 	u8 me_id, pipe_id, queue_id;
9378 	struct amdgpu_ring *ring;
9379 	int i;
9380 
9381 	me_id = (entry->ring_id & 0x0c) >> 2;
9382 	pipe_id = (entry->ring_id & 0x03) >> 0;
9383 	queue_id = (entry->ring_id & 0x70) >> 4;
9384 
9385 	switch (me_id) {
9386 	case 0:
9387 		for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9388 			ring = &adev->gfx.gfx_ring[i];
9389 			if (ring->me == me_id && ring->pipe == pipe_id &&
9390 			    ring->queue == queue_id)
9391 				drm_sched_fault(&ring->sched);
9392 		}
9393 		break;
9394 	case 1:
9395 	case 2:
9396 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9397 			ring = &adev->gfx.compute_ring[i];
9398 			if (ring->me == me_id && ring->pipe == pipe_id &&
9399 			    ring->queue == queue_id)
9400 				drm_sched_fault(&ring->sched);
9401 		}
9402 		break;
9403 	default:
9404 		BUG();
9405 	}
9406 }
9407 
9408 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
9409 				  struct amdgpu_irq_src *source,
9410 				  struct amdgpu_iv_entry *entry)
9411 {
9412 	DRM_ERROR("Illegal register access in command stream\n");
9413 	gfx_v10_0_handle_priv_fault(adev, entry);
9414 	return 0;
9415 }
9416 
9417 static int gfx_v10_0_bad_op_irq(struct amdgpu_device *adev,
9418 				struct amdgpu_irq_src *source,
9419 				struct amdgpu_iv_entry *entry)
9420 {
9421 	DRM_ERROR("Illegal opcode in command stream \n");
9422 	gfx_v10_0_handle_priv_fault(adev, entry);
9423 	return 0;
9424 }
9425 
9426 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
9427 				   struct amdgpu_irq_src *source,
9428 				   struct amdgpu_iv_entry *entry)
9429 {
9430 	DRM_ERROR("Illegal instruction in command stream\n");
9431 	gfx_v10_0_handle_priv_fault(adev, entry);
9432 	return 0;
9433 }
9434 
9435 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
9436 					     struct amdgpu_irq_src *src,
9437 					     unsigned int type,
9438 					     enum amdgpu_interrupt_state state)
9439 {
9440 	uint32_t tmp, target;
9441 	struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9442 
9443 	if (ring->me == 1)
9444 		target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9445 	else
9446 		target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
9447 	target += ring->pipe;
9448 
9449 	switch (type) {
9450 	case AMDGPU_CP_KIQ_IRQ_DRIVER0:
9451 		if (state == AMDGPU_IRQ_STATE_DISABLE) {
9452 			tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9453 			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9454 					    GENERIC2_INT_ENABLE, 0);
9455 			WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9456 
9457 			tmp = RREG32_SOC15_IP(GC, target);
9458 			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9459 					    GENERIC2_INT_ENABLE, 0);
9460 			WREG32_SOC15_IP(GC, target, tmp);
9461 		} else {
9462 			tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9463 			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9464 					    GENERIC2_INT_ENABLE, 1);
9465 			WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9466 
9467 			tmp = RREG32_SOC15_IP(GC, target);
9468 			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9469 					    GENERIC2_INT_ENABLE, 1);
9470 			WREG32_SOC15_IP(GC, target, tmp);
9471 		}
9472 		break;
9473 	default:
9474 		BUG(); /* kiq only support GENERIC2_INT now */
9475 		break;
9476 	}
9477 	return 0;
9478 }
9479 
9480 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
9481 			     struct amdgpu_irq_src *source,
9482 			     struct amdgpu_iv_entry *entry)
9483 {
9484 	u8 me_id, pipe_id, queue_id;
9485 	struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9486 
9487 	me_id = (entry->ring_id & 0x0c) >> 2;
9488 	pipe_id = (entry->ring_id & 0x03) >> 0;
9489 	queue_id = (entry->ring_id & 0x70) >> 4;
9490 	DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
9491 		   me_id, pipe_id, queue_id);
9492 
9493 	amdgpu_fence_process(ring);
9494 	return 0;
9495 }
9496 
9497 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
9498 {
9499 	const unsigned int gcr_cntl =
9500 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
9501 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
9502 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
9503 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
9504 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
9505 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
9506 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
9507 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
9508 
9509 	/* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
9510 	amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
9511 	amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
9512 	amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
9513 	amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
9514 	amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9515 	amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
9516 	amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9517 	amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9518 }
9519 
9520 static void gfx_v10_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)
9521 {
9522 	/* Header itself is a NOP packet */
9523 	if (num_nop == 1) {
9524 		amdgpu_ring_write(ring, ring->funcs->nop);
9525 		return;
9526 	}
9527 
9528 	/* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/
9529 	amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe)));
9530 
9531 	/* Header is at index 0, followed by num_nops - 1 NOP packet's */
9532 	amdgpu_ring_insert_nop(ring, num_nop - 1);
9533 }
9534 
9535 static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid)
9536 {
9537 	struct amdgpu_device *adev = ring->adev;
9538 	struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
9539 	struct amdgpu_ring *kiq_ring = &kiq->ring;
9540 	unsigned long flags;
9541 	u32 tmp;
9542 	u64 addr;
9543 	int r;
9544 
9545 	if (amdgpu_sriov_vf(adev))
9546 		return -EINVAL;
9547 
9548 	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
9549 		return -EINVAL;
9550 
9551 	spin_lock_irqsave(&kiq->ring_lock, flags);
9552 
9553 	if (amdgpu_ring_alloc(kiq_ring, 5 + 7 + 7 + kiq->pmf->map_queues_size)) {
9554 		spin_unlock_irqrestore(&kiq->ring_lock, flags);
9555 		return -ENOMEM;
9556 	}
9557 
9558 	addr = amdgpu_bo_gpu_offset(ring->mqd_obj) +
9559 		offsetof(struct v10_gfx_mqd, cp_gfx_hqd_active);
9560 	tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);
9561 	if (ring->pipe == 0)
9562 		tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << ring->queue);
9563 	else
9564 		tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << ring->queue);
9565 
9566 	gfx_v10_0_ring_emit_wreg(kiq_ring,
9567 				 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), tmp);
9568 	gfx_v10_0_wait_reg_mem(kiq_ring, 0, 1, 0,
9569 			       lower_32_bits(addr), upper_32_bits(addr),
9570 			       0, 1, 0x20);
9571 	gfx_v10_0_ring_emit_reg_wait(kiq_ring,
9572 				     SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0, 0xffffffff);
9573 	kiq->pmf->kiq_map_queues(kiq_ring, ring);
9574 	amdgpu_ring_commit(kiq_ring);
9575 
9576 	spin_unlock_irqrestore(&kiq->ring_lock, flags);
9577 
9578 	r = amdgpu_ring_test_ring(kiq_ring);
9579 	if (r)
9580 		return r;
9581 
9582 	r = amdgpu_bo_reserve(ring->mqd_obj, false);
9583 	if (unlikely(r != 0)) {
9584 		DRM_ERROR("fail to resv mqd_obj\n");
9585 		return r;
9586 	}
9587 	r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
9588 	if (!r) {
9589 		r = gfx_v10_0_kgq_init_queue(ring, true);
9590 		amdgpu_bo_kunmap(ring->mqd_obj);
9591 		ring->mqd_ptr = NULL;
9592 	}
9593 	amdgpu_bo_unreserve(ring->mqd_obj);
9594 	if (r) {
9595 		DRM_ERROR("fail to unresv mqd_obj\n");
9596 		return r;
9597 	}
9598 
9599 	return amdgpu_ring_test_ring(ring);
9600 }
9601 
9602 static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring,
9603 			       unsigned int vmid)
9604 {
9605 	struct amdgpu_device *adev = ring->adev;
9606 	struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
9607 	struct amdgpu_ring *kiq_ring = &kiq->ring;
9608 	unsigned long flags;
9609 	int i, r;
9610 
9611 	if (amdgpu_sriov_vf(adev))
9612 		return -EINVAL;
9613 
9614 	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
9615 		return -EINVAL;
9616 
9617 	spin_lock_irqsave(&kiq->ring_lock, flags);
9618 
9619 	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
9620 		spin_unlock_irqrestore(&kiq->ring_lock, flags);
9621 		return -ENOMEM;
9622 	}
9623 
9624 	kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES,
9625 				   0, 0);
9626 	amdgpu_ring_commit(kiq_ring);
9627 	spin_unlock_irqrestore(&kiq->ring_lock, flags);
9628 
9629 	r = amdgpu_ring_test_ring(kiq_ring);
9630 	if (r)
9631 		return r;
9632 
9633 	/* make sure dequeue is complete*/
9634 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
9635 	mutex_lock(&adev->srbm_mutex);
9636 	nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
9637 	for (i = 0; i < adev->usec_timeout; i++) {
9638 		if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
9639 			break;
9640 		udelay(1);
9641 	}
9642 	if (i >= adev->usec_timeout)
9643 		r = -ETIMEDOUT;
9644 	nv_grbm_select(adev, 0, 0, 0, 0);
9645 	mutex_unlock(&adev->srbm_mutex);
9646 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
9647 	if (r) {
9648 		dev_err(adev->dev, "fail to wait on hqd deactivate\n");
9649 		return r;
9650 	}
9651 
9652 	r = amdgpu_bo_reserve(ring->mqd_obj, false);
9653 	if (unlikely(r != 0)) {
9654 		dev_err(adev->dev, "fail to resv mqd_obj\n");
9655 		return r;
9656 	}
9657 	r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
9658 	if (!r) {
9659 		r = gfx_v10_0_kcq_init_queue(ring, true);
9660 		amdgpu_bo_kunmap(ring->mqd_obj);
9661 		ring->mqd_ptr = NULL;
9662 	}
9663 	amdgpu_bo_unreserve(ring->mqd_obj);
9664 	if (r) {
9665 		dev_err(adev->dev, "fail to unresv mqd_obj\n");
9666 		return r;
9667 	}
9668 
9669 	spin_lock_irqsave(&kiq->ring_lock, flags);
9670 	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size)) {
9671 		spin_unlock_irqrestore(&kiq->ring_lock, flags);
9672 		return -ENOMEM;
9673 	}
9674 	kiq->pmf->kiq_map_queues(kiq_ring, ring);
9675 	amdgpu_ring_commit(kiq_ring);
9676 	spin_unlock_irqrestore(&kiq->ring_lock, flags);
9677 
9678 	r = amdgpu_ring_test_ring(kiq_ring);
9679 	if (r)
9680 		return r;
9681 
9682 	return amdgpu_ring_test_ring(ring);
9683 }
9684 
9685 static void gfx_v10_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
9686 {
9687 	struct amdgpu_device *adev = ip_block->adev;
9688 	uint32_t i, j, k, reg, index = 0;
9689 	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
9690 
9691 	if (!adev->gfx.ip_dump_core)
9692 		return;
9693 
9694 	for (i = 0; i < reg_count; i++)
9695 		drm_printf(p, "%-50s \t 0x%08x\n",
9696 			   gc_reg_list_10_1[i].reg_name,
9697 			   adev->gfx.ip_dump_core[i]);
9698 
9699 	/* print compute queue registers for all instances */
9700 	if (!adev->gfx.ip_dump_compute_queues)
9701 		return;
9702 
9703 	reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
9704 	drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n",
9705 		   adev->gfx.mec.num_mec,
9706 		   adev->gfx.mec.num_pipe_per_mec,
9707 		   adev->gfx.mec.num_queue_per_pipe);
9708 
9709 	for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9710 		for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9711 			for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
9712 				drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
9713 				for (reg = 0; reg < reg_count; reg++) {
9714 					drm_printf(p, "%-50s \t 0x%08x\n",
9715 						   gc_cp_reg_list_10[reg].reg_name,
9716 						   adev->gfx.ip_dump_compute_queues[index + reg]);
9717 				}
9718 				index += reg_count;
9719 			}
9720 		}
9721 	}
9722 
9723 	/* print gfx queue registers for all instances */
9724 	if (!adev->gfx.ip_dump_gfx_queues)
9725 		return;
9726 
9727 	index = 0;
9728 	reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
9729 	drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",
9730 		   adev->gfx.me.num_me,
9731 		   adev->gfx.me.num_pipe_per_me,
9732 		   adev->gfx.me.num_queue_per_pipe);
9733 
9734 	for (i = 0; i < adev->gfx.me.num_me; i++) {
9735 		for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9736 			for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
9737 				drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);
9738 				for (reg = 0; reg < reg_count; reg++) {
9739 					drm_printf(p, "%-50s \t 0x%08x\n",
9740 						   gc_gfx_queue_reg_list_10[reg].reg_name,
9741 						   adev->gfx.ip_dump_gfx_queues[index + reg]);
9742 				}
9743 				index += reg_count;
9744 			}
9745 		}
9746 	}
9747 }
9748 
9749 static void gfx_v10_ip_dump(struct amdgpu_ip_block *ip_block)
9750 {
9751 	struct amdgpu_device *adev = ip_block->adev;
9752 	uint32_t i, j, k, reg, index = 0;
9753 	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
9754 
9755 	if (!adev->gfx.ip_dump_core)
9756 		return;
9757 
9758 	amdgpu_gfx_off_ctrl(adev, false);
9759 	for (i = 0; i < reg_count; i++)
9760 		adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
9761 	amdgpu_gfx_off_ctrl(adev, true);
9762 
9763 	/* dump compute queue registers for all instances */
9764 	if (!adev->gfx.ip_dump_compute_queues)
9765 		return;
9766 
9767 	reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
9768 	amdgpu_gfx_off_ctrl(adev, false);
9769 	mutex_lock(&adev->srbm_mutex);
9770 	for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9771 		for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9772 			for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
9773 				/* ME0 is for GFX so start from 1 for CP */
9774 				nv_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);
9775 
9776 				for (reg = 0; reg < reg_count; reg++) {
9777 					adev->gfx.ip_dump_compute_queues[index + reg] =
9778 						RREG32(SOC15_REG_ENTRY_OFFSET(
9779 							gc_cp_reg_list_10[reg]));
9780 				}
9781 				index += reg_count;
9782 			}
9783 		}
9784 	}
9785 	nv_grbm_select(adev, 0, 0, 0, 0);
9786 	mutex_unlock(&adev->srbm_mutex);
9787 	amdgpu_gfx_off_ctrl(adev, true);
9788 
9789 	/* dump gfx queue registers for all instances */
9790 	if (!adev->gfx.ip_dump_gfx_queues)
9791 		return;
9792 
9793 	index = 0;
9794 	reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
9795 	amdgpu_gfx_off_ctrl(adev, false);
9796 	mutex_lock(&adev->srbm_mutex);
9797 	for (i = 0; i < adev->gfx.me.num_me; i++) {
9798 		for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9799 			for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
9800 				nv_grbm_select(adev, i, j, k, 0);
9801 
9802 				for (reg = 0; reg < reg_count; reg++) {
9803 					adev->gfx.ip_dump_gfx_queues[index + reg] =
9804 						RREG32(SOC15_REG_ENTRY_OFFSET(
9805 							gc_gfx_queue_reg_list_10[reg]));
9806 				}
9807 				index += reg_count;
9808 			}
9809 		}
9810 	}
9811 	nv_grbm_select(adev, 0, 0, 0, 0);
9812 	mutex_unlock(&adev->srbm_mutex);
9813 	amdgpu_gfx_off_ctrl(adev, true);
9814 }
9815 
9816 static void gfx_v10_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring)
9817 {
9818 	/* Emit the cleaner shader */
9819 	amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0));
9820 	amdgpu_ring_write(ring, 0);  /* RESERVED field, programmed to zero */
9821 }
9822 
9823 static void gfx_v10_0_ring_begin_use(struct amdgpu_ring *ring)
9824 {
9825 	amdgpu_gfx_profile_ring_begin_use(ring);
9826 
9827 	amdgpu_gfx_enforce_isolation_ring_begin_use(ring);
9828 }
9829 
9830 static void gfx_v10_0_ring_end_use(struct amdgpu_ring *ring)
9831 {
9832 	amdgpu_gfx_profile_ring_end_use(ring);
9833 
9834 	amdgpu_gfx_enforce_isolation_ring_end_use(ring);
9835 }
9836 
9837 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9838 	.name = "gfx_v10_0",
9839 	.early_init = gfx_v10_0_early_init,
9840 	.late_init = gfx_v10_0_late_init,
9841 	.sw_init = gfx_v10_0_sw_init,
9842 	.sw_fini = gfx_v10_0_sw_fini,
9843 	.hw_init = gfx_v10_0_hw_init,
9844 	.hw_fini = gfx_v10_0_hw_fini,
9845 	.suspend = gfx_v10_0_suspend,
9846 	.resume = gfx_v10_0_resume,
9847 	.is_idle = gfx_v10_0_is_idle,
9848 	.wait_for_idle = gfx_v10_0_wait_for_idle,
9849 	.soft_reset = gfx_v10_0_soft_reset,
9850 	.set_clockgating_state = gfx_v10_0_set_clockgating_state,
9851 	.set_powergating_state = gfx_v10_0_set_powergating_state,
9852 	.get_clockgating_state = gfx_v10_0_get_clockgating_state,
9853 	.dump_ip_state = gfx_v10_ip_dump,
9854 	.print_ip_state = gfx_v10_ip_print,
9855 };
9856 
9857 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9858 	.type = AMDGPU_RING_TYPE_GFX,
9859 	.align_mask = 0xff,
9860 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
9861 	.support_64bit_ptrs = true,
9862 	.secure_submission_supported = true,
9863 	.get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9864 	.get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9865 	.set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9866 	.emit_frame_size = /* totally 242 maximum if 16 IBs */
9867 		5 + /* COND_EXEC */
9868 		7 + /* PIPELINE_SYNC */
9869 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9870 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9871 		4 + /* VM_FLUSH */
9872 		8 + /* FENCE for VM_FLUSH */
9873 		20 + /* GDS switch */
9874 		4 + /* double SWITCH_BUFFER,
9875 		     * the first COND_EXEC jump to the place
9876 		     * just prior to this double SWITCH_BUFFER
9877 		     */
9878 		5 + /* COND_EXEC */
9879 		7 + /* HDP_flush */
9880 		4 + /* VGT_flush */
9881 		14 + /*	CE_META */
9882 		31 + /*	DE_META */
9883 		3 + /* CNTX_CTRL */
9884 		5 + /* HDP_INVL */
9885 		8 + 8 + /* FENCE x2 */
9886 		2 + /* SWITCH_BUFFER */
9887 		8 + /* gfx_v10_0_emit_mem_sync */
9888 		2, /* gfx_v10_0_ring_emit_cleaner_shader */
9889 	.emit_ib_size =	4, /* gfx_v10_0_ring_emit_ib_gfx */
9890 	.emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9891 	.emit_fence = gfx_v10_0_ring_emit_fence,
9892 	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9893 	.emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9894 	.emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9895 	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9896 	.test_ring = gfx_v10_0_ring_test_ring,
9897 	.test_ib = gfx_v10_0_ring_test_ib,
9898 	.insert_nop = gfx_v10_ring_insert_nop,
9899 	.pad_ib = amdgpu_ring_generic_pad_ib,
9900 	.emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9901 	.emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9902 	.init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9903 	.preempt_ib = gfx_v10_0_ring_preempt_ib,
9904 	.emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9905 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
9906 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9907 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9908 	.soft_recovery = gfx_v10_0_ring_soft_recovery,
9909 	.emit_mem_sync = gfx_v10_0_emit_mem_sync,
9910 	.reset = gfx_v10_0_reset_kgq,
9911 	.emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,
9912 	.begin_use = gfx_v10_0_ring_begin_use,
9913 	.end_use = gfx_v10_0_ring_end_use,
9914 };
9915 
9916 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9917 	.type = AMDGPU_RING_TYPE_COMPUTE,
9918 	.align_mask = 0xff,
9919 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
9920 	.support_64bit_ptrs = true,
9921 	.get_rptr = gfx_v10_0_ring_get_rptr_compute,
9922 	.get_wptr = gfx_v10_0_ring_get_wptr_compute,
9923 	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
9924 	.emit_frame_size =
9925 		20 + /* gfx_v10_0_ring_emit_gds_switch */
9926 		7 + /* gfx_v10_0_ring_emit_hdp_flush */
9927 		5 + /* hdp invalidate */
9928 		7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9929 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9930 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9931 		2 + /* gfx_v10_0_ring_emit_vm_flush */
9932 		8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9933 		8 + /* gfx_v10_0_emit_mem_sync */
9934 		2, /* gfx_v10_0_ring_emit_cleaner_shader */
9935 	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */
9936 	.emit_ib = gfx_v10_0_ring_emit_ib_compute,
9937 	.emit_fence = gfx_v10_0_ring_emit_fence,
9938 	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9939 	.emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9940 	.emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9941 	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9942 	.test_ring = gfx_v10_0_ring_test_ring,
9943 	.test_ib = gfx_v10_0_ring_test_ib,
9944 	.insert_nop = gfx_v10_ring_insert_nop,
9945 	.pad_ib = amdgpu_ring_generic_pad_ib,
9946 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
9947 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9948 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9949 	.soft_recovery = gfx_v10_0_ring_soft_recovery,
9950 	.emit_mem_sync = gfx_v10_0_emit_mem_sync,
9951 	.reset = gfx_v10_0_reset_kcq,
9952 	.emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,
9953 	.begin_use = gfx_v10_0_ring_begin_use,
9954 	.end_use = gfx_v10_0_ring_end_use,
9955 };
9956 
9957 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9958 	.type = AMDGPU_RING_TYPE_KIQ,
9959 	.align_mask = 0xff,
9960 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
9961 	.support_64bit_ptrs = true,
9962 	.get_rptr = gfx_v10_0_ring_get_rptr_compute,
9963 	.get_wptr = gfx_v10_0_ring_get_wptr_compute,
9964 	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
9965 	.emit_frame_size =
9966 		20 + /* gfx_v10_0_ring_emit_gds_switch */
9967 		7 + /* gfx_v10_0_ring_emit_hdp_flush */
9968 		5 + /*hdp invalidate */
9969 		7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9970 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9971 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9972 		8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9973 	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */
9974 	.emit_ib = gfx_v10_0_ring_emit_ib_compute,
9975 	.emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9976 	.test_ring = gfx_v10_0_ring_test_ring,
9977 	.test_ib = gfx_v10_0_ring_test_ib,
9978 	.insert_nop = amdgpu_ring_insert_nop,
9979 	.pad_ib = amdgpu_ring_generic_pad_ib,
9980 	.emit_rreg = gfx_v10_0_ring_emit_rreg,
9981 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
9982 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9983 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9984 };
9985 
9986 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9987 {
9988 	int i;
9989 
9990 	adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9991 
9992 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9993 		adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9994 
9995 	for (i = 0; i < adev->gfx.num_compute_rings; i++)
9996 		adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9997 }
9998 
9999 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
10000 	.set = gfx_v10_0_set_eop_interrupt_state,
10001 	.process = gfx_v10_0_eop_irq,
10002 };
10003 
10004 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
10005 	.set = gfx_v10_0_set_priv_reg_fault_state,
10006 	.process = gfx_v10_0_priv_reg_irq,
10007 };
10008 
10009 static const struct amdgpu_irq_src_funcs gfx_v10_0_bad_op_irq_funcs = {
10010 	.set = gfx_v10_0_set_bad_op_fault_state,
10011 	.process = gfx_v10_0_bad_op_irq,
10012 };
10013 
10014 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
10015 	.set = gfx_v10_0_set_priv_inst_fault_state,
10016 	.process = gfx_v10_0_priv_inst_irq,
10017 };
10018 
10019 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
10020 	.set = gfx_v10_0_kiq_set_interrupt_state,
10021 	.process = gfx_v10_0_kiq_irq,
10022 };
10023 
10024 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
10025 {
10026 	adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
10027 	adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
10028 
10029 	adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
10030 	adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs;
10031 
10032 	adev->gfx.priv_reg_irq.num_types = 1;
10033 	adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
10034 
10035 	adev->gfx.bad_op_irq.num_types = 1;
10036 	adev->gfx.bad_op_irq.funcs = &gfx_v10_0_bad_op_irq_funcs;
10037 
10038 	adev->gfx.priv_inst_irq.num_types = 1;
10039 	adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
10040 }
10041 
10042 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
10043 {
10044 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
10045 	case IP_VERSION(10, 1, 10):
10046 	case IP_VERSION(10, 1, 1):
10047 	case IP_VERSION(10, 1, 3):
10048 	case IP_VERSION(10, 1, 4):
10049 	case IP_VERSION(10, 3, 2):
10050 	case IP_VERSION(10, 3, 1):
10051 	case IP_VERSION(10, 3, 4):
10052 	case IP_VERSION(10, 3, 5):
10053 	case IP_VERSION(10, 3, 6):
10054 	case IP_VERSION(10, 3, 3):
10055 	case IP_VERSION(10, 3, 7):
10056 		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
10057 		break;
10058 	case IP_VERSION(10, 1, 2):
10059 	case IP_VERSION(10, 3, 0):
10060 		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
10061 		break;
10062 	default:
10063 		break;
10064 	}
10065 }
10066 
10067 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
10068 {
10069 	unsigned int total_cu = adev->gfx.config.max_cu_per_sh *
10070 			    adev->gfx.config.max_sh_per_se *
10071 			    adev->gfx.config.max_shader_engines;
10072 
10073 	adev->gds.gds_size = 0x10000;
10074 	adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
10075 	adev->gds.gws_size = 64;
10076 	adev->gds.oa_size = 16;
10077 }
10078 
10079 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev)
10080 {
10081 	/* set gfx eng mqd */
10082 	adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
10083 		sizeof(struct v10_gfx_mqd);
10084 	adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
10085 		gfx_v10_0_gfx_mqd_init;
10086 	/* set compute eng mqd */
10087 	adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
10088 		sizeof(struct v10_compute_mqd);
10089 	adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
10090 		gfx_v10_0_compute_mqd_init;
10091 }
10092 
10093 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
10094 							  u32 bitmap)
10095 {
10096 	u32 data;
10097 
10098 	if (!bitmap)
10099 		return;
10100 
10101 	data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
10102 	data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
10103 
10104 	WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
10105 }
10106 
10107 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
10108 {
10109 	u32 disabled_mask =
10110 		~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
10111 	u32 efuse_setting = 0;
10112 	u32 vbios_setting = 0;
10113 
10114 	efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
10115 	efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
10116 	efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
10117 
10118 	vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
10119 	vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
10120 	vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
10121 
10122 	disabled_mask |= efuse_setting | vbios_setting;
10123 
10124 	return (~disabled_mask);
10125 }
10126 
10127 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
10128 {
10129 	u32 wgp_idx, wgp_active_bitmap;
10130 	u32 cu_bitmap_per_wgp, cu_active_bitmap;
10131 
10132 	wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
10133 	cu_active_bitmap = 0;
10134 
10135 	for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
10136 		/* if there is one WGP enabled, it means 2 CUs will be enabled */
10137 		cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
10138 		if (wgp_active_bitmap & (1 << wgp_idx))
10139 			cu_active_bitmap |= cu_bitmap_per_wgp;
10140 	}
10141 
10142 	return cu_active_bitmap;
10143 }
10144 
10145 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
10146 				 struct amdgpu_cu_info *cu_info)
10147 {
10148 	int i, j, k, counter, active_cu_number = 0;
10149 	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
10150 	unsigned int disable_masks[4 * 2];
10151 
10152 	if (!adev || !cu_info)
10153 		return -EINVAL;
10154 
10155 	amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
10156 
10157 	mutex_lock(&adev->grbm_idx_mutex);
10158 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
10159 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
10160 			bitmap = i * adev->gfx.config.max_sh_per_se + j;
10161 			if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==
10162 			      IP_VERSION(10, 3, 0)) ||
10163 			     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
10164 			      IP_VERSION(10, 3, 3)) ||
10165 			     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
10166 			      IP_VERSION(10, 3, 6)) ||
10167 			     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
10168 			      IP_VERSION(10, 3, 7))) &&
10169 			    ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
10170 				continue;
10171 			mask = 1;
10172 			ao_bitmap = 0;
10173 			counter = 0;
10174 			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
10175 			if (i < 4 && j < 2)
10176 				gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
10177 					adev, disable_masks[i * 2 + j]);
10178 			bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
10179 			cu_info->bitmap[0][i][j] = bitmap;
10180 
10181 			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
10182 				if (bitmap & mask) {
10183 					if (counter < adev->gfx.config.max_cu_per_sh)
10184 						ao_bitmap |= mask;
10185 					counter++;
10186 				}
10187 				mask <<= 1;
10188 			}
10189 			active_cu_number += counter;
10190 			if (i < 2 && j < 2)
10191 				ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
10192 			cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
10193 		}
10194 	}
10195 	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
10196 	mutex_unlock(&adev->grbm_idx_mutex);
10197 
10198 	cu_info->number = active_cu_number;
10199 	cu_info->ao_cu_mask = ao_cu_mask;
10200 	cu_info->simd_per_cu = NUM_SIMD_PER_CU;
10201 
10202 	return 0;
10203 }
10204 
10205 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
10206 {
10207 	uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
10208 
10209 	efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
10210 	efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
10211 	efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
10212 
10213 	vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
10214 	vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
10215 	vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
10216 
10217 	max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
10218 						adev->gfx.config.max_shader_engines);
10219 	disabled_sa = efuse_setting | vbios_setting;
10220 	disabled_sa &= max_sa_mask;
10221 
10222 	return disabled_sa;
10223 }
10224 
10225 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
10226 {
10227 	uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
10228 	uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
10229 
10230 	disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
10231 
10232 	max_sa_per_se = adev->gfx.config.max_sh_per_se;
10233 	max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
10234 	max_shader_engines = adev->gfx.config.max_shader_engines;
10235 
10236 	for (se_index = 0; max_shader_engines > se_index; se_index++) {
10237 		disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
10238 		disabled_sa_per_se &= max_sa_per_se_mask;
10239 		if (disabled_sa_per_se == max_sa_per_se_mask) {
10240 			WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
10241 			break;
10242 		}
10243 	}
10244 }
10245 
10246 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
10247 {
10248 	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
10249 		     (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
10250 		     (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
10251 		     (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
10252 
10253 	WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
10254 	WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
10255 		     (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
10256 		     (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
10257 		     (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
10258 		     (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
10259 
10260 	WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
10261 		     (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
10262 		     (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
10263 		     (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
10264 
10265 	WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
10266 
10267 	WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
10268 		     (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
10269 }
10270 
10271 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = {
10272 	.type = AMD_IP_BLOCK_TYPE_GFX,
10273 	.major = 10,
10274 	.minor = 0,
10275 	.rev = 0,
10276 	.funcs = &gfx_v10_0_ip_funcs,
10277 };
10278