1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Exynos specific definitions for Samsung pinctrl and gpiolib driver. 4 * 5 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 * Copyright (c) 2012 Linaro Ltd 8 * http://www.linaro.org 9 * 10 * This file contains the Exynos specific definitions for the Samsung 11 * pinctrl/gpiolib interface drivers. 12 * 13 * Author: Thomas Abraham <thomas.ab@samsung.com> 14 */ 15 16 #ifndef __PINCTRL_SAMSUNG_EXYNOS_H 17 #define __PINCTRL_SAMSUNG_EXYNOS_H 18 19 /* Values for the pin CON register */ 20 #define EXYNOS_PIN_CON_FUNC_EINT 0xf 21 22 /* External GPIO and wakeup interrupt related definitions */ 23 #define EXYNOS_GPIO_ECON_OFFSET 0x700 24 #define EXYNOS_GPIO_EFLTCON_OFFSET 0x800 25 #define EXYNOS_GPIO_EMASK_OFFSET 0x900 26 #define EXYNOS_GPIO_EPEND_OFFSET 0xA00 27 #define EXYNOS_WKUP_ECON_OFFSET 0xE00 28 #define EXYNOS_WKUP_EMASK_OFFSET 0xF00 29 #define EXYNOS_WKUP_EPEND_OFFSET 0xF40 30 #define EXYNOS7_WKUP_ECON_OFFSET 0x700 31 #define EXYNOS7_WKUP_EMASK_OFFSET 0x900 32 #define EXYNOS7_WKUP_EPEND_OFFSET 0xA00 33 #define EXYNOS_SVC_OFFSET 0xB08 34 #define EXYNOSAUTO_SVC_OFFSET 0xF008 35 36 /* helpers to access interrupt service register */ 37 #define EXYNOS_SVC_GROUP_SHIFT 3 38 #define EXYNOS_SVC_GROUP_MASK 0x1f 39 #define EXYNOS_SVC_NUM_MASK 7 40 #define EXYNOS_SVC_GROUP(x) ((x >> EXYNOS_SVC_GROUP_SHIFT) & \ 41 EXYNOS_SVC_GROUP_MASK) 42 43 /* Exynos specific external interrupt trigger types */ 44 #define EXYNOS_EINT_LEVEL_LOW 0 45 #define EXYNOS_EINT_LEVEL_HIGH 1 46 #define EXYNOS_EINT_EDGE_FALLING 2 47 #define EXYNOS_EINT_EDGE_RISING 3 48 #define EXYNOS_EINT_EDGE_BOTH 4 49 #define EXYNOS_EINT_CON_MASK 0xF 50 #define EXYNOS_EINT_CON_LEN 4 51 52 #define EXYNOS_EINT_MAX_PER_BANK 8 53 #define EXYNOS_EINT_NR_WKUP_EINT 54 55 #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ 56 { \ 57 .type = &bank_type_off, \ 58 .pctl_offset = reg, \ 59 .nr_pins = pins, \ 60 .eint_type = EINT_TYPE_NONE, \ 61 .name = id \ 62 } 63 64 #define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \ 65 { \ 66 .type = &bank_type_off, \ 67 .pctl_offset = reg, \ 68 .nr_pins = pins, \ 69 .eint_type = EINT_TYPE_GPIO, \ 70 .eint_offset = offs, \ 71 .name = id \ 72 } 73 74 #define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \ 75 { \ 76 .type = &bank_type_alive, \ 77 .pctl_offset = reg, \ 78 .nr_pins = pins, \ 79 .eint_type = EINT_TYPE_WKUP, \ 80 .eint_offset = offs, \ 81 .name = id \ 82 } 83 84 #define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs) \ 85 { \ 86 .type = &exynos5433_bank_type_off, \ 87 .pctl_offset = reg, \ 88 .nr_pins = pins, \ 89 .eint_type = EINT_TYPE_GPIO, \ 90 .eint_offset = offs, \ 91 .name = id \ 92 } 93 94 #define EXYNOS5433_PIN_BANK_EINTW(pins, reg, id, offs) \ 95 { \ 96 .type = &exynos5433_bank_type_alive, \ 97 .pctl_offset = reg, \ 98 .nr_pins = pins, \ 99 .eint_type = EINT_TYPE_WKUP, \ 100 .eint_offset = offs, \ 101 .name = id \ 102 } 103 104 #define EXYNOS5433_PIN_BANK_EINTW_EXT(pins, reg, id, offs, pctl_idx) \ 105 { \ 106 .type = &exynos5433_bank_type_off, \ 107 .pctl_offset = reg, \ 108 .nr_pins = pins, \ 109 .eint_type = EINT_TYPE_WKUP, \ 110 .eint_offset = offs, \ 111 .name = id, \ 112 .pctl_res_idx = pctl_idx, \ 113 } \ 114 115 #define EXYNOS850_PIN_BANK_EINTN(pins, reg, id) \ 116 { \ 117 .type = &exynos850_bank_type_alive, \ 118 .pctl_offset = reg, \ 119 .nr_pins = pins, \ 120 .eint_type = EINT_TYPE_NONE, \ 121 .name = id \ 122 } 123 124 #define EXYNOS850_PIN_BANK_EINTG(pins, reg, id, offs) \ 125 { \ 126 .type = &exynos850_bank_type_off, \ 127 .pctl_offset = reg, \ 128 .nr_pins = pins, \ 129 .eint_type = EINT_TYPE_GPIO, \ 130 .eint_offset = offs, \ 131 .name = id \ 132 } 133 134 #define EXYNOS850_PIN_BANK_EINTW(pins, reg, id, offs) \ 135 { \ 136 .type = &exynos850_bank_type_alive, \ 137 .pctl_offset = reg, \ 138 .nr_pins = pins, \ 139 .eint_type = EINT_TYPE_WKUP, \ 140 .eint_offset = offs, \ 141 .name = id \ 142 } 143 144 #define EXYNOS8895_PIN_BANK_EINTG(pins, reg, id, offs) \ 145 { \ 146 .type = &exynos8895_bank_type_off, \ 147 .pctl_offset = reg, \ 148 .nr_pins = pins, \ 149 .eint_type = EINT_TYPE_GPIO, \ 150 .eint_offset = offs, \ 151 .name = id \ 152 } 153 154 #define EXYNOSV920_PIN_BANK_EINTG(pins, reg, id, con_offs, mask_offs, pend_offs) \ 155 { \ 156 .type = &exynos850_bank_type_off, \ 157 .pctl_offset = reg, \ 158 .nr_pins = pins, \ 159 .eint_type = EINT_TYPE_GPIO, \ 160 .eint_con_offset = con_offs, \ 161 .eint_mask_offset = mask_offs, \ 162 .eint_pend_offset = pend_offs, \ 163 .name = id \ 164 } 165 166 #define EXYNOSV920_PIN_BANK_EINTW(pins, reg, id, con_offs, mask_offs, pend_offs) \ 167 { \ 168 .type = &exynos850_bank_type_alive, \ 169 .pctl_offset = reg, \ 170 .nr_pins = pins, \ 171 .eint_type = EINT_TYPE_WKUP, \ 172 .eint_con_offset = con_offs, \ 173 .eint_mask_offset = mask_offs, \ 174 .eint_pend_offset = pend_offs, \ 175 .name = id \ 176 } 177 178 /** 179 * struct exynos_weint_data: irq specific data for all the wakeup interrupts 180 * generated by the external wakeup interrupt controller. 181 * @irq: interrupt number within the domain. 182 * @bank: bank responsible for this interrupt 183 */ 184 struct exynos_weint_data { 185 unsigned int irq; 186 struct samsung_pin_bank *bank; 187 }; 188 189 /** 190 * struct exynos_muxed_weint_data: irq specific data for muxed wakeup interrupts 191 * generated by the external wakeup interrupt controller. 192 * @nr_banks: count of banks being part of the mux 193 * @banks: array of banks being part of the mux 194 */ 195 struct exynos_muxed_weint_data { 196 unsigned int nr_banks; 197 struct samsung_pin_bank *banks[] __counted_by(nr_banks); 198 }; 199 200 int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d); 201 int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d); 202 void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata); 203 void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata); 204 struct samsung_retention_ctrl * 205 exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, 206 const struct samsung_retention_data *data); 207 208 #endif /* __PINCTRL_SAMSUNG_EXYNOS_H */ 209