1 /*
2 *
3 * CDDL HEADER START
4 *
5 * The contents of this file are subject to the terms of the
6 * Common Development and Distribution License (the "License").
7 * You may not use this file except in compliance with the License.
8 *
9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 * or http://www.opensolaris.org/os/licensing.
11 * See the License for the specific language governing permissions
12 * and limitations under the License.
13 *
14 * When distributing Covered Code, include this CDDL HEADER in each
15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 *
20 * CDDL HEADER END
21 */
22 /*
23 * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
24 * Copyright 2019 Joyent, Inc.
25 * Copyright 2024 Oxide Computer Company
26 */
27
28 /*
29 * Copyright (c) 2010, Intel Corporation.
30 * All rights reserved.
31 */
32
33 /* Copyright (c) 1988 AT&T */
34 /* All Rights Reserved */
35
36 #include "dis_tables.h"
37
38 /* BEGIN CSTYLED */
39
40 /*
41 * Disassembly begins in dis_distable, which is equivalent to the One-byte
42 * Opcode Map in the Intel IA32 ISA Reference (page A-6 in my copy). The
43 * decoding loops then traverse out through the other tables as necessary to
44 * decode a given instruction.
45 *
46 * The behavior of this file can be controlled by one of the following flags:
47 *
48 * DIS_TEXT Include text for disassembly
49 * DIS_MEM Include memory-size calculations
50 *
51 * Either or both of these can be defined.
52 *
53 * This file is not, and will never be, cstyled. If anything, the tables should
54 * be taken out another tab stop or two so nothing overlaps.
55 */
56
57 /*
58 * These functions must be provided for the consumer to do disassembly.
59 */
60 #ifdef DIS_TEXT
61 extern char *strncpy(char *, const char *, size_t);
62 extern size_t strlen(const char *);
63 extern int strcmp(const char *, const char *);
64 extern int strncmp(const char *, const char *, size_t);
65 extern size_t strlcat(char *, const char *, size_t);
66 #endif
67
68
69 #define TERM 0 /* used to indicate that the 'indirect' */
70 /* field terminates - no pointer. */
71
72 /* Used to decode instructions. */
73 typedef struct instable {
74 struct instable *it_indirect; /* for decode op codes */
75 uchar_t it_adrmode;
76 #ifdef DIS_TEXT
77 char it_name[NCPS];
78 uint_t it_suffix:1; /* mnem + "w", "l", or "d" */
79 #endif
80 #ifdef DIS_MEM
81 uint_t it_size:16;
82 #endif
83 uint_t it_invalid64:1; /* opcode invalid in amd64 */
84 uint_t it_always64:1; /* 64 bit when in 64 bit mode */
85 uint_t it_invalid32:1; /* invalid in IA32 */
86 uint_t it_stackop:1; /* push/pop stack operation */
87 uint_t it_vexwoxmm:1; /* VEX instructions that don't use XMM/YMM */
88 uint_t it_avxsuf:3; /* AVX2/AVX512 suffix rqd. */
89 uint_t it_vexopmask:1; /* VEX inst. that use opmask */
90 } instable_t;
91
92 /*
93 * Instruction formats.
94 */
95 enum {
96 UNKNOWN,
97 MRw,
98 IMlw,
99 IMw,
100 IR,
101 OA,
102 AO,
103 MS,
104 SM,
105 Mv,
106 Mw,
107 M, /* register or memory */
108 MG9, /* register or memory in group 9 (prefix optional) */
109 Mb, /* register or memory, always byte sized */
110 MO, /* memory only (no registers) */
111 PREF,
112 SWAPGS_RDTSCP,
113 MONITOR_MWAIT,
114 R,
115 RA,
116 SEG,
117 MR,
118 RM,
119 RM_66r, /* RM, but with a required 0x66 prefix */
120 IA,
121 MA,
122 SD,
123 AD,
124 SA,
125 D,
126 INM,
127 SO,
128 BD,
129 I,
130 P,
131 V,
132 DSHIFT, /* for double shift that has an 8-bit immediate */
133 U,
134 OVERRIDE,
135 NORM, /* instructions w/o ModR/M byte, no memory access */
136 IMPLMEM, /* instructions w/o ModR/M byte, implicit mem access */
137 O, /* for call */
138 JTAB, /* jump table */
139 IMUL, /* for 186 iimul instr */
140 CBW, /* so data16 can be evaluated for cbw and variants */
141 MvI, /* for 186 logicals */
142 ENTER, /* for 186 enter instr */
143 RMw, /* for 286 arpl instr */
144 Ib, /* for push immediate byte */
145 F, /* for 287 instructions */
146 FF, /* for 287 instructions */
147 FFC, /* for 287 instructions */
148 DM, /* 16-bit data */
149 AM, /* 16-bit addr */
150 LSEG, /* for 3-bit seg reg encoding */
151 MIb, /* for 386 logicals */
152 SREG, /* for 386 special registers */
153 PREFIX, /* a REP instruction prefix */
154 LOCK, /* a LOCK instruction prefix */
155 INT3, /* The int 3 instruction, which has a fake operand */
156 INTx, /* The normal int instruction, with explicit int num */
157 DSHIFTcl, /* for double shift that implicitly uses %cl */
158 CWD, /* so data16 can be evaluated for cwd and variants */
159 RET, /* single immediate 16-bit operand */
160 MOVZ, /* for movs and movz, with different size operands */
161 CRC32, /* for crc32, with different size operands */
162 XADDB, /* for xaddb */
163 MOVSXZ, /* AMD64 mov sign extend 32 to 64 bit instruction */
164 MOVBE, /* movbe instruction */
165 MOVDIR, /* movdir64b register semantics m512 -> r16/32/64 */
166 RMATCH, /* register, but type matches CPU, not prefixes */
167
168 /*
169 * MMX/SIMD addressing modes.
170 */
171
172 MMO, /* Prefixable MMX/SIMD-Int mm/mem -> mm */
173 MMOIMPL, /* Prefixable MMX/SIMD-Int mm -> mm (mem) */
174 MMO3P, /* Prefixable MMX/SIMD-Int mm -> r32,imm8 */
175 MMOM3, /* Prefixable MMX/SIMD-Int mm -> r32 */
176 MMOS, /* Prefixable MMX/SIMD-Int mm -> mm/mem */
177 MMOMS, /* Prefixable MMX/SIMD-Int mm -> mem */
178 MMOPM, /* MMX/SIMD-Int mm/mem -> mm,imm8 */
179 MMOPM_66o, /* MMX/SIMD-Int 0x66 optional mm/mem -> mm,imm8 */
180 MMOPRM, /* Prefixable MMX/SIMD-Int r32/mem -> mm,imm8 */
181 MMOSH, /* Prefixable MMX mm,imm8 */
182 MM, /* MMX/SIMD-Int mm/mem -> mm */
183 MMS, /* MMX/SIMD-Int mm -> mm/mem */
184 MMSH, /* MMX mm,imm8 */
185 XMMO, /* Prefixable SIMD xmm/mem -> xmm */
186 XMMOS, /* Prefixable SIMD xmm -> xmm/mem */
187 XMMOPM, /* Prefixable SIMD xmm/mem w/to xmm,imm8 */
188 XMMOMX, /* Prefixable SIMD mm/mem -> xmm */
189 XMMOX3, /* Prefixable SIMD xmm -> r32 */
190 XMMOXMM, /* Prefixable SIMD xmm/mem -> mm */
191 XMMOM, /* Prefixable SIMD xmm -> mem */
192 XMMOMS, /* Prefixable SIMD mem -> xmm */
193 XMM, /* SIMD xmm/mem -> xmm */
194 XMM_66r, /* SIMD 0x66 prefix required xmm/mem -> xmm */
195 XMM_66o, /* SIMD 0x66 prefix optional xmm/mem -> xmm */
196 XMMXIMPL, /* SIMD xmm -> xmm (mem) */
197 XMM3P, /* SIMD xmm -> r32,imm8 */
198 XMM3PM_66r, /* SIMD 0x66 prefix required xmm -> r32/mem,imm8 */
199 XMMP, /* SIMD xmm/mem w/to xmm,imm8 */
200 XMMP_66o, /* SIMD 0x66 prefix optional xmm/mem w/to xmm,imm8 */
201 XMMP_66r, /* SIMD 0x66 prefix required xmm/mem w/to xmm,imm8 */
202 XMMPRM, /* SIMD r32/mem -> xmm,imm8 */
203 XMMPRM_66r, /* SIMD 0x66 prefix required r32/mem -> xmm,imm8 */
204 XMMS, /* SIMD xmm -> xmm/mem */
205 XMMM, /* SIMD mem -> xmm */
206 XMMM_66r, /* SIMD 0x66 prefix required mem -> xmm */
207 XMMMS, /* SIMD xmm -> mem */
208 XMM3MX, /* SIMD r32/mem -> xmm */
209 XMM3MXS, /* SIMD xmm -> r32/mem */
210 XMMSH, /* SIMD xmm,imm8 */
211 XMMXM3, /* SIMD xmm/mem -> r32 */
212 XMMX3, /* SIMD xmm -> r32 */
213 XMMXMM, /* SIMD xmm/mem -> mm */
214 XMMMX, /* SIMD mm -> xmm */
215 XMMXM, /* SIMD xmm -> mm */
216 XMMX2I, /* SIMD xmm -> xmm, imm, imm */
217 XMM2I, /* SIMD xmm, imm, imm */
218 XMMFENCE, /* SIMD lfence or mfence */
219 XMMSFNC, /* SIMD sfence (none or mem) */
220 FSGS, /* FSGSBASE if reg */
221 XGETBV_XSETBV,
222 VEX_NONE, /* VEX no operand */
223 VEX_MO, /* VEX mod_rm -> implicit reg */
224 VEX_RMrX, /* VEX VEX.vvvv, mod_rm -> mod_reg */
225 VEX_VRMrX, /* VEX mod_rm, VEX.vvvv -> mod_rm */
226 VEX_RRX, /* VEX VEX.vvvv, mod_reg -> mod_rm */
227 VEX_RMRX, /* VEX VEX.vvvv, mod_rm, imm8[7:4] -> mod_reg */
228 VEX_MX, /* VEX mod_rm -> mod_reg */
229 VEX_MXI, /* VEX mod_rm, imm8 -> mod_reg */
230 VEX_XXI, /* VEX mod_rm, imm8 -> VEX.vvvv */
231 VEX_MR, /* VEX mod_rm -> mod_reg */
232 VEX_RRI, /* VEX mod_reg, mod_rm -> implicit(eflags/r32) */
233 VEX_RX, /* VEX mod_reg -> mod_rm */
234 VEX_KRR, /* VEX mod_rm -> mod_reg */
235 VEX_KMR, /* VEX mod_reg -> mod_rm */
236 VEX_KRM, /* VEX mod_rm -> mod_reg */
237 VEX_RR, /* VEX mod_rm -> mod_reg */
238 VEX_RRi, /* VEX mod_rm, imm8 -> mod_reg */
239 VEX_RM, /* VEX mod_reg -> mod_rm */
240 VEX_RIM, /* VEX mod_reg, imm8 -> mod_rm */
241 VEX_RRM, /* VEX VEX.vvvv, mod_reg -> mod_rm */
242 VEX_RMX, /* VEX VEX.vvvv, mod_rm -> mod_reg */
243 VEX_SbVM, /* VEX SIB, VEX.vvvv -> mod_rm */
244 VMx, /* vmcall/vmlaunch/vmresume/vmxoff */
245 VMxo, /* VMx instruction with optional prefix */
246 SVM, /* AMD SVM instructions */
247 BLS, /* BLSR, BLSMSK, BLSI */
248 FMA, /* FMA instructions, all VEX_RMrX */
249 ADX, /* ADX instructions, support REX.w, mod_rm->mod_reg */
250 EVEX_RX, /* EVEX mod_reg -> mod_rm */
251 EVEX_RXT1S8B, /* EVEX Tuple1 8/16-bit Scalar mod_reg -> mod_rm */
252 EVEX_MX, /* EVEX mod_rm -> mod_reg */
253 EVEX_MXT1S8B, /* EVEX mod_rm Tuple 1 8/156-bit Scalar -> mod_reg */
254 EVEX_MBX, /* EVEX mod_rm/bcast -> mod_reg */
255 EVEX_RMrX, /* EVEX EVEX.vvvv, mod_rm -> mod_reg */
256 EVEX_RMBrX, /* EVEX EVEX.vvvv, mod_rm/bcast -> mod_reg */
257 EVEX_RMRX, /* EVEX EVEX.vvvv, mod_rm, imm8 -> mod_reg */
258 EVEX_RMBRX, /* EVEX EVEX.vvvv, mod_rm/bcast, imm8 -> mod_reg */
259 EVEX_RMrK, /* EVEX EVEX.vvvv, mod_rm -> opmask */
260 EVEX_KR /* EVEX opmask (mod_rm) -> mod_reg */
261 };
262
263 /*
264 * VEX prefixes
265 */
266 #define VEX_2bytes 0xC5 /* the first byte of two-byte form */
267 #define VEX_3bytes 0xC4 /* the first byte of three-byte form */
268
269 #define FILL 0x90 /* Fill byte used for alignment (nop) */
270
271 /*
272 ** Register numbers for the i386
273 */
274 #define EAX_REGNO 0
275 #define ECX_REGNO 1
276 #define EDX_REGNO 2
277 #define EBX_REGNO 3
278 #define ESP_REGNO 4
279 #define EBP_REGNO 5
280 #define ESI_REGNO 6
281 #define EDI_REGNO 7
282
283 /*
284 * modes for immediate values
285 */
286 #define MODE_NONE 0
287 #define MODE_IPREL 1 /* signed IP relative value */
288 #define MODE_SIGNED 2 /* sign extended immediate */
289 #define MODE_IMPLIED 3 /* constant value implied from opcode */
290 #define MODE_OFFSET 4 /* offset part of an address */
291 #define MODE_RIPREL 5 /* like IPREL, but from %rip (amd64) */
292
293 /*
294 * The letters used in these macros are:
295 * IND - indirect to another to another table
296 * "T" - means to Terminate indirections (this is the final opcode)
297 * "S" - means "operand length suffix required"
298 * "Sa" - means AVX2 suffix (q/d) required
299 * "Sq" - means AVX512 suffix (q/d) required
300 * "Sd" - means AVX512 suffix (d/s) required
301 * "Sb" - means AVX512 suffix (b/w) required
302 * "NS" - means "no suffix" which is the operand length suffix of the opcode
303 * "Z" - means instruction size arg required
304 * "u" - means the opcode is invalid in IA32 but valid in amd64
305 * "x" - means the opcode is invalid in amd64, but not IA32
306 * "y" - means the operand size is always 64 bits in 64 bit mode
307 * "p" - means push/pop stack operation
308 * "vr" - means VEX instruction that operates on normal registers, not fpu
309 * "vo" - means VEX instruction that operates on opmask registers, not fpu
310 */
311
312 #define AVS2 (uint_t)1 /* it_avxsuf: AVX2 q/d suffix handling */
313 #define AVS5Q (uint_t)2 /* it_avxsuf: AVX512 q/d suffix handling */
314 #define AVS5D (uint_t)3 /* it_avxsuf: AVX512 d/s suffix handling */
315 #define AVS5B (uint_t)4 /* it_avxsuf: AVX512 b/w suffix handling */
316
317 #if defined(DIS_TEXT) && defined(DIS_MEM)
318 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0, 0}
319 #define INDx(table) {(instable_t *)table, 0, "", 0, 0, 1, 0, 0, 0}
320 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0}
321 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 0, 1, 0}
322 #define TNSx(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0, 0}
323 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 0}
324 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 1}
325 #define TNSSb(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5B }
326 #define TNSSd(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5D }
327 #define TNSSq(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5Q }
328 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0}
329 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, sz, 0, 1, 0, 0}
330 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0, 1}
331 #define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 0, 1}
332 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0}
333 #define TSx(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0, 0}
334 #define TSy(name, amode) {TERM, amode, name, 1, 0, 0, 1, 0, 0}
335 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 1}
336 #define TSZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0}
337 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0, 0, AVS2}
338 #define TSq(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5Q}
339 #define TSd(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5D}
340 #define TSZx(name, amode, sz) {TERM, amode, name, 1, sz, 1, 0, 0, 0}
341 #define TSZy(name, amode, sz) {TERM, amode, name, 1, sz, 0, 1, 0, 0}
342 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0}
343 #elif defined(DIS_TEXT)
344 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0}
345 #define INDx(table) {(instable_t *)table, 0, "", 0, 1, 0, 0, 0}
346 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0}
347 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0}
348 #define TNSx(name, amode) {TERM, amode, name, 0, 1, 0, 0, 0}
349 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0}
350 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 1, 0, 1}
351 #define TNSSb(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, AVS5B }
352 #define TNSSd(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, AVS5D }
353 #define TNSSq(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, AVS5Q }
354 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0}
355 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, 0, 1, 0, 0}
356 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0, 1}
357 #define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 1}
358 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0}
359 #define TSx(name, amode) {TERM, amode, name, 1, 1, 0, 0, 0}
360 #define TSy(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0}
361 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 1}
362 #define TSZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0}
363 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0, 0, AVS2}
364 #define TSq(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, AVS5Q}
365 #define TSZx(name, amode, sz) {TERM, amode, name, 1, 1, 0, 0, 0}
366 #define TSZy(name, amode, sz) {TERM, amode, name, 1, 0, 1, 0, 0}
367 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0}
368 #elif defined(DIS_MEM)
369 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0, 0}
370 #define INDx(table) {(instable_t *)table, 0, 0, 1, 0, 0, 0}
371 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0, 0}
372 #define TNSu(name, amode) {TERM, amode, 0, 0, 0, 1, 0}
373 #define TNSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0}
374 #define TNSyp(name, amode) {TERM, amode, 0, 0, 1, 0, 1}
375 #define TNSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0}
376 #define TNSSb(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, AVS5B }
377 #define TNSSd(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, AVS5D }
378 #define TNSSq(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, AVS5Q }
379 #define TNSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0}
380 #define TNSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0}
381 #define TNSZvr(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 1}
382 #define TSvo(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 0, 1}
383 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0, 0}
384 #define TSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0}
385 #define TSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0}
386 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 0, 1}
387 #define TSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0}
388 #define TSaZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 0, AVS2}
389 #define TSq(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, AVS5Q}
390 #define TSZx(name, amode, sz) {TERM, amode, sz, 1, 0, 0, 0}
391 #define TSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0}
392 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0, 0}
393 #else
394 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0}
395 #define INDx(table) {(instable_t *)table, 0, 1, 0, 0, 0}
396 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0}
397 #define TNSu(name, amode) {TERM, amode, 0, 0, 1, 0}
398 #define TNSy(name, amode) {TERM, amode, 0, 1, 0, 0}
399 #define TNSyp(name, amode) {TERM, amode, 0, 1, 0, 1}
400 #define TNSx(name, amode) {TERM, amode, 1, 0, 0, 0}
401 #define TNSSb(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5B }
402 #define TNSSd(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5D }
403 #define TNSSq(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5Q }
404 #define TNSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0}
405 #define TNSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0}
406 #define TNSZvr(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 1}
407 #define TSvo(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 1}
408 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0}
409 #define TSx(name, amode) {TERM, amode, 1, 0, 0, 0}
410 #define TSy(name, amode) {TERM, amode, 0, 1, 0, 0}
411 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 1}
412 #define TSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0}
413 #define TSaZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 0, AVS2}
414 #define TSq(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5Q}
415 #define TSd(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5D}
416 #define TSZx(name, amode, sz) {TERM, amode, 1, 0, 0, 0}
417 #define TSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0}
418 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0}
419 #endif
420
421 #ifdef DIS_TEXT
422 /*
423 * this decodes the r_m field for mode's 0, 1, 2 in 16 bit mode
424 */
425 const char *const dis_addr16[3][8] = {
426 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "",
427 "(%bx)",
428 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di", "(%bp)",
429 "(%bx)",
430 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "(%bp)",
431 "(%bx)",
432 };
433
434
435 /*
436 * This decodes 32 bit addressing mode r_m field for modes 0, 1, 2
437 */
438 const char *const dis_addr32_mode0[16] = {
439 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "", "(%esi)", "(%edi)",
440 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "", "(%r14d)", "(%r15d)"
441 };
442
443 const char *const dis_addr32_mode12[16] = {
444 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "(%ebp)", "(%esi)", "(%edi)",
445 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "(%r13d)", "(%r14d)", "(%r15d)"
446 };
447
448 /*
449 * This decodes 64 bit addressing mode r_m field for modes 0, 1, 2
450 */
451 const char *const dis_addr64_mode0[16] = {
452 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rip)", "(%rsi)", "(%rdi)",
453 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%rip)", "(%r14)", "(%r15)"
454 };
455 const char *const dis_addr64_mode12[16] = {
456 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rbp)", "(%rsi)", "(%rdi)",
457 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%r13)", "(%r14)", "(%r15)"
458 };
459
460 /*
461 * decode for scale from SIB byte
462 */
463 const char *const dis_scale_factor[4] = { ")", ",2)", ",4)", ",8)" };
464
465 /*
466 * decode for scale from VSIB byte, note that we always include the scale factor
467 * to match gas.
468 */
469 const char *const dis_vscale_factor[4] = { ",1)", ",2)", ",4)", ",8)" };
470
471 /*
472 * register decoding for normal references to registers (ie. not addressing)
473 */
474 const char *const dis_REG8[16] = {
475 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
476 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
477 };
478
479 const char *const dis_REG8_REX[16] = {
480 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
481 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
482 };
483
484 const char *const dis_REG16[16] = {
485 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
486 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
487 };
488
489 const char *const dis_REG32[16] = {
490 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
491 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
492 };
493
494 const char *const dis_REG64[16] = {
495 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
496 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
497 };
498
499 const char *const dis_DEBUGREG[16] = {
500 "%db0", "%db1", "%db2", "%db3", "%db4", "%db5", "%db6", "%db7",
501 "%db8", "%db9", "%db10", "%db11", "%db12", "%db13", "%db14", "%db15"
502 };
503
504 const char *const dis_CONTROLREG[16] = {
505 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5?", "%cr6?", "%cr7?",
506 "%cr8", "%cr9?", "%cr10?", "%cr11?", "%cr12?", "%cr13?", "%cr14?", "%cr15?"
507 };
508
509 const char *const dis_TESTREG[16] = {
510 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7",
511 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7"
512 };
513
514 const char *const dis_MMREG[16] = {
515 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7",
516 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7"
517 };
518
519 const char *const dis_XMMREG[32] = {
520 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
521 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
522 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
523 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
524 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
525 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
526 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
527 "%xmm28", "%xmm29", "%xmm30", "%xmm31",
528 };
529
530 const char *const dis_YMMREG[32] = {
531 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
532 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
533 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
534 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
535 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
536 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
537 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
538 "%ymm28", "%ymm29", "%ymm30", "%ymm31",
539 };
540
541 const char *const dis_ZMMREG[32] = {
542 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
543 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
544 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
545 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
546 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
547 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
548 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
549 "%zmm28", "%zmm29", "%zmm30", "%zmm31",
550 };
551
552 const char *const dis_KOPMASKREG[8] = {
553 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
554 };
555
556 const char *const dis_SEGREG[16] = {
557 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>",
558 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>"
559 };
560
561 /*
562 * SIMD predicate suffixes
563 */
564 const char *const dis_PREDSUFFIX[8] = {
565 "eq", "lt", "le", "unord", "neq", "nlt", "nle", "ord"
566 };
567
568 const char *const dis_AVXvgrp7[3][8] = {
569 /*0 1 2 3 4 5 6 7*/
570 /*71*/ {"", "", "vpsrlw", "", "vpsraw", "", "vpsllw", ""},
571 /*72*/ {"", "", "vpsrld", "", "vpsrad", "", "vpslld", ""},
572 /*73*/ {"", "", "vpsrlq", "vpsrldq", "", "", "vpsllq", "vpslldq"}
573 };
574
575 #endif /* DIS_TEXT */
576
577 /*
578 * "decode table" for 64 bit mode MOVSXD instruction (opcode 0x63)
579 */
580 const instable_t dis_opMOVSLD = TNS("movslq",MOVSXZ);
581
582 /*
583 * "decode table" for pause and clflush instructions
584 */
585 const instable_t dis_opPause = TNS("pause", NORM);
586
587 /*
588 * "decode table" for wbnoinvd instruction
589 */
590 const instable_t dis_opWbnoinvd = TNS("wbnoinvd", NORM);
591
592 /*
593 * Decode table for 0x0F00 opcodes
594 */
595 const instable_t dis_op0F00[8] = {
596
597 /* [0] */ TNS("sldt",M), TNS("str",M), TNSy("lldt",M), TNSy("ltr",M),
598 /* [4] */ TNSZ("verr",M,2), TNSZ("verw",M,2), INVALID, INVALID,
599 };
600
601
602 /*
603 * Decode table for 0x0F01 opcodes
604 */
605 const instable_t dis_op0F01[8] = {
606
607 /* [0] */ TNSZ("sgdt",VMx,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",SVM,6),
608 /* [4] */ TNSZ("smsw",M,2), INVALID, TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS_RDTSCP),
609 };
610
611 /*
612 * Decode table for 0x0F18 opcodes -- SIMD prefetch
613 */
614 const instable_t dis_op0F18[8] = {
615
616 /* [0] */ TNS("prefetchnta",PREF),TNS("prefetcht0",PREF), TNS("prefetcht1",PREF), TNS("prefetcht2",PREF),
617 /* [4] */ INVALID, INVALID, TNSu("prefetchit1",PREF),TNSu("prefetchit0",PREF),
618 };
619
620 /*
621 * Decode table for 0x0FAE opcodes -- SIMD state save/restore
622 */
623 const instable_t dis_op0FAE[8] = {
624 /* [0] */ TNSZ("fxsave",FSGS,512),TNSZ("fxrstor",FSGS,512),TNS("ldmxcsr",FSGS), TNS("stmxcsr",FSGS),
625 /* [4] */ TNSZ("xsave",M,512), TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE), TNS("sfence",XMMSFNC),
626 };
627
628 /*
629 * Decode table for 0xF30FAE opcodes -- FSGSBASE
630 */
631 const instable_t dis_opF30FAE[8] = {
632 /* [0] */ TNSx("rdfsbase",FSGS), TNSx("rdgsbase",FSGS), TNSx("wrfsbase",FSGS), TNSx("wrgsbase",FSGS),
633 /* [4] */ INVALID, INVALID, INVALID, INVALID,
634 };
635
636 /*
637 * Decode table for 0x0FBA opcodes
638 */
639
640 const instable_t dis_op0FBA[8] = {
641
642 /* [0] */ INVALID, INVALID, INVALID, INVALID,
643 /* [4] */ TS("bt",MIb), TS("bts",MIb), TS("btr",MIb), TS("btc",MIb),
644 };
645
646 /*
647 * Decode table for 0x0FC7 opcode (group 9)
648 */
649
650 const instable_t dis_op0FC7[8] = {
651
652 /* [0] */ INVALID, TNS("cmpxchg8b",M), INVALID, TNS("xrstors",MG9),
653 /* [4] */ TNS("xsavec",MG9), TNS("xsaves",MG9), TNS("vmptrld",MG9), TNS("vmptrst",MG9),
654 };
655
656 /*
657 * Decode table for 0x0FC7 opcode (group 9) mode 3
658 */
659
660 const instable_t dis_op0FC7m3[8] = {
661
662 /* [0] */ INVALID, INVALID, INVALID, INVALID,
663 /* [4] */ INVALID, INVALID, TNS("rdrand",MG9), TNS("rdseed", MG9),
664 };
665
666 /*
667 * Decode table for 0x0FC7 opcode with 0x66 prefix
668 */
669
670 const instable_t dis_op660FC7[8] = {
671
672 /* [0] */ INVALID, INVALID, INVALID, INVALID,
673 /* [4] */ INVALID, INVALID, TNS("vmclear",M), INVALID,
674 };
675
676 /*
677 * Decode table for 0x0FC7 opcode with 0xF3 prefix -- memory instructions
678 */
679
680 const instable_t dis_opF30FC7[8] = {
681
682 /* [0] */ INVALID, INVALID, INVALID, INVALID,
683 /* [4] */ INVALID, INVALID, TNS("vmxon",M), INVALID,
684 };
685
686 /*
687 * Decode table for 0x0FC7 opcode with 0xF3 prefix -- register instructions
688 */
689
690 const instable_t dis_opF30FC7m3[8] = {
691
692 /* [0] */ INVALID, INVALID, INVALID, INVALID,
693 /* [4] */ INVALID, INVALID, INVALID, TNS("rdpid",RMATCH)
694 };
695
696 /*
697 * Decode table for 0x0FC8 opcode -- 486 bswap instruction
698 *
699 *bit pattern: 0000 1111 1100 1reg
700 */
701 const instable_t dis_op0FC8[4] = {
702 /* [0] */ TNS("bswap",R), INVALID, INVALID, INVALID,
703 };
704
705 /*
706 * Decode table for 0x0F71, 0x0F72, and 0x0F73 opcodes -- MMX instructions
707 */
708 const instable_t dis_op0F7123[4][8] = {
709 {
710 /* [70].0 */ INVALID, INVALID, INVALID, INVALID,
711 /* .4 */ INVALID, INVALID, INVALID, INVALID,
712 }, {
713 /* [71].0 */ INVALID, INVALID, TNS("psrlw",MMOSH), INVALID,
714 /* .4 */ TNS("psraw",MMOSH), INVALID, TNS("psllw",MMOSH), INVALID,
715 }, {
716 /* [72].0 */ INVALID, INVALID, TNS("psrld",MMOSH), INVALID,
717 /* .4 */ TNS("psrad",MMOSH), INVALID, TNS("pslld",MMOSH), INVALID,
718 }, {
719 /* [73].0 */ INVALID, INVALID, TNS("psrlq",MMOSH), TNS("INVALID",MMOSH),
720 /* .4 */ INVALID, INVALID, TNS("psllq",MMOSH), TNS("INVALID",MMOSH),
721 } };
722
723 /*
724 * Decode table for SIMD extensions to above 0x0F71-0x0F73 opcodes.
725 */
726 const instable_t dis_opSIMD7123[32] = {
727 /* [70].0 */ INVALID, INVALID, INVALID, INVALID,
728 /* .4 */ INVALID, INVALID, INVALID, INVALID,
729
730 /* [71].0 */ INVALID, INVALID, TNS("psrlw",XMMSH), INVALID,
731 /* .4 */ TNS("psraw",XMMSH), INVALID, TNS("psllw",XMMSH), INVALID,
732
733 /* [72].0 */ INVALID, INVALID, TNS("psrld",XMMSH), INVALID,
734 /* .4 */ TNS("psrad",XMMSH), INVALID, TNS("pslld",XMMSH), INVALID,
735
736 /* [73].0 */ INVALID, INVALID, TNS("psrlq",XMMSH), TNS("psrldq",XMMSH),
737 /* .4 */ INVALID, INVALID, TNS("psllq",XMMSH), TNS("pslldq",XMMSH),
738 };
739
740 /*
741 * SIMD instructions have been wedged into the existing IA32 instruction
742 * set through the use of prefixes. That is, while 0xf0 0x58 may be
743 * addps, 0xf3 0xf0 0x58 (literally, repz addps) is a completely different
744 * instruction - addss. At present, three prefixes have been coopted in
745 * this manner - address size (0x66), repnz (0xf2) and repz (0xf3). The
746 * following tables are used to provide the prefixed instruction names.
747 * The arrays are sparse, but they're fast.
748 */
749
750 /*
751 * Decode table for SIMD instructions with the address size (0x66) prefix.
752 */
753 const instable_t dis_opSIMDdata16[256] = {
754 /* [00] */ INVALID, INVALID, INVALID, INVALID,
755 /* [04] */ INVALID, INVALID, INVALID, INVALID,
756 /* [08] */ INVALID, INVALID, INVALID, INVALID,
757 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
758
759 /* [10] */ TNSZ("movupd",XMM,16), TNSZ("movupd",XMMS,16), TNSZ("movlpd",XMMM,8), TNSZ("movlpd",XMMMS,8),
760 /* [14] */ TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8), TNSZ("movhpd",XMMMS,8),
761 /* [18] */ INVALID, INVALID, INVALID, INVALID,
762 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
763
764 /* [20] */ INVALID, INVALID, INVALID, INVALID,
765 /* [24] */ INVALID, INVALID, INVALID, INVALID,
766 /* [28] */ TNSZ("movapd",XMM,16), TNSZ("movapd",XMMS,16), TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd",XMMOMS,16),
767 /* [2C] */ TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8),
768
769 /* [30] */ INVALID, INVALID, INVALID, INVALID,
770 /* [34] */ INVALID, INVALID, INVALID, INVALID,
771 /* [38] */ INVALID, INVALID, INVALID, INVALID,
772 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
773
774 /* [40] */ INVALID, INVALID, INVALID, INVALID,
775 /* [44] */ INVALID, INVALID, INVALID, INVALID,
776 /* [48] */ INVALID, INVALID, INVALID, INVALID,
777 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
778
779 /* [50] */ TNS("movmskpd",XMMOX3), TNSZ("sqrtpd",XMM,16), INVALID, INVALID,
780 /* [54] */ TNSZ("andpd",XMM,16), TNSZ("andnpd",XMM,16), TNSZ("orpd",XMM,16), TNSZ("xorpd",XMM,16),
781 /* [58] */ TNSZ("addpd",XMM,16), TNSZ("mulpd",XMM,16), TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XMM,16),
782 /* [5C] */ TNSZ("subpd",XMM,16), TNSZ("minpd",XMM,16), TNSZ("divpd",XMM,16), TNSZ("maxpd",XMM,16),
783
784 /* [60] */ TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packsswb",XMM,16),
785 /* [64] */ TNSZ("pcmpgtb",XMM,16), TNSZ("pcmpgtw",XMM,16), TNSZ("pcmpgtd",XMM,16), TNSZ("packuswb",XMM,16),
786 /* [68] */ TNSZ("punpckhbw",XMM,16),TNSZ("punpckhwd",XMM,16),TNSZ("punpckhdq",XMM,16),TNSZ("packssdw",XMM,16),
787 /* [6C] */ TNSZ("punpcklqdq",XMM,16),TNSZ("punpckhqdq",XMM,16),TNSZ("movd",XMM3MX,4),TNSZ("movdqa",XMM,16),
788
789 /* [70] */ TNSZ("pshufd",XMMP,16), INVALID, INVALID, INVALID,
790 /* [74] */ TNSZ("pcmpeqb",XMM,16), TNSZ("pcmpeqw",XMM,16), TNSZ("pcmpeqd",XMM,16), INVALID,
791 /* [78] */ TNSZ("extrq",XMM2I,16), TNSZ("extrq",XMM,16), INVALID, INVALID,
792 /* [7C] */ TNSZ("haddpd",XMM,16), TNSZ("hsubpd",XMM,16), TNSZ("movd",XMM3MXS,4), TNSZ("movdqa",XMMS,16),
793
794 /* [80] */ INVALID, INVALID, INVALID, INVALID,
795 /* [84] */ INVALID, INVALID, INVALID, INVALID,
796 /* [88] */ INVALID, INVALID, INVALID, INVALID,
797 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
798
799 /* [90] */ INVALID, INVALID, INVALID, INVALID,
800 /* [94] */ INVALID, INVALID, INVALID, INVALID,
801 /* [98] */ INVALID, INVALID, INVALID, INVALID,
802 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
803
804 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
805 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
806 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
807 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
808
809 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
810 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
811 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
812 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
813
814 /* [C0] */ INVALID, INVALID, TNSZ("cmppd",XMMP,16), INVALID,
815 /* [C4] */ TNSZ("pinsrw",XMMPRM,2),TNS("pextrw",XMM3P), TNSZ("shufpd",XMMP,16), INVALID,
816 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
817 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
818
819 /* [D0] */ TNSZ("addsubpd",XMM,16),TNSZ("psrlw",XMM,16), TNSZ("psrld",XMM,16), TNSZ("psrlq",XMM,16),
820 /* [D4] */ TNSZ("paddq",XMM,16), TNSZ("pmullw",XMM,16), TNSZ("movq",XMMS,8), TNS("pmovmskb",XMMX3),
821 /* [D8] */ TNSZ("psubusb",XMM,16), TNSZ("psubusw",XMM,16), TNSZ("pminub",XMM,16), TNSZ("pand",XMM,16),
822 /* [DC] */ TNSZ("paddusb",XMM,16), TNSZ("paddusw",XMM,16), TNSZ("pmaxub",XMM,16), TNSZ("pandn",XMM,16),
823
824 /* [E0] */ TNSZ("pavgb",XMM,16), TNSZ("psraw",XMM,16), TNSZ("psrad",XMM,16), TNSZ("pavgw",XMM,16),
825 /* [E4] */ TNSZ("pmulhuw",XMM,16), TNSZ("pmulhw",XMM,16), TNSZ("cvttpd2dq",XMM,16),TNSZ("movntdq",XMMS,16),
826 /* [E8] */ TNSZ("psubsb",XMM,16), TNSZ("psubsw",XMM,16), TNSZ("pminsw",XMM,16), TNSZ("por",XMM,16),
827 /* [EC] */ TNSZ("paddsb",XMM,16), TNSZ("paddsw",XMM,16), TNSZ("pmaxsw",XMM,16), TNSZ("pxor",XMM,16),
828
829 /* [F0] */ INVALID, TNSZ("psllw",XMM,16), TNSZ("pslld",XMM,16), TNSZ("psllq",XMM,16),
830 /* [F4] */ TNSZ("pmuludq",XMM,16), TNSZ("pmaddwd",XMM,16), TNSZ("psadbw",XMM,16), TNSZ("maskmovdqu", XMMXIMPL,16),
831 /* [F8] */ TNSZ("psubb",XMM,16), TNSZ("psubw",XMM,16), TNSZ("psubd",XMM,16), TNSZ("psubq",XMM,16),
832 /* [FC] */ TNSZ("paddb",XMM,16), TNSZ("paddw",XMM,16), TNSZ("paddd",XMM,16), INVALID,
833 };
834
835 const instable_t dis_opAVX660F[256] = {
836 /* [00] */ INVALID, INVALID, INVALID, INVALID,
837 /* [04] */ INVALID, INVALID, INVALID, INVALID,
838 /* [08] */ INVALID, INVALID, INVALID, INVALID,
839 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
840
841 /* [10] */ TNSZ("vmovupd",VEX_MX,16), TNSZ("vmovupd",VEX_RX,16), TNSZ("vmovlpd",VEX_RMrX,8), TNSZ("vmovlpd",VEX_RM,8),
842 /* [14] */ TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8), TNSZ("vmovhpd",VEX_RM,8),
843 /* [18] */ INVALID, INVALID, INVALID, INVALID,
844 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
845
846 /* [20] */ INVALID, INVALID, INVALID, INVALID,
847 /* [24] */ INVALID, INVALID, INVALID, INVALID,
848 /* [28] */ TNSZ("vmovapd",VEX_MX,16), TNSZ("vmovapd",VEX_RX,16), INVALID, TNSZ("vmovntpd",VEX_RM,16),
849 /* [2C] */ INVALID, INVALID, TNSZ("vucomisd",VEX_MX,8),TNSZ("vcomisd",VEX_MX,8),
850
851 /* [30] */ INVALID, INVALID, INVALID, INVALID,
852 /* [34] */ INVALID, INVALID, INVALID, INVALID,
853 /* [38] */ INVALID, INVALID, INVALID, INVALID,
854 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
855
856 /* [40] */ INVALID, TSvo("kand",VEX_RMX), TSvo("kandn",VEX_RMX), INVALID,
857 /* [44] */ TSvo("knot",VEX_MX), TSvo("kor",VEX_RMX), TSvo("kxnor",VEX_RMX), TSvo("kxor",VEX_RMX),
858 /* [48] */ INVALID, INVALID, TSvo("kadd",VEX_RMX), TSvo("kunpck",VEX_RMX),
859 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
860
861 /* [50] */ TNS("vmovmskpd",VEX_MR), TNSZ("vsqrtpd",VEX_MX,16), INVALID, INVALID,
862 /* [54] */ TNSZ("vandpd",VEX_RMrX,16), TNSZ("vandnpd",VEX_RMrX,16), TNSZ("vorpd",VEX_RMrX,16), TNSZ("vxorpd",VEX_RMrX,16),
863 /* [58] */ TNSZ("vaddpd",VEX_RMrX,16), TNSZ("vmulpd",VEX_RMrX,16), TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16),
864 /* [5C] */ TNSZ("vsubpd",VEX_RMrX,16), TNSZ("vminpd",VEX_RMrX,16), TNSZ("vdivpd",VEX_RMrX,16), TNSZ("vmaxpd",VEX_RMrX,16),
865
866 /* [60] */ TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16),
867 /* [64] */ TNSZ("vpcmpgtb",VEX_RMrX,16), TNSZ("vpcmpgtw",VEX_RMrX,16), TNSZ("vpcmpgtd",VEX_RMrX,16), TNSZ("vpackuswb",VEX_RMrX,16),
868 /* [68] */ TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16),
869 /* [6C] */ TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16),
870
871 /* [70] */ TNSZ("vpshufd",VEX_MXI,16), TNSZ("vgrp71",VEX_XXI,16), TNSZ("vgrp72",VEX_XXI,16), TNSZ("vgrp73",VEX_XXI,16),
872 /* [74] */ TNSZ("vpcmpeqb",VEX_RMrX,16), TNSZ("vpcmpeqw",VEX_RMrX,16), TNSZ("vpcmpeqd",VEX_RMrX,16), INVALID,
873 /* [78] */ INVALID, INVALID, INVALID, INVALID,
874 /* [7C] */ TNSZ("vhaddpd",VEX_RMrX,16), TNSZ("vhsubpd",VEX_RMrX,16), TNSZ("vmovd",VEX_RR,4), TNSZ("vmovdqa",VEX_RX,16),
875
876 /* [80] */ INVALID, INVALID, INVALID, INVALID,
877 /* [84] */ INVALID, INVALID, INVALID, INVALID,
878 /* [88] */ INVALID, INVALID, INVALID, INVALID,
879 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
880
881 /* [90] */ TSvo("kmov",VEX_KRM), TSvo("kmov",VEX_KMR), TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR),
882 /* [94] */ INVALID, INVALID, INVALID, INVALID,
883 /* [98] */ TSvo("kortest",VEX_MX), TSvo("ktest",VEX_MX), INVALID, INVALID,
884 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
885
886 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
887 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
888 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
889 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
890
891 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
892 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
893 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
894 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
895
896 /* [C0] */ INVALID, INVALID, TNSZ("vcmppd",VEX_RMRX,16), INVALID,
897 /* [C4] */ TNSZ("vpinsrw",VEX_RMRX,2),TNS("vpextrw",VEX_MR), TNSZ("vshufpd",VEX_RMRX,16), INVALID,
898 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
899 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
900
901 /* [D0] */ TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16), TNSZ("vpsrld",VEX_RMrX,16), TNSZ("vpsrlq",VEX_RMrX,16),
902 /* [D4] */ TNSZ("vpaddq",VEX_RMrX,16), TNSZ("vpmullw",VEX_RMrX,16), TNSZ("vmovq",VEX_RX,8), TNS("vpmovmskb",VEX_MR),
903 /* [D8] */ TNSZ("vpsubusb",VEX_RMrX,16), TNSZ("vpsubusw",VEX_RMrX,16), TNSZ("vpminub",VEX_RMrX,16), TNSZ("vpand",VEX_RMrX,16),
904 /* [DC] */ TNSZ("vpaddusb",VEX_RMrX,16), TNSZ("vpaddusw",VEX_RMrX,16), TNSZ("vpmaxub",VEX_RMrX,16), TNSZ("vpandn",VEX_RMrX,16),
905
906 /* [E0] */ TNSZ("vpavgb",VEX_RMrX,16), TNSZ("vpsraw",VEX_RMrX,16), TNSZ("vpsrad",VEX_RMrX,16), TNSZ("vpavgw",VEX_RMrX,16),
907 /* [E4] */ TNSZ("vpmulhuw",VEX_RMrX,16), TNSZ("vpmulhw",VEX_RMrX,16), TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16),
908 /* [E8] */ TNSZ("vpsubsb",VEX_RMrX,16), TNSZ("vpsubsw",VEX_RMrX,16), TNSZ("vpminsw",VEX_RMrX,16), TNSZ("vpor",VEX_RMrX,16),
909 /* [EC] */ TNSZ("vpaddsb",VEX_RMrX,16), TNSZ("vpaddsw",VEX_RMrX,16), TNSZ("vpmaxsw",VEX_RMrX,16), TNSZ("vpxor",VEX_RMrX,16),
910
911 /* [F0] */ INVALID, TNSZ("vpsllw",VEX_RMrX,16), TNSZ("vpslld",VEX_RMrX,16), TNSZ("vpsllq",VEX_RMrX,16),
912 /* [F4] */ TNSZ("vpmuludq",VEX_RMrX,16), TNSZ("vpmaddwd",VEX_RMrX,16), TNSZ("vpsadbw",VEX_RMrX,16), TNS("vmaskmovdqu",VEX_MX),
913 /* [F8] */ TNSZ("vpsubb",VEX_RMrX,16), TNSZ("vpsubw",VEX_RMrX,16), TNSZ("vpsubd",VEX_RMrX,16), TNSZ("vpsubq",VEX_RMrX,16),
914 /* [FC] */ TNSZ("vpaddb",VEX_RMrX,16), TNSZ("vpaddw",VEX_RMrX,16), TNSZ("vpaddd",VEX_RMrX,16), INVALID,
915 };
916
917 /*
918 * Decode table for SIMD instructions with the repnz (0xf2) prefix.
919 */
920 const instable_t dis_opSIMDrepnz[256] = {
921 /* [00] */ INVALID, INVALID, INVALID, INVALID,
922 /* [04] */ INVALID, INVALID, INVALID, INVALID,
923 /* [08] */ INVALID, INVALID, INVALID, INVALID,
924 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
925
926 /* [10] */ TNSZ("movsd",XMM,8), TNSZ("movsd",XMMS,8), TNSZ("movddup",XMM,8), INVALID,
927 /* [14] */ INVALID, INVALID, INVALID, INVALID,
928 /* [18] */ INVALID, INVALID, INVALID, INVALID,
929 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
930
931 /* [20] */ INVALID, INVALID, INVALID, INVALID,
932 /* [24] */ INVALID, INVALID, INVALID, INVALID,
933 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2sd",XMM3MX,4),TNSZ("movntsd",XMMMS,8),
934 /* [2C] */ TNSZ("cvttsd2si",XMMXM3,8),TNSZ("cvtsd2si",XMMXM3,8),INVALID, INVALID,
935
936 /* [30] */ INVALID, INVALID, INVALID, INVALID,
937 /* [34] */ INVALID, INVALID, INVALID, INVALID,
938 /* [38] */ INVALID, INVALID, INVALID, INVALID,
939 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
940
941 /* [40] */ INVALID, INVALID, INVALID, INVALID,
942 /* [44] */ INVALID, INVALID, INVALID, INVALID,
943 /* [48] */ INVALID, INVALID, INVALID, INVALID,
944 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
945
946 /* [50] */ INVALID, TNSZ("sqrtsd",XMM,8), INVALID, INVALID,
947 /* [54] */ INVALID, INVALID, INVALID, INVALID,
948 /* [58] */ TNSZ("addsd",XMM,8), TNSZ("mulsd",XMM,8), TNSZ("cvtsd2ss",XMM,8), INVALID,
949 /* [5C] */ TNSZ("subsd",XMM,8), TNSZ("minsd",XMM,8), TNSZ("divsd",XMM,8), TNSZ("maxsd",XMM,8),
950
951 /* [60] */ INVALID, INVALID, INVALID, INVALID,
952 /* [64] */ INVALID, INVALID, INVALID, INVALID,
953 /* [68] */ INVALID, INVALID, INVALID, INVALID,
954 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
955
956 /* [70] */ TNSZ("pshuflw",XMMP,16),INVALID, INVALID, INVALID,
957 /* [74] */ INVALID, INVALID, INVALID, INVALID,
958 /* [78] */ TNSZ("insertq",XMMX2I,16),TNSZ("insertq",XMM,8),INVALID, INVALID,
959 /* [7C] */ TNSZ("haddps",XMM,16), TNSZ("hsubps",XMM,16), INVALID, INVALID,
960
961 /* [80] */ INVALID, INVALID, INVALID, INVALID,
962 /* [84] */ INVALID, INVALID, INVALID, INVALID,
963 /* [88] */ INVALID, INVALID, INVALID, INVALID,
964 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
965
966 /* [90] */ INVALID, INVALID, INVALID, INVALID,
967 /* [94] */ INVALID, INVALID, INVALID, INVALID,
968 /* [98] */ INVALID, INVALID, INVALID, INVALID,
969 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
970
971 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
972 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
973 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
974 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
975
976 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
977 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
978 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
979 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
980
981 /* [C0] */ INVALID, INVALID, TNSZ("cmpsd",XMMP,8), INVALID,
982 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
983 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
984 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
985
986 /* [D0] */ TNSZ("addsubps",XMM,16),INVALID, INVALID, INVALID,
987 /* [D4] */ INVALID, INVALID, TNS("movdq2q",XMMXM), INVALID,
988 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
989 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
990
991 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
992 /* [E4] */ INVALID, INVALID, TNSZ("cvtpd2dq",XMM,16),INVALID,
993 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
994 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
995
996 /* [F0] */ TNS("lddqu",XMMM), INVALID, INVALID, INVALID,
997 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
998 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
999 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1000 };
1001
1002 const instable_t dis_opAVXF20F[256] = {
1003 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1004 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1005 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1006 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1007
1008 /* [10] */ TNSZ("vmovsd",VEX_RMrX,8), TNSZ("vmovsd",VEX_RRX,8), TNSZ("vmovddup",VEX_MX,8), INVALID,
1009 /* [14] */ INVALID, INVALID, INVALID, INVALID,
1010 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1011 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1012
1013 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1014 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1015 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2sd",VEX_RMrX,4),INVALID,
1016 /* [2C] */ TNSZ("vcvttsd2si",VEX_MR,8),TNSZ("vcvtsd2si",VEX_MR,8),INVALID, INVALID,
1017
1018 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1019 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1020 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1021 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1022
1023 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1024 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1025 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1026 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1027
1028 /* [50] */ INVALID, TNSZ("vsqrtsd",VEX_RMrX,8), INVALID, INVALID,
1029 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1030 /* [58] */ TNSZ("vaddsd",VEX_RMrX,8), TNSZ("vmulsd",VEX_RMrX,8), TNSZ("vcvtsd2ss",VEX_RMrX,8), INVALID,
1031 /* [5C] */ TNSZ("vsubsd",VEX_RMrX,8), TNSZ("vminsd",VEX_RMrX,8), TNSZ("vdivsd",VEX_RMrX,8), TNSZ("vmaxsd",VEX_RMrX,8),
1032
1033 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1034 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1035 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1036 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1037
1038 /* [70] */ TNSZ("vpshuflw",VEX_MXI,16),INVALID, INVALID, INVALID,
1039 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1040 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1041 /* [7C] */ TNSZ("vhaddps",VEX_RMrX,8), TNSZ("vhsubps",VEX_RMrX,8), INVALID, INVALID,
1042
1043 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1044 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1045 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1046 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1047
1048 /* [90] */ INVALID, INVALID, TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR),
1049 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1050 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1051 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1052
1053 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1054 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1055 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1056 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1057
1058 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1059 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1060 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1061 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1062
1063 /* [C0] */ INVALID, INVALID, TNSZ("vcmpsd",VEX_RMRX,8), INVALID,
1064 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1065 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1066 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1067
1068 /* [D0] */ TNSZ("vaddsubps",VEX_RMrX,8), INVALID, INVALID, INVALID,
1069 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1070 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1071 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1072
1073 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1074 /* [E4] */ INVALID, INVALID, TNSZ("vcvtpd2dq",VEX_MX,16),INVALID,
1075 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1076 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1077
1078 /* [F0] */ TNSZ("vlddqu",VEX_MX,16), INVALID, INVALID, INVALID,
1079 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1080 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1081 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1082 };
1083
1084 const instable_t dis_opAVXF20F3A[256] = {
1085 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1086 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1087 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1088 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1089
1090 /* [10] */ INVALID, INVALID, INVALID, INVALID,
1091 /* [14] */ INVALID, INVALID, INVALID, INVALID,
1092 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1093 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1094
1095 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1096 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1097 /* [28] */ INVALID, INVALID, INVALID, INVALID,
1098 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
1099
1100 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1101 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1102 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1103 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1104
1105 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1106 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1107 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1108 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1109
1110 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1111 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1112 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1113 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1114
1115 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1116 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1117 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1118 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1119
1120 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1121 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1122 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1123 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1124
1125 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1126 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1127 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1128 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1129
1130 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1131 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1132 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1133 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1134
1135 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1136 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1137 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1138 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1139
1140 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1141 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1142 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1143 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1144
1145 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1146 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1147 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1148 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1149
1150 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1151 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1152 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1153 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1154
1155 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1156 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1157 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1158 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1159
1160 /* [F0] */ TNSZvr("rorx",VEX_MXI,6),INVALID, INVALID, INVALID,
1161 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1162 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1163 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1164 };
1165
1166 const instable_t dis_opAVXF20F38[256] = {
1167 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1168 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1169 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1170 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1171
1172 /* [10] */ INVALID, INVALID, INVALID, INVALID,
1173 /* [14] */ INVALID, INVALID, INVALID, INVALID,
1174 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1175 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1176
1177 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1178 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1179 /* [28] */ INVALID, INVALID, INVALID, INVALID,
1180 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
1181
1182 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1183 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1184 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1185 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1186
1187 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1188 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1189 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1190 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1191
1192 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1193 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1194 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1195 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1196
1197 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1198 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1199 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1200 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1201
1202 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1203 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1204 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1205 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1206
1207 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1208 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1209 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1210 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1211
1212 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1213 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1214 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1215 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1216
1217 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1218 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1219 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1220 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1221
1222 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1223 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1224 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1225 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1226
1227 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1228 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1229 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1230 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1231
1232 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1233 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1234 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1235 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1236
1237 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1238 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1239 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1240 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1241
1242 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1243 /* [F4] */ INVALID, TNSZvr("pdep",VEX_RMrX,5),TNSZvr("mulx",VEX_RMrX,5),TNSZvr("shrx",VEX_VRMrX,5),
1244 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1245 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1246 };
1247
1248 const instable_t dis_opAVXF30F38[256] = {
1249 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1250 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1251 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1252 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1253
1254 /* [10] */ INVALID, INVALID, INVALID, INVALID,
1255 /* [14] */ INVALID, INVALID, INVALID, INVALID,
1256 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1257 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1258
1259 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1260 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1261 /* [28] */ INVALID, INVALID, INVALID, INVALID,
1262 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
1263
1264 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1265 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1266 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1267 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1268
1269 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1270 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1271 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1272 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1273
1274 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1275 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1276 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1277 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1278
1279 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1280 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1281 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1282 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1283
1284 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1285 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1286 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1287 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1288
1289 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1290 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1291 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1292 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1293
1294 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1295 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1296 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1297 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1298
1299 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1300 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1301 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1302 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1303
1304 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1305 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1306 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1307 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1308
1309 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1310 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1311 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1312 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1313
1314 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1315 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1316 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1317 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1318
1319 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1320 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1321 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1322 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1323
1324 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1325 /* [F4] */ INVALID, TNSZvr("pext",VEX_RMrX,5),INVALID, TNSZvr("sarx",VEX_VRMrX,5),
1326 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1327 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1328 };
1329 /*
1330 * Decode table for SIMD instructions with the repz (0xf3) prefix.
1331 */
1332 const instable_t dis_opSIMDrepz[256] = {
1333 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1334 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1335 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1336 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1337
1338 /* [10] */ TNSZ("movss",XMM,4), TNSZ("movss",XMMS,4), TNSZ("movsldup",XMM,16),INVALID,
1339 /* [14] */ INVALID, INVALID, TNSZ("movshdup",XMM,16),INVALID,
1340 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1341 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1342
1343 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1344 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1345 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2ss",XMM3MX,4),TNSZ("movntss",XMMMS,4),
1346 /* [2C] */ TNSZ("cvttss2si",XMMXM3,4),TNSZ("cvtss2si",XMMXM3,4),INVALID, INVALID,
1347
1348 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1349 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1350 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1351 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1352
1353 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1354 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1355 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1356 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1357
1358 /* [50] */ INVALID, TNSZ("sqrtss",XMM,4), TNSZ("rsqrtss",XMM,4), TNSZ("rcpss",XMM,4),
1359 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1360 /* [58] */ TNSZ("addss",XMM,4), TNSZ("mulss",XMM,4), TNSZ("cvtss2sd",XMM,4), TNSZ("cvttps2dq",XMM,16),
1361 /* [5C] */ TNSZ("subss",XMM,4), TNSZ("minss",XMM,4), TNSZ("divss",XMM,4), TNSZ("maxss",XMM,4),
1362
1363 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1364 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1365 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1366 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("movdqu",XMM,16),
1367
1368 /* [70] */ TNSZ("pshufhw",XMMP,16),INVALID, INVALID, INVALID,
1369 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1370 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1371 /* [7C] */ INVALID, INVALID, TNSZ("movq",XMM,8), TNSZ("movdqu",XMMS,16),
1372
1373 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1374 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1375 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1376 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1377
1378 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1379 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1380 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1381 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1382
1383 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1384 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1385 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1386 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1387
1388 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1389 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1390 /* [B8] */ TS("popcnt",MRw), INVALID, INVALID, INVALID,
1391 /* [BC] */ TNSZ("tzcnt",MRw,5), TS("lzcnt",MRw), INVALID, INVALID,
1392
1393 /* [C0] */ INVALID, INVALID, TNSZ("cmpss",XMMP,4), INVALID,
1394 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1395 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1396 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1397
1398 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1399 /* [D4] */ INVALID, INVALID, TNS("movq2dq",XMMMX), INVALID,
1400 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1401 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1402
1403 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1404 /* [E4] */ INVALID, INVALID, TNSZ("cvtdq2pd",XMM,8), INVALID,
1405 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1406 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1407
1408 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1409 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1410 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1411 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1412 };
1413
1414 const instable_t dis_opAVXF30F[256] = {
1415 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1416 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1417 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1418 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1419
1420 /* [10] */ TNSZ("vmovss",VEX_RMrX,4), TNSZ("vmovss",VEX_RRX,4), TNSZ("vmovsldup",VEX_MX,4), INVALID,
1421 /* [14] */ INVALID, INVALID, TNSZ("vmovshdup",VEX_MX,4), INVALID,
1422 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1423 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1424
1425 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1426 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1427 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2ss",VEX_RMrX,4),INVALID,
1428 /* [2C] */ TNSZ("vcvttss2si",VEX_MR,4),TNSZ("vcvtss2si",VEX_MR,4),INVALID, INVALID,
1429
1430 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1431 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1432 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1433 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1434
1435 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1436 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1437 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1438 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1439
1440 /* [50] */ INVALID, TNSZ("vsqrtss",VEX_RMrX,4), TNSZ("vrsqrtss",VEX_RMrX,4), TNSZ("vrcpss",VEX_RMrX,4),
1441 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1442 /* [58] */ TNSZ("vaddss",VEX_RMrX,4), TNSZ("vmulss",VEX_RMrX,4), TNSZ("vcvtss2sd",VEX_RMrX,4), TNSZ("vcvttps2dq",VEX_MX,16),
1443 /* [5C] */ TNSZ("vsubss",VEX_RMrX,4), TNSZ("vminss",VEX_RMrX,4), TNSZ("vdivss",VEX_RMrX,4), TNSZ("vmaxss",VEX_RMrX,4),
1444
1445 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1446 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1447 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1448 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("vmovdqu",VEX_MX,16),
1449
1450 /* [70] */ TNSZ("vpshufhw",VEX_MXI,16),INVALID, INVALID, INVALID,
1451 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1452 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1453 /* [7C] */ INVALID, INVALID, TNSZ("vmovq",VEX_MX,8), TNSZ("vmovdqu",VEX_RX,16),
1454
1455 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1456 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1457 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1458 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1459
1460 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1461 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1462 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1463 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1464
1465 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1466 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1467 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1468 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1469
1470 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1471 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1472 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1473 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1474
1475 /* [C0] */ INVALID, INVALID, TNSZ("vcmpss",VEX_RMRX,4), INVALID,
1476 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1477 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1478 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1479
1480 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1481 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1482 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1483 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1484
1485 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1486 /* [E4] */ INVALID, INVALID, TNSZ("vcvtdq2pd",VEX_MX,8), INVALID,
1487 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1488 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1489
1490 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1491 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1492 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1493 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1494 };
1495
1496 /*
1497 * Table for instructions with an EVEX prefix followed by 0F.
1498 */
1499 const instable_t dis_opEVEX0F[256] = {
1500 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1501 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1502 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1503 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1504
1505 /* [10] */ TNS("vmovups",EVEX_MX), TNS("vmovups",EVEX_RX), INVALID, INVALID,
1506 /* [14] */ INVALID, INVALID, INVALID, INVALID,
1507 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1508 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1509
1510 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1511 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1512 /* [28] */ TNS("vmovaps",EVEX_MX), TNS("vmovaps",EVEX_RX), INVALID, INVALID,
1513 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
1514
1515 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1516 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1517 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1518 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1519
1520 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1521 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1522 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1523 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1524
1525 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1526 /* [54] */ TNS("vandps",EVEX_RMrX),TNS("vandnps",EVEX_RMrX),TNS("vorps",EVEX_RMrX),TNS("vxorps",EVEX_RMrX),
1527 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1528 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1529
1530 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1531 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1532 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1533 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1534
1535 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1536 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1537 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1538 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1539
1540 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1541 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1542 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1543 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1544
1545 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1546 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1547 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1548 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1549
1550 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1551 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1552 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1553 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1554
1555 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1556 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1557 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1558 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1559
1560 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1561 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1562 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1563 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1564
1565 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1566 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1567 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1568 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1569
1570 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1571 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1572 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1573 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1574
1575 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1576 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1577 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1578 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1579 };
1580
1581 /*
1582 * Decode tables for EVEX 66 0F
1583 */
1584 const instable_t dis_opEVEX660F[256] = {
1585 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1586 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1587 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1588 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1589
1590 /* [10] */ TNS("vmovupd",EVEX_MX), TNS("vmovupd",EVEX_RX), INVALID, INVALID,
1591 /* [14] */ INVALID, INVALID, INVALID, INVALID,
1592 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1593 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1594
1595 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1596 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1597 /* [28] */ TNS("vmovapd",EVEX_MX), TNS("vmovapd",EVEX_RX), INVALID, INVALID,
1598 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
1599
1600 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1601 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1602 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1603 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1604
1605 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1606 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1607 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1608 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1609
1610 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1611 /* [54] */ TNS("vandpd",EVEX_RMrX),TNS("vandnpd",EVEX_RMrX),TNS("vorpd",EVEX_RMrX),TNS("vxorpd",EVEX_RMrX),
1612 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1613 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1614
1615 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1616 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1617 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1618 /* [6C] */ INVALID, INVALID, INVALID, TNS("vmovdqa",EVEX_MX),
1619
1620 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1621 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1622 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1623 /* [7C] */ INVALID, INVALID, INVALID, TNS("vmovdqa",EVEX_RX),
1624
1625 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1626 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1627 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1628 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1629
1630 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1631 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1632 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1633 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1634
1635 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1636 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1637 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1638 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1639
1640 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1641 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1642 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1643 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1644
1645 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1646 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1647 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1648 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1649
1650 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1651 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1652 /* [D8] */ INVALID, INVALID, INVALID, TSq("vpand",EVEX_RMrX),
1653 /* [DC] */ INVALID, INVALID, INVALID, TSq("vpandn",EVEX_RMrX),
1654
1655 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1656 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1657 /* [E8] */ INVALID, INVALID, INVALID, TSq("vpor",EVEX_RMrX),
1658 /* [EC] */ INVALID, INVALID, INVALID, TSq("vpxor",EVEX_RMrX),
1659
1660 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1661 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1662 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1663 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1664 };
1665
1666 const instable_t dis_opEVEX660F38[256] = {
1667 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1668 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1669 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1670 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1671
1672 /* [10] */ INVALID, INVALID, INVALID, INVALID,
1673 /* [14] */ INVALID, INVALID, INVALID, INVALID,
1674 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1675 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1676
1677 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1678 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1679 /* [28] */ INVALID, INVALID, INVALID, INVALID,
1680 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
1681
1682 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1683 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1684 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1685 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1686
1687 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1688 /* [44] */ TNSSq("vplzcnt",EVEX_MBX),INVALID, INVALID, INVALID,
1689 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1690 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1691
1692 /* [50] */ TNSZ("vpdpbusd",EVEX_RMBrX,16),TNSZ("vpdpbusds",EVEX_RMBrX,16),TNSZ("vpdpwssd",EVEX_RMBrX,16),TNSZ("vpdpwssds",EVEX_RMBrX,16),
1693 /* [54] */ TNSSb("vpopcnt",EVEX_MX),TNSSq("vpopcnt",EVEX_MBX),INVALID, INVALID,
1694 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1695 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1696
1697 /* [60] */ INVALID, INVALID, TNSSb("vpexpand",EVEX_MXT1S8B),TNSSb("vpcompress",EVEX_RXT1S8B),
1698 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1699 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1700 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1701
1702 /* [70] */ TNSSb("vpshldv",EVEX_RMrX),TNSSq("vpshldv",EVEX_RMBrX),TNSSb("vpshrdv",EVEX_RMrX),TNSSq("vpshrdv",EVEX_RMBrX),
1703 /* [74] */ INVALID, TNSSb("vpermi2",EVEX_RMrX),TNSSq("vpermi2",EVEX_RMBrX),TNSSd("vpermi2p",EVEX_RMBrX),
1704 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1705 /* [7C] */ INVALID, TNSSb("vpermt2",EVEX_RMrX),TNSSq("vpermt2",EVEX_RMBrX),TNSSd("vpermt2p",EVEX_RMBrX),
1706
1707 /* [80] */ INVALID, INVALID, INVALID, TNS("vpmultishiftqb",EVEX_RMBrX),
1708 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1709 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1710 /* [8C] */ INVALID, TNSSb("vperm",EVEX_RMrX),INVALID, TNS("vpshufbitqmb",EVEX_RMrK),
1711
1712 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1713 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1714 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1715 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1716
1717 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1718 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1719 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1720 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1721
1722 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1723 /* [B4] */ TNS("vpmadd52luq",EVEX_RMBrX),TNS("vpmadd52huq",EVEX_RMBrX),INVALID, INVALID,
1724 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1725 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1726
1727 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1728 /* [C4] */ TNSSq("vpconflict",EVEX_MBX),INVALID, INVALID, INVALID,
1729 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1730 /* [CC] */ INVALID, INVALID, INVALID, TNS("vgf2p8mulb",EVEX_RMrX),
1731
1732 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1733 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1734 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1735 /* [DC] */ TNSZ("vaesenc",EVEX_RMrX,16),TNSZ("vaesenclast",EVEX_RMrX,16),TNSZ("vaesdec",EVEX_RMrX,16),TNSZ("vaesdeclast",EVEX_RMrX,16),
1736
1737 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1738 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1739 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1740 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1741
1742 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1743 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1744 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1745 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1746 };
1747
1748 const instable_t dis_opEVEX660F3A[256] = {
1749 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1750 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1751 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1752 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1753
1754 /* [10] */ INVALID, INVALID, INVALID, INVALID,
1755 /* [14] */ INVALID, INVALID, INVALID, INVALID,
1756 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1757 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1758
1759 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1760 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1761 /* [28] */ INVALID, INVALID, INVALID, INVALID,
1762 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
1763
1764 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1765 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1766 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1767 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1768
1769 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1770 /* [44] */ TNSZ("vpclmulqdq",EVEX_RMRX,16),INVALID, INVALID, INVALID,
1771 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1772 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1773
1774 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1775 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1776 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1777 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1778
1779 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1780 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1781 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1782 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1783
1784 /* [70] */ TNSSb("vpshld",EVEX_RMRX),TNSSq("vpshld",EVEX_RMBRX),TNSSb("vpshrd",EVEX_RMRX),TNSSq("vpshrd",EVEX_RMBRX),
1785 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1786 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1787 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1788
1789 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1790 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1791 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1792 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
1793
1794 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1795 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1796 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1797 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1798
1799 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1800 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1801 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1802 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1803
1804 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1805 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1806 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1807 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1808
1809 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1810 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1811 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1812 /* [CC] */ INVALID, INVALID, TNS("vgf2p8affineqb",EVEX_RMRX),TNS("vgf2p8affineinvqb",EVEX_RMRX),
1813
1814 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1815 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1816 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1817 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1818
1819 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1820 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1821 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1822 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1823
1824 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1825 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1826 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1827 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1828 };
1829
1830
1831 const instable_t dis_opEVEXF20F[256] = {
1832 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1833 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1834 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1835 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1836
1837 /* [10] */ INVALID, INVALID, INVALID, INVALID,
1838 /* [14] */ INVALID, INVALID, INVALID, INVALID,
1839 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1840 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1841
1842 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1843 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1844 /* [28] */ INVALID, INVALID, INVALID, INVALID,
1845 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
1846
1847 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1848 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1849 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1850 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1851
1852 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1853 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1854 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1855 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1856
1857 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1858 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1859 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1860 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1861
1862 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1863 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1864 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1865 /* [6C] */ INVALID, INVALID, INVALID, TNS("vmovdqu",EVEX_MX),
1866
1867 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1868 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1869 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1870 /* [7C] */ INVALID, INVALID, INVALID, TNS("vmovdqu",EVEX_RX),
1871
1872 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1873 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1874 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1875 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1876
1877 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1878 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1879 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1880 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1881
1882 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1883 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1884 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1885 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1886
1887 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1888 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1889 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1890 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1891
1892 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1893 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1894 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1895 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1896
1897 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1898 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1899 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1900 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1901
1902 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1903 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1904 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1905 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1906
1907 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1908 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1909 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1910 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1911 };
1912
1913 const instable_t dis_opEVEXF20F38[256] = {
1914 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1915 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1916 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1917 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1918
1919 /* [10] */ INVALID, INVALID, INVALID, INVALID,
1920 /* [14] */ INVALID, INVALID, INVALID, INVALID,
1921 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1922 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1923
1924 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1925 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1926 /* [28] */ INVALID, INVALID, INVALID, INVALID,
1927 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
1928
1929 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1930 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1931 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1932 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1933
1934 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1935 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1936 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1937 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1938
1939 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1940 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1941 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1942 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1943
1944 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1945 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1946 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1947 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1948
1949 /* [70] */ INVALID, INVALID, TNS("vcvtneps2bf16",EVEX_RMBrX),INVALID,
1950 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1951 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1952 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1953
1954 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1955 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1956 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1957 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1958
1959 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1960 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1961 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1962 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1963
1964 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1965 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1966 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1967 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1968
1969 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1970 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1971 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1972 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1973
1974 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1975 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1976 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1977 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1978
1979 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1980 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1981 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1982 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1983
1984 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1985 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1986 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1987 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1988
1989 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1990 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1991 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1992 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1993 };
1994
1995 const instable_t dis_opEVEXF30F[256] = {
1996 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1997 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1998 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1999 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
2000
2001 /* [10] */ INVALID, INVALID, INVALID, INVALID,
2002 /* [14] */ INVALID, INVALID, INVALID, INVALID,
2003 /* [18] */ INVALID, INVALID, INVALID, INVALID,
2004 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
2005
2006 /* [20] */ INVALID, INVALID, INVALID, INVALID,
2007 /* [24] */ INVALID, INVALID, INVALID, INVALID,
2008 /* [28] */ INVALID, INVALID, INVALID, INVALID,
2009 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
2010
2011 /* [30] */ INVALID, INVALID, INVALID, INVALID,
2012 /* [34] */ INVALID, INVALID, INVALID, INVALID,
2013 /* [38] */ INVALID, INVALID, INVALID, INVALID,
2014 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
2015
2016 /* [40] */ INVALID, INVALID, INVALID, INVALID,
2017 /* [44] */ INVALID, INVALID, INVALID, INVALID,
2018 /* [48] */ INVALID, INVALID, INVALID, INVALID,
2019 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
2020
2021 /* [50] */ INVALID, INVALID, INVALID, INVALID,
2022 /* [54] */ INVALID, INVALID, INVALID, INVALID,
2023 /* [58] */ INVALID, INVALID, INVALID, INVALID,
2024 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
2025
2026 /* [60] */ INVALID, INVALID, INVALID, INVALID,
2027 /* [64] */ INVALID, INVALID, INVALID, INVALID,
2028 /* [68] */ INVALID, INVALID, INVALID, INVALID,
2029 /* [6C] */ INVALID, INVALID, INVALID, TNS("vmovdqu",EVEX_MX),
2030
2031 /* [70] */ INVALID, INVALID, INVALID, INVALID,
2032 /* [74] */ INVALID, INVALID, INVALID, INVALID,
2033 /* [78] */ INVALID, INVALID, INVALID, INVALID,
2034 /* [7C] */ INVALID, INVALID, INVALID, TNS("vmovdqu",EVEX_RX),
2035
2036 /* [80] */ INVALID, INVALID, INVALID, INVALID,
2037 /* [84] */ INVALID, INVALID, INVALID, INVALID,
2038 /* [88] */ INVALID, INVALID, INVALID, INVALID,
2039 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
2040
2041 /* [90] */ INVALID, INVALID, INVALID, INVALID,
2042 /* [94] */ INVALID, INVALID, INVALID, INVALID,
2043 /* [98] */ INVALID, INVALID, INVALID, INVALID,
2044 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
2045
2046 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
2047 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
2048 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
2049 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
2050
2051 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
2052 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
2053 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
2054 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
2055
2056 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
2057 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
2058 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
2059 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
2060
2061 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
2062 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
2063 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
2064 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
2065
2066 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
2067 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
2068 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
2069 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
2070
2071 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
2072 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
2073 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
2074 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
2075 };
2076
2077 const instable_t dis_opEVEXF30F38[256] = {
2078 /* [00] */ INVALID, INVALID, INVALID, INVALID,
2079 /* [04] */ INVALID, INVALID, INVALID, INVALID,
2080 /* [08] */ INVALID, INVALID, INVALID, INVALID,
2081 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
2082
2083 /* [10] */ INVALID, INVALID, INVALID, INVALID,
2084 /* [14] */ INVALID, INVALID, INVALID, INVALID,
2085 /* [18] */ INVALID, INVALID, INVALID, INVALID,
2086 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
2087
2088 /* [20] */ INVALID, INVALID, INVALID, INVALID,
2089 /* [24] */ INVALID, INVALID, INVALID, INVALID,
2090 /* [28] */ INVALID, INVALID, TNSSq("vpbroadcastmb2",EVEX_KR),INVALID,
2091 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
2092
2093 /* [30] */ INVALID, INVALID, INVALID, INVALID,
2094 /* [34] */ INVALID, INVALID, INVALID, INVALID,
2095 /* [38] */ INVALID, INVALID, TNSSq("vpbroadcastmw2",EVEX_KR),INVALID,
2096 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
2097
2098 /* [40] */ INVALID, INVALID, INVALID, INVALID,
2099 /* [44] */ INVALID, INVALID, INVALID, INVALID,
2100 /* [48] */ INVALID, INVALID, INVALID, INVALID,
2101 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
2102
2103 /* [50] */ INVALID, INVALID, TNS("vdpbf16ps",EVEX_RMBrX),INVALID,
2104 /* [54] */ INVALID, INVALID, INVALID, INVALID,
2105 /* [58] */ INVALID, INVALID, INVALID, INVALID,
2106 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
2107
2108 /* [60] */ INVALID, INVALID, INVALID, INVALID,
2109 /* [64] */ INVALID, INVALID, INVALID, INVALID,
2110 /* [68] */ INVALID, INVALID, INVALID, INVALID,
2111 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
2112
2113 /* [70] */ INVALID, INVALID, TNS("vcvtneps2bf16",EVEX_MBX),INVALID,
2114 /* [74] */ INVALID, INVALID, INVALID, INVALID,
2115 /* [78] */ INVALID, INVALID, INVALID, INVALID,
2116 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
2117
2118 /* [80] */ INVALID, INVALID, INVALID, INVALID,
2119 /* [84] */ INVALID, INVALID, INVALID, INVALID,
2120 /* [88] */ INVALID, INVALID, INVALID, INVALID,
2121 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
2122
2123 /* [90] */ INVALID, INVALID, INVALID, INVALID,
2124 /* [94] */ INVALID, INVALID, INVALID, INVALID,
2125 /* [98] */ INVALID, INVALID, INVALID, INVALID,
2126 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
2127
2128 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
2129 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
2130 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
2131 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
2132
2133 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
2134 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
2135 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
2136 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
2137
2138 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
2139 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
2140 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
2141 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
2142
2143 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
2144 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
2145 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
2146 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
2147
2148 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
2149 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
2150 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
2151 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
2152
2153 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
2154 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
2155 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
2156 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
2157 };
2158
2159
2160 /*
2161 * The following two tables are used to encode crc32 and movbe
2162 * since they share the same opcodes.
2163 */
2164 const instable_t dis_op0F38F0[2] = {
2165 /* [00] */ TNS("crc32b",CRC32),
2166 TS("movbe",MOVBE),
2167 };
2168
2169 const instable_t dis_op0F38F1[2] = {
2170 /* [00] */ TS("crc32",CRC32),
2171 TS("movbe",MOVBE),
2172 };
2173
2174 /*
2175 * The following table is used to distinguish between adox and adcx which share
2176 * the same opcodes.
2177 */
2178 const instable_t dis_op0F38F6[2] = {
2179 /* [00] */ TNS("adcx",ADX),
2180 TNS("adox",ADX),
2181 };
2182
2183 const instable_t dis_op0F38[256] = {
2184 /* [00] */ TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16),
2185 /* [04] */ TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16), TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16),
2186 /* [08] */ TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16),
2187 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
2188
2189 /* [10] */ TNSZ("pblendvb",XMM_66r,16),INVALID, INVALID, INVALID,
2190 /* [14] */ TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID, TNSZ("ptest",XMM_66r,16),
2191 /* [18] */ INVALID, INVALID, INVALID, INVALID,
2192 /* [1C] */ TNSZ("pabsb",XMM_66o,16),TNSZ("pabsw",XMM_66o,16),TNSZ("pabsd",XMM_66o,16),INVALID,
2193
2194 /* [20] */ TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16),
2195 /* [24] */ TNSZ("pmovsxwq",XMM_66r,16),TNSZ("pmovsxdq",XMM_66r,16),INVALID, INVALID,
2196 /* [28] */ TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16),
2197 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
2198
2199 /* [30] */ TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16),
2200 /* [34] */ TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID, TNSZ("pcmpgtq",XMM_66r,16),
2201 /* [38] */ TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16),
2202 /* [3C] */ TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16),
2203
2204 /* [40] */ TNSZ("pmulld",XMM_66r,16),TNSZ("phminposuw",XMM_66r,16),INVALID, INVALID,
2205 /* [44] */ INVALID, INVALID, INVALID, INVALID,
2206 /* [48] */ INVALID, INVALID, INVALID, INVALID,
2207 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
2208
2209 /* [50] */ INVALID, INVALID, INVALID, INVALID,
2210 /* [54] */ INVALID, INVALID, INVALID, INVALID,
2211 /* [58] */ INVALID, INVALID, INVALID, INVALID,
2212 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
2213
2214 /* [60] */ INVALID, INVALID, INVALID, INVALID,
2215 /* [64] */ INVALID, INVALID, INVALID, INVALID,
2216 /* [68] */ INVALID, INVALID, INVALID, INVALID,
2217 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
2218
2219 /* [70] */ INVALID, INVALID, INVALID, INVALID,
2220 /* [74] */ INVALID, INVALID, INVALID, INVALID,
2221 /* [78] */ INVALID, INVALID, INVALID, INVALID,
2222 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
2223
2224 /* [80] */ TNSy("invept", RM_66r), TNSy("invvpid", RM_66r),TNSy("invpcid", RM_66r),INVALID,
2225 /* [84] */ INVALID, INVALID, INVALID, INVALID,
2226 /* [88] */ INVALID, INVALID, INVALID, INVALID,
2227 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
2228
2229 /* [90] */ INVALID, INVALID, INVALID, INVALID,
2230 /* [94] */ INVALID, INVALID, INVALID, INVALID,
2231 /* [98] */ INVALID, INVALID, INVALID, INVALID,
2232 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
2233
2234 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
2235 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
2236 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
2237 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
2238
2239 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
2240 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
2241 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
2242 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
2243
2244 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
2245 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
2246 /* [C8] */ TNSZ("sha1nexte",XMM,16),TNSZ("sha1msg1",XMM,16),TNSZ("sha1msg2",XMM,16),TNSZ("sha256rnds2",XMM,16),
2247 /* [CC] */ TNSZ("sha256msg1",XMM,16),TNSZ("sha256msg2",XMM,16),INVALID, TNS("gf2p8mulb",XMM_66r),
2248
2249 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
2250 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
2251 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("aesimc",XMM_66r,16),
2252 /* [DC] */ TNSZ("aesenc",XMM_66r,16),TNSZ("aesenclast",XMM_66r,16),TNSZ("aesdec",XMM_66r,16),TNSZ("aesdeclast",XMM_66r,16),
2253
2254 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
2255 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
2256 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
2257 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
2258 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID,
2259 /* [F4] */ INVALID, INVALID, IND(dis_op0F38F6), INVALID,
2260 /* [F8] */ TNS("movdir64b",MOVDIR),TNS("movdiri",RM), INVALID, INVALID,
2261 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
2262 };
2263
2264 const instable_t dis_opAVX660F38[256] = {
2265 /* [00] */ TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16),
2266 /* [04] */ TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16), TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16),
2267 /* [08] */ TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16),
2268 /* [0C] */ TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8), TNSZ("vtestpd",VEX_RRI,16),
2269
2270 /* [10] */ INVALID, INVALID, INVALID, TNSZ("vcvtph2ps",VEX_MX,16),
2271 /* [14] */ INVALID, INVALID, TNSZ("vpermps",VEX_RMrX,16),TNSZ("vptest",VEX_RRI,16),
2272 /* [18] */ TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID,
2273 /* [1C] */ TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID,
2274
2275 /* [20] */ TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16),
2276 /* [24] */ TNSZ("vpmovsxwq",VEX_MX,16),TNSZ("vpmovsxdq",VEX_MX,16),INVALID, INVALID,
2277 /* [28] */ TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16),
2278 /* [2C] */ TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16),
2279
2280 /* [30] */ TNSZ("vpmovzxbw",VEX_MX,16),TNSZ("vpmovzxbd",VEX_MX,16),TNSZ("vpmovzxbq",VEX_MX,16),TNSZ("vpmovzxwd",VEX_MX,16),
2281 /* [34] */ TNSZ("vpmovzxwq",VEX_MX,16),TNSZ("vpmovzxdq",VEX_MX,16),TNSZ("vpermd",VEX_RMrX,16),TNSZ("vpcmpgtq",VEX_RMrX,16),
2282 /* [38] */ TNSZ("vpminsb",VEX_RMrX,16),TNSZ("vpminsd",VEX_RMrX,16),TNSZ("vpminuw",VEX_RMrX,16),TNSZ("vpminud",VEX_RMrX,16),
2283 /* [3C] */ TNSZ("vpmaxsb",VEX_RMrX,16),TNSZ("vpmaxsd",VEX_RMrX,16),TNSZ("vpmaxuw",VEX_RMrX,16),TNSZ("vpmaxud",VEX_RMrX,16),
2284
2285 /* [40] */ TNSZ("vpmulld",VEX_RMrX,16),TNSZ("vphminposuw",VEX_MX,16),INVALID, INVALID,
2286 /* [44] */ INVALID, TSaZ("vpsrlv",VEX_RMrX,16),TNSZ("vpsravd",VEX_RMrX,16),TSaZ("vpsllv",VEX_RMrX,16),
2287 /* [48] */ INVALID, INVALID, INVALID, INVALID,
2288 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
2289
2290 /* [50] */ INVALID, INVALID, INVALID, INVALID,
2291 /* [54] */ INVALID, INVALID, INVALID, INVALID,
2292 /* [58] */ TNSZ("vpbroadcastd",VEX_MX,16),TNSZ("vpbroadcastq",VEX_MX,16),TNSZ("vbroadcasti128",VEX_MX,16),INVALID,
2293 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
2294
2295 /* [60] */ INVALID, INVALID, INVALID, INVALID,
2296 /* [64] */ INVALID, INVALID, INVALID, INVALID,
2297 /* [68] */ INVALID, INVALID, INVALID, INVALID,
2298 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
2299
2300 /* [70] */ INVALID, INVALID, INVALID, INVALID,
2301 /* [74] */ INVALID, INVALID, INVALID, INVALID,
2302 /* [78] */ TNSZ("vpbroadcastb",VEX_MX,16),TNSZ("vpbroadcastw",VEX_MX,16),INVALID, INVALID,
2303 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
2304
2305 /* [80] */ INVALID, INVALID, INVALID, INVALID,
2306 /* [84] */ INVALID, INVALID, INVALID, INVALID,
2307 /* [88] */ INVALID, INVALID, INVALID, INVALID,
2308 /* [8C] */ TSaZ("vpmaskmov",VEX_RMrX,16),INVALID, TSaZ("vpmaskmov",VEX_RRM,16),INVALID,
2309
2310 /* [90] */ TNSZ("vpgatherd",VEX_SbVM,16),TNSZ("vpgatherq",VEX_SbVM,16),TNSZ("vgatherdp",VEX_SbVM,16),TNSZ("vgatherqp",VEX_SbVM,16),
2311 /* [94] */ INVALID, INVALID, TNSZ("vfmaddsub132p",FMA,16),TNSZ("vfmsubadd132p",FMA,16),
2312 /* [98] */ TNSZ("vfmadd132p",FMA,16),TNSZ("vfmadd132s",FMA,16),TNSZ("vfmsub132p",FMA,16),TNSZ("vfmsub132s",FMA,16),
2313 /* [9C] */ TNSZ("vfnmadd132p",FMA,16),TNSZ("vfnmadd132s",FMA,16),TNSZ("vfnmsub132p",FMA,16),TNSZ("vfnmsub132s",FMA,16),
2314
2315 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
2316 /* [A4] */ INVALID, INVALID, TNSZ("vfmaddsub213p",FMA,16),TNSZ("vfmsubadd213p",FMA,16),
2317 /* [A8] */ TNSZ("vfmadd213p",FMA,16),TNSZ("vfmadd213s",FMA,16),TNSZ("vfmsub213p",FMA,16),TNSZ("vfmsub213s",FMA,16),
2318 /* [AC] */ TNSZ("vfnmadd213p",FMA,16),TNSZ("vfnmadd213s",FMA,16),TNSZ("vfnmsub213p",FMA,16),TNSZ("vfnmsub213s",FMA,16),
2319
2320 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
2321 /* [B4] */ INVALID, INVALID, TNSZ("vfmaddsub231p",FMA,16),TNSZ("vfmsubadd231p",FMA,16),
2322 /* [B8] */ TNSZ("vfmadd231p",FMA,16),TNSZ("vfmadd231s",FMA,16),TNSZ("vfmsub231p",FMA,16),TNSZ("vfmsub231s",FMA,16),
2323 /* [BC] */ TNSZ("vfnmadd231p",FMA,16),TNSZ("vfnmadd231s",FMA,16),TNSZ("vfnmsub231p",FMA,16),TNSZ("vfnmsub231s",FMA,16),
2324
2325 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
2326 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
2327 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
2328 /* [CC] */ INVALID, INVALID, INVALID, TNS("vgf2p8mulb",VEX_RMrX),
2329
2330 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
2331 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
2332 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("vaesimc",VEX_MX,16),
2333 /* [DC] */ TNSZ("vaesenc",VEX_RMrX,16),TNSZ("vaesenclast",VEX_RMrX,16),TNSZ("vaesdec",VEX_RMrX,16),TNSZ("vaesdeclast",VEX_RMrX,16),
2334
2335 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
2336 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
2337 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
2338 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
2339 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID,
2340 /* [F4] */ INVALID, INVALID, INVALID, TNSZvr("shlx",VEX_VRMrX,5),
2341 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
2342 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
2343 };
2344
2345 const instable_t dis_op0F3A[256] = {
2346 /* [00] */ INVALID, INVALID, INVALID, INVALID,
2347 /* [04] */ INVALID, INVALID, INVALID, INVALID,
2348 /* [08] */ TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16),
2349 /* [0C] */ TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16),
2350
2351 /* [10] */ INVALID, INVALID, INVALID, INVALID,
2352 /* [14] */ TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16),
2353 /* [18] */ INVALID, INVALID, INVALID, INVALID,
2354 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
2355
2356 /* [20] */ TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID,
2357 /* [24] */ INVALID, INVALID, INVALID, INVALID,
2358 /* [28] */ INVALID, INVALID, INVALID, INVALID,
2359 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
2360
2361 /* [30] */ INVALID, INVALID, INVALID, INVALID,
2362 /* [34] */ INVALID, INVALID, INVALID, INVALID,
2363 /* [38] */ INVALID, INVALID, INVALID, INVALID,
2364 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
2365
2366 /* [40] */ TNSZ("dpps",XMMP_66r,16),TNSZ("dppd",XMMP_66r,16),TNSZ("mpsadbw",XMMP_66r,16),INVALID,
2367 /* [44] */ TNSZ("pclmulqdq",XMMP_66r,16),INVALID, INVALID, INVALID,
2368 /* [48] */ INVALID, INVALID, INVALID, INVALID,
2369 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
2370
2371 /* [50] */ INVALID, INVALID, INVALID, INVALID,
2372 /* [54] */ INVALID, INVALID, INVALID, INVALID,
2373 /* [58] */ INVALID, INVALID, INVALID, INVALID,
2374 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
2375
2376 /* [60] */ TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16),
2377 /* [64] */ INVALID, INVALID, INVALID, INVALID,
2378 /* [68] */ INVALID, INVALID, INVALID, INVALID,
2379 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
2380
2381 /* [70] */ INVALID, INVALID, INVALID, INVALID,
2382 /* [74] */ INVALID, INVALID, INVALID, INVALID,
2383 /* [78] */ INVALID, INVALID, INVALID, INVALID,
2384 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
2385
2386 /* [80] */ INVALID, INVALID, INVALID, INVALID,
2387 /* [84] */ INVALID, INVALID, INVALID, INVALID,
2388 /* [88] */ INVALID, INVALID, INVALID, INVALID,
2389 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
2390
2391 /* [90] */ INVALID, INVALID, INVALID, INVALID,
2392 /* [94] */ INVALID, INVALID, INVALID, INVALID,
2393 /* [98] */ INVALID, INVALID, INVALID, INVALID,
2394 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
2395
2396 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
2397 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
2398 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
2399 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
2400
2401 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
2402 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
2403 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
2404 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
2405
2406 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
2407 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
2408 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
2409 /* [CC] */ TNSZ("sha1rnds4",XMMP,16),INVALID, TNS("gf2p8affineqb",XMMP_66r),TNS("gf2p8affineinvqb",XMMP_66r),
2410
2411 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
2412 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
2413 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
2414 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("aeskeygenassist",XMMP_66r,16),
2415
2416 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
2417 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
2418 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
2419 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
2420
2421 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
2422 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
2423 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
2424 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
2425 };
2426
2427 const instable_t dis_opAVX660F3A[256] = {
2428 /* [00] */ TNSZ("vpermq",VEX_MXI,16),TNSZ("vpermpd",VEX_MXI,16),TNSZ("vpblendd",VEX_RMRX,16),INVALID,
2429 /* [04] */ TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID,
2430 /* [08] */ TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16),
2431 /* [0C] */ TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16),
2432
2433 /* [10] */ INVALID, INVALID, INVALID, INVALID,
2434 /* [14] */ TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16),
2435 /* [18] */ TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID, INVALID,
2436 /* [1C] */ INVALID, TNSZ("vcvtps2ph",VEX_RX,16), INVALID, INVALID,
2437
2438 /* [20] */ TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID,
2439 /* [24] */ INVALID, INVALID, INVALID, INVALID,
2440 /* [28] */ INVALID, INVALID, INVALID, INVALID,
2441 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
2442
2443 /* [30] */ TSvo("kshiftr",VEX_MXI), TSvo("kshiftr",VEX_MXI), TSvo("kshiftl",VEX_MXI), TSvo("kshiftl",VEX_MXI),
2444 /* [34] */ INVALID, INVALID, INVALID, INVALID,
2445 /* [38] */ TNSZ("vinserti128",VEX_RMRX,16),TNSZ("vextracti128",VEX_RIM,16),INVALID, INVALID,
2446 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
2447
2448 /* [40] */ TNSZ("vdpps",VEX_RMRX,16),TNSZ("vdppd",VEX_RMRX,16),TNSZ("vmpsadbw",VEX_RMRX,16),INVALID,
2449 /* [44] */ TNSZ("vpclmulqdq",VEX_RMRX,16),INVALID, TNSZ("vperm2i128",VEX_RMRX,16),INVALID,
2450 /* [48] */ INVALID, INVALID, TNSZ("vblendvps",VEX_RMRX,8), TNSZ("vblendvpd",VEX_RMRX,16),
2451 /* [4C] */ TNSZ("vpblendvb",VEX_RMRX,16),INVALID, INVALID, INVALID,
2452
2453 /* [50] */ INVALID, INVALID, INVALID, INVALID,
2454 /* [54] */ INVALID, INVALID, INVALID, INVALID,
2455 /* [58] */ INVALID, INVALID, INVALID, INVALID,
2456 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
2457
2458 /* [60] */ TNSZ("vpcmpestrm",VEX_MXI,16),TNSZ("vpcmpestri",VEX_MXI,16),TNSZ("vpcmpistrm",VEX_MXI,16),TNSZ("vpcmpistri",VEX_MXI,16),
2459 /* [64] */ INVALID, INVALID, INVALID, INVALID,
2460 /* [68] */ INVALID, INVALID, INVALID, INVALID,
2461 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
2462
2463 /* [70] */ INVALID, INVALID, INVALID, INVALID,
2464 /* [74] */ INVALID, INVALID, INVALID, INVALID,
2465 /* [78] */ INVALID, INVALID, INVALID, INVALID,
2466 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
2467
2468 /* [80] */ INVALID, INVALID, INVALID, INVALID,
2469 /* [84] */ INVALID, INVALID, INVALID, INVALID,
2470 /* [88] */ INVALID, INVALID, INVALID, INVALID,
2471 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
2472
2473 /* [90] */ INVALID, INVALID, INVALID, INVALID,
2474 /* [94] */ INVALID, INVALID, INVALID, INVALID,
2475 /* [98] */ INVALID, INVALID, INVALID, INVALID,
2476 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
2477
2478 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
2479 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
2480 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
2481 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
2482
2483 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
2484 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
2485 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
2486 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
2487
2488 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
2489 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
2490 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
2491 /* [CC] */ INVALID, INVALID, TNS("vgf2p8affineqb",VEX_RMRX),TNS("vgf2p8affineinvqb",VEX_RMRX),
2492
2493 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
2494 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
2495 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
2496 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("vaeskeygenassist",VEX_MXI,16),
2497
2498 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
2499 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
2500 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
2501 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
2502
2503 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
2504 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
2505 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
2506 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
2507 };
2508
2509 /*
2510 * Decode table for 0x0F0D which uses the first byte of the mod_rm to
2511 * indicate a sub-code.
2512 */
2513 const instable_t dis_op0F0D[8] = {
2514 /* [00] */ TNS("prefetch",PREF), TNS("prefetchw",PREF), TNS("prefetchwt1",PREF),INVALID,
2515 /* [04] */ INVALID, INVALID, INVALID, INVALID,
2516 };
2517
2518 /*
2519 * Decode table for 0x0F opcodes
2520 */
2521
2522 const instable_t dis_op0F[16][16] = {
2523 {
2524 /* [00] */ IND(dis_op0F00), IND(dis_op0F01), TNS("lar",MR), TNS("lsl",MR),
2525 /* [04] */ INVALID, TNS("syscall",NORM), TNS("clts",NORM), TNS("sysret",NORM),
2526 /* [08] */ TNS("invd",NORM), TNS("wbinvd",NORM), INVALID, TNS("ud2",NORM),
2527 /* [0C] */ INVALID, IND(dis_op0F0D), INVALID, INVALID,
2528 }, {
2529 /* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8),
2530 /* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8),
2531 /* [18] */ IND(dis_op0F18), INVALID, INVALID, INVALID,
2532 /* [1C] */ INVALID, INVALID, INVALID, TS("nop",Mw),
2533 }, {
2534 /* [20] */ TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG),
2535 /* [24] */ TSx("mov",SREG), INVALID, TSx("mov",SREG), INVALID,
2536 /* [28] */ TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16),
2537 /* [2C] */ TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4),
2538 }, {
2539 /* [30] */ TNS("wrmsr",NORM), TNS("rdtsc",NORM), TNS("rdmsr",NORM), TNS("rdpmc",NORM),
2540 /* [34] */ TNS("sysenter",NORM), TNS("sysexit",NORM), INVALID, INVALID,
2541 /* [38] */ INVALID, INVALID, INVALID, INVALID,
2542 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
2543 }, {
2544 /* [40] */ TS("cmovx.o",MR), TS("cmovx.no",MR), TS("cmovx.b",MR), TS("cmovx.ae",MR),
2545 /* [44] */ TS("cmovx.e",MR), TS("cmovx.ne",MR), TS("cmovx.be",MR), TS("cmovx.a",MR),
2546 /* [48] */ TS("cmovx.s",MR), TS("cmovx.ns",MR), TS("cmovx.pe",MR), TS("cmovx.po",MR),
2547 /* [4C] */ TS("cmovx.l",MR), TS("cmovx.ge",MR), TS("cmovx.le",MR), TS("cmovx.g",MR),
2548 }, {
2549 /* [50] */ TNS("movmskps",XMMOX3), TNSZ("sqrtps",XMMO,16), TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16),
2550 /* [54] */ TNSZ("andps",XMMO,16), TNSZ("andnps",XMMO,16), TNSZ("orps",XMMO,16), TNSZ("xorps",XMMO,16),
2551 /* [58] */ TNSZ("addps",XMMO,16), TNSZ("mulps",XMMO,16), TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16),
2552 /* [5C] */ TNSZ("subps",XMMO,16), TNSZ("minps",XMMO,16), TNSZ("divps",XMMO,16), TNSZ("maxps",XMMO,16),
2553 }, {
2554 /* [60] */ TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8),
2555 /* [64] */ TNSZ("pcmpgtb",MMO,8), TNSZ("pcmpgtw",MMO,8), TNSZ("pcmpgtd",MMO,8), TNSZ("packuswb",MMO,8),
2556 /* [68] */ TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8),
2557 /* [6C] */ TNSZ("INVALID",MMO,0), TNSZ("INVALID",MMO,0), TNSZ("movd",MMO,4), TNSZ("movq",MMO,8),
2558 }, {
2559 /* [70] */ TNSZ("pshufw",MMOPM,8), TNS("psrXXX",MR), TNS("psrXXX",MR), TNS("psrXXX",MR),
2560 /* [74] */ TNSZ("pcmpeqb",MMO,8), TNSZ("pcmpeqw",MMO,8), TNSZ("pcmpeqd",MMO,8), TNS("emms",NORM),
2561 /* [78] */ TNSy("vmread",RM), TNSy("vmwrite",MR), INVALID, INVALID,
2562 /* [7C] */ INVALID, INVALID, TNSZ("movd",MMOS,4), TNSZ("movq",MMOS,8),
2563 }, {
2564 /* [80] */ TNS("jo",D), TNS("jno",D), TNS("jb",D), TNS("jae",D),
2565 /* [84] */ TNS("je",D), TNS("jne",D), TNS("jbe",D), TNS("ja",D),
2566 /* [88] */ TNS("js",D), TNS("jns",D), TNS("jp",D), TNS("jnp",D),
2567 /* [8C] */ TNS("jl",D), TNS("jge",D), TNS("jle",D), TNS("jg",D),
2568 }, {
2569 /* [90] */ TNS("seto",Mb), TNS("setno",Mb), TNS("setb",Mb), TNS("setae",Mb),
2570 /* [94] */ TNS("sete",Mb), TNS("setne",Mb), TNS("setbe",Mb), TNS("seta",Mb),
2571 /* [98] */ TNS("sets",Mb), TNS("setns",Mb), TNS("setp",Mb), TNS("setnp",Mb),
2572 /* [9C] */ TNS("setl",Mb), TNS("setge",Mb), TNS("setle",Mb), TNS("setg",Mb),
2573 }, {
2574 /* [A0] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("cpuid",NORM), TS("bt",RMw),
2575 /* [A4] */ TS("shld",DSHIFT), TS("shld",DSHIFTcl), INVALID, INVALID,
2576 /* [A8] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("rsm",NORM), TS("bts",RMw),
2577 /* [AC] */ TS("shrd",DSHIFT), TS("shrd",DSHIFTcl), IND(dis_op0FAE), TS("imul",MRw),
2578 }, {
2579 /* [B0] */ TNS("cmpxchgb",RMw), TS("cmpxchg",RMw), TS("lss",MR), TS("btr",RMw),
2580 /* [B4] */ TS("lfs",MR), TS("lgs",MR), TS("movzb",MOVZ), TNS("movzwl",MOVZ),
2581 /* [B8] */ TNS("INVALID",MRw), INVALID, IND(dis_op0FBA), TS("btc",RMw),
2582 /* [BC] */ TS("bsf",MRw), TS("bsr",MRw), TS("movsb",MOVZ), TNS("movswl",MOVZ),
2583 }, {
2584 /* [C0] */ TNS("xaddb",XADDB), TS("xadd",RMw), TNSZ("cmpps",XMMOPM,16),TNS("movnti",RM),
2585 /* [C4] */ TNSZ("pinsrw",MMOPRM,2),TNS("pextrw",MMO3P), TNSZ("shufps",XMMOPM,16),IND(dis_op0FC7),
2586 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
2587 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
2588 }, {
2589 /* [D0] */ INVALID, TNSZ("psrlw",MMO,8), TNSZ("psrld",MMO,8), TNSZ("psrlq",MMO,8),
2590 /* [D4] */ TNSZ("paddq",MMO,8), TNSZ("pmullw",MMO,8), TNSZ("INVALID",MMO,0), TNS("pmovmskb",MMOM3),
2591 /* [D8] */ TNSZ("psubusb",MMO,8), TNSZ("psubusw",MMO,8), TNSZ("pminub",MMO,8), TNSZ("pand",MMO,8),
2592 /* [DC] */ TNSZ("paddusb",MMO,8), TNSZ("paddusw",MMO,8), TNSZ("pmaxub",MMO,8), TNSZ("pandn",MMO,8),
2593 }, {
2594 /* [E0] */ TNSZ("pavgb",MMO,8), TNSZ("psraw",MMO,8), TNSZ("psrad",MMO,8), TNSZ("pavgw",MMO,8),
2595 /* [E4] */ TNSZ("pmulhuw",MMO,8), TNSZ("pmulhw",MMO,8), TNS("INVALID",XMMO), TNSZ("movntq",MMOMS,8),
2596 /* [E8] */ TNSZ("psubsb",MMO,8), TNSZ("psubsw",MMO,8), TNSZ("pminsw",MMO,8), TNSZ("por",MMO,8),
2597 /* [EC] */ TNSZ("paddsb",MMO,8), TNSZ("paddsw",MMO,8), TNSZ("pmaxsw",MMO,8), TNSZ("pxor",MMO,8),
2598 }, {
2599 /* [F0] */ INVALID, TNSZ("psllw",MMO,8), TNSZ("pslld",MMO,8), TNSZ("psllq",MMO,8),
2600 /* [F4] */ TNSZ("pmuludq",MMO,8), TNSZ("pmaddwd",MMO,8), TNSZ("psadbw",MMO,8), TNSZ("maskmovq",MMOIMPL,8),
2601 /* [F8] */ TNSZ("psubb",MMO,8), TNSZ("psubw",MMO,8), TNSZ("psubd",MMO,8), TNSZ("psubq",MMO,8),
2602 /* [FC] */ TNSZ("paddb",MMO,8), TNSZ("paddw",MMO,8), TNSZ("paddd",MMO,8), INVALID,
2603 } };
2604
2605 const instable_t dis_opAVX0F[16][16] = {
2606 {
2607 /* [00] */ INVALID, INVALID, INVALID, INVALID,
2608 /* [04] */ INVALID, INVALID, INVALID, INVALID,
2609 /* [08] */ INVALID, INVALID, INVALID, INVALID,
2610 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
2611 }, {
2612 /* [10] */ TNSZ("vmovups",VEX_MX,16), TNSZ("vmovups",VEX_RM,16),TNSZ("vmovlps",VEX_RMrX,8), TNSZ("vmovlps",VEX_RM,8),
2613 /* [14] */ TNSZ("vunpcklps",VEX_RMrX,16),TNSZ("vunpckhps",VEX_RMrX,16),TNSZ("vmovhps",VEX_RMrX,8),TNSZ("vmovhps",VEX_RM,8),
2614 /* [18] */ INVALID, INVALID, INVALID, INVALID,
2615 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
2616 }, {
2617 /* [20] */ INVALID, INVALID, INVALID, INVALID,
2618 /* [24] */ INVALID, INVALID, INVALID, INVALID,
2619 /* [28] */ TNSZ("vmovaps",VEX_MX,16), TNSZ("vmovaps",VEX_RX,16),INVALID, TNSZ("vmovntps",VEX_RM,16),
2620 /* [2C] */ INVALID, INVALID, TNSZ("vucomiss",VEX_MX,4),TNSZ("vcomiss",VEX_MX,4),
2621 }, {
2622 /* [30] */ INVALID, INVALID, INVALID, INVALID,
2623 /* [34] */ INVALID, INVALID, INVALID, INVALID,
2624 /* [38] */ INVALID, INVALID, INVALID, INVALID,
2625 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
2626 }, {
2627 /* [40] */ INVALID, TSvo("kand",VEX_RMX), TSvo("kandn",VEX_RMX), INVALID,
2628 /* [44] */ TSvo("knot",VEX_MX), TSvo("kor",VEX_RMX), TSvo("kxnor",VEX_RMX), TSvo("kxor",VEX_RMX),
2629 /* [48] */ INVALID, INVALID, TSvo("kadd",VEX_RMX), TSvo("kunpck",VEX_RMX),
2630 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
2631 }, {
2632 /* [50] */ TNS("vmovmskps",VEX_MR), TNSZ("vsqrtps",VEX_MX,16), TNSZ("vrsqrtps",VEX_MX,16),TNSZ("vrcpps",VEX_MX,16),
2633 /* [54] */ TNSZ("vandps",VEX_RMrX,16), TNSZ("vandnps",VEX_RMrX,16), TNSZ("vorps",VEX_RMrX,16), TNSZ("vxorps",VEX_RMrX,16),
2634 /* [58] */ TNSZ("vaddps",VEX_RMrX,16), TNSZ("vmulps",VEX_RMrX,16), TNSZ("vcvtps2pd",VEX_MX,8),TNSZ("vcvtdq2ps",VEX_MX,16),
2635 /* [5C] */ TNSZ("vsubps",VEX_RMrX,16), TNSZ("vminps",VEX_RMrX,16), TNSZ("vdivps",VEX_RMrX,16), TNSZ("vmaxps",VEX_RMrX,16),
2636 }, {
2637 /* [60] */ INVALID, INVALID, INVALID, INVALID,
2638 /* [64] */ INVALID, INVALID, INVALID, INVALID,
2639 /* [68] */ INVALID, INVALID, INVALID, INVALID,
2640 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
2641 }, {
2642 /* [70] */ INVALID, INVALID, INVALID, INVALID,
2643 /* [74] */ INVALID, INVALID, INVALID, TNS("vzeroupper", VEX_NONE),
2644 /* [78] */ INVALID, INVALID, INVALID, INVALID,
2645 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
2646 }, {
2647 /* [80] */ INVALID, INVALID, INVALID, INVALID,
2648 /* [84] */ INVALID, INVALID, INVALID, INVALID,
2649 /* [88] */ INVALID, INVALID, INVALID, INVALID,
2650 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
2651 }, {
2652 /* [90] */ TSvo("kmov",VEX_KRM), TSvo("kmov",VEX_KMR), TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR),
2653 /* [94] */ INVALID, INVALID, INVALID, INVALID,
2654 /* [98] */ TSvo("kortest",VEX_MX), TSvo("ktest",VEX_MX), INVALID, INVALID,
2655 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
2656 }, {
2657 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
2658 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
2659 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
2660 /* [AC] */ INVALID, INVALID, TNSZ("vldmxcsr",VEX_MO,2), INVALID,
2661 }, {
2662 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
2663 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
2664 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
2665 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
2666 }, {
2667 /* [C0] */ INVALID, INVALID, TNSZ("vcmpps",VEX_RMRX,16),INVALID,
2668 /* [C4] */ INVALID, INVALID, TNSZ("vshufps",VEX_RMRX,16),INVALID,
2669 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
2670 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
2671 }, {
2672 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
2673 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
2674 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
2675 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
2676 }, {
2677 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
2678 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
2679 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
2680 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
2681 }, {
2682 /* [F0] */ INVALID, INVALID, TNSZvr("andn",VEX_RMrX,5),TNSZvr("bls",BLS,5),
2683 /* [F4] */ INVALID, TNSZvr("bzhi",VEX_VRMrX,5),INVALID, TNSZvr("bextr",VEX_VRMrX,5),
2684 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
2685 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
2686 } };
2687
2688 /*
2689 * Decode table for 0x80 opcodes
2690 */
2691
2692 const instable_t dis_op80[8] = {
2693
2694 /* [0] */ TNS("addb",IMlw), TNS("orb",IMw), TNS("adcb",IMlw), TNS("sbbb",IMlw),
2695 /* [4] */ TNS("andb",IMw), TNS("subb",IMlw), TNS("xorb",IMw), TNS("cmpb",IMlw),
2696 };
2697
2698
2699 /*
2700 * Decode table for 0x81 opcodes.
2701 */
2702
2703 const instable_t dis_op81[8] = {
2704
2705 /* [0] */ TS("add",IMlw), TS("or",IMw), TS("adc",IMlw), TS("sbb",IMlw),
2706 /* [4] */ TS("and",IMw), TS("sub",IMlw), TS("xor",IMw), TS("cmp",IMlw),
2707 };
2708
2709
2710 /*
2711 * Decode table for 0x82 opcodes.
2712 */
2713
2714 const instable_t dis_op82[8] = {
2715
2716 /* [0] */ TNSx("addb",IMlw), TNSx("orb",IMlw), TNSx("adcb",IMlw), TNSx("sbbb",IMlw),
2717 /* [4] */ TNSx("andb",IMlw), TNSx("subb",IMlw), TNSx("xorb",IMlw), TNSx("cmpb",IMlw),
2718 };
2719 /*
2720 * Decode table for 0x83 opcodes.
2721 */
2722
2723 const instable_t dis_op83[8] = {
2724
2725 /* [0] */ TS("add",IMlw), TS("or",IMlw), TS("adc",IMlw), TS("sbb",IMlw),
2726 /* [4] */ TS("and",IMlw), TS("sub",IMlw), TS("xor",IMlw), TS("cmp",IMlw),
2727 };
2728
2729 /*
2730 * Decode table for 0xC0 opcodes.
2731 */
2732
2733 const instable_t dis_opC0[8] = {
2734
2735 /* [0] */ TNS("rolb",MvI), TNS("rorb",MvI), TNS("rclb",MvI), TNS("rcrb",MvI),
2736 /* [4] */ TNS("shlb",MvI), TNS("shrb",MvI), INVALID, TNS("sarb",MvI),
2737 };
2738
2739 /*
2740 * Decode table for 0xD0 opcodes.
2741 */
2742
2743 const instable_t dis_opD0[8] = {
2744
2745 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv),
2746 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv),
2747 };
2748
2749 /*
2750 * Decode table for 0xC1 opcodes.
2751 * 186 instruction set
2752 */
2753
2754 const instable_t dis_opC1[8] = {
2755
2756 /* [0] */ TS("rol",MvI), TS("ror",MvI), TS("rcl",MvI), TS("rcr",MvI),
2757 /* [4] */ TS("shl",MvI), TS("shr",MvI), TS("sal",MvI), TS("sar",MvI),
2758 };
2759
2760 /*
2761 * Decode table for 0xD1 opcodes.
2762 */
2763
2764 const instable_t dis_opD1[8] = {
2765
2766 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv),
2767 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("sal",Mv), TS("sar",Mv),
2768 };
2769
2770
2771 /*
2772 * Decode table for 0xD2 opcodes.
2773 */
2774
2775 const instable_t dis_opD2[8] = {
2776
2777 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv),
2778 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv),
2779 };
2780 /*
2781 * Decode table for 0xD3 opcodes.
2782 */
2783
2784 const instable_t dis_opD3[8] = {
2785
2786 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv),
2787 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("salb",Mv), TS("sar",Mv),
2788 };
2789
2790
2791 /*
2792 * Decode table for 0xF6 opcodes.
2793 */
2794
2795 const instable_t dis_opF6[8] = {
2796
2797 /* [0] */ TNS("testb",IMw), TNS("testb",IMw), TNS("notb",Mw), TNS("negb",Mw),
2798 /* [4] */ TNS("mulb",MA), TNS("imulb",MA), TNS("divb",MA), TNS("idivb",MA),
2799 };
2800
2801
2802 /*
2803 * Decode table for 0xF7 opcodes.
2804 */
2805
2806 const instable_t dis_opF7[8] = {
2807
2808 /* [0] */ TS("test",IMw), TS("test",IMw), TS("not",Mw), TS("neg",Mw),
2809 /* [4] */ TS("mul",MA), TS("imul",MA), TS("div",MA), TS("idiv",MA),
2810 };
2811
2812
2813 /*
2814 * Decode table for 0xFE opcodes.
2815 */
2816
2817 const instable_t dis_opFE[8] = {
2818
2819 /* [0] */ TNS("incb",Mw), TNS("decb",Mw), INVALID, INVALID,
2820 /* [4] */ INVALID, INVALID, INVALID, INVALID,
2821 };
2822 /*
2823 * Decode table for 0xFF opcodes.
2824 */
2825
2826 const instable_t dis_opFF[8] = {
2827
2828 /* [0] */ TS("inc",Mw), TS("dec",Mw), TNSyp("call",INM), TNS("lcall",INM),
2829 /* [4] */ TNSy("jmp",INM), TNS("ljmp",INM), TSp("push",M), INVALID,
2830 };
2831
2832 /* for 287 instructions, which are a mess to decode */
2833
2834 const instable_t dis_opFP1n2[8][8] = {
2835 {
2836 /* bit pattern: 1101 1xxx MODxx xR/M */
2837 /* [0,0] */ TNS("fadds",M), TNS("fmuls",M), TNS("fcoms",M), TNS("fcomps",M),
2838 /* [0,4] */ TNS("fsubs",M), TNS("fsubrs",M), TNS("fdivs",M), TNS("fdivrs",M),
2839 }, {
2840 /* [1,0] */ TNS("flds",M), INVALID, TNS("fsts",M), TNS("fstps",M),
2841 /* [1,4] */ TNSZ("fldenv",M,28), TNSZ("fldcw",M,2), TNSZ("fnstenv",M,28), TNSZ("fnstcw",M,2),
2842 }, {
2843 /* [2,0] */ TNS("fiaddl",M), TNS("fimull",M), TNS("ficoml",M), TNS("ficompl",M),
2844 /* [2,4] */ TNS("fisubl",M), TNS("fisubrl",M), TNS("fidivl",M), TNS("fidivrl",M),
2845 }, {
2846 /* [3,0] */ TNS("fildl",M), TNSZ("tisttpl",M,4), TNS("fistl",M), TNS("fistpl",M),
2847 /* [3,4] */ INVALID, TNSZ("fldt",M,10), INVALID, TNSZ("fstpt",M,10),
2848 }, {
2849 /* [4,0] */ TNSZ("faddl",M,8), TNSZ("fmull",M,8), TNSZ("fcoml",M,8), TNSZ("fcompl",M,8),
2850 /* [4,1] */ TNSZ("fsubl",M,8), TNSZ("fsubrl",M,8), TNSZ("fdivl",M,8), TNSZ("fdivrl",M,8),
2851 }, {
2852 /* [5,0] */ TNSZ("fldl",M,8), TNSZ("fisttpll",M,8), TNSZ("fstl",M,8), TNSZ("fstpl",M,8),
2853 /* [5,4] */ TNSZ("frstor",M,108), INVALID, TNSZ("fnsave",M,108), TNSZ("fnstsw",M,2),
2854 }, {
2855 /* [6,0] */ TNSZ("fiadd",M,2), TNSZ("fimul",M,2), TNSZ("ficom",M,2), TNSZ("ficomp",M,2),
2856 /* [6,4] */ TNSZ("fisub",M,2), TNSZ("fisubr",M,2), TNSZ("fidiv",M,2), TNSZ("fidivr",M,2),
2857 }, {
2858 /* [7,0] */ TNSZ("fild",M,2), TNSZ("fisttp",M,2), TNSZ("fist",M,2), TNSZ("fistp",M,2),
2859 /* [7,4] */ TNSZ("fbld",M,10), TNSZ("fildll",M,8), TNSZ("fbstp",M,10), TNSZ("fistpll",M,8),
2860 } };
2861
2862 const instable_t dis_opFP3[8][8] = {
2863 {
2864 /* bit pattern: 1101 1xxx 11xx xREG */
2865 /* [0,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F),
2866 /* [0,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF),
2867 }, {
2868 /* [1,0] */ TNS("fld",F), TNS("fxch",F), TNS("fnop",NORM), TNS("fstp",F),
2869 /* [1,4] */ INVALID, INVALID, INVALID, INVALID,
2870 }, {
2871 /* [2,0] */ INVALID, INVALID, INVALID, INVALID,
2872 /* [2,4] */ INVALID, TNS("fucompp",NORM), INVALID, INVALID,
2873 }, {
2874 /* [3,0] */ INVALID, INVALID, INVALID, INVALID,
2875 /* [3,4] */ INVALID, INVALID, INVALID, INVALID,
2876 }, {
2877 /* [4,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F),
2878 /* [4,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF),
2879 }, {
2880 /* [5,0] */ TNS("ffree",F), TNS("fxch",F), TNS("fst",F), TNS("fstp",F),
2881 /* [5,4] */ TNS("fucom",F), TNS("fucomp",F), INVALID, INVALID,
2882 }, {
2883 /* [6,0] */ TNS("faddp",FF), TNS("fmulp",FF), TNS("fcomp",F), TNS("fcompp",NORM),
2884 /* [6,4] */ TNS("fsubp",FF), TNS("fsubrp",FF), TNS("fdivp",FF), TNS("fdivrp",FF),
2885 }, {
2886 /* [7,0] */ TNS("ffreep",F), TNS("fxch",F), TNS("fstp",F), TNS("fstp",F),
2887 /* [7,4] */ TNS("fnstsw",M), TNS("fucomip",FFC), TNS("fcomip",FFC), INVALID,
2888 } };
2889
2890 const instable_t dis_opFP4[4][8] = {
2891 {
2892 /* bit pattern: 1101 1001 111x xxxx */
2893 /* [0,0] */ TNS("fchs",NORM), TNS("fabs",NORM), INVALID, INVALID,
2894 /* [0,4] */ TNS("ftst",NORM), TNS("fxam",NORM), TNS("ftstp",NORM), INVALID,
2895 }, {
2896 /* [1,0] */ TNS("fld1",NORM), TNS("fldl2t",NORM), TNS("fldl2e",NORM), TNS("fldpi",NORM),
2897 /* [1,4] */ TNS("fldlg2",NORM), TNS("fldln2",NORM), TNS("fldz",NORM), INVALID,
2898 }, {
2899 /* [2,0] */ TNS("f2xm1",NORM), TNS("fyl2x",NORM), TNS("fptan",NORM), TNS("fpatan",NORM),
2900 /* [2,4] */ TNS("fxtract",NORM), TNS("fprem1",NORM), TNS("fdecstp",NORM), TNS("fincstp",NORM),
2901 }, {
2902 /* [3,0] */ TNS("fprem",NORM), TNS("fyl2xp1",NORM), TNS("fsqrt",NORM), TNS("fsincos",NORM),
2903 /* [3,4] */ TNS("frndint",NORM), TNS("fscale",NORM), TNS("fsin",NORM), TNS("fcos",NORM),
2904 } };
2905
2906 const instable_t dis_opFP5[8] = {
2907 /* bit pattern: 1101 1011 111x xxxx */
2908 /* [0] */ TNS("feni",NORM), TNS("fdisi",NORM), TNS("fnclex",NORM), TNS("fninit",NORM),
2909 /* [4] */ TNS("fsetpm",NORM), TNS("frstpm",NORM), INVALID, INVALID,
2910 };
2911
2912 const instable_t dis_opFP6[8] = {
2913 /* bit pattern: 1101 1011 11yy yxxx */
2914 /* [00] */ TNS("fcmov.nb",FF), TNS("fcmov.ne",FF), TNS("fcmov.nbe",FF), TNS("fcmov.nu",FF),
2915 /* [04] */ INVALID, TNS("fucomi",F), TNS("fcomi",F), INVALID,
2916 };
2917
2918 const instable_t dis_opFP7[8] = {
2919 /* bit pattern: 1101 1010 11yy yxxx */
2920 /* [00] */ TNS("fcmov.b",FF), TNS("fcmov.e",FF), TNS("fcmov.be",FF), TNS("fcmov.u",FF),
2921 /* [04] */ INVALID, INVALID, INVALID, INVALID,
2922 };
2923
2924 /*
2925 * Main decode table for the op codes. The first two nibbles
2926 * will be used as an index into the table. If there is a
2927 * a need to further decode an instruction, the array to be
2928 * referenced is indicated with the other two entries being
2929 * empty.
2930 */
2931
2932 const instable_t dis_distable[16][16] = {
2933 {
2934 /* [0,0] */ TNS("addb",RMw), TS("add",RMw), TNS("addb",MRw), TS("add",MRw),
2935 /* [0,4] */ TNS("addb",IA), TS("add",IA), TSx("push",SEG), TSx("pop",SEG),
2936 /* [0,8] */ TNS("orb",RMw), TS("or",RMw), TNS("orb",MRw), TS("or",MRw),
2937 /* [0,C] */ TNS("orb",IA), TS("or",IA), TSx("push",SEG), IND(dis_op0F),
2938 }, {
2939 /* [1,0] */ TNS("adcb",RMw), TS("adc",RMw), TNS("adcb",MRw), TS("adc",MRw),
2940 /* [1,4] */ TNS("adcb",IA), TS("adc",IA), TSx("push",SEG), TSx("pop",SEG),
2941 /* [1,8] */ TNS("sbbb",RMw), TS("sbb",RMw), TNS("sbbb",MRw), TS("sbb",MRw),
2942 /* [1,C] */ TNS("sbbb",IA), TS("sbb",IA), TSx("push",SEG), TSx("pop",SEG),
2943 }, {
2944 /* [2,0] */ TNS("andb",RMw), TS("and",RMw), TNS("andb",MRw), TS("and",MRw),
2945 /* [2,4] */ TNS("andb",IA), TS("and",IA), TNSx("%es:",OVERRIDE), TNSx("daa",NORM),
2946 /* [2,8] */ TNS("subb",RMw), TS("sub",RMw), TNS("subb",MRw), TS("sub",MRw),
2947 /* [2,C] */ TNS("subb",IA), TS("sub",IA), TNS("%cs:",OVERRIDE), TNSx("das",NORM),
2948 }, {
2949 /* [3,0] */ TNS("xorb",RMw), TS("xor",RMw), TNS("xorb",MRw), TS("xor",MRw),
2950 /* [3,4] */ TNS("xorb",IA), TS("xor",IA), TNSx("%ss:",OVERRIDE), TNSx("aaa",NORM),
2951 /* [3,8] */ TNS("cmpb",RMw), TS("cmp",RMw), TNS("cmpb",MRw), TS("cmp",MRw),
2952 /* [3,C] */ TNS("cmpb",IA), TS("cmp",IA), TNSx("%ds:",OVERRIDE), TNSx("aas",NORM),
2953 }, {
2954 /* [4,0] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R),
2955 /* [4,4] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R),
2956 /* [4,8] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R),
2957 /* [4,C] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R),
2958 }, {
2959 /* [5,0] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R),
2960 /* [5,4] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R),
2961 /* [5,8] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R),
2962 /* [5,C] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R),
2963 }, {
2964 /* [6,0] */ TSZx("pusha",IMPLMEM,28),TSZx("popa",IMPLMEM,28), TSx("bound",RM), TNS("arpl",RMw),
2965 /* [6,4] */ TNS("%fs:",OVERRIDE), TNS("%gs:",OVERRIDE), TNS("data16",DM), TNS("addr16",AM),
2966 /* [6,8] */ TSp("push",I), TS("imul",IMUL), TSp("push",Ib), TS("imul",IMUL),
2967 /* [6,C] */ TNSZ("insb",IMPLMEM,1), TSZ("ins",IMPLMEM,4), TNSZ("outsb",IMPLMEM,1),TSZ("outs",IMPLMEM,4),
2968 }, {
2969 /* [7,0] */ TNSy("jo",BD), TNSy("jno",BD), TNSy("jb",BD), TNSy("jae",BD),
2970 /* [7,4] */ TNSy("je",BD), TNSy("jne",BD), TNSy("jbe",BD), TNSy("ja",BD),
2971 /* [7,8] */ TNSy("js",BD), TNSy("jns",BD), TNSy("jp",BD), TNSy("jnp",BD),
2972 /* [7,C] */ TNSy("jl",BD), TNSy("jge",BD), TNSy("jle",BD), TNSy("jg",BD),
2973 }, {
2974 /* [8,0] */ IND(dis_op80), IND(dis_op81), INDx(dis_op82), IND(dis_op83),
2975 /* [8,4] */ TNS("testb",RMw), TS("test",RMw), TNS("xchgb",RMw), TS("xchg",RMw),
2976 /* [8,8] */ TNS("movb",RMw), TS("mov",RMw), TNS("movb",MRw), TS("mov",MRw),
2977 /* [8,C] */ TNS("movw",SM), TS("lea",MR), TNS("movw",MS), TSp("pop",M),
2978 }, {
2979 /* [9,0] */ TNS("nop",NORM), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA),
2980 /* [9,4] */ TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA),
2981 /* [9,8] */ TNS("cXtX",CBW), TNS("cXtX",CWD), TNSx("lcall",SO), TNS("fwait",NORM),
2982 /* [9,C] */ TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4), TNS("sahf",NORM), TNS("lahf",NORM),
2983 }, {
2984 /* [A,0] */ TNS("movb",OA), TS("mov",OA), TNS("movb",AO), TS("mov",AO),
2985 /* [A,4] */ TNSZ("movsb",SD,1), TS("movs",SD), TNSZ("cmpsb",SD,1), TS("cmps",SD),
2986 /* [A,8] */ TNS("testb",IA), TS("test",IA), TNS("stosb",AD), TS("stos",AD),
2987 /* [A,C] */ TNS("lodsb",SA), TS("lods",SA), TNS("scasb",AD), TS("scas",AD),
2988 }, {
2989 /* [B,0] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR),
2990 /* [B,4] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR),
2991 /* [B,8] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR),
2992 /* [B,C] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR),
2993 }, {
2994 /* [C,0] */ IND(dis_opC0), IND(dis_opC1), TNSyp("ret",RET), TNSyp("ret",NORM),
2995 /* [C,4] */ TNSx("les",MR), TNSx("lds",MR), TNS("movb",IMw), TS("mov",IMw),
2996 /* [C,8] */ TNSyp("enter",ENTER), TNSyp("leave",NORM), TNS("lret",RET), TNS("lret",NORM),
2997 /* [C,C] */ TNS("int",INT3), TNS("int",INTx), TNSx("into",NORM), TNS("iret",NORM),
2998 }, {
2999 /* [D,0] */ IND(dis_opD0), IND(dis_opD1), IND(dis_opD2), IND(dis_opD3),
3000 /* [D,4] */ TNSx("aam",U), TNSx("aad",U), TNSx("falc",NORM), TNSZ("xlat",IMPLMEM,1),
3001
3002 /* 287 instructions. Note that although the indirect field */
3003 /* indicates opFP1n2 for further decoding, this is not necessarily */
3004 /* the case since the opFP arrays are not partitioned according to key1 */
3005 /* and key2. opFP1n2 is given only to indicate that we haven't */
3006 /* finished decoding the instruction. */
3007 /* [D,8] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2),
3008 /* [D,C] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2),
3009 }, {
3010 /* [E,0] */ TNSy("loopnz",BD), TNSy("loopz",BD), TNSy("loop",BD), TNSy("jcxz",BD),
3011 /* [E,4] */ TNS("inb",P), TS("in",P), TNS("outb",P), TS("out",P),
3012 /* [E,8] */ TNSyp("call",D), TNSy("jmp",D), TNSx("ljmp",SO), TNSy("jmp",BD),
3013 /* [E,C] */ TNS("inb",V), TS("in",V), TNS("outb",V), TS("out",V),
3014 }, {
3015 /* [F,0] */ TNS("lock",LOCK), TNS("icebp", NORM), TNS("repnz",PREFIX), TNS("repz",PREFIX),
3016 /* [F,4] */ TNS("hlt",NORM), TNS("cmc",NORM), IND(dis_opF6), IND(dis_opF7),
3017 /* [F,8] */ TNS("clc",NORM), TNS("stc",NORM), TNS("cli",NORM), TNS("sti",NORM),
3018 /* [F,C] */ TNS("cld",NORM), TNS("std",NORM), IND(dis_opFE), IND(dis_opFF),
3019 } };
3020
3021 /* END CSTYLED */
3022
3023 /*
3024 * common functions to decode and disassemble an x86 or amd64 instruction
3025 */
3026
3027 /*
3028 * These are the individual fields of a REX prefix. Note that a REX
3029 * prefix with none of these set is still needed to:
3030 * - use the MOVSXD (sign extend 32 to 64 bits) instruction
3031 * - access the %sil, %dil, %bpl, %spl registers
3032 */
3033 #define REX_W 0x08 /* 64 bit operand size when set */
3034 #define REX_R 0x04 /* high order bit extension of ModRM reg field */
3035 #define REX_X 0x02 /* high order bit extension of SIB index field */
3036 #define REX_B 0x01 /* extends ModRM r_m, SIB base, or opcode reg */
3037
3038 /*
3039 * These are the individual fields of a VEX/EVEX prefix.
3040 */
3041 #define VEX_R 0x08 /* REX.R in 1's complement form */
3042 #define VEX_X 0x04 /* REX.X in 1's complement form */
3043 #define VEX_B 0x02 /* REX.B in 1's complement form */
3044
3045 /* Additional EVEX prefix definitions */
3046 #define EVEX_R 0x01 /* REX.R' in 1's complement form */
3047 #define EVEX_OPREG_MASK 0x7 /* bit mask for selecting opmask register number */
3048 #define EVEX_ZERO_MASK 0x80 /* bit mask for selecting zeroing */
3049
3050 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */
3051 #define VEX_L 0x04
3052 #define EVEX_B 0x01 /* Embedded Broadcast, RC, SAE context */
3053 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector, 2: 512-bit */
3054 #define EVEX_L 0x06 /* bit mask for EVEX.L'L vector length/RC */
3055 #define VEX_W 0x08 /* opcode specific, use like REX.W */
3056 #define VEX_m 0x1F /* VEX m-mmmm field */
3057 #define EVEX_m 0x3 /* EVEX mm field */
3058 #define VEX_v 0x78 /* VEX/EVEX register specifier */
3059 #define VEX_p 0x03 /* VEX pp field, opcode extension */
3060 #define EVEX_V 0x8 /* EVEX.V' field, register extension */
3061
3062 /* VEX m-mmmm field, only used by three bytes prefix */
3063 #define VEX_m_0F 0x01 /* implied 0F leading opcode byte */
3064 #define VEX_m_0F38 0x02 /* implied 0F 38 leading opcode byte */
3065 #define VEX_m_0F3A 0x03 /* implied 0F 3A leading opcode byte */
3066
3067 /* VEX pp field, providing equivalent functionality of a SIMD prefix */
3068 #define VEX_p_66 0x01
3069 #define VEX_p_F3 0x02
3070 #define VEX_p_F2 0x03
3071
3072 /*
3073 * Even in 64 bit mode, usually only 4 byte immediate operands are supported.
3074 */
3075 static int isize[] = {1, 2, 4, 4};
3076 static int isize64[] = {1, 2, 4, 8};
3077
3078 /*
3079 * Just a bunch of useful macros.
3080 */
3081 #define WBIT(x) (x & 0x1) /* to get w bit */
3082 #define REGNO(x) (x & 0x7) /* to get 3 bit register */
3083 #define VBIT(x) ((x)>>1 & 0x1) /* to get 'v' bit */
3084 #define OPSIZE(osize, wbit) ((wbit) ? isize[osize] : 1)
3085 #define OPSIZE64(osize, wbit) ((wbit) ? isize64[osize] : 1)
3086
3087 #define REG_ONLY 3 /* mode to indicate a register operand (not memory) */
3088
3089 #define BYTE_OPND 0 /* w-bit value indicating byte register */
3090 #define LONG_OPND 1 /* w-bit value indicating opnd_size register */
3091 #define MM_OPND 2 /* "value" used to indicate a mmx reg */
3092 #define XMM_OPND 3 /* "value" used to indicate a xmm reg */
3093 #define SEG_OPND 4 /* "value" used to indicate a segment reg */
3094 #define CONTROL_OPND 5 /* "value" used to indicate a control reg */
3095 #define DEBUG_OPND 6 /* "value" used to indicate a debug reg */
3096 #define TEST_OPND 7 /* "value" used to indicate a test reg */
3097 #define WORD_OPND 8 /* w-bit value indicating word size reg */
3098 #define YMM_OPND 9 /* "value" used to indicate a ymm reg */
3099 #define KOPMASK_OPND 10 /* "value" used to indicate an opmask reg */
3100 #define ZMM_OPND 11 /* "value" used to indicate a zmm reg */
3101
3102 /*
3103 * The AVX2 gather instructions are a bit of a mess. While there's a pattern,
3104 * there's not really a consistent scheme that we can use to know what the mode
3105 * is supposed to be for a given type. Various instructions, like VPGATHERDD,
3106 * always match the value of VEX_L. Other instructions like VPGATHERDQ, have
3107 * some registers match VEX_L, but the VSIB is always XMM.
3108 *
3109 * The simplest way to deal with this is to just define a table based on the
3110 * instruction opcodes, which are 0x90-0x93, so we subtract 0x90 to index into
3111 * them.
3112 *
3113 * We further have to subdivide this based on the value of VEX_W and the value
3114 * of VEX_L. The array is constructed to be indexed as:
3115 * [opcode - 0x90][VEX_W][VEX_L].
3116 */
3117 /* w = 0, 0x90 */
3118 typedef struct dis_gather_regs {
3119 uint_t dgr_arg0; /* src reg */
3120 uint_t dgr_arg1; /* vsib reg */
3121 uint_t dgr_arg2; /* dst reg */
3122 char *dgr_suffix; /* suffix to append */
3123 } dis_gather_regs_t;
3124
3125 static dis_gather_regs_t dis_vgather[4][2][2] = {
3126 {
3127 /* op 0x90, W.0 */
3128 {
3129 { XMM_OPND, XMM_OPND, XMM_OPND, "d" },
3130 { YMM_OPND, YMM_OPND, YMM_OPND, "d" }
3131 },
3132 /* op 0x90, W.1 */
3133 {
3134 { XMM_OPND, XMM_OPND, XMM_OPND, "q" },
3135 { YMM_OPND, XMM_OPND, YMM_OPND, "q" }
3136 }
3137 },
3138 {
3139 /* op 0x91, W.0 */
3140 {
3141 { XMM_OPND, XMM_OPND, XMM_OPND, "d" },
3142 { XMM_OPND, YMM_OPND, XMM_OPND, "d" },
3143 },
3144 /* op 0x91, W.1 */
3145 {
3146 { XMM_OPND, XMM_OPND, XMM_OPND, "q" },
3147 { YMM_OPND, YMM_OPND, YMM_OPND, "q" },
3148 }
3149 },
3150 {
3151 /* op 0x92, W.0 */
3152 {
3153 { XMM_OPND, XMM_OPND, XMM_OPND, "s" },
3154 { YMM_OPND, YMM_OPND, YMM_OPND, "s" }
3155 },
3156 /* op 0x92, W.1 */
3157 {
3158 { XMM_OPND, XMM_OPND, XMM_OPND, "d" },
3159 { YMM_OPND, XMM_OPND, YMM_OPND, "d" }
3160 }
3161 },
3162 {
3163 /* op 0x93, W.0 */
3164 {
3165 { XMM_OPND, XMM_OPND, XMM_OPND, "s" },
3166 { XMM_OPND, YMM_OPND, XMM_OPND, "s" }
3167 },
3168 /* op 0x93, W.1 */
3169 {
3170 { XMM_OPND, XMM_OPND, XMM_OPND, "d" },
3171 { YMM_OPND, YMM_OPND, YMM_OPND, "d" }
3172 }
3173 }
3174 };
3175
3176 /*
3177 * Get the next byte and separate the op code into the high and low nibbles.
3178 */
3179 static int
dtrace_get_opcode(dis86_t * x,uint_t * high,uint_t * low)3180 dtrace_get_opcode(dis86_t *x, uint_t *high, uint_t *low)
3181 {
3182 int byte;
3183
3184 /*
3185 * x86 instructions have a maximum length of 15 bytes. Bail out if
3186 * we try to read more.
3187 */
3188 if (x->d86_len >= 15)
3189 return (x->d86_error = 1);
3190
3191 if (x->d86_error)
3192 return (1);
3193 byte = x->d86_get_byte(x->d86_data);
3194 if (byte < 0)
3195 return (x->d86_error = 1);
3196 x->d86_bytes[x->d86_len++] = byte;
3197 *low = byte & 0xf; /* ----xxxx low 4 bits */
3198 *high = byte >> 4 & 0xf; /* xxxx---- bits 7 to 4 */
3199 return (0);
3200 }
3201
3202 /*
3203 * Get and decode an SIB (scaled index base) byte
3204 */
3205 static void
dtrace_get_SIB(dis86_t * x,uint_t * ss,uint_t * index,uint_t * base)3206 dtrace_get_SIB(dis86_t *x, uint_t *ss, uint_t *index, uint_t *base)
3207 {
3208 int byte;
3209
3210 if (x->d86_error)
3211 return;
3212
3213 byte = x->d86_get_byte(x->d86_data);
3214 if (byte < 0) {
3215 x->d86_error = 1;
3216 return;
3217 }
3218 x->d86_bytes[x->d86_len++] = byte;
3219
3220 *base = byte & 0x7;
3221 *index = (byte >> 3) & 0x7;
3222 *ss = (byte >> 6) & 0x3;
3223 }
3224
3225 /*
3226 * Get the byte following the op code and separate it into the
3227 * mode, register, and r/m fields.
3228 */
3229 static void
dtrace_get_modrm(dis86_t * x,uint_t * mode,uint_t * reg,uint_t * r_m)3230 dtrace_get_modrm(dis86_t *x, uint_t *mode, uint_t *reg, uint_t *r_m)
3231 {
3232 if (x->d86_got_modrm == 0) {
3233 if (x->d86_rmindex == -1)
3234 x->d86_rmindex = x->d86_len;
3235 dtrace_get_SIB(x, mode, reg, r_m);
3236 x->d86_got_modrm = 1;
3237 }
3238 }
3239
3240 /*
3241 * Adjust register selection based on any REX prefix bits present.
3242 */
3243 /*ARGSUSED*/
3244 static void
dtrace_rex_adjust(uint_t rex_prefix,uint_t mode,uint_t * reg,uint_t * r_m)3245 dtrace_rex_adjust(uint_t rex_prefix, uint_t mode, uint_t *reg, uint_t *r_m)
3246 {
3247 if (reg != NULL && r_m == NULL) {
3248 if (rex_prefix & REX_B)
3249 *reg += 8;
3250 } else {
3251 if (reg != NULL && (REX_R & rex_prefix) != 0)
3252 *reg += 8;
3253 if (r_m != NULL && (REX_B & rex_prefix) != 0)
3254 *r_m += 8;
3255 }
3256 }
3257
3258 /*
3259 * Adjust register selection based on any VEX prefix bits present.
3260 * Notes: VEX.R, VEX.X and VEX.B use the inverted form compared with REX prefix
3261 */
3262 /*ARGSUSED*/
3263 static void
dtrace_vex_adjust(uint_t vex_byte1,uint_t mode,uint_t * reg,uint_t * r_m)3264 dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m)
3265 {
3266 if (reg != NULL && r_m == NULL) {
3267 if (!(vex_byte1 & VEX_B))
3268 *reg += 8;
3269 } else {
3270 if (reg != NULL && ((VEX_R & vex_byte1) == 0))
3271 *reg += 8;
3272 if (r_m != NULL && ((VEX_B & vex_byte1) == 0))
3273 *r_m += 8;
3274 }
3275 }
3276
3277 /*
3278 * Adjust the instruction mnemonic with the appropriate suffix.
3279 */
3280 /* ARGSUSED */
3281 static void
dtrace_evex_mnem_adjust(dis86_t * x,const instable_t * dp,uint_t vex_W,uint_t evex_byte2)3282 dtrace_evex_mnem_adjust(dis86_t *x, const instable_t *dp, uint_t vex_W,
3283 uint_t evex_byte2)
3284 {
3285 #ifdef DIS_TEXT
3286 if (dp == &dis_opEVEX660F[0x7f] || /* vmovdqa */
3287 dp == &dis_opEVEX660F[0x6f]) {
3288 (void) strlcat(x->d86_mnem, vex_W != 0 ? "64" : "32",
3289 OPLEN);
3290 }
3291
3292 if (dp == &dis_opEVEXF20F[0x7f] || /* vmovdqu */
3293 dp == &dis_opEVEXF20F[0x6f] ||
3294 dp == &dis_opEVEXF30F[0x7f] ||
3295 dp == &dis_opEVEXF30F[0x6f]) {
3296 switch (evex_byte2 & 0x81) {
3297 case 0x0:
3298 (void) strlcat(x->d86_mnem, "32", OPLEN);
3299 break;
3300 case 0x1:
3301 (void) strlcat(x->d86_mnem, "8", OPLEN);
3302 break;
3303 case 0x80:
3304 (void) strlcat(x->d86_mnem, "64", OPLEN);
3305 break;
3306 case 0x81:
3307 (void) strlcat(x->d86_mnem, "16", OPLEN);
3308 break;
3309 }
3310 }
3311
3312 if (dp->it_avxsuf == AVS5Q) {
3313 (void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d",
3314 OPLEN);
3315 } else if (dp->it_avxsuf == AVS5D) {
3316 (void) strlcat(x->d86_mnem, vex_W != 0 ? "s" : "d",
3317 OPLEN);
3318 } else if (dp->it_avxsuf == AVS5B) {
3319 (void) strlcat(x->d86_mnem, vex_W != 0 ? "w" : "b",
3320 OPLEN);
3321 }
3322 #endif
3323 }
3324
3325 /*
3326 * The following three functions adjust the register selection based on any
3327 * EVEX prefix bits present. See Intel 64 and IA-32 Architectures Software
3328 * Developer’s Manual Volume 2 (IASDv2), section 2.6.1 Table 2-30 and
3329 * section 2.6.2 Table 2-31.
3330 */
3331 static void
dtrace_evex_adjust_reg(uint_t evex_byte1,uint_t * reg)3332 dtrace_evex_adjust_reg(uint_t evex_byte1, uint_t *reg)
3333 {
3334 if (reg != NULL) {
3335 if ((VEX_R & evex_byte1) == 0) {
3336 *reg += 8;
3337 }
3338 if ((EVEX_R & evex_byte1) == 0) {
3339 *reg += 16;
3340 }
3341 }
3342 }
3343
3344 static void
dtrace_evex_adjust_rm(uint_t evex_byte1,uint_t * r_m)3345 dtrace_evex_adjust_rm(uint_t evex_byte1, uint_t *r_m)
3346 {
3347 if (r_m != NULL) {
3348 if ((VEX_B & evex_byte1) == 0) {
3349 *r_m += 8;
3350 }
3351 if ((VEX_X & evex_byte1) == 0) {
3352 *r_m += 16;
3353 }
3354 }
3355 }
3356
3357 /*
3358 * Use evex_L to set wbit. See IASDv2 Section 2.6.10 and Table 2-36.
3359 */
3360 static void
dtrace_evex_adjust_reg_name(uint_t evex_L,uint_t * wbitp)3361 dtrace_evex_adjust_reg_name(uint_t evex_L, uint_t *wbitp)
3362 {
3363 switch (evex_L) {
3364 case 0x0:
3365 *wbitp = XMM_OPND;
3366 break;
3367 case 0x1:
3368 *wbitp = YMM_OPND;
3369 break;
3370 case 0x2:
3371 *wbitp = ZMM_OPND;
3372 break;
3373 }
3374 }
3375
3376 typedef enum {
3377 /*
3378 * Indicates that this follows the normal full memory disp8*n behavior
3379 * and that there is no embedded broadcast.
3380 */
3381 EVEX_DISP8_MEM,
3382 /*
3383 * Indicates that this needs to use the compressed displacement affected
3384 * by embedded broadcast table. The first of these is for full tuples,
3385 * which is the more common case. The second group is for half tuples.
3386 */
3387 EVEX_DISP8_BCAST,
3388 EVEX_DISP8_BCAST_HALF,
3389
3390 /*
3391 * Indicates that this is an 8/16-bit Tuple1 Scalar. The 32/64-bit share
3392 * T1S and use EVEX.W to determine what multiples to use. Strictly
3393 * speaking the table has the 8/16-bit as different cases, but we find
3394 * that they generally are distinguished for what we support based on W,
3395 * so we cheat and use that for cases for not until this proves to not
3396 * work.
3397 */
3398 EVEX_DISP8_T1S_8B,
3399 EVEX_DISP8_T1S,
3400 /*
3401 * Tuple1 Fixed type which ignores EVEX.W and instead is based upon a
3402 * fixed, expected type.
3403 */
3404 EVEX_DISP8_T1F32,
3405 EVEX_DISP8_T1F64,
3406 /*
3407 * T2 and T4 are Tuple2 and Tuple4 respectively. They both change based
3408 * upon EVEX.W.
3409 */
3410 EVEX_DISP8_T2,
3411 EVEX_DISP8_T4,
3412 /*
3413 * Tuple8, which only really acts upon 32-bit broadcasts.
3414 */
3415 EVEX_DISP8_T8,
3416 /*
3417 * (H)alf memory, (Q)uarter memory, and (E)ighth memory. These ignore
3418 * the input size and EVEX.W. They just are fixed factors based on the
3419 * vector length.
3420 */
3421 EVEX_DISP8_HMEM,
3422 EVEX_DISP8_QMEM,
3423 EVEX_DISP8_EMEM,
3424 /*
3425 * This is the Mem128 type, which is used for various shift counts. It
3426 * ignores the input size and EVEX.W.
3427 */
3428 EVEX_DISP8_MEM128,
3429 /*
3430 * This seems like a special case for VMOVDUP. It has its own
3431 * multiplication pattern.
3432 */
3433 EVEX_DISP8_MOVDUP
3434 } evex_disp8_tuple_type_t;
3435
3436 typedef struct {
3437 evex_disp8_tuple_type_t ed8_type;
3438 uint_t ed8_vl;
3439 uint_t ed8_evex_b;
3440 uint_t ed8_evex_w;
3441 } evex_disp8_adj_t;
3442
3443 /*
3444 * Adjust operand value for disp8*N immediate. See IASDv2 Section 2.7.5
3445 * (December 2023).
3446 */
3447 static void
dtrace_evex_adjust_disp8_n(dis86_t * x,uint_t opindex,uint_t modrm,evex_disp8_tuple_type_t type,uint_t evex_L,uint_t evex_B,uint_t evex_W)3448 dtrace_evex_adjust_disp8_n(dis86_t *x, uint_t opindex, uint_t modrm,
3449 evex_disp8_tuple_type_t type, uint_t evex_L, uint_t evex_B, uint_t evex_W)
3450 {
3451 uint8_t mult[3];
3452 d86opnd_t *opnd = &x->d86_opnd[opindex];
3453
3454 if (x->d86_error)
3455 return;
3456
3457 /* Check disp8 bit in the ModR/M byte */
3458 if ((modrm & 0x80) == 0x80)
3459 return;
3460
3461 switch (type) {
3462 case EVEX_DISP8_MEM:
3463 mult[0] = 16;
3464 mult[1] = 32;
3465 mult[2] = 64;
3466 break;
3467 case EVEX_DISP8_BCAST:
3468 if (evex_B != 0) {
3469 if (evex_W != 0) {
3470 mult[0] = 8;
3471 mult[1] = 8;
3472 mult[2] = 8;
3473 } else {
3474 mult[0] = 4;
3475 mult[1] = 4;
3476 mult[2] = 4;
3477 }
3478 } else {
3479 mult[0] = 16;
3480 mult[1] = 32;
3481 mult[2] = 64;
3482 }
3483 break;
3484 case EVEX_DISP8_BCAST_HALF:
3485 if (evex_W != 0) {
3486 x->d86_error = 1;
3487 return;
3488 }
3489 if (evex_B != 0) {
3490 mult[0] = 4;
3491 mult[1] = 4;
3492 mult[2] = 4;
3493 } else {
3494 mult[0] = 8;
3495 mult[1] = 16;
3496 mult[2] = 32;
3497 }
3498 break;
3499 case EVEX_DISP8_T1S_8B:
3500 if (evex_W != 0) {
3501 mult[0] = 2;
3502 mult[1] = 2;
3503 mult[2] = 2;
3504 } else {
3505 mult[0] = 1;
3506 mult[1] = 1;
3507 mult[2] = 1;
3508 }
3509 break;
3510 case EVEX_DISP8_T1S:
3511 if (evex_W != 0) {
3512 mult[0] = 4;
3513 mult[1] = 4;
3514 mult[2] = 4;
3515 } else {
3516 mult[0] = 8;
3517 mult[1] = 8;
3518 mult[2] = 8;
3519 }
3520 break;
3521 case EVEX_DISP8_T1F32:
3522 mult[0] = 4;
3523 mult[1] = 4;
3524 mult[2] = 4;
3525 break;
3526 case EVEX_DISP8_T1F64:
3527 mult[0] = 8;
3528 mult[1] = 8;
3529 mult[2] = 8;
3530 break;
3531 case EVEX_DISP8_T2:
3532 if (evex_W != 0) {
3533 mult[0] = 8;
3534 mult[1] = 8;
3535 mult[2] = 8;
3536 } else {
3537 mult[0] = 16;
3538 mult[1] = 16;
3539 mult[2] = 16;
3540 }
3541 break;
3542 case EVEX_DISP8_T4:
3543 if (evex_W != 0) {
3544 mult[0] = 16;
3545 mult[1] = 16;
3546 mult[2] = 16;
3547 } else {
3548 mult[0] = 32;
3549 mult[1] = 32;
3550 mult[2] = 32;
3551 }
3552 break;
3553 case EVEX_DISP8_T8:
3554 if (evex_W != 0) {
3555 x->d86_error = 1;
3556 return;
3557 }
3558 mult[0] = 32;
3559 mult[1] = 32;
3560 mult[2] = 32;
3561 break;
3562 case EVEX_DISP8_HMEM:
3563 mult[0] = 8;
3564 mult[1] = 16;
3565 mult[2] = 32;
3566 break;
3567 case EVEX_DISP8_QMEM:
3568 mult[0] = 4;
3569 mult[1] = 8;
3570 mult[2] = 16;
3571 break;
3572 case EVEX_DISP8_EMEM:
3573 mult[0] = 2;
3574 mult[1] = 4;
3575 mult[2] = 8;
3576 break;
3577 case EVEX_DISP8_MEM128:
3578 mult[0] = 16;
3579 mult[1] = 16;
3580 mult[2] = 16;
3581 break;
3582 case EVEX_DISP8_MOVDUP:
3583 mult[0] = 8;
3584 mult[1] = 32;
3585 mult[2] = 64;
3586 break;
3587 }
3588
3589 opnd->d86_value *= mult[evex_L];
3590 }
3591
3592 /*
3593 * Adjust target for opmask and zeroing. See IASDv2 Section 2.6.1 Table 2-30.
3594 */
3595 static void
dtrace_evex_adjust_z_opmask(dis86_t * x,uint_t tgtop,uint_t evex_byte3)3596 dtrace_evex_adjust_z_opmask(dis86_t *x, uint_t tgtop, uint_t evex_byte3)
3597 {
3598 #ifdef DIS_TEXT
3599 char *opnd = x->d86_opnd[tgtop].d86_opnd;
3600 int opmask_reg = evex_byte3 & EVEX_OPREG_MASK;
3601 #endif
3602 if (x->d86_error)
3603 return;
3604
3605 #ifdef DIS_TEXT
3606 if (opmask_reg != 0) {
3607 /* Append the opmask register to operand 1 */
3608 (void) strlcat(opnd, "{", OPLEN);
3609 (void) strlcat(opnd, dis_KOPMASKREG[opmask_reg], OPLEN);
3610 (void) strlcat(opnd, "}", OPLEN);
3611 }
3612 if ((evex_byte3 & EVEX_ZERO_MASK) != 0) {
3613 /* Append the 'zeroing' modifier to operand 1 */
3614 (void) strlcat(opnd, "{z}", OPLEN);
3615 }
3616 #endif /* DIS_TEXT */
3617 }
3618
3619 /*
3620 * Adjust the target for broadcast mode. This uses the GNU syntax for
3621 * broadcasting of {1toX}. The EVEX W bit determines whether we have a 32-bit or
3622 * 64-bit target that we're broadcasting to. Once we know that, then the
3623 * register length determines the ratio.
3624 */
3625 static void
dtrace_evex_adjust_bcast(dis86_t * x,uint_t tgtop,uint_t vex_W,uint_t wbit,uint_t evex_b)3626 dtrace_evex_adjust_bcast(dis86_t *x, uint_t tgtop, uint_t vex_W, uint_t wbit,
3627 uint_t evex_b)
3628 {
3629 #ifdef DIS_TEXT
3630 char *opnd = x->d86_opnd[tgtop].d86_opnd;
3631 const char *bcast;
3632 #endif
3633 if (x->d86_error || evex_b == 0)
3634 return;
3635
3636 /*
3637 * vex_W tells us whether this is a 32-bit or 64-bit broadcast. The
3638 * ratio then assumes a full tuple right now and therefore this is just
3639 * vector / size.
3640 */
3641 switch (wbit) {
3642 case XMM_OPND:
3643 #ifdef DIS_TEXT
3644 bcast = vex_W == 0 ? "4" : "2";
3645 #endif
3646 break;
3647 case YMM_OPND:
3648 #ifdef DIS_TEXT
3649 bcast = vex_W == 0 ? "8" : "4";
3650 #endif
3651 break;
3652 case ZMM_OPND:
3653 #ifdef DIS_TEXT
3654 bcast = vex_W == 0 ? "16" : "8";
3655 #endif
3656 break;
3657 default:
3658 x->d86_error = 1;
3659 return;
3660 }
3661
3662 #ifdef DIS_TEXT
3663 (void) strlcat(opnd, "{1to", OPLEN);
3664 (void) strlcat(opnd, bcast, OPLEN);
3665 (void) strlcat(opnd, "}", OPLEN);
3666 #endif /* DIS_TEXT */
3667 }
3668
3669 /*
3670 * Get an immediate operand of the given size, with sign extension.
3671 */
3672 static void
dtrace_imm_opnd(dis86_t * x,int wbit,int size,int opindex)3673 dtrace_imm_opnd(dis86_t *x, int wbit, int size, int opindex)
3674 {
3675 int i;
3676 int byte;
3677 int valsize;
3678
3679 if (x->d86_numopnds < opindex + 1)
3680 x->d86_numopnds = opindex + 1;
3681
3682 switch (wbit) {
3683 case BYTE_OPND:
3684 valsize = 1;
3685 break;
3686 case LONG_OPND:
3687 if (x->d86_opnd_size == SIZE16)
3688 valsize = 2;
3689 else if (x->d86_opnd_size == SIZE32)
3690 valsize = 4;
3691 else
3692 valsize = 8;
3693 break;
3694 case MM_OPND:
3695 case XMM_OPND:
3696 case YMM_OPND:
3697 case ZMM_OPND:
3698 case SEG_OPND:
3699 case CONTROL_OPND:
3700 case DEBUG_OPND:
3701 case TEST_OPND:
3702 valsize = size;
3703 break;
3704 case WORD_OPND:
3705 valsize = 2;
3706 break;
3707 }
3708 if (valsize < size)
3709 valsize = size;
3710
3711 if (x->d86_error)
3712 return;
3713 x->d86_opnd[opindex].d86_value = 0;
3714 for (i = 0; i < size; ++i) {
3715 byte = x->d86_get_byte(x->d86_data);
3716 if (byte < 0) {
3717 x->d86_error = 1;
3718 return;
3719 }
3720 x->d86_bytes[x->d86_len++] = byte;
3721 x->d86_opnd[opindex].d86_value |= (uint64_t)byte << (i * 8);
3722 }
3723 /* Do sign extension */
3724 if (x->d86_bytes[x->d86_len - 1] & 0x80) {
3725 for (; i < sizeof (uint64_t); i++)
3726 x->d86_opnd[opindex].d86_value |=
3727 (uint64_t)0xff << (i * 8);
3728 }
3729 #ifdef DIS_TEXT
3730 x->d86_opnd[opindex].d86_mode = MODE_SIGNED;
3731 x->d86_opnd[opindex].d86_value_size = valsize;
3732 x->d86_imm_bytes += size;
3733 #endif
3734 }
3735
3736 /*
3737 * Get an ip relative operand of the given size, with sign extension.
3738 */
3739 static void
dtrace_disp_opnd(dis86_t * x,int wbit,int size,int opindex)3740 dtrace_disp_opnd(dis86_t *x, int wbit, int size, int opindex)
3741 {
3742 dtrace_imm_opnd(x, wbit, size, opindex);
3743 #ifdef DIS_TEXT
3744 x->d86_opnd[opindex].d86_mode = MODE_IPREL;
3745 #endif
3746 }
3747
3748 /*
3749 * Check to see if there is a segment override prefix pending.
3750 * If so, print it in the current 'operand' location and set
3751 * the override flag back to false.
3752 */
3753 /*ARGSUSED*/
3754 static void
dtrace_check_override(dis86_t * x,int opindex)3755 dtrace_check_override(dis86_t *x, int opindex)
3756 {
3757 #ifdef DIS_TEXT
3758 if (x->d86_seg_prefix) {
3759 (void) strlcat(x->d86_opnd[opindex].d86_prefix,
3760 x->d86_seg_prefix, PFIXLEN);
3761 }
3762 #endif
3763 x->d86_seg_prefix = NULL;
3764 }
3765
3766
3767 /*
3768 * Process a single instruction Register or Memory operand.
3769 *
3770 * mode = addressing mode from ModRM byte
3771 * r_m = r_m (or reg if mode == 3) field from ModRM byte
3772 * wbit = indicates which register (8bit, 16bit, ... MMX, etc.) set to use.
3773 * o = index of operand that we are processing (0, 1 or 2)
3774 *
3775 * the value of reg or r_m must have already been adjusted for any REX prefix.
3776 */
3777 /*ARGSUSED*/
3778 static void
dtrace_get_operand(dis86_t * x,uint_t mode,uint_t r_m,int wbit,int opindex)3779 dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex)
3780 {
3781 int have_SIB = 0; /* flag presence of scale-index-byte */
3782 uint_t ss; /* scale-factor from opcode */
3783 uint_t index; /* index register number */
3784 uint_t base; /* base register number */
3785 int dispsize; /* size of displacement in bytes */
3786 #ifdef DIS_TEXT
3787 char *opnd = x->d86_opnd[opindex].d86_opnd;
3788 #endif
3789
3790 if (x->d86_numopnds < opindex + 1)
3791 x->d86_numopnds = opindex + 1;
3792
3793 if (x->d86_error)
3794 return;
3795
3796 /*
3797 * first handle a simple register
3798 */
3799 if (mode == REG_ONLY) {
3800 #ifdef DIS_TEXT
3801 switch (wbit) {
3802 case MM_OPND:
3803 (void) strlcat(opnd, dis_MMREG[r_m], OPLEN);
3804 break;
3805 case XMM_OPND:
3806 (void) strlcat(opnd, dis_XMMREG[r_m], OPLEN);
3807 break;
3808 case YMM_OPND:
3809 (void) strlcat(opnd, dis_YMMREG[r_m], OPLEN);
3810 break;
3811 case ZMM_OPND:
3812 (void) strlcat(opnd, dis_ZMMREG[r_m], OPLEN);
3813 break;
3814 case KOPMASK_OPND:
3815 (void) strlcat(opnd, dis_KOPMASKREG[r_m], OPLEN);
3816 break;
3817 case SEG_OPND:
3818 (void) strlcat(opnd, dis_SEGREG[r_m], OPLEN);
3819 break;
3820 case CONTROL_OPND:
3821 (void) strlcat(opnd, dis_CONTROLREG[r_m], OPLEN);
3822 break;
3823 case DEBUG_OPND:
3824 (void) strlcat(opnd, dis_DEBUGREG[r_m], OPLEN);
3825 break;
3826 case TEST_OPND:
3827 (void) strlcat(opnd, dis_TESTREG[r_m], OPLEN);
3828 break;
3829 case BYTE_OPND:
3830 if (x->d86_rex_prefix == 0)
3831 (void) strlcat(opnd, dis_REG8[r_m], OPLEN);
3832 else
3833 (void) strlcat(opnd, dis_REG8_REX[r_m], OPLEN);
3834 break;
3835 case WORD_OPND:
3836 (void) strlcat(opnd, dis_REG16[r_m], OPLEN);
3837 break;
3838 case LONG_OPND:
3839 if (x->d86_opnd_size == SIZE16)
3840 (void) strlcat(opnd, dis_REG16[r_m], OPLEN);
3841 else if (x->d86_opnd_size == SIZE32)
3842 (void) strlcat(opnd, dis_REG32[r_m], OPLEN);
3843 else
3844 (void) strlcat(opnd, dis_REG64[r_m], OPLEN);
3845 break;
3846 }
3847 #endif /* DIS_TEXT */
3848 return;
3849 }
3850
3851 /*
3852 * if symbolic representation, skip override prefix, if any
3853 */
3854 dtrace_check_override(x, opindex);
3855
3856 /*
3857 * Handle 16 bit memory references first, since they decode
3858 * the mode values more simply.
3859 * mode 1 is r_m + 8 bit displacement
3860 * mode 2 is r_m + 16 bit displacement
3861 * mode 0 is just r_m, unless r_m is 6 which is 16 bit disp
3862 */
3863 if (x->d86_addr_size == SIZE16) {
3864 if ((mode == 0 && r_m == 6) || mode == 2)
3865 dtrace_imm_opnd(x, WORD_OPND, 2, opindex);
3866 else if (mode == 1)
3867 dtrace_imm_opnd(x, BYTE_OPND, 1, opindex);
3868 #ifdef DIS_TEXT
3869 if (mode == 0 && r_m == 6)
3870 x->d86_opnd[opindex].d86_mode = MODE_SIGNED;
3871 else if (mode == 0)
3872 x->d86_opnd[opindex].d86_mode = MODE_NONE;
3873 else
3874 x->d86_opnd[opindex].d86_mode = MODE_OFFSET;
3875 (void) strlcat(opnd, dis_addr16[mode][r_m], OPLEN);
3876 #endif
3877 return;
3878 }
3879
3880 /*
3881 * 32 and 64 bit addressing modes are more complex since they can
3882 * involve an SIB (scaled index and base) byte to decode. When using VEX
3883 * and EVEX encodings, the r_m indicator for a SIB may be offset by 8
3884 * and 24 (8 + 16) respectively.
3885 */
3886 if (r_m == ESP_REGNO || r_m == ESP_REGNO + 8 || r_m == ESP_REGNO + 24) {
3887 have_SIB = 1;
3888 dtrace_get_SIB(x, &ss, &index, &base);
3889 if (x->d86_error)
3890 return;
3891 if (base != 5 || mode != 0)
3892 if (x->d86_rex_prefix & REX_B)
3893 base += 8;
3894 if (x->d86_rex_prefix & REX_X)
3895 index += 8;
3896 } else {
3897 base = r_m;
3898 }
3899
3900 /*
3901 * Compute the displacement size and get its bytes
3902 */
3903 dispsize = 0;
3904
3905 if (mode == 1)
3906 dispsize = 1;
3907 else if (mode == 2)
3908 dispsize = 4;
3909 else if ((r_m & 7) == EBP_REGNO ||
3910 (have_SIB && (base & 7) == EBP_REGNO))
3911 dispsize = 4;
3912
3913 if (dispsize > 0) {
3914 dtrace_imm_opnd(x, dispsize == 4 ? LONG_OPND : BYTE_OPND,
3915 dispsize, opindex);
3916 if (x->d86_error)
3917 return;
3918 }
3919
3920 #ifdef DIS_TEXT
3921 if (dispsize > 0)
3922 x->d86_opnd[opindex].d86_mode = MODE_OFFSET;
3923
3924 if (have_SIB == 0) {
3925 if (x->d86_mode == SIZE32) {
3926 if (mode == 0)
3927 (void) strlcat(opnd, dis_addr32_mode0[r_m],
3928 OPLEN);
3929 else
3930 (void) strlcat(opnd, dis_addr32_mode12[r_m],
3931 OPLEN);
3932 } else {
3933 if (mode == 0) {
3934 (void) strlcat(opnd, dis_addr64_mode0[r_m],
3935 OPLEN);
3936 if (r_m == 5) {
3937 x->d86_opnd[opindex].d86_mode =
3938 MODE_RIPREL;
3939 }
3940 } else {
3941 (void) strlcat(opnd, dis_addr64_mode12[r_m],
3942 OPLEN);
3943 }
3944 }
3945 } else {
3946 uint_t need_paren = 0;
3947 char **regs;
3948 char **bregs;
3949 const char *const *sf;
3950 if (x->d86_mode == SIZE32) /* NOTE this is not addr_size! */
3951 regs = (char **)dis_REG32;
3952 else
3953 regs = (char **)dis_REG64;
3954
3955 if (x->d86_vsib != 0) {
3956 if (wbit == YMM_OPND) { /* NOTE this is not addr_size */
3957 bregs = (char **)dis_YMMREG;
3958 } else if (wbit == XMM_OPND) {
3959 bregs = (char **)dis_XMMREG;
3960 } else {
3961 bregs = (char **)dis_ZMMREG;
3962 }
3963 sf = dis_vscale_factor;
3964 } else {
3965 bregs = regs;
3966 sf = dis_scale_factor;
3967 }
3968
3969 /*
3970 * print the base (if any)
3971 */
3972 if (base == EBP_REGNO && mode == 0) {
3973 if (index != ESP_REGNO || x->d86_vsib != 0) {
3974 (void) strlcat(opnd, "(", OPLEN);
3975 need_paren = 1;
3976 }
3977 } else {
3978 (void) strlcat(opnd, "(", OPLEN);
3979 (void) strlcat(opnd, regs[base], OPLEN);
3980 need_paren = 1;
3981 }
3982
3983 /*
3984 * print the index (if any)
3985 */
3986 if (index != ESP_REGNO || x->d86_vsib) {
3987 (void) strlcat(opnd, ",", OPLEN);
3988 (void) strlcat(opnd, bregs[index], OPLEN);
3989 (void) strlcat(opnd, sf[ss], OPLEN);
3990 } else
3991 if (need_paren)
3992 (void) strlcat(opnd, ")", OPLEN);
3993 }
3994 #endif
3995 }
3996
3997 /*
3998 * Operand sequence for standard instruction involving one register
3999 * and one register/memory operand.
4000 * wbit indicates a byte(0) or opnd_size(1) operation
4001 * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r")
4002 */
4003 #define STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, vbit) { \
4004 dtrace_get_modrm(x, &mode, ®, &r_m); \
4005 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
4006 dtrace_get_operand(x, mode, r_m, wbit, vbit); \
4007 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1 - vbit); \
4008 }
4009
4010 /*
4011 * Similar to above, but allows for the two operands to be of different
4012 * classes (ie. wbit).
4013 * wbit is for the r_m operand
4014 * w2 is for the reg operand
4015 */
4016 #define MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, w2, vbit) { \
4017 dtrace_get_modrm(x, &mode, ®, &r_m); \
4018 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
4019 dtrace_get_operand(x, mode, r_m, wbit, vbit); \
4020 dtrace_get_operand(x, REG_ONLY, reg, w2, 1 - vbit); \
4021 }
4022
4023 /*
4024 * Similar, but for 2 operands plus an immediate.
4025 * vbit indicates direction
4026 * 0 for "opcode imm, r, r_m" or
4027 * 1 for "opcode imm, r_m, r"
4028 */
4029 #define THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize, vbit) { \
4030 dtrace_get_modrm(x, &mode, ®, &r_m); \
4031 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
4032 dtrace_get_operand(x, mode, r_m, wbit, 2-vbit); \
4033 dtrace_get_operand(x, REG_ONLY, reg, w2, 1+vbit); \
4034 dtrace_imm_opnd(x, wbit, immsize, 0); \
4035 }
4036
4037 /*
4038 * Similar, but for 2 operands plus two immediates.
4039 */
4040 #define FOUROPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize) { \
4041 dtrace_get_modrm(x, &mode, ®, &r_m); \
4042 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
4043 dtrace_get_operand(x, mode, r_m, wbit, 2); \
4044 dtrace_get_operand(x, REG_ONLY, reg, w2, 3); \
4045 dtrace_imm_opnd(x, wbit, immsize, 1); \
4046 dtrace_imm_opnd(x, wbit, immsize, 0); \
4047 }
4048
4049 /*
4050 * 1 operands plus two immediates.
4051 */
4052 #define ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, wbit, immsize) { \
4053 dtrace_get_modrm(x, &mode, ®, &r_m); \
4054 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
4055 dtrace_get_operand(x, mode, r_m, wbit, 2); \
4056 dtrace_imm_opnd(x, wbit, immsize, 1); \
4057 dtrace_imm_opnd(x, wbit, immsize, 0); \
4058 }
4059
4060 /*
4061 * Dissassemble a single x86 or amd64 instruction.
4062 *
4063 * Mode determines the default operating mode (SIZE16, SIZE32 or SIZE64)
4064 * for interpreting instructions.
4065 *
4066 * returns non-zero for bad opcode
4067 */
4068 int
dtrace_disx86(dis86_t * x,uint_t cpu_mode)4069 dtrace_disx86(dis86_t *x, uint_t cpu_mode)
4070 {
4071 const instable_t *dp = NULL; /* decode table being used */
4072 #ifdef DIS_TEXT
4073 uint_t i;
4074 #endif
4075 #ifdef DIS_MEM
4076 uint_t nomem = 0;
4077 #define NOMEM (nomem = 1)
4078 #else
4079 #define NOMEM /* nothing */
4080 #endif
4081 uint_t opnd_size; /* SIZE16, SIZE32 or SIZE64 */
4082 uint_t addr_size; /* SIZE16, SIZE32 or SIZE64 */
4083 uint_t wbit; /* opcode wbit, 0 is 8 bit, !0 for opnd_size */
4084 uint_t w2; /* wbit value for second operand */
4085 uint_t vbit;
4086 uint_t mode = 0; /* mode value from ModRM byte */
4087 uint_t reg; /* reg value from ModRM byte */
4088 uint_t r_m; /* r_m value from ModRM byte */
4089
4090 uint_t opcode1; /* high nibble of 1st byte */
4091 uint_t opcode2; /* low nibble of 1st byte */
4092 uint_t opcode3; /* extra opcode bits usually from ModRM byte */
4093 uint_t opcode4; /* high nibble of 2nd byte */
4094 uint_t opcode5; /* low nibble of 2nd byte */
4095 uint_t opcode6; /* high nibble of 3rd byte */
4096 uint_t opcode7; /* low nibble of 3rd byte */
4097 uint_t opcode8; /* high nibble of 4th byte */
4098 uint_t opcode9; /* low nibble of 4th byte */
4099 uint_t opcode_bytes = 1;
4100
4101 /*
4102 * legacy prefixes come in 5 flavors, you should have only one of each
4103 */
4104 uint_t opnd_size_prefix = 0;
4105 uint_t addr_size_prefix = 0;
4106 uint_t segment_prefix = 0;
4107 uint_t lock_prefix = 0;
4108 uint_t rep_prefix = 0;
4109 uint_t rex_prefix = 0; /* amd64 register extension prefix */
4110
4111 /*
4112 * Intel VEX instruction encoding prefix and fields
4113 */
4114
4115 /* 0xC4 means 3 bytes prefix, 0xC5 means 2 bytes prefix */
4116 uint_t vex_prefix = 0;
4117
4118 /*
4119 * VEX prefix byte 1, includes vex.r, vex.x and vex.b
4120 * (for 3 bytes prefix)
4121 */
4122 uint_t vex_byte1 = 0;
4123
4124 /*
4125 * EVEX prefix byte 1 includes vex.r, vex.x, vex.b and evex.r.
4126 */
4127 uint_t evex_byte1 = 0;
4128 uint_t evex_byte2 = 0;
4129 uint_t evex_byte3 = 0;
4130
4131 /*
4132 * For 32-bit mode, it should prefetch the next byte to
4133 * distinguish between AVX and les/lds
4134 */
4135 uint_t vex_prefetch = 0;
4136
4137 uint_t vex_m = 0;
4138 uint_t vex_v = 0;
4139 uint_t vex_p = 0;
4140 uint_t vex_R = 1;
4141 uint_t vex_X = 1;
4142 uint_t vex_B = 1;
4143 uint_t vex_W = 0;
4144 uint_t vex_L = 0;
4145 uint_t evex_L = 0;
4146 uint_t evex_b = 0;
4147 uint_t evex_modrm = 0;
4148 uint_t evex_prefix = 0;
4149 dis_gather_regs_t *vreg;
4150
4151 #ifdef DIS_TEXT
4152 /* Instruction name for BLS* family of instructions */
4153 char *blsinstr;
4154 #endif
4155
4156 size_t off;
4157
4158 instable_t dp_mmx;
4159
4160 x->d86_len = 0;
4161 x->d86_rmindex = -1;
4162 x->d86_error = 0;
4163 #ifdef DIS_TEXT
4164 x->d86_numopnds = 0;
4165 x->d86_seg_prefix = NULL;
4166 x->d86_mnem[0] = 0;
4167 for (i = 0; i < 4; ++i) {
4168 x->d86_opnd[i].d86_opnd[0] = 0;
4169 x->d86_opnd[i].d86_prefix[0] = 0;
4170 x->d86_opnd[i].d86_value_size = 0;
4171 x->d86_opnd[i].d86_value = 0;
4172 x->d86_opnd[i].d86_mode = MODE_NONE;
4173 }
4174 #endif
4175 x->d86_rex_prefix = 0;
4176 x->d86_got_modrm = 0;
4177 x->d86_memsize = 0;
4178 x->d86_vsib = 0;
4179
4180 if (cpu_mode == SIZE16) {
4181 opnd_size = SIZE16;
4182 addr_size = SIZE16;
4183 } else if (cpu_mode == SIZE32) {
4184 opnd_size = SIZE32;
4185 addr_size = SIZE32;
4186 } else {
4187 opnd_size = SIZE32;
4188 addr_size = SIZE64;
4189 }
4190
4191 /*
4192 * Get one opcode byte and check for zero padding that follows
4193 * jump tables.
4194 */
4195 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
4196 goto error;
4197
4198 if (opcode1 == 0 && opcode2 == 0 &&
4199 x->d86_check_func != NULL && x->d86_check_func(x->d86_data)) {
4200 #ifdef DIS_TEXT
4201 (void) strncpy(x->d86_mnem, ".byte\t0", OPLEN);
4202 #endif
4203 goto done;
4204 }
4205
4206 /*
4207 * Gather up legacy x86 prefix bytes.
4208 */
4209 for (;;) {
4210 uint_t *which_prefix = NULL;
4211
4212 dp = (instable_t *)&dis_distable[opcode1][opcode2];
4213
4214 switch (dp->it_adrmode) {
4215 case PREFIX:
4216 which_prefix = &rep_prefix;
4217 break;
4218 case LOCK:
4219 which_prefix = &lock_prefix;
4220 break;
4221 case OVERRIDE:
4222 which_prefix = &segment_prefix;
4223 #ifdef DIS_TEXT
4224 x->d86_seg_prefix = (char *)dp->it_name;
4225 #endif
4226 if (dp->it_invalid64 && cpu_mode == SIZE64)
4227 goto error;
4228 break;
4229 case AM:
4230 which_prefix = &addr_size_prefix;
4231 break;
4232 case DM:
4233 which_prefix = &opnd_size_prefix;
4234 break;
4235 }
4236 if (which_prefix == NULL)
4237 break;
4238 *which_prefix = (opcode1 << 4) | opcode2;
4239 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
4240 goto error;
4241 }
4242
4243 /*
4244 * Handle amd64 mode PREFIX values.
4245 * Some of the segment prefixes are no-ops. (only FS/GS actually work)
4246 * We might have a REX prefix (opcodes 0x40-0x4f)
4247 */
4248 if (cpu_mode == SIZE64) {
4249 if (segment_prefix != 0x64 && segment_prefix != 0x65)
4250 segment_prefix = 0;
4251
4252 if (opcode1 == 0x4) {
4253 rex_prefix = (opcode1 << 4) | opcode2;
4254 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
4255 goto error;
4256 dp = (instable_t *)&dis_distable[opcode1][opcode2];
4257 } else if (opcode1 == 0xC &&
4258 (opcode2 == 0x4 || opcode2 == 0x5)) {
4259 /* AVX instructions */
4260 vex_prefix = (opcode1 << 4) | opcode2;
4261 x->d86_rex_prefix = 0x40;
4262 }
4263 } else if (opcode1 == 0xC && (opcode2 == 0x4 || opcode2 == 0x5)) {
4264 /* LDS, LES or AVX */
4265 dtrace_get_modrm(x, &mode, ®, &r_m);
4266 vex_prefetch = 1;
4267
4268 if (mode == REG_ONLY) {
4269 /* AVX */
4270 vex_prefix = (opcode1 << 4) | opcode2;
4271 x->d86_rex_prefix = 0x40;
4272 opcode3 = (((mode << 3) | reg)>>1) & 0x0F;
4273 opcode4 = ((reg << 3) | r_m) & 0x0F;
4274 }
4275 }
4276
4277 /*
4278 * The EVEX prefix and "bound" instruction share the same first byte.
4279 * "bound" is only valid for 32-bit. For 64-bit this byte begins the
4280 * EVEX prefix and the 2nd byte must have bits 2 & 3 set to 0.
4281 */
4282 if (opcode1 == 0x6 && opcode2 == 0x2) {
4283 evex_prefix = 0x62;
4284
4285 /*
4286 * An EVEX prefix is 4 bytes long, get the next 3 bytes.
4287 */
4288 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0)
4289 goto error;
4290
4291 if (addr_size == SIZE32 && (opcode4 & 0xf) == 0) {
4292 /*
4293 * Upper bits in 2nd byte == 0 is 'bound' instn.
4294 *
4295 * We've already read the byte so perform the
4296 * equivalent of dtrace_get_modrm on the byte and set
4297 * the flag to indicate we've already read it.
4298 */
4299 char b = (opcode4 << 4) | opcode5;
4300
4301 r_m = b & 0x7;
4302 reg = (b >> 3) & 0x7;
4303 mode = (b >> 6) & 0x3;
4304 vex_prefetch = 1;
4305 goto not_avx512;
4306 }
4307
4308 /* check for correct bits being 0 in 2nd byte */
4309 if ((opcode5 & 0xc) != 0)
4310 goto error;
4311
4312 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
4313 goto error;
4314 /* check for correct bit being 1 in 3rd byte */
4315 if ((opcode7 & 0x4) == 0)
4316 goto error;
4317
4318 if (dtrace_get_opcode(x, &opcode8, &opcode9) != 0)
4319 goto error;
4320
4321 /* Reuse opcode1 & opcode2 to get the real opcode now */
4322 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
4323 goto error;
4324
4325 /*
4326 * We only use the high nibble from the 2nd byte of the prefix
4327 * and save it in the low bits of evex_byte1. This is because
4328 * two of the bits in opcode5 are constant 0 (checked above),
4329 * and the other two bits are captured in vex_m. Also, the VEX
4330 * constants we check in evex_byte1 are against the low bits.
4331 */
4332 evex_byte1 = opcode4;
4333 evex_byte2 = (opcode6 << 4) | opcode7;
4334 evex_byte3 = (opcode8 << 4) | opcode9;
4335
4336 vex_m = opcode5 & EVEX_m;
4337 vex_W = (opcode6 & VEX_W) >> 3;
4338 vex_p = opcode7 & VEX_p;
4339
4340 /*
4341 * We store both EVEX.V' and EVEX.vvvv in here.
4342 */
4343 vex_v = (((opcode6 << 4) | opcode7) & VEX_v) >> 3;
4344 vex_v |= (evex_byte3 & EVEX_V) << 1;
4345
4346 /*
4347 * Store the corresponding prefix information for later use when
4348 * calculating the SIB.
4349 */
4350 if ((evex_byte1 & VEX_R) == 0)
4351 x->d86_rex_prefix |= REX_R;
4352 if ((evex_byte1 & VEX_X) == 0)
4353 x->d86_rex_prefix |= REX_X;
4354 if ((evex_byte1 & VEX_B) == 0)
4355 x->d86_rex_prefix |= REX_B;
4356
4357 /* Currently only 3 valid values for evex L'L: 00, 01, 10 */
4358 evex_L = (opcode8 & EVEX_L) >> 1;
4359 evex_b = opcode8 & EVEX_B;
4360
4361 switch (vex_p) {
4362 case VEX_p_66:
4363 switch (vex_m) {
4364 case VEX_m_0F:
4365 dp = &dis_opEVEX660F[(opcode1 << 4) | opcode2];
4366 break;
4367 case VEX_m_0F38:
4368 dp = &dis_opEVEX660F38[(opcode1 << 4) |
4369 opcode2];
4370 break;
4371 case VEX_m_0F3A:
4372 dp = &dis_opEVEX660F3A[(opcode1 << 4) |
4373 opcode2];
4374 break;
4375 default:
4376 goto error;
4377 }
4378 break;
4379 case VEX_p_F3:
4380 switch (vex_m) {
4381 case VEX_m_0F:
4382 dp = &dis_opEVEXF30F[(opcode1 << 4) | opcode2];
4383 break;
4384 case VEX_m_0F38:
4385 dp = &dis_opEVEXF30F38[(opcode1 << 4) |
4386 opcode2];
4387 break;
4388 default:
4389 goto error;
4390 }
4391 break;
4392 case VEX_p_F2:
4393 switch (vex_m) {
4394 case VEX_m_0F:
4395 dp = &dis_opEVEXF20F[(opcode1 << 4) | opcode2];
4396 break;
4397 case VEX_m_0F38:
4398 dp = &dis_opEVEXF20F38[(opcode1 << 4) |
4399 opcode2];
4400 break;
4401 default:
4402 goto error;
4403 }
4404 break;
4405 default:
4406 dp = &dis_opEVEX0F[(opcode1 << 4) | opcode2];
4407 break;
4408 }
4409 }
4410 not_avx512:
4411
4412 if (vex_prefix == VEX_2bytes) {
4413 if (!vex_prefetch) {
4414 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0)
4415 goto error;
4416 }
4417 vex_R = ((opcode3 & VEX_R) & 0x0F) >> 3;
4418 vex_L = ((opcode4 & VEX_L) & 0x0F) >> 2;
4419 vex_v = (((opcode3 << 4) | opcode4) & VEX_v) >> 3;
4420 vex_p = opcode4 & VEX_p;
4421 /*
4422 * The vex.x and vex.b bits are not defined in two bytes
4423 * mode vex prefix, their default values are 1
4424 */
4425 vex_byte1 = (opcode3 & VEX_R) | VEX_X | VEX_B;
4426
4427 if (vex_R == 0)
4428 x->d86_rex_prefix |= REX_R;
4429
4430 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
4431 goto error;
4432
4433 switch (vex_p) {
4434 case VEX_p_66:
4435 dp = (instable_t *)
4436 &dis_opAVX660F[(opcode1 << 4) | opcode2];
4437 break;
4438 case VEX_p_F3:
4439 dp = (instable_t *)
4440 &dis_opAVXF30F[(opcode1 << 4) | opcode2];
4441 break;
4442 case VEX_p_F2:
4443 dp = (instable_t *)
4444 &dis_opAVXF20F [(opcode1 << 4) | opcode2];
4445 break;
4446 default:
4447 dp = (instable_t *)
4448 &dis_opAVX0F[opcode1][opcode2];
4449
4450 }
4451
4452 } else if (vex_prefix == VEX_3bytes) {
4453 if (!vex_prefetch) {
4454 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0)
4455 goto error;
4456 }
4457 vex_R = (opcode3 & VEX_R) >> 3;
4458 vex_X = (opcode3 & VEX_X) >> 2;
4459 vex_B = (opcode3 & VEX_B) >> 1;
4460 vex_m = (((opcode3 << 4) | opcode4) & VEX_m);
4461 vex_byte1 = opcode3 & (VEX_R | VEX_X | VEX_B);
4462
4463 if (vex_R == 0)
4464 x->d86_rex_prefix |= REX_R;
4465 if (vex_X == 0)
4466 x->d86_rex_prefix |= REX_X;
4467 if (vex_B == 0)
4468 x->d86_rex_prefix |= REX_B;
4469
4470 if (dtrace_get_opcode(x, &opcode5, &opcode6) != 0)
4471 goto error;
4472 vex_W = (opcode5 & VEX_W) >> 3;
4473 vex_L = (opcode6 & VEX_L) >> 2;
4474 vex_v = (((opcode5 << 4) | opcode6) & VEX_v) >> 3;
4475 vex_p = opcode6 & VEX_p;
4476
4477 if (vex_W)
4478 x->d86_rex_prefix |= REX_W;
4479
4480 /* Only these three vex_m values valid; others are reserved */
4481 if ((vex_m != VEX_m_0F) && (vex_m != VEX_m_0F38) &&
4482 (vex_m != VEX_m_0F3A))
4483 goto error;
4484
4485 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
4486 goto error;
4487
4488 switch (vex_p) {
4489 case VEX_p_66:
4490 if (vex_m == VEX_m_0F) {
4491 dp = (instable_t *)
4492 &dis_opAVX660F
4493 [(opcode1 << 4) | opcode2];
4494 } else if (vex_m == VEX_m_0F38) {
4495 dp = (instable_t *)
4496 &dis_opAVX660F38
4497 [(opcode1 << 4) | opcode2];
4498 } else if (vex_m == VEX_m_0F3A) {
4499 dp = (instable_t *)
4500 &dis_opAVX660F3A
4501 [(opcode1 << 4) | opcode2];
4502 } else {
4503 goto error;
4504 }
4505 break;
4506 case VEX_p_F3:
4507 if (vex_m == VEX_m_0F) {
4508 dp = (instable_t *)
4509 &dis_opAVXF30F
4510 [(opcode1 << 4) | opcode2];
4511 } else if (vex_m == VEX_m_0F38) {
4512 dp = (instable_t *)
4513 &dis_opAVXF30F38
4514 [(opcode1 << 4) | opcode2];
4515 } else {
4516 goto error;
4517 }
4518 break;
4519 case VEX_p_F2:
4520 if (vex_m == VEX_m_0F) {
4521 dp = (instable_t *)
4522 &dis_opAVXF20F
4523 [(opcode1 << 4) | opcode2];
4524 } else if (vex_m == VEX_m_0F3A) {
4525 dp = (instable_t *)
4526 &dis_opAVXF20F3A
4527 [(opcode1 << 4) | opcode2];
4528 } else if (vex_m == VEX_m_0F38) {
4529 dp = (instable_t *)
4530 &dis_opAVXF20F38
4531 [(opcode1 << 4) | opcode2];
4532 } else {
4533 goto error;
4534 }
4535 break;
4536 default:
4537 dp = (instable_t *)
4538 &dis_opAVX0F[opcode1][opcode2];
4539
4540 }
4541 }
4542 if (vex_prefix) {
4543 if (dp->it_vexwoxmm) {
4544 wbit = LONG_OPND;
4545 } else if (dp->it_vexopmask) {
4546 wbit = KOPMASK_OPND;
4547 } else {
4548 if (vex_L) {
4549 wbit = YMM_OPND;
4550 } else {
4551 wbit = XMM_OPND;
4552 }
4553 }
4554 }
4555
4556 /*
4557 * Deal with selection of operand and address size now.
4558 * Note that the REX.W bit being set causes opnd_size_prefix to be
4559 * ignored.
4560 */
4561 if (cpu_mode == SIZE64) {
4562 if ((rex_prefix & REX_W) || vex_W)
4563 opnd_size = SIZE64;
4564 else if (opnd_size_prefix)
4565 opnd_size = SIZE16;
4566
4567 if (addr_size_prefix)
4568 addr_size = SIZE32;
4569 } else if (cpu_mode == SIZE32) {
4570 if (opnd_size_prefix)
4571 opnd_size = SIZE16;
4572 if (addr_size_prefix)
4573 addr_size = SIZE16;
4574 } else {
4575 if (opnd_size_prefix)
4576 opnd_size = SIZE32;
4577 if (addr_size_prefix)
4578 addr_size = SIZE32;
4579 }
4580 /*
4581 * The pause instruction - a repz'd nop. This doesn't fit
4582 * with any of the other prefix goop added for SSE, so we'll
4583 * special-case it here.
4584 */
4585 if (rep_prefix == 0xf3 && opcode1 == 0x9 && opcode2 == 0x0) {
4586 rep_prefix = 0;
4587 dp = (instable_t *)&dis_opPause;
4588 }
4589
4590 /*
4591 * Some 386 instructions have 2 bytes of opcode before the mod_r/m
4592 * byte so we may need to perform a table indirection.
4593 */
4594 if (dp->it_indirect == (instable_t *)dis_op0F) {
4595 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0)
4596 goto error;
4597 opcode_bytes = 2;
4598 if (opcode4 == 0x7 && opcode5 >= 0x1 && opcode5 <= 0x3) {
4599 uint_t subcode;
4600
4601 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
4602 goto error;
4603 opcode_bytes = 3;
4604 subcode = ((opcode6 & 0x3) << 1) |
4605 ((opcode7 & 0x8) >> 3);
4606 dp = (instable_t *)&dis_op0F7123[opcode5][subcode];
4607 } else if ((opcode4 == 0xc) && (opcode5 >= 0x8)) {
4608 dp = (instable_t *)&dis_op0FC8[0];
4609 } else if ((opcode4 == 0x3) && (opcode5 == 0xA)) {
4610 opcode_bytes = 3;
4611 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
4612 goto error;
4613 if (opnd_size == SIZE16)
4614 opnd_size = SIZE32;
4615
4616 dp = (instable_t *)&dis_op0F3A[(opcode6<<4)|opcode7];
4617 #ifdef DIS_TEXT
4618 if (strcmp(dp->it_name, "INVALID") == 0)
4619 goto error;
4620 #endif
4621 switch (dp->it_adrmode) {
4622 case XMMP:
4623 break;
4624 case XMMP_66r:
4625 case XMMPRM_66r:
4626 case XMM3PM_66r:
4627 if (opnd_size_prefix == 0) {
4628 goto error;
4629 }
4630
4631 break;
4632 case XMMP_66o:
4633 if (opnd_size_prefix == 0) {
4634 /* SSSE3 MMX instructions */
4635 dp_mmx = *dp;
4636 dp_mmx.it_adrmode = MMOPM_66o;
4637 #ifdef DIS_MEM
4638 dp_mmx.it_size = 8;
4639 #endif
4640 dp = &dp_mmx;
4641 }
4642 break;
4643 default:
4644 goto error;
4645 }
4646 } else if ((opcode4 == 0x3) && (opcode5 == 0x8)) {
4647 opcode_bytes = 3;
4648 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
4649 goto error;
4650 dp = (instable_t *)&dis_op0F38[(opcode6<<4)|opcode7];
4651
4652 /*
4653 * Both crc32 and movbe have the same 3rd opcode
4654 * byte of either 0xF0 or 0xF1, so we use another
4655 * indirection to distinguish between the two.
4656 */
4657 if (dp->it_indirect == (instable_t *)dis_op0F38F0 ||
4658 dp->it_indirect == (instable_t *)dis_op0F38F1) {
4659
4660 dp = dp->it_indirect;
4661 if (rep_prefix != 0xF2) {
4662 /* It is movbe */
4663 dp++;
4664 }
4665 }
4666
4667 /*
4668 * The adx family of instructions (adcx and adox)
4669 * continue the classic Intel tradition of abusing
4670 * arbitrary prefixes without actually meaning the
4671 * prefix bit. Therefore, if we find either the
4672 * opnd_size_prefix or rep_prefix we end up zeroing it
4673 * out after making our determination so as to ensure
4674 * that we don't get confused and accidentally print
4675 * repz prefixes and the like on these instructions.
4676 *
4677 * In addition, these instructions are actually much
4678 * closer to AVX instructions in semantics. Importantly,
4679 * they always default to having 32-bit operands.
4680 * However, if the CPU is in 64-bit mode, then and only
4681 * then, does it use REX.w promotes things to 64-bits
4682 * and REX.r allows 64-bit mode to use register r8-r15.
4683 */
4684 if (dp->it_indirect == (instable_t *)dis_op0F38F6) {
4685 dp = dp->it_indirect;
4686 if (opnd_size_prefix == 0 &&
4687 rep_prefix == 0xf3) {
4688 /* It is adox */
4689 dp++;
4690 } else if (opnd_size_prefix != 0x66 &&
4691 rep_prefix != 0) {
4692 /* It isn't adcx */
4693 goto error;
4694 }
4695 opnd_size_prefix = 0;
4696 rep_prefix = 0;
4697 opnd_size = SIZE32;
4698 if (rex_prefix & REX_W)
4699 opnd_size = SIZE64;
4700 }
4701
4702 #ifdef DIS_TEXT
4703 if (strcmp(dp->it_name, "INVALID") == 0)
4704 goto error;
4705 #endif
4706 switch (dp->it_adrmode) {
4707 case ADX:
4708 case XMM:
4709 break;
4710 case RM_66r:
4711 case XMM_66r:
4712 case XMMM_66r:
4713 if (opnd_size_prefix == 0) {
4714 goto error;
4715 }
4716 break;
4717 case XMM_66o:
4718 if (opnd_size_prefix == 0) {
4719 /* SSSE3 MMX instructions */
4720 dp_mmx = *dp;
4721 dp_mmx.it_adrmode = MM;
4722 #ifdef DIS_MEM
4723 dp_mmx.it_size = 8;
4724 #endif
4725 dp = &dp_mmx;
4726 }
4727 break;
4728 case CRC32:
4729 if (rep_prefix != 0xF2) {
4730 goto error;
4731 }
4732 rep_prefix = 0;
4733 break;
4734 case MOVBE:
4735 if (rep_prefix != 0x0) {
4736 goto error;
4737 }
4738 break;
4739 case RM:
4740 /*
4741 * Currently the MOVDIRI instruction is
4742 * the only known case here. It is not
4743 * allowed to have a prefix.
4744 */
4745 if (rep_prefix != 0x0) {
4746 goto error;
4747 }
4748 break;
4749 case MOVDIR:
4750 /*
4751 * MOVDIR64B requires a opnd size prefix
4752 * of 0x66, but ignores it. This means
4753 * that we need to undo what we did
4754 * earlier and readjust the operator and
4755 * address size prefixes.
4756 */
4757 if (opnd_size_prefix != 0x66) {
4758 goto error;
4759 }
4760 if (cpu_mode == SIZE64 ||
4761 cpu_mode == SIZE16) {
4762 if (addr_size_prefix == 0x67) {
4763 opnd_size = SIZE32;
4764 } else {
4765 opnd_size = cpu_mode;
4766 }
4767 } else {
4768 if (addr_size_prefix == 0x67) {
4769 opnd_size = SIZE16;
4770 } else {
4771 opnd_size = SIZE32;
4772 }
4773 }
4774 addr_size = opnd_size;
4775 addr_size_prefix = 0;
4776 opnd_size_prefix = 0;
4777 break;
4778 default:
4779 goto error;
4780 }
4781 } else if (rep_prefix == 0xf3 && opcode4 == 0 && opcode5 == 9) {
4782 rep_prefix = 0;
4783 dp = (instable_t *)&dis_opWbnoinvd;
4784 } else {
4785 dp = (instable_t *)&dis_op0F[opcode4][opcode5];
4786 }
4787 }
4788
4789 /*
4790 * If still not at a TERM decode entry, then a ModRM byte
4791 * exists and its fields further decode the instruction.
4792 */
4793 x->d86_got_modrm = 0;
4794 if (dp->it_indirect != TERM) {
4795 dtrace_get_modrm(x, &mode, &opcode3, &r_m);
4796 if (x->d86_error)
4797 goto error;
4798 reg = opcode3;
4799
4800 /*
4801 * decode 287 instructions (D8-DF) from opcodeN
4802 */
4803 if (opcode1 == 0xD && opcode2 >= 0x8) {
4804 if (opcode2 == 0xB && mode == 0x3 && opcode3 == 4)
4805 dp = (instable_t *)&dis_opFP5[r_m];
4806 else if (opcode2 == 0xA && mode == 0x3 && opcode3 < 4)
4807 dp = (instable_t *)&dis_opFP7[opcode3];
4808 else if (opcode2 == 0xB && mode == 0x3)
4809 dp = (instable_t *)&dis_opFP6[opcode3];
4810 else if (opcode2 == 0x9 && mode == 0x3 && opcode3 >= 4)
4811 dp = (instable_t *)&dis_opFP4[opcode3 - 4][r_m];
4812 else if (mode == 0x3)
4813 dp = (instable_t *)
4814 &dis_opFP3[opcode2 - 8][opcode3];
4815 else
4816 dp = (instable_t *)
4817 &dis_opFP1n2[opcode2 - 8][opcode3];
4818 } else {
4819 dp = (instable_t *)dp->it_indirect + opcode3;
4820 }
4821 }
4822
4823 /*
4824 * In amd64 bit mode, ARPL opcode is changed to MOVSXD (sign extend
4825 * 32-bit to 64-bit). Note, this isn't done when there's either a vex or
4826 * evex prefix.
4827 */
4828 if (evex_prefix == 0 && vex_prefix == 0 && cpu_mode == SIZE64 &&
4829 opcode1 == 0x6 && opcode2 == 0x3)
4830 dp = (instable_t *)&dis_opMOVSLD;
4831
4832 /*
4833 * at this point we should have a correct (or invalid) opcode
4834 */
4835 if ((cpu_mode == SIZE64 && dp->it_invalid64) ||
4836 (cpu_mode != SIZE64 && dp->it_invalid32))
4837 goto error;
4838 if (dp->it_indirect != TERM)
4839 goto error;
4840
4841 /*
4842 * Deal with MMX/SSE opcodes which are changed by prefixes. Note, we do
4843 * need to include UNKNOWN below, as we may have instructions that
4844 * actually have a prefix, but don't exist in any other form.
4845 */
4846 switch (dp->it_adrmode) {
4847 case UNKNOWN:
4848 case MMO:
4849 case MMOIMPL:
4850 case MMO3P:
4851 case MMOM3:
4852 case MMOMS:
4853 case MMOPM:
4854 case MMOPRM:
4855 case MMOS:
4856 case XMMO:
4857 case XMMOM:
4858 case XMMOMS:
4859 case XMMOPM:
4860 case XMMOS:
4861 case XMMOMX:
4862 case XMMOX3:
4863 case XMMOXMM:
4864 /*
4865 * This is horrible. Some SIMD instructions take the
4866 * form 0x0F 0x?? ..., which is easily decoded using the
4867 * existing tables. Other SIMD instructions use various
4868 * prefix bytes to overload existing instructions. For
4869 * Example, addps is F0, 58, whereas addss is F3 (repz),
4870 * F0, 58. Presumably someone got a raise for this.
4871 *
4872 * If we see one of the instructions which can be
4873 * modified in this way (if we've got one of the SIMDO*
4874 * address modes), we'll check to see if the last prefix
4875 * was a repz. If it was, we strip the prefix from the
4876 * mnemonic, and we indirect using the dis_opSIMDrepz
4877 * table.
4878 */
4879
4880 /*
4881 * Calculate our offset in dis_op0F
4882 */
4883 if ((uintptr_t)dp - (uintptr_t)dis_op0F > sizeof (dis_op0F))
4884 goto error;
4885
4886 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) /
4887 sizeof (instable_t);
4888
4889 /*
4890 * Rewrite if this instruction used one of the magic prefixes.
4891 */
4892 if (rep_prefix) {
4893 if (rep_prefix == 0xf2)
4894 dp = (instable_t *)&dis_opSIMDrepnz[off];
4895 else
4896 dp = (instable_t *)&dis_opSIMDrepz[off];
4897 rep_prefix = 0;
4898 } else if (opnd_size_prefix) {
4899 dp = (instable_t *)&dis_opSIMDdata16[off];
4900 opnd_size_prefix = 0;
4901 if (opnd_size == SIZE16)
4902 opnd_size = SIZE32;
4903 }
4904 break;
4905
4906 case MG9:
4907 /*
4908 * More horribleness: the group 9 (0xF0 0xC7) instructions are
4909 * allowed an optional prefix of 0x66 or 0xF3. This is similar
4910 * to the SIMD business described above, but with a different
4911 * addressing mode (and an indirect table), so we deal with it
4912 * separately (if similarly).
4913 *
4914 * Intel further complicated this with the release of Ivy Bridge
4915 * where they overloaded these instructions based on the ModR/M
4916 * bytes. The VMX instructions have a mode of 0 since they are
4917 * memory instructions but rdrand instructions have a mode of
4918 * 0b11 (REG_ONLY) because they only operate on registers.
4919 */
4920
4921 /*
4922 * Calculate our offset in dis_op0FC7 (the group 9 table)
4923 */
4924 if ((uintptr_t)dp - (uintptr_t)dis_op0FC7 > sizeof (dis_op0FC7))
4925 goto error;
4926
4927 off = ((uintptr_t)dp - (uintptr_t)dis_op0FC7) /
4928 sizeof (instable_t);
4929
4930 /*
4931 * If we have a mode of 0b11 then we have to rewrite this. We
4932 * must check prefixes first.
4933 */
4934 dtrace_get_modrm(x, &mode, ®, &r_m);
4935
4936 /*
4937 * Rewrite if this instruction used one of the magic prefixes.
4938 */
4939 if (rep_prefix) {
4940 if (rep_prefix == 0xf3 && mode == REG_ONLY)
4941 dp = (instable_t *)&dis_opF30FC7m3[off];
4942 else if (rep_prefix == 0xf3)
4943 dp = (instable_t *)&dis_opF30FC7[off];
4944 else
4945 goto error;
4946 rep_prefix = 0;
4947 } else if (opnd_size_prefix) {
4948 if (mode == REG_ONLY) {
4949 dp = (instable_t *)&dis_op0FC7m3[reg];
4950 } else {
4951 dp = (instable_t *)&dis_op660FC7[off];
4952 opnd_size_prefix = 0;
4953 if (opnd_size == SIZE16)
4954 opnd_size = SIZE32;
4955 }
4956 } else if (mode == REG_ONLY) {
4957 dp = (instable_t *)&dis_op0FC7m3[off];
4958 } else if (reg == 4 || reg == 5) {
4959 /*
4960 * We have xsavec (4) or xsaves (5), so rewrite.
4961 */
4962 dp = (instable_t *)&dis_op0FC7[reg];
4963 }
4964 break;
4965
4966
4967 case MMOSH:
4968 /*
4969 * As with the "normal" SIMD instructions, the MMX
4970 * shuffle instructions are overloaded. These
4971 * instructions, however, are special in that they use
4972 * an extra byte, and thus an extra table. As of this
4973 * writing, they only use the opnd_size prefix.
4974 */
4975
4976 /*
4977 * Calculate our offset in dis_op0F7123
4978 */
4979 if ((uintptr_t)dp - (uintptr_t)dis_op0F7123 >
4980 sizeof (dis_op0F7123))
4981 goto error;
4982
4983 if (opnd_size_prefix) {
4984 off = ((uintptr_t)dp - (uintptr_t)dis_op0F7123) /
4985 sizeof (instable_t);
4986 dp = (instable_t *)&dis_opSIMD7123[off];
4987 opnd_size_prefix = 0;
4988 if (opnd_size == SIZE16)
4989 opnd_size = SIZE32;
4990 }
4991 break;
4992 case MRw:
4993 if (rep_prefix) {
4994 if (rep_prefix == 0xf3) {
4995
4996 /*
4997 * Calculate our offset in dis_op0F
4998 */
4999 if ((uintptr_t)dp - (uintptr_t)dis_op0F >
5000 sizeof (dis_op0F))
5001 goto error;
5002
5003 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) /
5004 sizeof (instable_t);
5005
5006 dp = (instable_t *)&dis_opSIMDrepz[off];
5007 rep_prefix = 0;
5008 } else {
5009 goto error;
5010 }
5011 }
5012 break;
5013 case FSGS:
5014 if (rep_prefix == 0xf3) {
5015 if ((uintptr_t)dp - (uintptr_t)dis_op0FAE >
5016 sizeof (dis_op0FAE))
5017 goto error;
5018
5019 off = ((uintptr_t)dp - (uintptr_t)dis_op0FAE) /
5020 sizeof (instable_t);
5021 dp = (instable_t *)&dis_opF30FAE[off];
5022 rep_prefix = 0;
5023 } else if (rep_prefix != 0x00) {
5024 goto error;
5025 }
5026 }
5027
5028 /*
5029 * In 64 bit mode, some opcodes automatically use opnd_size == SIZE64.
5030 */
5031 if (cpu_mode == SIZE64)
5032 if (dp->it_always64 || (opnd_size == SIZE32 && dp->it_stackop))
5033 opnd_size = SIZE64;
5034
5035 #ifdef DIS_TEXT
5036 /*
5037 * At this point most instructions can format the opcode mnemonic
5038 * including the prefixes.
5039 */
5040 if (lock_prefix)
5041 (void) strlcat(x->d86_mnem, "lock ", OPLEN);
5042
5043 if (rep_prefix == 0xf2)
5044 (void) strlcat(x->d86_mnem, "repnz ", OPLEN);
5045 else if (rep_prefix == 0xf3)
5046 (void) strlcat(x->d86_mnem, "repz ", OPLEN);
5047
5048 if (cpu_mode == SIZE64 && addr_size_prefix)
5049 (void) strlcat(x->d86_mnem, "addr32 ", OPLEN);
5050
5051 if (dp->it_adrmode != CBW &&
5052 dp->it_adrmode != CWD &&
5053 dp->it_adrmode != XMMSFNC) {
5054 if (strcmp(dp->it_name, "INVALID") == 0)
5055 goto error;
5056 (void) strlcat(x->d86_mnem, dp->it_name, OPLEN);
5057 if (dp->it_avxsuf == AVS2 && dp->it_suffix) {
5058 (void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d",
5059 OPLEN);
5060 } else if (dp->it_vexopmask && dp->it_suffix) {
5061 /* opmask instructions */
5062
5063 if (opcode1 == 4 && opcode2 == 0xb) {
5064 /* It's a kunpck. */
5065 if (vex_prefix == VEX_2bytes) {
5066 (void) strlcat(x->d86_mnem,
5067 vex_p == 0 ? "wd" : "bw", OPLEN);
5068 } else {
5069 /* vex_prefix == VEX_3bytes */
5070 (void) strlcat(x->d86_mnem,
5071 "dq", OPLEN);
5072 }
5073 } else if (opcode1 == 3) {
5074 /* It's a kshift[l|r]. */
5075 if (vex_W == 0) {
5076 (void) strlcat(x->d86_mnem,
5077 opcode2 == 2 ||
5078 opcode2 == 0 ?
5079 "b" : "d", OPLEN);
5080 } else {
5081 /* W == 1 */
5082 (void) strlcat(x->d86_mnem,
5083 opcode2 == 3 || opcode2 == 1 ?
5084 "q" : "w", OPLEN);
5085 }
5086 } else {
5087 /* if (vex_prefix == VEX_2bytes) { */
5088 if ((cpu_mode == SIZE64 && opnd_size == 2) ||
5089 vex_prefix == VEX_2bytes) {
5090 (void) strlcat(x->d86_mnem,
5091 vex_p == 0 ? "w" :
5092 vex_p == 1 ? "b" : "d",
5093 OPLEN);
5094 } else {
5095 /* vex_prefix == VEX_3bytes */
5096 (void) strlcat(x->d86_mnem,
5097 vex_p == 1 ? "d" : "q", OPLEN);
5098 }
5099 }
5100 } else if (dp->it_suffix) {
5101 char *types[] = {"", "w", "l", "q"};
5102 if (opcode_bytes == 2 && opcode4 == 4) {
5103 /* It's a cmovx.yy. Replace the suffix x */
5104 for (i = 5; i < OPLEN; i++) {
5105 if (x->d86_mnem[i] == '.')
5106 break;
5107 }
5108 x->d86_mnem[i - 1] = *types[opnd_size];
5109 } else if ((opnd_size == 2) && (opcode_bytes == 3) &&
5110 ((opcode6 == 1 && opcode7 == 6) ||
5111 (opcode6 == 2 && opcode7 == 2))) {
5112 /*
5113 * To handle PINSRD and PEXTRD
5114 */
5115 (void) strlcat(x->d86_mnem, "d", OPLEN);
5116 } else if (dp != &dis_distable[0x6][0x2]) {
5117 /* bound instructions (0x62) have no suffix */
5118 (void) strlcat(x->d86_mnem, types[opnd_size],
5119 OPLEN);
5120 }
5121 }
5122 }
5123 #endif
5124
5125 /*
5126 * Process operands based on the addressing modes.
5127 */
5128 x->d86_mode = cpu_mode;
5129 /*
5130 * In vex mode the rex_prefix has no meaning
5131 */
5132 if (!vex_prefix && evex_prefix == 0)
5133 x->d86_rex_prefix = rex_prefix;
5134 x->d86_opnd_size = opnd_size;
5135 x->d86_addr_size = addr_size;
5136 vbit = 0; /* initialize for mem/reg -> reg */
5137 switch (dp->it_adrmode) {
5138 /*
5139 * amd64 instruction to sign extend 32 bit reg/mem operands
5140 * into 64 bit register values
5141 */
5142 case MOVSXZ:
5143 #ifdef DIS_TEXT
5144 if (rex_prefix == 0)
5145 (void) strncpy(x->d86_mnem, "movzld", OPLEN);
5146 #endif
5147 dtrace_get_modrm(x, &mode, ®, &r_m);
5148 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
5149 x->d86_opnd_size = SIZE64;
5150 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
5151 x->d86_opnd_size = opnd_size = SIZE32;
5152 wbit = LONG_OPND;
5153 dtrace_get_operand(x, mode, r_m, wbit, 0);
5154 break;
5155
5156 /*
5157 * movsbl movsbw movsbq (0x0FBE) or movswl movswq (0x0FBF)
5158 * movzbl movzbw movzbq (0x0FB6) or movzwl movzwq (0x0FB7)
5159 * wbit lives in 2nd byte, note that operands
5160 * are different sized
5161 */
5162 case MOVZ:
5163 if (rex_prefix & REX_W) {
5164 /* target register size = 64 bit */
5165 x->d86_mnem[5] = 'q';
5166 }
5167 dtrace_get_modrm(x, &mode, ®, &r_m);
5168 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
5169 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
5170 x->d86_opnd_size = opnd_size = SIZE16;
5171 wbit = WBIT(opcode5);
5172 dtrace_get_operand(x, mode, r_m, wbit, 0);
5173 break;
5174 case CRC32:
5175 opnd_size = SIZE32;
5176 if (rex_prefix & REX_W)
5177 opnd_size = SIZE64;
5178 x->d86_opnd_size = opnd_size;
5179
5180 dtrace_get_modrm(x, &mode, ®, &r_m);
5181 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
5182 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
5183 wbit = WBIT(opcode7);
5184 if (opnd_size_prefix)
5185 x->d86_opnd_size = opnd_size = SIZE16;
5186 dtrace_get_operand(x, mode, r_m, wbit, 0);
5187 break;
5188 case MOVBE:
5189 opnd_size = SIZE32;
5190 if (rex_prefix & REX_W)
5191 opnd_size = SIZE64;
5192 x->d86_opnd_size = opnd_size;
5193
5194 dtrace_get_modrm(x, &mode, ®, &r_m);
5195 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
5196 wbit = WBIT(opcode7);
5197 if (opnd_size_prefix)
5198 x->d86_opnd_size = opnd_size = SIZE16;
5199 if (wbit) {
5200 /* reg -> mem */
5201 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
5202 dtrace_get_operand(x, mode, r_m, wbit, 1);
5203 } else {
5204 /* mem -> reg */
5205 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
5206 dtrace_get_operand(x, mode, r_m, wbit, 0);
5207 }
5208 break;
5209
5210 /*
5211 * imul instruction, with either 8-bit or longer immediate
5212 * opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s)
5213 */
5214 case IMUL:
5215 wbit = LONG_OPND;
5216 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND,
5217 OPSIZE(opnd_size, opcode2 == 0x9), 1);
5218 break;
5219
5220 /* memory or register operand to register, with 'w' bit */
5221 case MRw:
5222 case ADX:
5223 wbit = WBIT(opcode2);
5224 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
5225 break;
5226
5227 /* register to memory or register operand, with 'w' bit */
5228 /* arpl happens to fit here also because it is odd */
5229 case RMw:
5230 if (opcode_bytes == 2)
5231 wbit = WBIT(opcode5);
5232 else
5233 wbit = WBIT(opcode2);
5234 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
5235 break;
5236
5237 /* xaddb instruction */
5238 case XADDB:
5239 wbit = 0;
5240 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
5241 break;
5242
5243 /* MMX register to memory or register operand */
5244 case MMS:
5245 case MMOS:
5246 #ifdef DIS_TEXT
5247 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND;
5248 #else
5249 wbit = LONG_OPND;
5250 #endif
5251 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1);
5252 break;
5253
5254 /* MMX register to memory */
5255 case MMOMS:
5256 dtrace_get_modrm(x, &mode, ®, &r_m);
5257 if (mode == REG_ONLY)
5258 goto error;
5259 wbit = MM_OPND;
5260 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1);
5261 break;
5262
5263 /* Double shift. Has immediate operand specifying the shift. */
5264 case DSHIFT:
5265 wbit = LONG_OPND;
5266 dtrace_get_modrm(x, &mode, ®, &r_m);
5267 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
5268 dtrace_get_operand(x, mode, r_m, wbit, 2);
5269 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
5270 dtrace_imm_opnd(x, wbit, 1, 0);
5271 break;
5272
5273 /*
5274 * Double shift. With no immediate operand, specifies using %cl.
5275 */
5276 case DSHIFTcl:
5277 wbit = LONG_OPND;
5278 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
5279 break;
5280
5281 /* immediate to memory or register operand */
5282 case IMlw:
5283 wbit = WBIT(opcode2);
5284 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
5285 dtrace_get_operand(x, mode, r_m, wbit, 1);
5286 /*
5287 * Have long immediate for opcode 0x81, but not 0x80 nor 0x83
5288 */
5289 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, opcode2 == 1), 0);
5290 break;
5291
5292 /* immediate to memory or register operand with the */
5293 /* 'w' bit present */
5294 case IMw:
5295 wbit = WBIT(opcode2);
5296 dtrace_get_modrm(x, &mode, ®, &r_m);
5297 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
5298 dtrace_get_operand(x, mode, r_m, wbit, 1);
5299 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0);
5300 break;
5301
5302 /* immediate to register with register in low 3 bits */
5303 /* of op code */
5304 case IR:
5305 /* w-bit here (with regs) is bit 3 */
5306 wbit = opcode2 >>3 & 0x1;
5307 reg = REGNO(opcode2);
5308 dtrace_rex_adjust(rex_prefix, mode, ®, NULL);
5309 mode = REG_ONLY;
5310 r_m = reg;
5311 dtrace_get_operand(x, mode, r_m, wbit, 1);
5312 dtrace_imm_opnd(x, wbit, OPSIZE64(opnd_size, wbit), 0);
5313 break;
5314
5315 /* MMX immediate shift of register */
5316 case MMSH:
5317 case MMOSH:
5318 wbit = MM_OPND;
5319 goto mm_shift; /* in next case */
5320
5321 /* SIMD immediate shift of register */
5322 case XMMSH:
5323 wbit = XMM_OPND;
5324 mm_shift:
5325 reg = REGNO(opcode7);
5326 dtrace_rex_adjust(rex_prefix, mode, ®, NULL);
5327 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5328 dtrace_imm_opnd(x, wbit, 1, 0);
5329 NOMEM;
5330 break;
5331
5332 /* accumulator to memory operand */
5333 case AO:
5334 vbit = 1;
5335 /*FALLTHROUGH*/
5336
5337 /* memory operand to accumulator */
5338 case OA:
5339 wbit = WBIT(opcode2);
5340 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1 - vbit);
5341 dtrace_imm_opnd(x, wbit, OPSIZE64(addr_size, LONG_OPND), vbit);
5342 #ifdef DIS_TEXT
5343 x->d86_opnd[vbit].d86_mode = MODE_OFFSET;
5344 #endif
5345 break;
5346
5347
5348 /* segment register to memory or register operand */
5349 case SM:
5350 vbit = 1;
5351 /*FALLTHROUGH*/
5352
5353 /* memory or register operand to segment register */
5354 case MS:
5355 dtrace_get_modrm(x, &mode, ®, &r_m);
5356 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
5357 dtrace_get_operand(x, mode, r_m, LONG_OPND, vbit);
5358 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 1 - vbit);
5359 break;
5360
5361 /*
5362 * rotate or shift instructions, which may shift by 1 or
5363 * consult the cl register, depending on the 'v' bit
5364 */
5365 case Mv:
5366 vbit = VBIT(opcode2);
5367 wbit = WBIT(opcode2);
5368 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
5369 dtrace_get_operand(x, mode, r_m, wbit, 1);
5370 #ifdef DIS_TEXT
5371 if (vbit) {
5372 (void) strlcat(x->d86_opnd[0].d86_opnd, "%cl", OPLEN);
5373 } else {
5374 x->d86_opnd[0].d86_mode = MODE_SIGNED;
5375 x->d86_opnd[0].d86_value_size = 1;
5376 x->d86_opnd[0].d86_value = 1;
5377 }
5378 #endif
5379 break;
5380 /*
5381 * immediate rotate or shift instructions
5382 */
5383 case MvI:
5384 wbit = WBIT(opcode2);
5385 normal_imm_mem:
5386 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
5387 dtrace_get_operand(x, mode, r_m, wbit, 1);
5388 dtrace_imm_opnd(x, wbit, 1, 0);
5389 break;
5390
5391 /* bit test instructions */
5392 case MIb:
5393 wbit = LONG_OPND;
5394 goto normal_imm_mem;
5395
5396 /* single memory or register operand with 'w' bit present */
5397 case Mw:
5398 wbit = WBIT(opcode2);
5399 just_mem:
5400 dtrace_get_modrm(x, &mode, ®, &r_m);
5401 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
5402 dtrace_get_operand(x, mode, r_m, wbit, 0);
5403 break;
5404
5405 case SWAPGS_RDTSCP:
5406 if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) {
5407 #ifdef DIS_TEXT
5408 (void) strncpy(x->d86_mnem, "swapgs", OPLEN);
5409 #endif
5410 NOMEM;
5411 break;
5412 } else if (mode == 3 && r_m == 1) {
5413 #ifdef DIS_TEXT
5414 (void) strncpy(x->d86_mnem, "rdtscp", OPLEN);
5415 #endif
5416 NOMEM;
5417 break;
5418 } else if (mode == 3 && r_m == 2) {
5419 #ifdef DIS_TEXT
5420 (void) strncpy(x->d86_mnem, "monitorx", OPLEN);
5421 #endif
5422 NOMEM;
5423 break;
5424 } else if (mode == 3 && r_m == 3) {
5425 #ifdef DIS_TEXT
5426 (void) strncpy(x->d86_mnem, "mwaitx", OPLEN);
5427 #endif
5428 NOMEM;
5429 break;
5430 } else if (mode == 3 && r_m == 4) {
5431 #ifdef DIS_TEXT
5432 (void) strncpy(x->d86_mnem, "clzero", OPLEN);
5433 #endif
5434 NOMEM;
5435 break;
5436 }
5437
5438 /*FALLTHROUGH*/
5439
5440 /* prefetch instruction - memory operand, but no memory acess */
5441 case PREF:
5442 NOMEM;
5443 /*FALLTHROUGH*/
5444
5445 /* single memory or register operand */
5446 case M:
5447 case MG9:
5448 wbit = LONG_OPND;
5449 goto just_mem;
5450
5451 /* single memory or register byte operand */
5452 case Mb:
5453 wbit = BYTE_OPND;
5454 goto just_mem;
5455
5456 case VMx:
5457 if (mode == 3) {
5458 #ifdef DIS_TEXT
5459 char *vminstr;
5460
5461 switch (r_m) {
5462 case 1:
5463 vminstr = "vmcall";
5464 break;
5465 case 2:
5466 vminstr = "vmlaunch";
5467 break;
5468 case 3:
5469 vminstr = "vmresume";
5470 break;
5471 case 4:
5472 vminstr = "vmxoff";
5473 break;
5474 default:
5475 goto error;
5476 }
5477
5478 (void) strncpy(x->d86_mnem, vminstr, OPLEN);
5479 #else
5480 if (r_m < 1 || r_m > 4)
5481 goto error;
5482 #endif
5483
5484 NOMEM;
5485 break;
5486 }
5487 /*FALLTHROUGH*/
5488 case SVM:
5489 if (mode == 3) {
5490 #if DIS_TEXT
5491 char *vinstr;
5492
5493 switch (r_m) {
5494 case 0:
5495 vinstr = "vmrun";
5496 break;
5497 case 1:
5498 vinstr = "vmmcall";
5499 break;
5500 case 2:
5501 vinstr = "vmload";
5502 break;
5503 case 3:
5504 vinstr = "vmsave";
5505 break;
5506 case 4:
5507 vinstr = "stgi";
5508 break;
5509 case 5:
5510 vinstr = "clgi";
5511 break;
5512 case 6:
5513 vinstr = "skinit";
5514 break;
5515 case 7:
5516 vinstr = "invlpga";
5517 break;
5518 }
5519
5520 (void) strncpy(x->d86_mnem, vinstr, OPLEN);
5521 #endif
5522 NOMEM;
5523 break;
5524 }
5525 /*FALLTHROUGH*/
5526 case MONITOR_MWAIT:
5527 if (mode == 3) {
5528 if (r_m == 0) {
5529 #ifdef DIS_TEXT
5530 (void) strncpy(x->d86_mnem, "monitor", OPLEN);
5531 #endif
5532 NOMEM;
5533 break;
5534 } else if (r_m == 1) {
5535 #ifdef DIS_TEXT
5536 (void) strncpy(x->d86_mnem, "mwait", OPLEN);
5537 #endif
5538 NOMEM;
5539 break;
5540 } else if (r_m == 2) {
5541 #ifdef DIS_TEXT
5542 (void) strncpy(x->d86_mnem, "clac", OPLEN);
5543 #endif
5544 NOMEM;
5545 break;
5546 } else if (r_m == 3) {
5547 #ifdef DIS_TEXT
5548 (void) strncpy(x->d86_mnem, "stac", OPLEN);
5549 #endif
5550 NOMEM;
5551 break;
5552 } else {
5553 goto error;
5554 }
5555 }
5556 /*FALLTHROUGH*/
5557 case XGETBV_XSETBV:
5558 if (mode == 3) {
5559 if (r_m == 0) {
5560 #ifdef DIS_TEXT
5561 (void) strncpy(x->d86_mnem, "xgetbv", OPLEN);
5562 #endif
5563 NOMEM;
5564 break;
5565 } else if (r_m == 1) {
5566 #ifdef DIS_TEXT
5567 (void) strncpy(x->d86_mnem, "xsetbv", OPLEN);
5568 #endif
5569 NOMEM;
5570 break;
5571 } else {
5572 goto error;
5573 }
5574
5575 }
5576 /*FALLTHROUGH*/
5577 case MO:
5578 /* Similar to M, but only memory (no direct registers) */
5579 wbit = LONG_OPND;
5580 dtrace_get_modrm(x, &mode, ®, &r_m);
5581 if (mode == 3)
5582 goto error;
5583 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
5584 dtrace_get_operand(x, mode, r_m, wbit, 0);
5585 break;
5586
5587 /* move special register to register or reverse if vbit */
5588 case SREG:
5589 switch (opcode5) {
5590
5591 case 2:
5592 vbit = 1;
5593 /*FALLTHROUGH*/
5594 case 0:
5595 wbit = CONTROL_OPND;
5596 break;
5597
5598 case 3:
5599 vbit = 1;
5600 /*FALLTHROUGH*/
5601 case 1:
5602 wbit = DEBUG_OPND;
5603 break;
5604
5605 case 6:
5606 vbit = 1;
5607 /*FALLTHROUGH*/
5608 case 4:
5609 wbit = TEST_OPND;
5610 break;
5611
5612 }
5613 dtrace_get_modrm(x, &mode, ®, &r_m);
5614 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
5615 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit);
5616 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 1 - vbit);
5617 NOMEM;
5618 break;
5619
5620 /*
5621 * single register operand with register in the low 3
5622 * bits of op code
5623 */
5624 case R:
5625 if (opcode_bytes == 2)
5626 reg = REGNO(opcode5);
5627 else
5628 reg = REGNO(opcode2);
5629 dtrace_rex_adjust(rex_prefix, mode, ®, NULL);
5630 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
5631 NOMEM;
5632 break;
5633
5634 /*
5635 * register to accumulator with register in the low 3
5636 * bits of op code, xchg instructions
5637 */
5638 case RA:
5639 NOMEM;
5640 reg = REGNO(opcode2);
5641 dtrace_rex_adjust(rex_prefix, mode, ®, NULL);
5642 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
5643 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, LONG_OPND, 1);
5644 break;
5645
5646 case RMATCH:
5647 x->d86_opnd_size = x->d86_mode;
5648 dtrace_get_modrm(x, &mode, ®, &r_m);
5649 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
5650 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);
5651 break;
5652
5653 /*
5654 * single segment register operand, with register in
5655 * bits 3-4 of op code byte
5656 */
5657 case SEG:
5658 NOMEM;
5659 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x3;
5660 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0);
5661 break;
5662
5663 /*
5664 * single segment register operand, with register in
5665 * bits 3-5 of op code
5666 */
5667 case LSEG:
5668 NOMEM;
5669 /* long seg reg from opcode */
5670 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x7;
5671 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0);
5672 break;
5673
5674 /* memory or register operand to register */
5675 case MR:
5676 if (vex_prefetch)
5677 x->d86_got_modrm = 1;
5678 wbit = LONG_OPND;
5679 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
5680 break;
5681
5682 case RM:
5683 case RM_66r:
5684 if (vex_prefetch)
5685 x->d86_got_modrm = 1;
5686 wbit = LONG_OPND;
5687 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
5688 break;
5689
5690 /* MMX/SIMD-Int memory or mm reg to mm reg */
5691 case MM:
5692 case MMO:
5693 #ifdef DIS_TEXT
5694 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND;
5695 #else
5696 wbit = LONG_OPND;
5697 #endif
5698 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0);
5699 break;
5700
5701 case MMOIMPL:
5702 #ifdef DIS_TEXT
5703 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND;
5704 #else
5705 wbit = LONG_OPND;
5706 #endif
5707 dtrace_get_modrm(x, &mode, ®, &r_m);
5708 if (mode != REG_ONLY)
5709 goto error;
5710
5711 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
5712 dtrace_get_operand(x, mode, r_m, wbit, 0);
5713 dtrace_get_operand(x, REG_ONLY, reg, MM_OPND, 1);
5714 mode = 0; /* change for memory access size... */
5715 break;
5716
5717 /* MMX/SIMD-Int and SIMD-FP predicated mm reg to r32 */
5718 case MMO3P:
5719 wbit = MM_OPND;
5720 goto xmm3p;
5721 case XMM3P:
5722 wbit = XMM_OPND;
5723 xmm3p:
5724 dtrace_get_modrm(x, &mode, ®, &r_m);
5725 if (mode != REG_ONLY)
5726 goto error;
5727
5728 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 1,
5729 1);
5730 NOMEM;
5731 break;
5732
5733 case XMM3PM_66r:
5734 THREEOPERAND(x, mode, reg, r_m, rex_prefix, LONG_OPND, XMM_OPND,
5735 1, 0);
5736 break;
5737
5738 /* MMX/SIMD-Int predicated r32/mem to mm reg */
5739 case MMOPRM:
5740 wbit = LONG_OPND;
5741 w2 = MM_OPND;
5742 goto xmmprm;
5743 case XMMPRM:
5744 case XMMPRM_66r:
5745 wbit = LONG_OPND;
5746 w2 = XMM_OPND;
5747 xmmprm:
5748 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, 1, 1);
5749 break;
5750
5751 /* MMX/SIMD-Int predicated mm/mem to mm reg */
5752 case MMOPM:
5753 case MMOPM_66o:
5754 wbit = w2 = MM_OPND;
5755 goto xmmprm;
5756
5757 /* MMX/SIMD-Int mm reg to r32 */
5758 case MMOM3:
5759 NOMEM;
5760 dtrace_get_modrm(x, &mode, ®, &r_m);
5761 if (mode != REG_ONLY)
5762 goto error;
5763 wbit = MM_OPND;
5764 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0);
5765 break;
5766
5767 /* SIMD memory or xmm reg operand to xmm reg */
5768 case XMM:
5769 case XMM_66o:
5770 case XMM_66r:
5771 case XMMO:
5772 case XMMXIMPL:
5773 wbit = XMM_OPND;
5774 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
5775
5776 if (dp->it_adrmode == XMMXIMPL && mode != REG_ONLY)
5777 goto error;
5778
5779 #ifdef DIS_TEXT
5780 /*
5781 * movlps and movhlps share opcodes. They differ in the
5782 * addressing modes allowed for their operands.
5783 * movhps and movlhps behave similarly.
5784 */
5785 if (mode == REG_ONLY) {
5786 if (strcmp(dp->it_name, "movlps") == 0)
5787 (void) strncpy(x->d86_mnem, "movhlps", OPLEN);
5788 else if (strcmp(dp->it_name, "movhps") == 0)
5789 (void) strncpy(x->d86_mnem, "movlhps", OPLEN);
5790 }
5791 #endif
5792 if (dp->it_adrmode == XMMXIMPL)
5793 mode = 0; /* change for memory access size... */
5794 break;
5795
5796 /* SIMD xmm reg to memory or xmm reg */
5797 case XMMS:
5798 case XMMOS:
5799 case XMMMS:
5800 case XMMOMS:
5801 dtrace_get_modrm(x, &mode, ®, &r_m);
5802 #ifdef DIS_TEXT
5803 if ((strcmp(dp->it_name, "movlps") == 0 ||
5804 strcmp(dp->it_name, "movhps") == 0 ||
5805 strcmp(dp->it_name, "movntps") == 0) &&
5806 mode == REG_ONLY)
5807 goto error;
5808 #endif
5809 wbit = XMM_OPND;
5810 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1);
5811 break;
5812
5813 /* SIMD memory to xmm reg */
5814 case XMMM:
5815 case XMMM_66r:
5816 case XMMOM:
5817 wbit = XMM_OPND;
5818 dtrace_get_modrm(x, &mode, ®, &r_m);
5819 #ifdef DIS_TEXT
5820 if (mode == REG_ONLY) {
5821 if (strcmp(dp->it_name, "movhps") == 0)
5822 (void) strncpy(x->d86_mnem, "movlhps", OPLEN);
5823 else
5824 goto error;
5825 }
5826 #endif
5827 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);
5828 break;
5829
5830 /* SIMD memory or r32 to xmm reg */
5831 case XMM3MX:
5832 wbit = LONG_OPND;
5833 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);
5834 break;
5835
5836 case XMM3MXS:
5837 wbit = LONG_OPND;
5838 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1);
5839 break;
5840
5841 /* SIMD memory or mm reg to xmm reg */
5842 case XMMOMX:
5843 /* SIMD mm to xmm */
5844 case XMMMX:
5845 wbit = MM_OPND;
5846 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);
5847 break;
5848
5849 /* SIMD memory or xmm reg to mm reg */
5850 case XMMXMM:
5851 case XMMOXMM:
5852 case XMMXM:
5853 wbit = XMM_OPND;
5854 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0);
5855 break;
5856
5857
5858 /* SIMD memory or xmm reg to r32 */
5859 case XMMXM3:
5860 wbit = XMM_OPND;
5861 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0);
5862 break;
5863
5864 /* SIMD xmm to r32 */
5865 case XMMX3:
5866 case XMMOX3:
5867 dtrace_get_modrm(x, &mode, ®, &r_m);
5868 if (mode != REG_ONLY)
5869 goto error;
5870 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
5871 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0);
5872 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
5873 NOMEM;
5874 break;
5875
5876 /* SIMD predicated memory or xmm reg with/to xmm reg */
5877 case XMMP:
5878 case XMMP_66r:
5879 case XMMP_66o:
5880 case XMMOPM:
5881 wbit = XMM_OPND;
5882 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1,
5883 1);
5884
5885 #ifdef DIS_TEXT
5886 /*
5887 * cmpps and cmpss vary their instruction name based
5888 * on the value of imm8. Other XMMP instructions,
5889 * such as shufps, require explicit specification of
5890 * the predicate.
5891 */
5892 if (dp->it_name[0] == 'c' &&
5893 dp->it_name[1] == 'm' &&
5894 dp->it_name[2] == 'p' &&
5895 strlen(dp->it_name) == 5) {
5896 uchar_t pred = x->d86_opnd[0].d86_value & 0xff;
5897
5898 if (pred >= (sizeof (dis_PREDSUFFIX) / sizeof (char *)))
5899 goto error;
5900
5901 (void) strncpy(x->d86_mnem, "cmp", OPLEN);
5902 (void) strlcat(x->d86_mnem, dis_PREDSUFFIX[pred],
5903 OPLEN);
5904 (void) strlcat(x->d86_mnem,
5905 dp->it_name + strlen(dp->it_name) - 2,
5906 OPLEN);
5907 x->d86_opnd[0] = x->d86_opnd[1];
5908 x->d86_opnd[1] = x->d86_opnd[2];
5909 x->d86_numopnds = 2;
5910 }
5911
5912 /*
5913 * The pclmulqdq instruction has a series of alternate names for
5914 * various encodings of the immediate byte. As such, if we
5915 * happen to find it and the immediate value matches, we'll
5916 * rewrite the mnemonic.
5917 */
5918 if (strcmp(dp->it_name, "pclmulqdq") == 0) {
5919 boolean_t changed = B_TRUE;
5920 switch (x->d86_opnd[0].d86_value) {
5921 case 0x00:
5922 (void) strncpy(x->d86_mnem, "pclmullqlqdq",
5923 OPLEN);
5924 break;
5925 case 0x01:
5926 (void) strncpy(x->d86_mnem, "pclmulhqlqdq",
5927 OPLEN);
5928 break;
5929 case 0x10:
5930 (void) strncpy(x->d86_mnem, "pclmullqhqdq",
5931 OPLEN);
5932 break;
5933 case 0x11:
5934 (void) strncpy(x->d86_mnem, "pclmulhqhqdq",
5935 OPLEN);
5936 break;
5937 default:
5938 changed = B_FALSE;
5939 break;
5940 }
5941
5942 if (changed == B_TRUE) {
5943 x->d86_opnd[0].d86_value_size = 0;
5944 x->d86_opnd[0] = x->d86_opnd[1];
5945 x->d86_opnd[1] = x->d86_opnd[2];
5946 x->d86_numopnds = 2;
5947 }
5948 }
5949 #endif
5950 break;
5951
5952 case XMMX2I:
5953 FOUROPERAND(x, mode, reg, r_m, rex_prefix, XMM_OPND, XMM_OPND,
5954 1);
5955 NOMEM;
5956 break;
5957
5958 case XMM2I:
5959 ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, XMM_OPND, 1);
5960 NOMEM;
5961 break;
5962
5963 /* immediate operand to accumulator */
5964 case IA:
5965 wbit = WBIT(opcode2);
5966 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1);
5967 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0);
5968 NOMEM;
5969 break;
5970
5971 /* memory or register operand to accumulator */
5972 case MA:
5973 wbit = WBIT(opcode2);
5974 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
5975 dtrace_get_operand(x, mode, r_m, wbit, 0);
5976 break;
5977
5978 /* si register to di register used to reference memory */
5979 case SD:
5980 #ifdef DIS_TEXT
5981 dtrace_check_override(x, 0);
5982 x->d86_numopnds = 2;
5983 if (addr_size == SIZE64) {
5984 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)",
5985 OPLEN);
5986 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)",
5987 OPLEN);
5988 } else if (addr_size == SIZE32) {
5989 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)",
5990 OPLEN);
5991 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)",
5992 OPLEN);
5993 } else {
5994 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)",
5995 OPLEN);
5996 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)",
5997 OPLEN);
5998 }
5999 #endif
6000 wbit = LONG_OPND;
6001 break;
6002
6003 /* accumulator to di register */
6004 case AD:
6005 wbit = WBIT(opcode2);
6006 #ifdef DIS_TEXT
6007 dtrace_check_override(x, 1);
6008 x->d86_numopnds = 2;
6009 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 0);
6010 if (addr_size == SIZE64)
6011 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)",
6012 OPLEN);
6013 else if (addr_size == SIZE32)
6014 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)",
6015 OPLEN);
6016 else
6017 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)",
6018 OPLEN);
6019 #endif
6020 break;
6021
6022 /* si register to accumulator */
6023 case SA:
6024 wbit = WBIT(opcode2);
6025 #ifdef DIS_TEXT
6026 dtrace_check_override(x, 0);
6027 x->d86_numopnds = 2;
6028 if (addr_size == SIZE64)
6029 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)",
6030 OPLEN);
6031 else if (addr_size == SIZE32)
6032 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)",
6033 OPLEN);
6034 else
6035 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)",
6036 OPLEN);
6037 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1);
6038 #endif
6039 break;
6040
6041 /*
6042 * single operand, a 16/32 bit displacement
6043 */
6044 case D:
6045 wbit = LONG_OPND;
6046 dtrace_disp_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0);
6047 NOMEM;
6048 break;
6049
6050 /* jmp/call indirect to memory or register operand */
6051 case INM:
6052 #ifdef DIS_TEXT
6053 (void) strlcat(x->d86_opnd[0].d86_prefix, "*", OPLEN);
6054 #endif
6055 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
6056 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);
6057 wbit = LONG_OPND;
6058 break;
6059
6060 /*
6061 * for long jumps and long calls -- a new code segment
6062 * register and an offset in IP -- stored in object
6063 * code in reverse order. Note - not valid in amd64
6064 */
6065 case SO:
6066 dtrace_check_override(x, 1);
6067 wbit = LONG_OPND;
6068 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 1);
6069 #ifdef DIS_TEXT
6070 x->d86_opnd[1].d86_mode = MODE_SIGNED;
6071 #endif
6072 /* will now get segment operand */
6073 dtrace_imm_opnd(x, wbit, 2, 0);
6074 break;
6075
6076 /*
6077 * jmp/call. single operand, 8 bit displacement.
6078 * added to current EIP in 'compofff'
6079 */
6080 case BD:
6081 dtrace_disp_opnd(x, BYTE_OPND, 1, 0);
6082 NOMEM;
6083 break;
6084
6085 /* single 32/16 bit immediate operand */
6086 case I:
6087 wbit = LONG_OPND;
6088 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0);
6089 break;
6090
6091 /* single 8 bit immediate operand */
6092 case Ib:
6093 wbit = LONG_OPND;
6094 dtrace_imm_opnd(x, wbit, 1, 0);
6095 break;
6096
6097 case ENTER:
6098 wbit = LONG_OPND;
6099 dtrace_imm_opnd(x, wbit, 2, 0);
6100 dtrace_imm_opnd(x, wbit, 1, 1);
6101 switch (opnd_size) {
6102 case SIZE64:
6103 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 8;
6104 break;
6105 case SIZE32:
6106 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 4;
6107 break;
6108 case SIZE16:
6109 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 2;
6110 break;
6111 }
6112
6113 break;
6114
6115 /* 16-bit immediate operand */
6116 case RET:
6117 wbit = LONG_OPND;
6118 dtrace_imm_opnd(x, wbit, 2, 0);
6119 break;
6120
6121 /* single 8 bit port operand */
6122 case P:
6123 dtrace_check_override(x, 0);
6124 dtrace_imm_opnd(x, BYTE_OPND, 1, 0);
6125 NOMEM;
6126 break;
6127
6128 /* single operand, dx register (variable port instruction) */
6129 case V:
6130 x->d86_numopnds = 1;
6131 dtrace_check_override(x, 0);
6132 #ifdef DIS_TEXT
6133 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%dx)", OPLEN);
6134 #endif
6135 NOMEM;
6136 break;
6137
6138 /*
6139 * The int instruction, which has two forms:
6140 * int 3 (breakpoint) or
6141 * int n, where n is indicated in the subsequent
6142 * byte (format Ib). The int 3 instruction (opcode 0xCC),
6143 * where, although the 3 looks like an operand,
6144 * it is implied by the opcode. It must be converted
6145 * to the correct base and output.
6146 */
6147 case INT3:
6148 #ifdef DIS_TEXT
6149 x->d86_numopnds = 1;
6150 x->d86_opnd[0].d86_mode = MODE_SIGNED;
6151 x->d86_opnd[0].d86_value_size = 1;
6152 x->d86_opnd[0].d86_value = 3;
6153 #endif
6154 NOMEM;
6155 break;
6156
6157 /* single 8 bit immediate operand */
6158 case INTx:
6159 dtrace_imm_opnd(x, BYTE_OPND, 1, 0);
6160 NOMEM;
6161 break;
6162
6163 /* an unused byte must be discarded */
6164 case U:
6165 if (x->d86_get_byte(x->d86_data) < 0)
6166 goto error;
6167 x->d86_len++;
6168 NOMEM;
6169 break;
6170
6171 case CBW:
6172 #ifdef DIS_TEXT
6173 if (opnd_size == SIZE16)
6174 (void) strlcat(x->d86_mnem, "cbtw", OPLEN);
6175 else if (opnd_size == SIZE32)
6176 (void) strlcat(x->d86_mnem, "cwtl", OPLEN);
6177 else
6178 (void) strlcat(x->d86_mnem, "cltq", OPLEN);
6179 #endif
6180 wbit = LONG_OPND;
6181 NOMEM;
6182 break;
6183
6184 case CWD:
6185 #ifdef DIS_TEXT
6186 if (opnd_size == SIZE16)
6187 (void) strlcat(x->d86_mnem, "cwtd", OPLEN);
6188 else if (opnd_size == SIZE32)
6189 (void) strlcat(x->d86_mnem, "cltd", OPLEN);
6190 else
6191 (void) strlcat(x->d86_mnem, "cqtd", OPLEN);
6192 #endif
6193 wbit = LONG_OPND;
6194 NOMEM;
6195 break;
6196
6197 case XMMSFNC:
6198 /*
6199 * sfence is sfence if mode is REG_ONLY. If mode isn't
6200 * REG_ONLY, mnemonic should be 'clflush'.
6201 */
6202 dtrace_get_modrm(x, &mode, ®, &r_m);
6203
6204 /* sfence doesn't take operands */
6205 if (mode != REG_ONLY) {
6206 if (opnd_size_prefix == 0x66) {
6207 #ifdef DIS_TEXT
6208 (void) strlcat(x->d86_mnem, "clflushopt",
6209 OPLEN);
6210 #endif
6211 } else if (opnd_size_prefix == 0) {
6212 #ifdef DIS_TEXT
6213 (void) strlcat(x->d86_mnem, "clflush", OPLEN);
6214 #endif
6215 } else {
6216 /* Unknown instruction */
6217 goto error;
6218 }
6219
6220 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
6221 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0);
6222 NOMEM;
6223 #ifdef DIS_TEXT
6224 } else {
6225 (void) strlcat(x->d86_mnem, "sfence", OPLEN);
6226 #endif
6227 }
6228 break;
6229
6230 case FSGS:
6231 /*
6232 * The FSGSBASE instructions are taken only when the mode is set
6233 * to registers. They share opcodes with instructions like
6234 * fxrstor, stmxcsr, etc. We handle the repz prefix earlier.
6235 */
6236 wbit = WBIT(opcode2);
6237 dtrace_get_modrm(x, &mode, ®, &r_m);
6238 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
6239 dtrace_get_operand(x, mode, r_m, wbit, 0);
6240 if (mode == REG_ONLY) {
6241 NOMEM;
6242 }
6243 break;
6244
6245 /*
6246 * no disassembly, the mnemonic was all there was so go on
6247 */
6248 case NORM:
6249 if (dp->it_invalid32 && cpu_mode != SIZE64)
6250 goto error;
6251 NOMEM;
6252 /*FALLTHROUGH*/
6253 case IMPLMEM:
6254 break;
6255
6256 case XMMFENCE:
6257 /*
6258 * XRSTOR, XSAVEOPT and LFENCE share the same opcode but
6259 * differ in mode and reg.
6260 */
6261 dtrace_get_modrm(x, &mode, ®, &r_m);
6262
6263 if (mode == REG_ONLY) {
6264 /*
6265 * Only the following exact byte sequences are allowed:
6266 *
6267 * 0f ae e8 lfence
6268 * 0f ae f0 mfence
6269 */
6270 if ((uint8_t)x->d86_bytes[x->d86_len - 1] != 0xe8 &&
6271 (uint8_t)x->d86_bytes[x->d86_len - 1] != 0xf0)
6272 goto error;
6273 } else {
6274 #ifdef DIS_TEXT
6275 if (reg == 5) {
6276 (void) strncpy(x->d86_mnem, "xrstor", OPLEN);
6277 } else if (reg == 6) {
6278 if (opnd_size_prefix == 0x66) {
6279 (void) strncpy(x->d86_mnem, "clwb",
6280 OPLEN);
6281 } else if (opnd_size_prefix == 0x00) {
6282 (void) strncpy(x->d86_mnem, "xsaveopt",
6283 OPLEN);
6284 } else {
6285 goto error;
6286 }
6287 } else {
6288 goto error;
6289 }
6290 #endif
6291 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
6292 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0);
6293 }
6294 break;
6295
6296 /* float reg */
6297 case F:
6298 #ifdef DIS_TEXT
6299 x->d86_numopnds = 1;
6300 (void) strlcat(x->d86_opnd[0].d86_opnd, "%st(X)", OPLEN);
6301 x->d86_opnd[0].d86_opnd[4] = r_m + '0';
6302 #endif
6303 NOMEM;
6304 break;
6305
6306 /* float reg to float reg, with ret bit present */
6307 case FF:
6308 vbit = opcode2 >> 2 & 0x1; /* vbit = 1: st -> st(i) */
6309 /*FALLTHROUGH*/
6310 case FFC: /* case for vbit always = 0 */
6311 #ifdef DIS_TEXT
6312 x->d86_numopnds = 2;
6313 (void) strlcat(x->d86_opnd[1 - vbit].d86_opnd, "%st", OPLEN);
6314 (void) strlcat(x->d86_opnd[vbit].d86_opnd, "%st(X)", OPLEN);
6315 x->d86_opnd[vbit].d86_opnd[4] = r_m + '0';
6316 #endif
6317 NOMEM;
6318 break;
6319
6320 /* AVX instructions */
6321 case VEX_MO:
6322 /* op(ModR/M.r/m) */
6323 x->d86_numopnds = 1;
6324 dtrace_get_modrm(x, &mode, ®, &r_m);
6325 #ifdef DIS_TEXT
6326 if ((dp == &dis_opAVX0F[0xA][0xE]) && (reg == 3))
6327 (void) strncpy(x->d86_mnem, "vstmxcsr", OPLEN);
6328 #endif
6329 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
6330 dtrace_get_operand(x, mode, r_m, wbit, 0);
6331 break;
6332 case VEX_RMrX:
6333 case FMA:
6334 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r/m) */
6335 x->d86_numopnds = 3;
6336 dtrace_get_modrm(x, &mode, ®, &r_m);
6337 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
6338
6339 /*
6340 * In classic Intel fashion, the opcodes for all of the FMA
6341 * instructions all have two possible mnemonics which vary by
6342 * one letter, which is selected based on the value of the wbit.
6343 * When wbit is one, they have the 'd' suffix and when 'wbit' is
6344 * 0, they have the 's' suffix. Otherwise, the FMA instructions
6345 * are all a standard VEX_RMrX.
6346 */
6347 #ifdef DIS_TEXT
6348 if (dp->it_adrmode == FMA) {
6349 size_t len = strlen(dp->it_name);
6350 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN);
6351 if (len + 1 < OPLEN) {
6352 (void) strncpy(x->d86_mnem + len,
6353 vex_W != 0 ? "d" : "s", OPLEN - len);
6354 }
6355 }
6356 #endif
6357
6358 if (mode != REG_ONLY) {
6359 if ((dp == &dis_opAVXF20F[0x10]) ||
6360 (dp == &dis_opAVXF30F[0x10])) {
6361 /* vmovsd <m64>, <xmm> */
6362 /* or vmovss <m64>, <xmm> */
6363 x->d86_numopnds = 2;
6364 goto L_VEX_MX;
6365 }
6366 }
6367
6368 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
6369 /*
6370 * VEX prefix uses the 1's complement form to encode the
6371 * XMM/YMM regs
6372 */
6373 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
6374
6375 if ((dp == &dis_opAVXF20F[0x2A]) ||
6376 (dp == &dis_opAVXF30F[0x2A])) {
6377 /*
6378 * vcvtsi2si </r,m>, <xmm>, <xmm> or vcvtsi2ss </r,m>,
6379 * <xmm>, <xmm>
6380 */
6381 wbit = LONG_OPND;
6382 }
6383 #ifdef DIS_TEXT
6384 else if ((mode == REG_ONLY) &&
6385 (dp == &dis_opAVX0F[0x1][0x6])) { /* vmovlhps */
6386 (void) strncpy(x->d86_mnem, "vmovlhps", OPLEN);
6387 } else if ((mode == REG_ONLY) &&
6388 (dp == &dis_opAVX0F[0x1][0x2])) { /* vmovhlps */
6389 (void) strncpy(x->d86_mnem, "vmovhlps", OPLEN);
6390 }
6391 #endif
6392 dtrace_get_operand(x, mode, r_m, wbit, 0);
6393
6394 break;
6395
6396 case VEX_VRMrX:
6397 /* ModR/M.reg := op(MODR/M.r/m, VEX.vvvv) */
6398 x->d86_numopnds = 3;
6399 dtrace_get_modrm(x, &mode, ®, &r_m);
6400 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
6401
6402 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
6403 /*
6404 * VEX prefix uses the 1's complement form to encode the
6405 * XMM/YMM regs
6406 */
6407 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 0);
6408
6409 dtrace_get_operand(x, mode, r_m, wbit, 1);
6410 break;
6411
6412 case VEX_SbVM:
6413 /* ModR/M.reg := op(MODR/M.r/m, VSIB, VEX.vvvv) */
6414 x->d86_numopnds = 3;
6415 x->d86_vsib = 1;
6416
6417 /*
6418 * All instructions that use VSIB are currently a mess. See the
6419 * comment around the dis_gather_regs_t structure definition.
6420 */
6421
6422 vreg = &dis_vgather[opcode2][vex_W][vex_L];
6423
6424 #ifdef DIS_TEXT
6425 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN);
6426 (void) strlcat(x->d86_mnem + strlen(dp->it_name),
6427 vreg->dgr_suffix, OPLEN - strlen(dp->it_name));
6428 #endif
6429
6430 dtrace_get_modrm(x, &mode, ®, &r_m);
6431 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
6432
6433 dtrace_get_operand(x, REG_ONLY, reg, vreg->dgr_arg2, 2);
6434 /*
6435 * VEX prefix uses the 1's complement form to encode the
6436 * XMM/YMM regs
6437 */
6438 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), vreg->dgr_arg0,
6439 0);
6440 dtrace_get_operand(x, mode, r_m, vreg->dgr_arg1, 1);
6441 break;
6442
6443 case VEX_RRX:
6444 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */
6445 x->d86_numopnds = 3;
6446
6447 dtrace_get_modrm(x, &mode, ®, &r_m);
6448 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
6449
6450 if (mode != REG_ONLY) {
6451 if ((dp == &dis_opAVXF20F[0x11]) ||
6452 (dp == &dis_opAVXF30F[0x11])) {
6453 /* vmovsd <xmm>, <m64> */
6454 /* or vmovss <xmm>, <m64> */
6455 x->d86_numopnds = 2;
6456 goto L_VEX_RM;
6457 }
6458 }
6459
6460 dtrace_get_operand(x, mode, r_m, wbit, 2);
6461 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
6462 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
6463 break;
6464
6465 case VEX_RMRX:
6466 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r_m, imm8[7:4]) */
6467 x->d86_numopnds = 4;
6468
6469 dtrace_get_modrm(x, &mode, ®, &r_m);
6470 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
6471 dtrace_get_operand(x, REG_ONLY, reg, wbit, 3);
6472 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2);
6473 if (dp == &dis_opAVX660F3A[0x18]) {
6474 /* vinsertf128 <imm8>, <xmm>, <ymm>, <ymm> */
6475 dtrace_get_operand(x, mode, r_m, XMM_OPND, 1);
6476 } else if ((dp == &dis_opAVX660F3A[0x20]) ||
6477 (dp == & dis_opAVX660F[0xC4])) {
6478 /* vpinsrb <imm8>, <reg/mm>, <xmm>, <xmm> */
6479 /* or vpinsrw <imm8>, <reg/mm>, <xmm>, <xmm> */
6480 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
6481 } else if (dp == &dis_opAVX660F3A[0x22]) {
6482 /* vpinsrd/q <imm8>, <reg/mm>, <xmm>, <xmm> */
6483 #ifdef DIS_TEXT
6484 if (vex_W)
6485 x->d86_mnem[6] = 'q';
6486 #endif
6487 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
6488 } else {
6489 dtrace_get_operand(x, mode, r_m, wbit, 1);
6490 }
6491
6492 /* one byte immediate number */
6493 dtrace_imm_opnd(x, wbit, 1, 0);
6494
6495 /* vblendvpd, vblendvps, vblendvb use the imm encode the regs */
6496 if ((dp == &dis_opAVX660F3A[0x4A]) ||
6497 (dp == &dis_opAVX660F3A[0x4B]) ||
6498 (dp == &dis_opAVX660F3A[0x4C])) {
6499 #ifdef DIS_TEXT
6500 int regnum = (x->d86_opnd[0].d86_value & 0xF0) >> 4;
6501 #endif
6502 x->d86_opnd[0].d86_mode = MODE_NONE;
6503 #ifdef DIS_TEXT
6504 if (vex_L)
6505 (void) strncpy(x->d86_opnd[0].d86_opnd,
6506 dis_YMMREG[regnum], OPLEN);
6507 else
6508 (void) strncpy(x->d86_opnd[0].d86_opnd,
6509 dis_XMMREG[regnum], OPLEN);
6510 #endif
6511 }
6512 break;
6513
6514 case VEX_MX:
6515 /* ModR/M.reg := op(ModR/M.rm) */
6516 x->d86_numopnds = 2;
6517
6518 dtrace_get_modrm(x, &mode, ®, &r_m);
6519 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
6520 L_VEX_MX:
6521
6522 if ((dp == &dis_opAVXF20F[0xE6]) ||
6523 (dp == &dis_opAVX660F[0x5A]) ||
6524 (dp == &dis_opAVX660F[0xE6])) {
6525 /* vcvtpd2dq <ymm>, <xmm> */
6526 /* or vcvtpd2ps <ymm>, <xmm> */
6527 /* or vcvttpd2dq <ymm>, <xmm> */
6528 dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1);
6529 dtrace_get_operand(x, mode, r_m, wbit, 0);
6530 } else if ((dp == &dis_opAVXF30F[0xE6]) ||
6531 (dp == &dis_opAVX0F[0x5][0xA]) ||
6532 (dp == &dis_opAVX660F38[0x13]) ||
6533 (dp == &dis_opAVX660F38[0x18]) ||
6534 (dp == &dis_opAVX660F38[0x19]) ||
6535 (dp == &dis_opAVX660F38[0x58]) ||
6536 (dp == &dis_opAVX660F38[0x78]) ||
6537 (dp == &dis_opAVX660F38[0x79]) ||
6538 (dp == &dis_opAVX660F38[0x59])) {
6539 /* vcvtdq2pd <xmm>, <ymm> */
6540 /* or vcvtps2pd <xmm>, <ymm> */
6541 /* or vcvtph2ps <xmm>, <ymm> */
6542 /* or vbroadcasts* <xmm>, <ymm> */
6543 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
6544 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0);
6545 } else if (dp == &dis_opAVX660F[0x6E]) {
6546 /* vmovd/q <reg/mem 32/64>, <xmm> */
6547 #ifdef DIS_TEXT
6548 if (vex_W)
6549 x->d86_mnem[4] = 'q';
6550 #endif
6551 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
6552 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);
6553 } else {
6554 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
6555 dtrace_get_operand(x, mode, r_m, wbit, 0);
6556 }
6557
6558 break;
6559
6560 case VEX_MXI:
6561 /* ModR/M.reg := op(ModR/M.rm, imm8) */
6562 x->d86_numopnds = 3;
6563
6564 dtrace_get_modrm(x, &mode, ®, &r_m);
6565 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
6566
6567 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
6568 dtrace_get_operand(x, mode, r_m, wbit, 1);
6569
6570 /* one byte immediate number */
6571 dtrace_imm_opnd(x, wbit, 1, 0);
6572 break;
6573
6574 case VEX_XXI:
6575 /* VEX.vvvv := op(ModR/M.rm, imm8) */
6576 x->d86_numopnds = 3;
6577
6578 dtrace_get_modrm(x, &mode, ®, &r_m);
6579 #ifdef DIS_TEXT
6580 (void) strncpy(x->d86_mnem, dis_AVXvgrp7[opcode2 - 1][reg],
6581 OPLEN);
6582 #endif
6583 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
6584
6585 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2);
6586 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 1);
6587
6588 /* one byte immediate number */
6589 dtrace_imm_opnd(x, wbit, 1, 0);
6590 break;
6591
6592 case VEX_MR:
6593 /* ModR/M.reg (reg32/64) := op(ModR/M.rm) */
6594 if (dp == &dis_opAVX660F[0xC5]) {
6595 /* vpextrw <imm8>, <xmm>, <reg> */
6596 x->d86_numopnds = 2;
6597 vbit = 2;
6598 } else {
6599 x->d86_numopnds = 2;
6600 vbit = 1;
6601 }
6602
6603 dtrace_get_modrm(x, &mode, ®, &r_m);
6604 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
6605 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, vbit);
6606 dtrace_get_operand(x, mode, r_m, wbit, vbit - 1);
6607
6608 if (vbit == 2)
6609 dtrace_imm_opnd(x, wbit, 1, 0);
6610
6611 break;
6612
6613 case VEX_KMR:
6614 /* opmask: mod_rm := %k */
6615 x->d86_numopnds = 2;
6616 dtrace_get_modrm(x, &mode, ®, &r_m);
6617 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
6618 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
6619 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
6620 break;
6621
6622 case VEX_KRM:
6623 /* opmask: mod_reg := mod_rm */
6624 x->d86_numopnds = 2;
6625 dtrace_get_modrm(x, &mode, ®, &r_m);
6626 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
6627 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
6628 if (mode == REG_ONLY) {
6629 dtrace_get_operand(x, mode, r_m, KOPMASK_OPND, 0);
6630 } else {
6631 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);
6632 }
6633 break;
6634
6635 case VEX_KRR:
6636 /* opmask: mod_reg := mod_rm */
6637 x->d86_numopnds = 2;
6638 dtrace_get_modrm(x, &mode, ®, &r_m);
6639 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
6640 dtrace_get_operand(x, mode, reg, wbit, 1);
6641 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 0);
6642 break;
6643
6644 case VEX_RRI:
6645 /* implicit(eflags/r32) := op(ModR/M.reg, ModR/M.rm) */
6646 x->d86_numopnds = 2;
6647
6648 dtrace_get_modrm(x, &mode, ®, &r_m);
6649 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
6650 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
6651 dtrace_get_operand(x, mode, r_m, wbit, 0);
6652 break;
6653
6654 case VEX_RX:
6655 /* ModR/M.rm := op(ModR/M.reg) */
6656 /* vextractf128 || vcvtps2ph */
6657 if (dp == &dis_opAVX660F3A[0x19] ||
6658 dp == &dis_opAVX660F3A[0x1d]) {
6659 x->d86_numopnds = 3;
6660
6661 dtrace_get_modrm(x, &mode, ®, &r_m);
6662 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
6663
6664 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2);
6665 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
6666
6667 /* one byte immediate number */
6668 dtrace_imm_opnd(x, wbit, 1, 0);
6669 break;
6670 }
6671
6672 x->d86_numopnds = 2;
6673
6674 dtrace_get_modrm(x, &mode, ®, &r_m);
6675 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
6676 dtrace_get_operand(x, mode, r_m, wbit, 1);
6677 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
6678 break;
6679
6680 case VEX_RR:
6681 /* ModR/M.rm := op(ModR/M.reg) */
6682 x->d86_numopnds = 2;
6683
6684 dtrace_get_modrm(x, &mode, ®, &r_m);
6685 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
6686
6687 if (dp == &dis_opAVX660F[0x7E]) {
6688 /* vmovd/q <reg/mem 32/64>, <xmm> */
6689 #ifdef DIS_TEXT
6690 if (vex_W)
6691 x->d86_mnem[4] = 'q';
6692 #endif
6693 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
6694 } else
6695 dtrace_get_operand(x, mode, r_m, wbit, 1);
6696
6697 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
6698 break;
6699
6700 case VEX_RRi:
6701 /* ModR/M.rm := op(ModR/M.reg, imm) */
6702 x->d86_numopnds = 3;
6703
6704 dtrace_get_modrm(x, &mode, ®, &r_m);
6705 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
6706
6707 #ifdef DIS_TEXT
6708 if (dp == &dis_opAVX660F3A[0x16]) {
6709 /* vpextrd/q <imm>, <xmm>, <reg/mem 32/64> */
6710 if (vex_W)
6711 x->d86_mnem[6] = 'q';
6712 }
6713 #endif
6714 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2);
6715 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
6716
6717 /* one byte immediate number */
6718 dtrace_imm_opnd(x, wbit, 1, 0);
6719 break;
6720 case VEX_RIM:
6721 /* ModR/M.rm := op(ModR/M.reg, imm) */
6722 x->d86_numopnds = 3;
6723
6724 dtrace_get_modrm(x, &mode, ®, &r_m);
6725 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
6726
6727 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2);
6728 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
6729 /* one byte immediate number */
6730 dtrace_imm_opnd(x, wbit, 1, 0);
6731 break;
6732
6733 case VEX_RM:
6734 /* ModR/M.rm := op(ModR/M.reg) */
6735 if (dp == &dis_opAVX660F3A[0x17]) { /* vextractps */
6736 x->d86_numopnds = 3;
6737
6738 dtrace_get_modrm(x, &mode, ®, &r_m);
6739 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
6740
6741 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2);
6742 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
6743 /* one byte immediate number */
6744 dtrace_imm_opnd(x, wbit, 1, 0);
6745 break;
6746 }
6747 x->d86_numopnds = 2;
6748
6749 dtrace_get_modrm(x, &mode, ®, &r_m);
6750 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
6751 L_VEX_RM:
6752 vbit = 1;
6753 dtrace_get_operand(x, mode, r_m, wbit, vbit);
6754 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit - 1);
6755
6756 break;
6757
6758 case VEX_RRM:
6759 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */
6760 x->d86_numopnds = 3;
6761
6762 dtrace_get_modrm(x, &mode, ®, &r_m);
6763 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
6764 dtrace_get_operand(x, mode, r_m, wbit, 2);
6765 /* VEX use the 1's complement form encode the XMM/YMM regs */
6766 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
6767 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
6768 break;
6769
6770 case VEX_RMX:
6771 /* ModR/M.reg := op(VEX.vvvv, ModR/M.rm) */
6772 x->d86_numopnds = 3;
6773
6774 dtrace_get_modrm(x, &mode, ®, &r_m);
6775 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
6776 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
6777 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
6778 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 0);
6779 break;
6780
6781 case VEX_NONE:
6782 #ifdef DIS_TEXT
6783 if (vex_L)
6784 (void) strncpy(x->d86_mnem, "vzeroall", OPLEN);
6785 #endif
6786 break;
6787 case BLS: {
6788
6789 /*
6790 * The BLS instructions are VEX instructions that are based on
6791 * VEX.0F38.F3; however, they are considered special group 17
6792 * and like everything else, they use the bits in 3-5 of the
6793 * MOD R/M to determine the sub instruction. Unlike many others
6794 * like the VMX instructions, these are valid both for memory
6795 * and register forms.
6796 */
6797
6798 dtrace_get_modrm(x, &mode, ®, &r_m);
6799 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
6800
6801 switch (reg) {
6802 case 1:
6803 #ifdef DIS_TEXT
6804 blsinstr = "blsr";
6805 #endif
6806 break;
6807 case 2:
6808 #ifdef DIS_TEXT
6809 blsinstr = "blsmsk";
6810 #endif
6811 break;
6812 case 3:
6813 #ifdef DIS_TEXT
6814 blsinstr = "blsi";
6815 #endif
6816 break;
6817 default:
6818 goto error;
6819 }
6820
6821 x->d86_numopnds = 2;
6822 #ifdef DIS_TEXT
6823 (void) strncpy(x->d86_mnem, blsinstr, OPLEN);
6824 #endif
6825 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
6826 dtrace_get_operand(x, mode, r_m, wbit, 0);
6827 break;
6828 }
6829 case EVEX_MX:
6830 /* ModR/M.reg := op(ModR/M.rm) */
6831 x->d86_numopnds = 2;
6832 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2);
6833 dtrace_get_modrm(x, &mode, ®, &r_m);
6834 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff;
6835 dtrace_evex_adjust_reg(evex_byte1, ®);
6836 dtrace_evex_adjust_rm(evex_byte1, &r_m);
6837 dtrace_evex_adjust_reg_name(evex_L, &wbit);
6838 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
6839 dtrace_evex_adjust_z_opmask(x, 1, evex_byte3);
6840 dtrace_get_operand(x, mode, r_m, wbit, 0);
6841 dtrace_evex_adjust_disp8_n(x, 0, evex_modrm, EVEX_DISP8_MEM,
6842 evex_L, evex_b, vex_W);
6843 break;
6844 case EVEX_MXT1S8B:
6845 /* ModR/M.reg := op(ModR/M.rm) Tuple1 8-bit Scalar */
6846 x->d86_numopnds = 2;
6847 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2);
6848 dtrace_get_modrm(x, &mode, ®, &r_m);
6849 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff;
6850 dtrace_evex_adjust_reg(evex_byte1, ®);
6851 dtrace_evex_adjust_rm(evex_byte1, &r_m);
6852 dtrace_evex_adjust_reg_name(evex_L, &wbit);
6853 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
6854 dtrace_evex_adjust_z_opmask(x, 1, evex_byte3);
6855 dtrace_get_operand(x, mode, r_m, wbit, 0);
6856 dtrace_evex_adjust_disp8_n(x, 0, evex_modrm, EVEX_DISP8_T1S_8B,
6857 evex_L, evex_b, vex_W);
6858 break;
6859 case EVEX_MBX:
6860 /* ModR/M.reg := op(ModR/M.rm/M.bcast) */
6861 x->d86_numopnds = 2;
6862 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2);
6863 dtrace_get_modrm(x, &mode, ®, &r_m);
6864 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff;
6865 dtrace_evex_adjust_reg(evex_byte1, ®);
6866 dtrace_evex_adjust_rm(evex_byte1, &r_m);
6867 dtrace_evex_adjust_reg_name(evex_L, &wbit);
6868 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
6869 dtrace_evex_adjust_z_opmask(x, 1, evex_byte3);
6870 dtrace_get_operand(x, mode, r_m, wbit, 0);
6871 dtrace_evex_adjust_disp8_n(x, 0, evex_modrm, EVEX_DISP8_BCAST,
6872 evex_L, evex_b, vex_W);
6873 dtrace_evex_adjust_bcast(x, 0, vex_W, wbit, evex_b);
6874 break;
6875 case EVEX_RX:
6876 /* ModR/M.rm := op(ModR/M.reg) */
6877 x->d86_numopnds = 2;
6878 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2);
6879 dtrace_get_modrm(x, &mode, ®, &r_m);
6880 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff;
6881 dtrace_evex_adjust_reg(evex_byte1, ®);
6882 dtrace_evex_adjust_rm(evex_byte1, &r_m);
6883 dtrace_evex_adjust_reg_name(evex_L, &wbit);
6884 dtrace_get_operand(x, mode, r_m, wbit, 1);
6885 dtrace_evex_adjust_disp8_n(x, 1, evex_modrm, EVEX_DISP8_MEM,
6886 evex_L, evex_b, vex_W);
6887 dtrace_evex_adjust_z_opmask(x, 1, evex_byte3);
6888 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
6889 break;
6890 case EVEX_RXT1S8B:
6891 /* ModR/M.rm := op(ModR/M.reg) Tuple1 8-bit Scalar */
6892 x->d86_numopnds = 2;
6893 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2);
6894 dtrace_get_modrm(x, &mode, ®, &r_m);
6895 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff;
6896 dtrace_evex_adjust_reg(evex_byte1, ®);
6897 dtrace_evex_adjust_rm(evex_byte1, &r_m);
6898 dtrace_evex_adjust_reg_name(evex_L, &wbit);
6899 dtrace_get_operand(x, mode, r_m, wbit, 1);
6900 dtrace_evex_adjust_disp8_n(x, 1, evex_modrm, EVEX_DISP8_T1S_8B,
6901 evex_L, evex_b, vex_W);
6902 dtrace_evex_adjust_z_opmask(x, 1, evex_byte3);
6903 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
6904 break;
6905 case EVEX_RMrX:
6906 /* ModR/M.reg := op(EVEX.vvvv, ModR/M.r/m) */
6907 x->d86_numopnds = 3;
6908 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2);
6909 dtrace_get_modrm(x, &mode, ®, &r_m);
6910 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff;
6911 dtrace_evex_adjust_reg(evex_byte1, ®);
6912 dtrace_evex_adjust_rm(evex_byte1, &r_m);
6913 dtrace_evex_adjust_reg_name(evex_L, &wbit);
6914 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
6915 /*
6916 * EVEX.vvvv is the same as VEX.vvvv (ones complement of the
6917 * register specifier). The EVEX prefix handling uses the vex_v
6918 * variable for these bits.
6919 */
6920 dtrace_get_operand(x, REG_ONLY, (0x1F - vex_v), wbit, 1);
6921 dtrace_get_operand(x, mode, r_m, wbit, 0);
6922 dtrace_evex_adjust_disp8_n(x, 0, evex_modrm, EVEX_DISP8_MEM,
6923 evex_L, evex_b, vex_W);
6924 dtrace_evex_adjust_z_opmask(x, 2, evex_byte3);
6925 break;
6926 case EVEX_RMBrX:
6927 /* ModR/M.reg := op(EVEX.vvvv, ModR/M.r/m) */
6928 x->d86_numopnds = 3;
6929 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2);
6930 dtrace_get_modrm(x, &mode, ®, &r_m);
6931 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff;
6932 dtrace_evex_adjust_reg(evex_byte1, ®);
6933 dtrace_evex_adjust_rm(evex_byte1, &r_m);
6934 dtrace_evex_adjust_reg_name(evex_L, &wbit);
6935 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
6936 /*
6937 * EVEX.vvvv is the same as VEX.vvvv (ones complement of the
6938 * register specifier). The EVEX prefix handling uses the vex_v
6939 * variable for these bits.
6940 */
6941 dtrace_get_operand(x, REG_ONLY, (0x1F - vex_v), wbit, 1);
6942 dtrace_get_operand(x, mode, r_m, wbit, 0);
6943 dtrace_evex_adjust_disp8_n(x, 0, evex_modrm, EVEX_DISP8_BCAST,
6944 evex_L, evex_b, vex_W);
6945 dtrace_evex_adjust_z_opmask(x, 2, evex_byte3);
6946 dtrace_evex_adjust_bcast(x, 0, vex_W, wbit, evex_b);
6947 break;
6948 case EVEX_RMrK:
6949 /* opmask := op(EVEX.vvvv, ModR/M.r/m) */
6950 x->d86_numopnds = 3;
6951 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2);
6952 dtrace_get_modrm(x, &mode, ®, &r_m);
6953 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff;
6954 dtrace_evex_adjust_reg(evex_byte1, ®);
6955 dtrace_evex_adjust_rm(evex_byte1, &r_m);
6956 dtrace_evex_adjust_reg_name(evex_L, &wbit);
6957 dtrace_get_operand(x, REG_ONLY, reg, KOPMASK_OPND, 2);
6958 /*
6959 * EVEX.vvvv is the same as VEX.vvvv (ones complement of the
6960 * register specifier). The EVEX prefix handling uses the vex_v
6961 * variable for these bits.
6962 */
6963 dtrace_get_operand(x, REG_ONLY, (0x1F - vex_v), wbit, 1);
6964 dtrace_get_operand(x, mode, r_m, wbit, 0);
6965 dtrace_evex_adjust_disp8_n(x, 0, evex_modrm, EVEX_DISP8_MEM,
6966 evex_L, evex_b, vex_W);
6967 dtrace_evex_adjust_z_opmask(x, 2, evex_byte3);
6968 break;
6969 case EVEX_KR:
6970 /* mod_reg := op(mod_r/m (opmask only)) */
6971 x->d86_numopnds = 2;
6972
6973 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2);
6974 dtrace_get_modrm(x, &mode, ®, &r_m);
6975 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff;
6976 dtrace_evex_adjust_reg(evex_byte1, ®);
6977 dtrace_evex_adjust_rm(evex_byte1, &r_m);
6978 dtrace_evex_adjust_reg_name(evex_L, &wbit);
6979 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
6980 dtrace_get_operand(x, REG_ONLY, r_m, KOPMASK_OPND, 0);
6981 break;
6982 case EVEX_RMRX:
6983 /* ModR/M.reg := op(EVEX.vvvv, ModR/M.r_m, imm8) */
6984 x->d86_numopnds = 4;
6985
6986 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2);
6987 dtrace_get_modrm(x, &mode, ®, &r_m);
6988 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff;
6989 dtrace_evex_adjust_reg(evex_byte1, ®);
6990 dtrace_evex_adjust_rm(evex_byte1, &r_m);
6991 dtrace_evex_adjust_reg_name(evex_L, &wbit);
6992 dtrace_get_operand(x, REG_ONLY, reg, wbit, 3);
6993 /*
6994 * EVEX.vvvv is the same as VEX.vvvv (ones complement of the
6995 * register specifier). The EVEX prefix handling uses the vex_v
6996 * variable for these bits.
6997 */
6998 dtrace_get_operand(x, REG_ONLY, (0x1F - vex_v), wbit, 2);
6999 dtrace_get_operand(x, mode, r_m, wbit, 1);
7000 dtrace_evex_adjust_disp8_n(x, 1, evex_modrm, EVEX_DISP8_MEM,
7001 evex_L, evex_b, vex_W);
7002 dtrace_evex_adjust_z_opmask(x, 3, evex_byte3);
7003
7004 dtrace_imm_opnd(x, wbit, 1, 0);
7005 break;
7006 case EVEX_RMBRX:
7007 /* ModR/M.reg := op(EVEX.vvvv, ModR/M.r_m/bcast, imm8) */
7008 x->d86_numopnds = 4;
7009
7010 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2);
7011 dtrace_get_modrm(x, &mode, ®, &r_m);
7012 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff;
7013 dtrace_evex_adjust_reg(evex_byte1, ®);
7014 dtrace_evex_adjust_rm(evex_byte1, &r_m);
7015 dtrace_evex_adjust_reg_name(evex_L, &wbit);
7016 dtrace_get_operand(x, REG_ONLY, reg, wbit, 3);
7017 /*
7018 * EVEX.vvvv is the same as VEX.vvvv (ones complement of the
7019 * register specifier). The EVEX prefix handling uses the vex_v
7020 * variable for these bits.
7021 */
7022 dtrace_get_operand(x, REG_ONLY, (0x1F - vex_v), wbit, 2);
7023 dtrace_get_operand(x, mode, r_m, wbit, 1);
7024 dtrace_evex_adjust_disp8_n(x, 1, evex_modrm, EVEX_DISP8_BCAST,
7025 evex_L, evex_b, vex_W);
7026 dtrace_evex_adjust_bcast(x, 1, vex_W, wbit, evex_b);
7027 dtrace_evex_adjust_z_opmask(x, 3, evex_byte3);
7028
7029 dtrace_imm_opnd(x, wbit, 1, 0);
7030 break;
7031
7032 case MOVDIR:
7033 /*
7034 * The semantics of the movdir64b instruction is a little bit
7035 * weird and we need to trick the rest of the engine. In this
7036 * case we change d86_mode to match the operand/address size
7037 * that we overrode to earlier. Basically the standard CPU mode
7038 * doesn't actually influence which register set is used, but
7039 * the 0x67 prefix does.
7040 */
7041 x->d86_numopnds = 2;
7042 x->d86_mode = x->d86_opnd_size;
7043 dtrace_get_modrm(x, &mode, ®, &r_m);
7044 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
7045 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
7046 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);
7047 break;
7048 /* an invalid op code */
7049 case AM:
7050 case DM:
7051 case OVERRIDE:
7052 case PREFIX:
7053 case UNKNOWN:
7054 NOMEM;
7055 default:
7056 goto error;
7057 } /* end switch */
7058 if (x->d86_error)
7059 goto error;
7060
7061 done:
7062 #ifdef DIS_MEM
7063 if (dp == NULL)
7064 return (1);
7065 /*
7066 * compute the size of any memory accessed by the instruction
7067 */
7068 if (x->d86_memsize != 0) {
7069 return (0);
7070 } else if (dp->it_stackop) {
7071 switch (opnd_size) {
7072 case SIZE16:
7073 x->d86_memsize = 2;
7074 break;
7075 case SIZE32:
7076 x->d86_memsize = 4;
7077 break;
7078 case SIZE64:
7079 x->d86_memsize = 8;
7080 break;
7081 }
7082 } else if (nomem || mode == REG_ONLY) {
7083 x->d86_memsize = 0;
7084
7085 } else if (dp->it_size != 0) {
7086 /*
7087 * In 64 bit mode descriptor table entries
7088 * go up to 10 bytes and popf/pushf are always 8 bytes
7089 */
7090 if (x->d86_mode == SIZE64 && dp->it_size == 6)
7091 x->d86_memsize = 10;
7092 else if (x->d86_mode == SIZE64 && opcode1 == 0x9 &&
7093 (opcode2 == 0xc || opcode2 == 0xd))
7094 x->d86_memsize = 8;
7095 else
7096 x->d86_memsize = dp->it_size;
7097
7098 } else if (wbit == 0) {
7099 x->d86_memsize = 1;
7100
7101 } else if (wbit == LONG_OPND) {
7102 if (opnd_size == SIZE64)
7103 x->d86_memsize = 8;
7104 else if (opnd_size == SIZE32)
7105 x->d86_memsize = 4;
7106 else
7107 x->d86_memsize = 2;
7108
7109 } else if (wbit == SEG_OPND) {
7110 x->d86_memsize = 4;
7111
7112 } else {
7113 x->d86_memsize = 8;
7114 }
7115 #endif
7116 return (0);
7117
7118 error:
7119 #ifdef DIS_TEXT
7120 (void) strlcat(x->d86_mnem, "undef", OPLEN);
7121 #endif
7122 return (1);
7123 }
7124
7125 #ifdef DIS_TEXT
7126
7127 /*
7128 * Some instructions should have immediate operands printed
7129 * as unsigned integers. We compare against this table.
7130 */
7131 static char *unsigned_ops[] = {
7132 "or", "and", "xor", "test", "in", "out", "lcall", "ljmp",
7133 "rcr", "rcl", "ror", "rol", "shl", "shr", "sal", "psr", "psl",
7134 0
7135 };
7136
7137
7138 static int
isunsigned_op(char * opcode)7139 isunsigned_op(char *opcode)
7140 {
7141 char *where;
7142 int i;
7143 int is_unsigned = 0;
7144
7145 /*
7146 * Work back to start of last mnemonic, since we may have
7147 * prefixes on some opcodes.
7148 */
7149 where = opcode + strlen(opcode) - 1;
7150 while (where > opcode && *where != ' ')
7151 --where;
7152 if (*where == ' ')
7153 ++where;
7154
7155 for (i = 0; unsigned_ops[i]; ++i) {
7156 if (strncmp(where, unsigned_ops[i],
7157 strlen(unsigned_ops[i])))
7158 continue;
7159 is_unsigned = 1;
7160 break;
7161 }
7162 return (is_unsigned);
7163 }
7164
7165 /*
7166 * Print a numeric immediate into end of buf, maximum length buflen.
7167 * The immediate may be an address or a displacement. Mask is set
7168 * for address size. If the immediate is a "small negative", or
7169 * if it's a negative displacement of any magnitude, print as -<absval>.
7170 * Respect the "octal" flag. "Small negative" is defined as "in the
7171 * interval [NEG_LIMIT, 0)".
7172 *
7173 * Also, "isunsigned_op()" instructions never print negatives.
7174 *
7175 * Return whether we decided to print a negative value or not.
7176 */
7177
7178 #define NEG_LIMIT -255
7179 enum {IMM, DISP};
7180 enum {POS, TRY_NEG};
7181
7182 static int
print_imm(dis86_t * dis,uint64_t usv,uint64_t mask,char * buf,size_t buflen,int disp,int try_neg)7183 print_imm(dis86_t *dis, uint64_t usv, uint64_t mask, char *buf,
7184 size_t buflen, int disp, int try_neg)
7185 {
7186 int curlen;
7187 int64_t sv = (int64_t)usv;
7188 int octal = dis->d86_flags & DIS_F_OCTAL;
7189
7190 curlen = strlen(buf);
7191
7192 if (try_neg == TRY_NEG && sv < 0 &&
7193 (disp || sv >= NEG_LIMIT) &&
7194 !isunsigned_op(dis->d86_mnem)) {
7195 dis->d86_sprintf_func(buf + curlen, buflen - curlen,
7196 octal ? "-0%llo" : "-0x%llx", (-sv) & mask);
7197 return (1);
7198 } else {
7199 if (disp == DISP)
7200 dis->d86_sprintf_func(buf + curlen, buflen - curlen,
7201 octal ? "+0%llo" : "+0x%llx", usv & mask);
7202 else
7203 dis->d86_sprintf_func(buf + curlen, buflen - curlen,
7204 octal ? "0%llo" : "0x%llx", usv & mask);
7205 return (0);
7206
7207 }
7208 }
7209
7210
7211 static int
log2(int size)7212 log2(int size)
7213 {
7214 switch (size) {
7215 case 1: return (0);
7216 case 2: return (1);
7217 case 4: return (2);
7218 case 8: return (3);
7219 }
7220 return (0);
7221 }
7222
7223 /* ARGSUSED */
7224 void
dtrace_disx86_str(dis86_t * dis,uint_t mode,uint64_t pc,char * buf,size_t buflen)7225 dtrace_disx86_str(dis86_t *dis, uint_t mode, uint64_t pc, char *buf,
7226 size_t buflen)
7227 {
7228 uint64_t reltgt = 0;
7229 uint64_t tgt = 0;
7230 int curlen;
7231 int (*lookup)(void *, uint64_t, char *, size_t);
7232 int i;
7233 int64_t sv;
7234 uint64_t usv, mask, save_mask, save_usv;
7235 static uint64_t masks[] =
7236 {0xffU, 0xffffU, 0xffffffffU, 0xffffffffffffffffULL};
7237 save_usv = 0;
7238
7239 dis->d86_sprintf_func(buf, buflen, "%-6s ", dis->d86_mnem);
7240
7241 /*
7242 * For PC-relative jumps, the pc is really the next pc after executing
7243 * this instruction, so increment it appropriately.
7244 */
7245 pc += dis->d86_len;
7246
7247 for (i = 0; i < dis->d86_numopnds; i++) {
7248 d86opnd_t *op = &dis->d86_opnd[i];
7249
7250 if (i != 0)
7251 (void) strlcat(buf, ",", buflen);
7252
7253 (void) strlcat(buf, op->d86_prefix, buflen);
7254
7255 /*
7256 * sv is for the signed, possibly-truncated immediate or
7257 * displacement; usv retains the original size and
7258 * unsignedness for symbol lookup.
7259 */
7260
7261 sv = usv = op->d86_value;
7262
7263 /*
7264 * About masks: for immediates that represent
7265 * addresses, the appropriate display size is
7266 * the effective address size of the instruction.
7267 * This includes MODE_OFFSET, MODE_IPREL, and
7268 * MODE_RIPREL. Immediates that are simply
7269 * immediate values should display in the operand's
7270 * size, however, since they don't represent addresses.
7271 */
7272
7273 /* d86_addr_size is SIZEnn, which is log2(real size) */
7274 mask = masks[dis->d86_addr_size];
7275
7276 /* d86_value_size and d86_imm_bytes are in bytes */
7277 if (op->d86_mode == MODE_SIGNED ||
7278 op->d86_mode == MODE_IMPLIED)
7279 mask = masks[log2(op->d86_value_size)];
7280
7281 switch (op->d86_mode) {
7282
7283 case MODE_NONE:
7284
7285 (void) strlcat(buf, op->d86_opnd, buflen);
7286 break;
7287
7288 case MODE_SIGNED:
7289 case MODE_IMPLIED:
7290 case MODE_OFFSET:
7291
7292 tgt = usv;
7293
7294 if (dis->d86_seg_prefix)
7295 (void) strlcat(buf, dis->d86_seg_prefix,
7296 buflen);
7297
7298 if (op->d86_mode == MODE_SIGNED ||
7299 op->d86_mode == MODE_IMPLIED) {
7300 (void) strlcat(buf, "$", buflen);
7301 }
7302
7303 if (print_imm(dis, usv, mask, buf, buflen,
7304 IMM, TRY_NEG) &&
7305 (op->d86_mode == MODE_SIGNED ||
7306 op->d86_mode == MODE_IMPLIED)) {
7307
7308 /*
7309 * We printed a negative value for an
7310 * immediate that wasn't a
7311 * displacement. Note that fact so we can
7312 * print the positive value as an
7313 * annotation.
7314 */
7315
7316 save_usv = usv;
7317 save_mask = mask;
7318 }
7319 (void) strlcat(buf, op->d86_opnd, buflen);
7320 break;
7321
7322 case MODE_IPREL:
7323 case MODE_RIPREL:
7324
7325 reltgt = pc + sv;
7326
7327 switch (mode) {
7328 case SIZE16:
7329 reltgt = (uint16_t)reltgt;
7330 break;
7331 case SIZE32:
7332 reltgt = (uint32_t)reltgt;
7333 break;
7334 }
7335
7336 (void) print_imm(dis, usv, mask, buf, buflen,
7337 DISP, TRY_NEG);
7338
7339 if (op->d86_mode == MODE_RIPREL)
7340 (void) strlcat(buf, "(%rip)", buflen);
7341 break;
7342 }
7343 }
7344
7345 /*
7346 * The symbol lookups may result in false positives,
7347 * particularly on object files, where small numbers may match
7348 * the 0-relative non-relocated addresses of symbols.
7349 */
7350
7351 lookup = dis->d86_sym_lookup;
7352 if (tgt != 0) {
7353 if ((dis->d86_flags & DIS_F_NOIMMSYM) == 0 &&
7354 lookup(dis->d86_data, tgt, NULL, 0) == 0) {
7355 (void) strlcat(buf, "\t<", buflen);
7356 curlen = strlen(buf);
7357 lookup(dis->d86_data, tgt, buf + curlen,
7358 buflen - curlen);
7359 (void) strlcat(buf, ">", buflen);
7360 }
7361
7362 /*
7363 * If we printed a negative immediate above, print the
7364 * positive in case our heuristic was unhelpful
7365 */
7366 if (save_usv) {
7367 (void) strlcat(buf, "\t<", buflen);
7368 (void) print_imm(dis, save_usv, save_mask, buf, buflen,
7369 IMM, POS);
7370 (void) strlcat(buf, ">", buflen);
7371 }
7372 }
7373
7374 if (reltgt != 0) {
7375 /* Print symbol or effective address for reltgt */
7376
7377 (void) strlcat(buf, "\t<", buflen);
7378 curlen = strlen(buf);
7379 lookup(dis->d86_data, reltgt, buf + curlen,
7380 buflen - curlen);
7381 (void) strlcat(buf, ">", buflen);
7382 }
7383 }
7384
7385 #endif /* DIS_TEXT */
7386