1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef __ECORE_HSI_ETH__ 30 #define __ECORE_HSI_ETH__ 31 /************************************************************************/ 32 /* Add include to common eth target for both eCore and protocol driver */ 33 /************************************************************************/ 34 #include "eth_common.h" 35 36 /* 37 * The eth storm context for the Tstorm 38 */ 39 struct tstorm_eth_conn_st_ctx 40 { 41 __le32 reserved[4]; 42 }; 43 44 /* 45 * The eth storm context for the Pstorm 46 */ 47 struct pstorm_eth_conn_st_ctx 48 { 49 __le32 reserved[8]; 50 }; 51 52 /* 53 * The eth storm context for the Xstorm 54 */ 55 struct xstorm_eth_conn_st_ctx 56 { 57 __le32 reserved[60]; 58 }; 59 60 struct e4_xstorm_eth_conn_ag_ctx 61 { 62 u8 reserved0 /* cdu_validation */; 63 u8 state /* state */; 64 u8 flags0; 65 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 66 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 67 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 68 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1 69 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 70 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2 71 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 72 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 73 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 74 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4 75 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 76 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5 77 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 78 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6 79 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 80 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7 81 u8 flags1; 82 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 83 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0 84 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 85 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1 86 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 87 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2 88 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 89 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3 90 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 /* bit12 */ 91 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 92 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 /* bit13 */ 93 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 94 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 95 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 96 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 97 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 98 u8 flags2; 99 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 100 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0 101 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 102 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2 103 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 104 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4 105 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 106 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6 107 u8 flags3; 108 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 109 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0 110 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 111 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2 112 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 113 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4 114 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 115 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6 116 u8 flags4; 117 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 118 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0 119 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 120 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2 121 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 122 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4 123 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 124 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6 125 u8 flags5; 126 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 127 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0 128 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 129 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2 130 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 131 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4 132 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 133 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6 134 u8 flags6; 135 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 136 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 137 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 /* cf_array_cf */ 138 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 139 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 140 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4 141 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 142 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 143 u8 flags7; 144 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 145 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 146 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 147 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2 148 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 149 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4 150 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 151 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6 152 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 153 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7 154 u8 flags8; 155 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 156 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0 157 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 158 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1 159 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 160 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2 161 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 162 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3 163 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 164 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4 165 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 166 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5 167 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 168 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6 169 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 170 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7 171 u8 flags9; 172 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 173 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0 174 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 175 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1 176 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 177 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2 178 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 179 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3 180 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 181 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4 182 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 183 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5 184 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 185 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 186 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 /* cf_array_cf_en */ 187 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 188 u8 flags10; 189 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 190 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 191 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 192 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 193 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 194 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 195 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 196 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3 197 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 198 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 199 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 200 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 201 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 202 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6 203 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 204 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7 205 u8 flags11; 206 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 207 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0 208 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 209 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1 210 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 211 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 212 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 213 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3 214 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 215 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4 216 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 217 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5 218 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 219 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 220 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 221 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7 222 u8 flags12; 223 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 224 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0 225 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 226 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1 227 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 228 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 229 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 230 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 231 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 232 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4 233 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 234 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5 235 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 236 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6 237 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 238 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7 239 u8 flags13; 240 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 241 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0 242 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 243 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1 244 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 245 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 246 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 247 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 248 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 249 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 250 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 251 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 252 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 253 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 254 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 255 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 256 u8 flags14; 257 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 258 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 259 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 260 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 261 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 262 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 263 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 264 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 265 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 266 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 267 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 268 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 269 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */ 270 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 271 u8 edpm_event_id /* byte2 */; 272 __le16 physical_q0 /* physical_q0 */; 273 __le16 e5_reserved1 /* physical_q1 */; 274 __le16 edpm_num_bds /* physical_q2 */; 275 __le16 tx_bd_cons /* word3 */; 276 __le16 tx_bd_prod /* word4 */; 277 __le16 tx_class /* word5 */; 278 __le16 conn_dpi /* conn_dpi */; 279 u8 byte3 /* byte3 */; 280 u8 byte4 /* byte4 */; 281 u8 byte5 /* byte5 */; 282 u8 byte6 /* byte6 */; 283 __le32 reg0 /* reg0 */; 284 __le32 reg1 /* reg1 */; 285 __le32 reg2 /* reg2 */; 286 __le32 reg3 /* reg3 */; 287 __le32 reg4 /* reg4 */; 288 __le32 reg5 /* cf_array0 */; 289 __le32 reg6 /* cf_array1 */; 290 __le16 word7 /* word7 */; 291 __le16 word8 /* word8 */; 292 __le16 word9 /* word9 */; 293 __le16 word10 /* word10 */; 294 __le32 reg7 /* reg7 */; 295 __le32 reg8 /* reg8 */; 296 __le32 reg9 /* reg9 */; 297 u8 byte7 /* byte7 */; 298 u8 byte8 /* byte8 */; 299 u8 byte9 /* byte9 */; 300 u8 byte10 /* byte10 */; 301 u8 byte11 /* byte11 */; 302 u8 byte12 /* byte12 */; 303 u8 byte13 /* byte13 */; 304 u8 byte14 /* byte14 */; 305 u8 byte15 /* byte15 */; 306 u8 e5_reserved /* e5_reserved */; 307 __le16 word11 /* word11 */; 308 __le32 reg10 /* reg10 */; 309 __le32 reg11 /* reg11 */; 310 __le32 reg12 /* reg12 */; 311 __le32 reg13 /* reg13 */; 312 __le32 reg14 /* reg14 */; 313 __le32 reg15 /* reg15 */; 314 __le32 reg16 /* reg16 */; 315 __le32 reg17 /* reg17 */; 316 __le32 reg18 /* reg18 */; 317 __le32 reg19 /* reg19 */; 318 __le16 word12 /* word12 */; 319 __le16 word13 /* word13 */; 320 __le16 word14 /* word14 */; 321 __le16 word15 /* word15 */; 322 }; 323 324 /* 325 * The eth storm context for the Ystorm 326 */ 327 struct ystorm_eth_conn_st_ctx 328 { 329 __le32 reserved[8]; 330 }; 331 332 struct e4_ystorm_eth_conn_ag_ctx 333 { 334 u8 byte0 /* cdu_validation */; 335 u8 state /* state */; 336 u8 flags0; 337 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 338 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 339 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 340 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 341 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf0 */ 342 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2 343 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 /* cf1 */ 344 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4 345 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 346 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 347 u8 flags1; 348 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf0en */ 349 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0 350 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */ 351 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1 352 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 353 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 354 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 355 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 356 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 357 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 358 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 359 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 360 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 361 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 362 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 363 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 364 u8 tx_q0_int_coallecing_timeset /* byte2 */; 365 u8 byte3 /* byte3 */; 366 __le16 word0 /* word0 */; 367 __le32 terminate_spqe /* reg0 */; 368 __le32 reg1 /* reg1 */; 369 __le16 tx_bd_cons_upd /* word1 */; 370 __le16 word2 /* word2 */; 371 __le16 word3 /* word3 */; 372 __le16 word4 /* word4 */; 373 __le32 reg2 /* reg2 */; 374 __le32 reg3 /* reg3 */; 375 }; 376 377 struct e4_tstorm_eth_conn_ag_ctx 378 { 379 u8 byte0 /* cdu_validation */; 380 u8 byte1 /* state */; 381 u8 flags0; 382 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 383 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 384 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 385 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 386 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 387 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2 388 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 389 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3 390 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 391 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4 392 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 393 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5 394 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 395 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6 396 u8 flags1; 397 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 398 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0 399 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 400 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2 401 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 402 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4 403 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 404 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6 405 u8 flags2; 406 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 407 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0 408 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 409 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2 410 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 411 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4 412 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 413 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6 414 u8 flags3; 415 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 416 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0 417 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 418 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2 419 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 420 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4 421 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 422 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5 423 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 424 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6 425 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 426 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7 427 u8 flags4; 428 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 429 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0 430 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 431 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1 432 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 433 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2 434 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 435 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3 436 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 437 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4 438 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 439 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5 440 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 441 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6 442 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 443 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 444 u8 flags5; 445 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 446 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 447 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 448 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 449 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 450 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 451 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 452 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 453 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 454 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 455 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 /* rule6en */ 456 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5 457 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 458 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 459 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 460 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 461 __le32 reg0 /* reg0 */; 462 __le32 reg1 /* reg1 */; 463 __le32 reg2 /* reg2 */; 464 __le32 reg3 /* reg3 */; 465 __le32 reg4 /* reg4 */; 466 __le32 reg5 /* reg5 */; 467 __le32 reg6 /* reg6 */; 468 __le32 reg7 /* reg7 */; 469 __le32 reg8 /* reg8 */; 470 u8 byte2 /* byte2 */; 471 u8 byte3 /* byte3 */; 472 __le16 rx_bd_cons /* word0 */; 473 u8 byte4 /* byte4 */; 474 u8 byte5 /* byte5 */; 475 __le16 rx_bd_prod /* word1 */; 476 __le16 word2 /* conn_dpi */; 477 __le16 word3 /* word3 */; 478 __le32 reg9 /* reg9 */; 479 __le32 reg10 /* reg10 */; 480 }; 481 482 struct e4_ustorm_eth_conn_ag_ctx 483 { 484 u8 byte0 /* cdu_validation */; 485 u8 byte1 /* state */; 486 u8 flags0; 487 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 488 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 489 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 490 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 491 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3 /* timer0cf */ 492 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2 493 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3 /* timer1cf */ 494 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4 495 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 496 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 497 u8 flags1; 498 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 499 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0 500 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3 /* cf4 */ 501 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2 502 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3 /* cf5 */ 503 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4 504 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf6 */ 505 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6 506 u8 flags2; 507 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf0en */ 508 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0 509 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */ 510 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1 511 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 512 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 513 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 514 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3 515 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1 /* cf4en */ 516 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4 517 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1 /* cf5en */ 518 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5 519 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf6en */ 520 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6 521 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 522 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 523 u8 flags3; 524 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 525 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 526 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 527 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 528 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 529 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 530 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 531 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 532 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 533 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 534 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 535 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5 536 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 537 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 538 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 539 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 540 u8 byte2 /* byte2 */; 541 u8 byte3 /* byte3 */; 542 __le16 word0 /* conn_dpi */; 543 __le16 tx_bd_cons /* word1 */; 544 __le32 reg0 /* reg0 */; 545 __le32 reg1 /* reg1 */; 546 __le32 reg2 /* reg2 */; 547 __le32 tx_int_coallecing_timeset /* reg3 */; 548 __le16 tx_drv_bd_cons /* word2 */; 549 __le16 rx_drv_cqe_cons /* word3 */; 550 }; 551 552 /* 553 * The eth storm context for the Ustorm 554 */ 555 struct ustorm_eth_conn_st_ctx 556 { 557 __le32 reserved[40]; 558 }; 559 560 /* 561 * The eth storm context for the Mstorm 562 */ 563 struct mstorm_eth_conn_st_ctx 564 { 565 __le32 reserved[8]; 566 }; 567 568 /* 569 * eth connection context 570 */ 571 struct e4_eth_conn_context 572 { 573 struct tstorm_eth_conn_st_ctx tstorm_st_context /* tstorm storm context */; 574 struct regpair tstorm_st_padding[2] /* padding */; 575 struct pstorm_eth_conn_st_ctx pstorm_st_context /* pstorm storm context */; 576 struct xstorm_eth_conn_st_ctx xstorm_st_context /* xstorm storm context */; 577 struct e4_xstorm_eth_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 578 struct ystorm_eth_conn_st_ctx ystorm_st_context /* ystorm storm context */; 579 struct e4_ystorm_eth_conn_ag_ctx ystorm_ag_context /* ystorm aggregative context */; 580 struct e4_tstorm_eth_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 581 struct e4_ustorm_eth_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 582 struct ustorm_eth_conn_st_ctx ustorm_st_context /* ustorm storm context */; 583 struct mstorm_eth_conn_st_ctx mstorm_st_context /* mstorm storm context */; 584 }; 585 586 struct e5_xstorm_eth_conn_ag_ctx 587 { 588 u8 reserved0 /* cdu_validation */; 589 u8 state_and_core_id /* state_and_core_id */; 590 u8 flags0; 591 #define E5_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 592 #define E5_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 593 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 594 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1 595 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 596 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2 597 #define E5_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 598 #define E5_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 599 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 600 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4 601 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 602 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5 603 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 604 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6 605 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 606 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7 607 u8 flags1; 608 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 609 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0 610 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 611 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1 612 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 613 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2 614 #define E5_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 615 #define E5_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3 616 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_COPY_CONDITION_LO_MASK 0x1 /* bit12 */ 617 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_COPY_CONDITION_LO_SHIFT 4 618 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_COPY_CONDITION_HI_MASK 0x1 /* bit13 */ 619 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_COPY_CONDITION_HI_SHIFT 5 620 #define E5_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 621 #define E5_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 622 #define E5_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 623 #define E5_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 624 u8 flags2; 625 #define E5_XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 626 #define E5_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0 627 #define E5_XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 628 #define E5_XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2 629 #define E5_XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 630 #define E5_XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4 631 #define E5_XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 632 #define E5_XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6 633 u8 flags3; 634 #define E5_XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 635 #define E5_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0 636 #define E5_XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 637 #define E5_XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2 638 #define E5_XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 639 #define E5_XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4 640 #define E5_XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 641 #define E5_XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6 642 u8 flags4; 643 #define E5_XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 644 #define E5_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0 645 #define E5_XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 646 #define E5_XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2 647 #define E5_XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 648 #define E5_XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4 649 #define E5_XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 650 #define E5_XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6 651 u8 flags5; 652 #define E5_XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 653 #define E5_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0 654 #define E5_XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 655 #define E5_XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2 656 #define E5_XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 657 #define E5_XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4 658 #define E5_XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 659 #define E5_XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6 660 u8 flags6; 661 #define E5_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 662 #define E5_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 663 #define E5_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 /* cf_array_cf */ 664 #define E5_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 665 #define E5_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 666 #define E5_XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4 667 #define E5_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 668 #define E5_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 669 u8 flags7; 670 #define E5_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 671 #define E5_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 672 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 673 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2 674 #define E5_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 675 #define E5_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4 676 #define E5_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 677 #define E5_XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6 678 #define E5_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 679 #define E5_XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7 680 u8 flags8; 681 #define E5_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 682 #define E5_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0 683 #define E5_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 684 #define E5_XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1 685 #define E5_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 686 #define E5_XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2 687 #define E5_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 688 #define E5_XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3 689 #define E5_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 690 #define E5_XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4 691 #define E5_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 692 #define E5_XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5 693 #define E5_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 694 #define E5_XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6 695 #define E5_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 696 #define E5_XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7 697 u8 flags9; 698 #define E5_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 699 #define E5_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0 700 #define E5_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 701 #define E5_XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1 702 #define E5_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 703 #define E5_XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2 704 #define E5_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 705 #define E5_XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3 706 #define E5_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 707 #define E5_XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4 708 #define E5_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 709 #define E5_XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5 710 #define E5_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 711 #define E5_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 712 #define E5_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 /* cf_array_cf_en */ 713 #define E5_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 714 u8 flags10; 715 #define E5_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 716 #define E5_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 717 #define E5_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 718 #define E5_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 719 #define E5_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 720 #define E5_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 721 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 722 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3 723 #define E5_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 724 #define E5_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 725 #define E5_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 726 #define E5_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 727 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 728 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6 729 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 730 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7 731 u8 flags11; 732 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 733 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0 734 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 735 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1 736 #define E5_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 737 #define E5_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 738 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 739 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3 740 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 741 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4 742 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 743 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5 744 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 745 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 746 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 747 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7 748 u8 flags12; 749 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 750 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0 751 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 752 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1 753 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 754 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 755 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 756 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 757 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 758 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4 759 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 760 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5 761 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 762 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6 763 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 764 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7 765 u8 flags13; 766 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 767 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0 768 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 769 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1 770 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 771 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 772 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 773 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 774 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 775 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 776 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 777 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 778 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 779 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 780 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 781 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 782 u8 flags14; 783 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 784 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 785 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 786 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 787 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 788 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 789 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 790 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 791 #define E5_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 792 #define E5_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 793 #define E5_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 794 #define E5_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 795 #define E5_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */ 796 #define E5_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 797 u8 edpm_vport /* byte2 */; 798 __le16 physical_q0 /* physical_q0 */; 799 __le16 tx_l2_edpm_usg_cnt /* physical_q1 */; 800 __le16 edpm_num_bds /* physical_q2 */; 801 __le16 tx_bd_cons /* word3 */; 802 __le16 tx_bd_prod /* word4 */; 803 __le16 tx_class /* word5 */; 804 __le16 conn_dpi /* conn_dpi */; 805 u8 byte3 /* byte3 */; 806 u8 byte4 /* byte4 */; 807 u8 byte5 /* byte5 */; 808 u8 byte6 /* byte6 */; 809 __le32 reg0 /* reg0 */; 810 __le32 reg1 /* reg1 */; 811 __le32 reg2 /* reg2 */; 812 __le32 reg3 /* reg3 */; 813 __le32 reg4 /* reg4 */; 814 __le32 reg5 /* cf_array0 */; 815 __le32 reg6 /* cf_array1 */; 816 u8 flags15; 817 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_REDIRECTION_CONDITION_LO_MASK 0x1 /* bit22 */ 818 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_REDIRECTION_CONDITION_LO_SHIFT 0 819 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_REDIRECTION_CONDITION_HI_MASK 0x1 /* bit23 */ 820 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_REDIRECTION_CONDITION_HI_SHIFT 1 821 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit24 */ 822 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 823 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf24 */ 824 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 825 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf24en */ 826 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 827 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule26en */ 828 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 829 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule27en */ 830 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 831 u8 byte7 /* byte7 */; 832 __le16 word7 /* word7 */; 833 __le16 word8 /* word8 */; 834 __le16 word9 /* word9 */; 835 __le16 word10 /* word10 */; 836 __le16 word11 /* word11 */; 837 __le32 reg7 /* reg7 */; 838 __le32 reg8 /* reg8 */; 839 __le32 reg9 /* reg9 */; 840 u8 byte8 /* byte8 */; 841 u8 byte9 /* byte9 */; 842 u8 byte10 /* byte10 */; 843 u8 byte11 /* byte11 */; 844 u8 byte12 /* byte12 */; 845 u8 byte13 /* byte13 */; 846 u8 byte14 /* byte14 */; 847 u8 byte15 /* byte15 */; 848 __le32 reg10 /* reg10 */; 849 __le32 reg11 /* reg11 */; 850 __le32 reg12 /* reg12 */; 851 __le32 reg13 /* reg13 */; 852 __le32 reg14 /* reg14 */; 853 __le32 reg15 /* reg15 */; 854 __le32 reg16 /* reg16 */; 855 __le32 reg17 /* reg17 */; 856 __le32 reg18 /* reg18 */; 857 __le32 reg19 /* reg19 */; 858 __le16 word12 /* word12 */; 859 __le16 word13 /* word13 */; 860 __le16 word14 /* word14 */; 861 __le16 word15 /* word15 */; 862 }; 863 864 struct e5_tstorm_eth_conn_ag_ctx 865 { 866 u8 byte0 /* cdu_validation */; 867 u8 byte1 /* state_and_core_id */; 868 u8 flags0; 869 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 870 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 871 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 872 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 873 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 874 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2 875 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 876 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3 877 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 878 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4 879 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 880 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5 881 #define E5_TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 882 #define E5_TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6 883 u8 flags1; 884 #define E5_TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 885 #define E5_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0 886 #define E5_TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 887 #define E5_TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2 888 #define E5_TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 889 #define E5_TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4 890 #define E5_TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 891 #define E5_TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6 892 u8 flags2; 893 #define E5_TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 894 #define E5_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0 895 #define E5_TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 896 #define E5_TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2 897 #define E5_TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 898 #define E5_TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4 899 #define E5_TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 900 #define E5_TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6 901 u8 flags3; 902 #define E5_TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 903 #define E5_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0 904 #define E5_TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 905 #define E5_TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2 906 #define E5_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 907 #define E5_TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4 908 #define E5_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 909 #define E5_TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5 910 #define E5_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 911 #define E5_TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6 912 #define E5_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 913 #define E5_TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7 914 u8 flags4; 915 #define E5_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 916 #define E5_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0 917 #define E5_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 918 #define E5_TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1 919 #define E5_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 920 #define E5_TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2 921 #define E5_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 922 #define E5_TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3 923 #define E5_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 924 #define E5_TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4 925 #define E5_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 926 #define E5_TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5 927 #define E5_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 928 #define E5_TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6 929 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 930 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 931 u8 flags5; 932 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 933 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 934 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 935 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 936 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 937 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 938 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 939 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 940 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 941 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 942 #define E5_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 /* rule6en */ 943 #define E5_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5 944 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 945 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 946 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 947 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 948 u8 flags6; 949 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 950 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 951 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 952 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 953 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 954 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 955 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 956 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 957 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 958 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 959 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 960 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 961 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 962 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 963 u8 byte2 /* byte2 */; 964 __le16 rx_bd_cons /* word0 */; 965 __le32 reg0 /* reg0 */; 966 __le32 reg1 /* reg1 */; 967 __le32 reg2 /* reg2 */; 968 __le32 reg3 /* reg3 */; 969 __le32 reg4 /* reg4 */; 970 __le32 reg5 /* reg5 */; 971 __le32 reg6 /* reg6 */; 972 __le32 reg7 /* reg7 */; 973 __le32 reg8 /* reg8 */; 974 u8 byte3 /* byte3 */; 975 u8 byte4 /* byte4 */; 976 u8 byte5 /* byte5 */; 977 u8 e4_reserved8 /* byte6 */; 978 __le16 rx_bd_prod /* word1 */; 979 __le16 word2 /* conn_dpi */; 980 __le32 reg9 /* reg9 */; 981 __le16 word3 /* word3 */; 982 __le16 e4_reserved9 /* word4 */; 983 }; 984 985 struct e5_ystorm_eth_conn_ag_ctx 986 { 987 u8 byte0 /* cdu_validation */; 988 u8 state_and_core_id /* state_and_core_id */; 989 u8 flags0; 990 #define E5_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 991 #define E5_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 992 #define E5_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 993 #define E5_YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 994 #define E5_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf0 */ 995 #define E5_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2 996 #define E5_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 /* cf1 */ 997 #define E5_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4 998 #define E5_YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 999 #define E5_YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 1000 u8 flags1; 1001 #define E5_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf0en */ 1002 #define E5_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0 1003 #define E5_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */ 1004 #define E5_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1 1005 #define E5_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1006 #define E5_YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 1007 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1008 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 1009 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1010 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 1011 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1012 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 1013 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1014 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 1015 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1016 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 1017 u8 tx_q0_int_coallecing_timeset /* byte2 */; 1018 u8 byte3 /* byte3 */; 1019 __le16 word0 /* word0 */; 1020 __le32 terminate_spqe /* reg0 */; 1021 __le32 reg1 /* reg1 */; 1022 __le16 tx_bd_cons_upd /* word1 */; 1023 __le16 word2 /* word2 */; 1024 __le16 word3 /* word3 */; 1025 __le16 word4 /* word4 */; 1026 __le32 reg2 /* reg2 */; 1027 __le32 reg3 /* reg3 */; 1028 }; 1029 1030 struct e5_ustorm_eth_conn_ag_ctx 1031 { 1032 u8 byte0 /* cdu_validation */; 1033 u8 byte1 /* state_and_core_id */; 1034 u8 flags0; 1035 #define E5_USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1036 #define E5_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 1037 #define E5_USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1038 #define E5_USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 1039 #define E5_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3 /* timer0cf */ 1040 #define E5_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2 1041 #define E5_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3 /* timer1cf */ 1042 #define E5_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4 1043 #define E5_USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1044 #define E5_USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 1045 u8 flags1; 1046 #define E5_USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1047 #define E5_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0 1048 #define E5_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3 /* cf4 */ 1049 #define E5_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2 1050 #define E5_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3 /* cf5 */ 1051 #define E5_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4 1052 #define E5_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf6 */ 1053 #define E5_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6 1054 u8 flags2; 1055 #define E5_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf0en */ 1056 #define E5_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0 1057 #define E5_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */ 1058 #define E5_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1 1059 #define E5_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1060 #define E5_USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 1061 #define E5_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1062 #define E5_USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3 1063 #define E5_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1 /* cf4en */ 1064 #define E5_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4 1065 #define E5_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1 /* cf5en */ 1066 #define E5_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5 1067 #define E5_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf6en */ 1068 #define E5_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6 1069 #define E5_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1070 #define E5_USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 1071 u8 flags3; 1072 #define E5_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1073 #define E5_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 1074 #define E5_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1075 #define E5_USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 1076 #define E5_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1077 #define E5_USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 1078 #define E5_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1079 #define E5_USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 1080 #define E5_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1081 #define E5_USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 1082 #define E5_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1083 #define E5_USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5 1084 #define E5_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1085 #define E5_USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 1086 #define E5_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1087 #define E5_USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 1088 u8 flags4; 1089 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 1090 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1091 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 1092 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1093 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 1094 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1095 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 1096 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 1097 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 1098 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 1099 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 1100 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 1101 u8 byte2 /* byte2 */; 1102 __le16 word0 /* conn_dpi */; 1103 __le16 tx_bd_cons /* word1 */; 1104 __le32 reg0 /* reg0 */; 1105 __le32 reg1 /* reg1 */; 1106 __le32 reg2 /* reg2 */; 1107 __le32 tx_int_coallecing_timeset /* reg3 */; 1108 __le16 tx_drv_bd_cons /* word2 */; 1109 __le16 rx_drv_cqe_cons /* word3 */; 1110 }; 1111 1112 /* 1113 * eth connection context 1114 */ 1115 struct e5_eth_conn_context 1116 { 1117 struct tstorm_eth_conn_st_ctx tstorm_st_context /* tstorm storm context */; 1118 struct regpair tstorm_st_padding[2] /* padding */; 1119 struct pstorm_eth_conn_st_ctx pstorm_st_context /* pstorm storm context */; 1120 struct xstorm_eth_conn_st_ctx xstorm_st_context /* xstorm storm context */; 1121 struct regpair xstorm_st_padding[2] /* padding */; 1122 struct e5_xstorm_eth_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 1123 struct e5_tstorm_eth_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 1124 struct ystorm_eth_conn_st_ctx ystorm_st_context /* ystorm storm context */; 1125 struct e5_ystorm_eth_conn_ag_ctx ystorm_ag_context /* ystorm aggregative context */; 1126 struct e5_ustorm_eth_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 1127 struct ustorm_eth_conn_st_ctx ustorm_st_context /* ustorm storm context */; 1128 struct mstorm_eth_conn_st_ctx mstorm_st_context /* mstorm storm context */; 1129 }; 1130 1131 /* 1132 * Ethernet filter types: mac/vlan/pair 1133 */ 1134 enum eth_error_code 1135 { 1136 ETH_OK=0x00 /* command succeeded */, 1137 ETH_FILTERS_MAC_ADD_FAIL_FULL /* mac add filters command failed due to cam full state */, 1138 ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2 /* mac add filters command failed due to mtt2 full state */, 1139 ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2 /* mac add filters command failed due to duplicate mac address */, 1140 ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2 /* mac add filters command failed due to duplicate mac address */, 1141 ETH_FILTERS_MAC_DEL_FAIL_NOF /* mac delete filters command failed due to not found state */, 1142 ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2 /* mac delete filters command failed due to not found state */, 1143 ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2 /* mac delete filters command failed due to not found state */, 1144 ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC /* mac add filters command failed due to MAC Address of 00:00:00:00:00:00 */, 1145 ETH_FILTERS_VLAN_ADD_FAIL_FULL /* vlan add filters command failed due to cam full state */, 1146 ETH_FILTERS_VLAN_ADD_FAIL_DUP /* vlan add filters command failed due to duplicate VLAN filter */, 1147 ETH_FILTERS_VLAN_DEL_FAIL_NOF /* vlan delete filters command failed due to not found state */, 1148 ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1 /* vlan delete filters command failed due to not found state */, 1149 ETH_FILTERS_PAIR_ADD_FAIL_DUP /* pair add filters command failed due to duplicate request */, 1150 ETH_FILTERS_PAIR_ADD_FAIL_FULL /* pair add filters command failed due to full state */, 1151 ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC /* pair add filters command failed due to full state */, 1152 ETH_FILTERS_PAIR_DEL_FAIL_NOF /* pair add filters command failed due not found state */, 1153 ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1 /* pair add filters command failed due not found state */, 1154 ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC /* pair add filters command failed due to MAC Address of 00:00:00:00:00:00 */, 1155 ETH_FILTERS_VNI_ADD_FAIL_FULL /* vni add filters command failed due to cam full state */, 1156 ETH_FILTERS_VNI_ADD_FAIL_DUP /* vni add filters command failed due to duplicate VNI filter */, 1157 ETH_FILTERS_GFT_UPDATE_FAIL /* Fail update GFT filter. */, 1158 MAX_ETH_ERROR_CODE 1159 }; 1160 1161 /* 1162 * opcodes for the event ring 1163 */ 1164 enum eth_event_opcode 1165 { 1166 ETH_EVENT_UNUSED, 1167 ETH_EVENT_VPORT_START, 1168 ETH_EVENT_VPORT_UPDATE, 1169 ETH_EVENT_VPORT_STOP, 1170 ETH_EVENT_TX_QUEUE_START, 1171 ETH_EVENT_TX_QUEUE_STOP, 1172 ETH_EVENT_RX_QUEUE_START, 1173 ETH_EVENT_RX_QUEUE_UPDATE, 1174 ETH_EVENT_RX_QUEUE_STOP, 1175 ETH_EVENT_FILTERS_UPDATE, 1176 ETH_EVENT_RX_ADD_OPENFLOW_FILTER, 1177 ETH_EVENT_RX_DELETE_OPENFLOW_FILTER, 1178 ETH_EVENT_RX_CREATE_OPENFLOW_ACTION, 1179 ETH_EVENT_RX_ADD_UDP_FILTER, 1180 ETH_EVENT_RX_DELETE_UDP_FILTER, 1181 ETH_EVENT_RX_CREATE_GFT_ACTION, 1182 ETH_EVENT_RX_GFT_UPDATE_FILTER, 1183 ETH_EVENT_TX_QUEUE_UPDATE, 1184 MAX_ETH_EVENT_OPCODE 1185 }; 1186 1187 /* 1188 * Classify rule types in E2/E3 1189 */ 1190 enum eth_filter_action 1191 { 1192 ETH_FILTER_ACTION_UNUSED, 1193 ETH_FILTER_ACTION_REMOVE, 1194 ETH_FILTER_ACTION_ADD, 1195 ETH_FILTER_ACTION_REMOVE_ALL /* Remove all filters of given type and vport ID. */, 1196 MAX_ETH_FILTER_ACTION 1197 }; 1198 1199 /* 1200 * Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ 1201 */ 1202 struct eth_filter_cmd 1203 { 1204 u8 type /* Filter Type (MAC/VLAN/Pair/VNI) (use enum eth_filter_type) */; 1205 u8 vport_id /* the vport id */; 1206 u8 action /* filter command action: add/remove/replace (use enum eth_filter_action) */; 1207 u8 reserved0; 1208 __le32 vni; 1209 __le16 mac_lsb; 1210 __le16 mac_mid; 1211 __le16 mac_msb; 1212 __le16 vlan_id; 1213 }; 1214 1215 /* 1216 * $$KEEP_ENDIANNESS$$ 1217 */ 1218 struct eth_filter_cmd_header 1219 { 1220 u8 rx /* If set, apply these commands to the RX path */; 1221 u8 tx /* If set, apply these commands to the TX path */; 1222 u8 cmd_cnt /* Number of filter commands */; 1223 u8 assert_on_error /* 0 - dont assert in case of filter configuration error. Just return an error code. 1 - assert in case of filter configuration error. */; 1224 u8 reserved1[4]; 1225 }; 1226 1227 /* 1228 * Ethernet filter types: mac/vlan/pair 1229 */ 1230 enum eth_filter_type 1231 { 1232 ETH_FILTER_TYPE_UNUSED, 1233 ETH_FILTER_TYPE_MAC /* Add/remove a MAC address */, 1234 ETH_FILTER_TYPE_VLAN /* Add/remove a VLAN */, 1235 ETH_FILTER_TYPE_PAIR /* Add/remove a MAC-VLAN pair */, 1236 ETH_FILTER_TYPE_INNER_MAC /* Add/remove a inner MAC address */, 1237 ETH_FILTER_TYPE_INNER_VLAN /* Add/remove a inner VLAN */, 1238 ETH_FILTER_TYPE_INNER_PAIR /* Add/remove a inner MAC-VLAN pair */, 1239 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR /* Add/remove a inner MAC-VNI pair */, 1240 ETH_FILTER_TYPE_MAC_VNI_PAIR /* Add/remove a MAC-VNI pair */, 1241 ETH_FILTER_TYPE_VNI /* Add/remove a VNI */, 1242 MAX_ETH_FILTER_TYPE 1243 }; 1244 1245 /* 1246 * eth IPv4 Fragment Type 1247 */ 1248 enum eth_ipv4_frag_type 1249 { 1250 ETH_IPV4_NOT_FRAG /* IPV4 Packet Not Fragmented */, 1251 ETH_IPV4_FIRST_FRAG /* First Fragment of IPv4 Packet (contains headers) */, 1252 ETH_IPV4_NON_FIRST_FRAG /* Non-First Fragment of IPv4 Packet (does not contain headers) */, 1253 MAX_ETH_IPV4_FRAG_TYPE 1254 }; 1255 1256 /* 1257 * eth IPv4 Fragment Type 1258 */ 1259 enum eth_ip_type 1260 { 1261 ETH_IPV4 /* IPv4 */, 1262 ETH_IPV6 /* IPv6 */, 1263 MAX_ETH_IP_TYPE 1264 }; 1265 1266 /* 1267 * Ethernet Ramrod Command IDs 1268 */ 1269 enum eth_ramrod_cmd_id 1270 { 1271 ETH_RAMROD_UNUSED, 1272 ETH_RAMROD_VPORT_START /* VPort Start Ramrod */, 1273 ETH_RAMROD_VPORT_UPDATE /* VPort Update Ramrod */, 1274 ETH_RAMROD_VPORT_STOP /* VPort Stop Ramrod */, 1275 ETH_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */, 1276 ETH_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */, 1277 ETH_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */, 1278 ETH_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */, 1279 ETH_RAMROD_FILTERS_UPDATE /* Add or Remove Mac/Vlan/Pair filters */, 1280 ETH_RAMROD_RX_QUEUE_UPDATE /* RX Queue Update Ramrod */, 1281 ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION /* RX - Create an Openflow Action */, 1282 ETH_RAMROD_RX_ADD_OPENFLOW_FILTER /* RX - Add an Openflow Filter to the Searcher */, 1283 ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER /* RX - Delete an Openflow Filter to the Searcher */, 1284 ETH_RAMROD_RX_ADD_UDP_FILTER /* RX - Add a UDP Filter to the Searcher */, 1285 ETH_RAMROD_RX_DELETE_UDP_FILTER /* RX - Delete a UDP Filter to the Searcher */, 1286 ETH_RAMROD_RX_CREATE_GFT_ACTION /* RX - Create a Gft Action */, 1287 ETH_RAMROD_GFT_UPDATE_FILTER /* RX - Add/Delete a GFT Filter to the Searcher */, 1288 ETH_RAMROD_TX_QUEUE_UPDATE /* TX Queue Update Ramrod */, 1289 MAX_ETH_RAMROD_CMD_ID 1290 }; 1291 1292 /* 1293 * return code from eth sp ramrods 1294 */ 1295 struct eth_return_code 1296 { 1297 u8 value; 1298 #define ETH_RETURN_CODE_ERR_CODE_MASK 0x1F /* error code (use enum eth_error_code) */ 1299 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0 1300 #define ETH_RETURN_CODE_RESERVED_MASK 0x3 1301 #define ETH_RETURN_CODE_RESERVED_SHIFT 5 1302 #define ETH_RETURN_CODE_RX_TX_MASK 0x1 /* rx path - 0, tx path - 1 */ 1303 #define ETH_RETURN_CODE_RX_TX_SHIFT 7 1304 }; 1305 1306 /* 1307 * What to do in case an error occurs 1308 */ 1309 enum eth_tx_err 1310 { 1311 ETH_TX_ERR_DROP /* Drop erroneous packet. */, 1312 ETH_TX_ERR_ASSERT_MALICIOUS /* Assert an interrupt for PF, declare as malicious for VF */, 1313 MAX_ETH_TX_ERR 1314 }; 1315 1316 /* 1317 * Array of the different error type behaviors 1318 */ 1319 struct eth_tx_err_vals 1320 { 1321 __le16 values; 1322 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1 /* Wrong VLAN insertion mode (use enum eth_tx_err) */ 1323 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0 1324 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1 /* Packet is below minimal size (use enum eth_tx_err) */ 1325 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1 1326 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1 /* Vport has sent spoofed packet (use enum eth_tx_err) */ 1327 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2 1328 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1 /* Packet with illegal type of inband tag (use enum eth_tx_err) */ 1329 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3 1330 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1 /* Packet marked for VLAN insertion when inband tag is present (use enum eth_tx_err) */ 1331 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4 1332 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1 /* Non LSO packet larger than MTU (use enum eth_tx_err) */ 1333 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5 1334 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1 /* VF/PF has sent LLDP/PFC or any other type of control packet which is not allowed to (use enum eth_tx_err) */ 1335 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6 1336 #define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF 1337 #define ETH_TX_ERR_VALS_RESERVED_SHIFT 7 1338 }; 1339 1340 /* 1341 * vport rss configuration data 1342 */ 1343 struct eth_vport_rss_config 1344 { 1345 __le16 capabilities; 1346 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1 /* configuration of the IpV4 2-tuple capability */ 1347 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0 1348 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1 /* configuration of the IpV6 2-tuple capability */ 1349 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1 1350 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1 /* configuration of the IpV4 4-tuple capability for TCP */ 1351 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2 1352 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1 /* configuration of the IpV6 4-tuple capability for TCP */ 1353 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3 1354 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1 /* configuration of the IpV4 4-tuple capability for UDP */ 1355 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4 1356 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1 /* configuration of the IpV6 4-tuple capability for UDP */ 1357 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5 1358 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1 /* configuration of the 5-tuple capability */ 1359 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6 1360 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF /* if set update the rss keys */ 1361 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7 1362 u8 rss_id /* The RSS engine ID. Must be allocated to each vport with RSS enabled. Total number of RSS engines is ETH_RSS_ENGINE_NUM_ , according to chip type. */; 1363 u8 rss_mode /* The RSS mode for this function (use enum eth_vport_rss_mode) */; 1364 u8 update_rss_key /* if set update the rss key */; 1365 u8 update_rss_ind_table /* if set update the indirection table values */; 1366 u8 update_rss_capabilities /* if set update the capabilities and indirection table size. */; 1367 u8 tbl_size /* rss mask (Tbl size) */; 1368 __le32 reserved2[2]; 1369 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM] /* RSS indirection table */; 1370 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS] /* RSS key supplied to us by OS */; 1371 __le32 reserved3[2]; 1372 }; 1373 1374 /* 1375 * eth vport RSS mode 1376 */ 1377 enum eth_vport_rss_mode 1378 { 1379 ETH_VPORT_RSS_MODE_DISABLED /* RSS Disabled */, 1380 ETH_VPORT_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */, 1381 MAX_ETH_VPORT_RSS_MODE 1382 }; 1383 1384 /* 1385 * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ 1386 */ 1387 struct eth_vport_rx_mode 1388 { 1389 __le16 state; 1390 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1 /* drop all unicast packets */ 1391 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0 1392 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1 /* accept all unicast packets (subject to vlan) */ 1393 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1 1394 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1 /* accept all unmatched unicast packets */ 1395 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2 1396 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1 /* drop all multicast packets */ 1397 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3 1398 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1 /* accept all multicast packets (subject to vlan) */ 1399 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4 1400 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 /* accept all broadcast packets (subject to vlan) */ 1401 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5 1402 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF 1403 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6 1404 }; 1405 1406 /* 1407 * Command for setting tpa parameters 1408 */ 1409 struct eth_vport_tpa_param 1410 { 1411 u8 tpa_ipv4_en_flg /* Enable TPA for IPv4 packets */; 1412 u8 tpa_ipv6_en_flg /* Enable TPA for IPv6 packets */; 1413 u8 tpa_ipv4_tunn_en_flg /* Enable TPA for IPv4 over tunnel */; 1414 u8 tpa_ipv6_tunn_en_flg /* Enable TPA for IPv6 over tunnel */; 1415 u8 tpa_pkt_split_flg /* If set, start each TPA segment on new BD (GRO mode). One BD per segment allowed. */; 1416 u8 tpa_hdr_data_split_flg /* If set, put header of first TPA segment on first BD and data on second BD. */; 1417 u8 tpa_gro_consistent_flg /* If set, GRO data consistent will checked for TPA continue */; 1418 u8 tpa_max_aggs_num /* maximum number of opened aggregations per v-port */; 1419 __le16 tpa_max_size /* maximal size for the aggregated TPA packets */; 1420 __le16 tpa_min_size_to_start /* minimum TCP payload size for a packet to start aggregation */; 1421 __le16 tpa_min_size_to_cont /* minimum TCP payload size for a packet to continue aggregation */; 1422 u8 max_buff_num /* maximal number of buffers that can be used for one aggregation */; 1423 u8 reserved; 1424 }; 1425 1426 /* 1427 * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ 1428 */ 1429 struct eth_vport_tx_mode 1430 { 1431 __le16 state; 1432 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1 /* drop all unicast packets */ 1433 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0 1434 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1 /* accept all unicast packets (subject to vlan) */ 1435 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1 1436 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1 /* drop all multicast packets */ 1437 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2 1438 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1 /* accept all multicast packets (subject to vlan) */ 1439 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3 1440 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 /* accept all broadcast packets (subject to vlan) */ 1441 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4 1442 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF 1443 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5 1444 }; 1445 1446 /* 1447 * GFT filter update action type. 1448 */ 1449 enum gft_filter_update_action 1450 { 1451 GFT_ADD_FILTER, 1452 GFT_DELETE_FILTER, 1453 MAX_GFT_FILTER_UPDATE_ACTION 1454 }; 1455 1456 /* 1457 * Ramrod data for rx add openflow filter 1458 */ 1459 struct rx_add_openflow_filter_data 1460 { 1461 __le16 action_icid /* CID of Action to run for this filter */; 1462 u8 priority /* Searcher String - Packet priority */; 1463 u8 reserved0; 1464 __le32 tenant_id /* Searcher String - Tenant ID */; 1465 __le16 dst_mac_hi /* Searcher String - Destination Mac Bytes 0 to 1 */; 1466 __le16 dst_mac_mid /* Searcher String - Destination Mac Bytes 2 to 3 */; 1467 __le16 dst_mac_lo /* Searcher String - Destination Mac Bytes 4 to 5 */; 1468 __le16 src_mac_hi /* Searcher String - Source Mac 0 to 1 */; 1469 __le16 src_mac_mid /* Searcher String - Source Mac 2 to 3 */; 1470 __le16 src_mac_lo /* Searcher String - Source Mac 4 to 5 */; 1471 __le16 vlan_id /* Searcher String - Vlan ID */; 1472 __le16 l2_eth_type /* Searcher String - Last L2 Ethertype */; 1473 u8 ipv4_dscp /* Searcher String - IPv4 6 MSBs of the TOS Field */; 1474 u8 ipv4_frag_type /* Searcher String - IPv4 Fragmentation Type (use enum eth_ipv4_frag_type) */; 1475 u8 ipv4_over_ip /* Searcher String - IPv4 Over IP Type */; 1476 u8 tenant_id_exists /* Searcher String - Tenant ID Exists */; 1477 __le32 ipv4_dst_addr /* Searcher String - IPv4 Destination Address */; 1478 __le32 ipv4_src_addr /* Searcher String - IPv4 Source Address */; 1479 __le16 l4_dst_port /* Searcher String - TCP/UDP Destination Port */; 1480 __le16 l4_src_port /* Searcher String - TCP/UDP Source Port */; 1481 }; 1482 1483 /* 1484 * Ramrod data for rx create gft action 1485 */ 1486 struct rx_create_gft_action_data 1487 { 1488 u8 vport_id /* Vport Id of GFT Action */; 1489 u8 reserved[7]; 1490 }; 1491 1492 /* 1493 * Ramrod data for rx create openflow action 1494 */ 1495 struct rx_create_openflow_action_data 1496 { 1497 u8 vport_id /* ID of RX queue */; 1498 u8 reserved[7]; 1499 }; 1500 1501 /* 1502 * Ramrod data for rx queue start ramrod 1503 */ 1504 struct rx_queue_start_ramrod_data 1505 { 1506 __le16 rx_queue_id /* ID of RX queue */; 1507 __le16 num_of_pbl_pages /* Number of pages in CQE PBL */; 1508 __le16 bd_max_bytes /* maximal bytes that can be places on the bd */; 1509 __le16 sb_id /* Status block ID */; 1510 u8 sb_index /* index of the protocol index */; 1511 u8 vport_id /* ID of virtual port */; 1512 u8 default_rss_queue_flg /* set queue as default rss queue if set */; 1513 u8 complete_cqe_flg /* post completion to the CQE ring if set */; 1514 u8 complete_event_flg /* post completion to the event ring if set */; 1515 u8 stats_counter_id /* Statistics counter ID */; 1516 u8 pin_context /* Pin context in CCFC to improve performance */; 1517 u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD/SGE fetch */; 1518 u8 pxp_tph_valid_pkt /* PXP command TPH Valid - for packet placement */; 1519 u8 pxp_st_hint /* PXP command Steering tag hint. Use enum pxp_tph_st_hint */; 1520 __le16 pxp_st_index /* PXP command Steering tag index */; 1521 u8 pmd_mode /* Indicates that current queue belongs to poll-mode driver */; 1522 u8 notify_en /* Indicates that the current queue is using the TX notification queue mechanism - should be set only for PMD queue */; 1523 u8 toggle_val /* Initial value for the toggle valid bit - used in PMD mode */; 1524 u8 vf_rx_prod_index /* Index of RX producers in VF zone. Used for VF only. */; 1525 u8 vf_rx_prod_use_zone_a /* Backward compatibility mode. If set, unprotected mStorm queue zone will used for VF RX producers instead of VF zone. */; 1526 u8 reserved[5]; 1527 __le16 reserved1 /* FW reserved. */; 1528 struct regpair cqe_pbl_addr /* Base address on host of CQE PBL */; 1529 struct regpair bd_base /* bd address of the first bd page */; 1530 struct regpair reserved2 /* FW reserved. */; 1531 }; 1532 1533 /* 1534 * Ramrod data for rx queue stop ramrod 1535 */ 1536 struct rx_queue_stop_ramrod_data 1537 { 1538 __le16 rx_queue_id /* ID of RX queue */; 1539 u8 complete_cqe_flg /* post completion to the CQE ring if set */; 1540 u8 complete_event_flg /* post completion to the event ring if set */; 1541 u8 vport_id /* ID of virtual port */; 1542 u8 reserved[3]; 1543 }; 1544 1545 /* 1546 * Ramrod data for rx queue update ramrod 1547 */ 1548 struct rx_queue_update_ramrod_data 1549 { 1550 __le16 rx_queue_id /* ID of RX queue */; 1551 u8 complete_cqe_flg /* post completion to the CQE ring if set */; 1552 u8 complete_event_flg /* post completion to the event ring if set */; 1553 u8 vport_id /* ID of virtual port */; 1554 u8 set_default_rss_queue /* If set, update default rss queue to this RX queue. */; 1555 u8 reserved[3]; 1556 u8 reserved1 /* FW reserved. */; 1557 u8 reserved2 /* FW reserved. */; 1558 u8 reserved3 /* FW reserved. */; 1559 __le16 reserved4 /* FW reserved. */; 1560 __le16 reserved5 /* FW reserved. */; 1561 struct regpair reserved6 /* FW reserved. */; 1562 }; 1563 1564 /* 1565 * Ramrod data for rx Add UDP Filter 1566 */ 1567 struct rx_udp_filter_data 1568 { 1569 __le16 action_icid /* CID of Action to run for this filter */; 1570 __le16 vlan_id /* Searcher String - Vlan ID */; 1571 u8 ip_type /* Searcher String - IP Type (use enum eth_ip_type) */; 1572 u8 tenant_id_exists /* Searcher String - Tenant ID Exists */; 1573 __le16 reserved1; 1574 __le32 ip_dst_addr[4] /* Searcher String - IP Destination Address, for IPv4 use ip_dst_addr[0] only */; 1575 __le32 ip_src_addr[4] /* Searcher String - IP Source Address, for IPv4 use ip_dst_addr[0] only */; 1576 __le16 udp_dst_port /* Searcher String - UDP Destination Port */; 1577 __le16 udp_src_port /* Searcher String - UDP Source Port */; 1578 __le32 tenant_id /* Searcher String - Tenant ID */; 1579 }; 1580 1581 /* 1582 * add or delete GFT filter - filter is packet header of type of packet wished to pass certain FW flow 1583 */ 1584 struct rx_update_gft_filter_data 1585 { 1586 struct regpair pkt_hdr_addr /* Pointer to Packet Header That Defines GFT Filter */; 1587 __le16 pkt_hdr_length /* Packet Header Length */; 1588 __le16 action_icid /* Action icid. Valid if action_icid_valid flag set. */; 1589 __le16 rx_qid /* RX queue ID. Valid if rx_qid_valid set. */; 1590 __le16 flow_id /* RX flow ID. Valid if flow_id_valid set. */; 1591 __le16 vport_id /* RX vport Id. For drop flow, set to ETH_GFT_TRASHCAN_VPORT. */; 1592 u8 action_icid_valid /* If set, action_icid will used for GFT filter update. */; 1593 u8 rx_qid_valid /* If set, rx_qid will used for traffic steering, in additional to vport_id. flow_id_valid must be cleared. If cleared, queue ID will selected by RSS. */; 1594 u8 flow_id_valid /* If set, flow_id will reported by CQE, rx_qid_valid must be cleared. If cleared, flow_id 0 will reported by CQE. */; 1595 u8 filter_action /* Use to set type of action on filter (use enum gft_filter_update_action) */; 1596 u8 assert_on_error /* 0 - dont assert in case of error. Just return an error code. 1 - assert in case of error. */; 1597 u8 reserved; 1598 }; 1599 1600 /* 1601 * Ramrod data for tx queue start ramrod 1602 */ 1603 struct tx_queue_start_ramrod_data 1604 { 1605 __le16 sb_id /* Status block ID */; 1606 u8 sb_index /* Status block protocol index */; 1607 u8 vport_id /* VPort ID */; 1608 u8 reserved0 /* FW reserved. (qcn_rl_en) */; 1609 u8 stats_counter_id /* Statistics counter ID to use */; 1610 __le16 qm_pq_id /* QM PQ ID */; 1611 u8 flags; 1612 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1 /* 0: Enable QM opportunistic flow. 1: Disable QM opportunistic flow */ 1613 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0 1614 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1 /* If set, Test Mode - packets will be duplicated by Xstorm handler */ 1615 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1 1616 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1 /* If set, Test Mode - packets destination will be determined by dest_port_mode field from Tx BD */ 1617 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2 1618 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1 /* Indicates that current queue belongs to poll-mode driver */ 1619 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3 1620 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1 /* Indicates that the current queue is using the TX notification queue mechanism - should be set only for PMD queue */ 1621 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4 1622 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1 /* Pin context in CCFC to improve performance */ 1623 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5 1624 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3 1625 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6 1626 u8 pxp_st_hint /* PXP command Steering tag hint (use enum pxp_tph_st_hint) */; 1627 u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD fetch */; 1628 u8 pxp_tph_valid_pkt /* PXP command TPH Valid - for packet fetch */; 1629 __le16 pxp_st_index /* PXP command Steering tag index */; 1630 __le16 comp_agg_size /* TX completion min agg size - for PMD queues */; 1631 __le16 queue_zone_id /* queue zone ID to use */; 1632 __le16 reserved2 /* FW reserved. (test_dup_count) */; 1633 __le16 pbl_size /* Number of BD pages pointed by PBL */; 1634 __le16 tx_queue_id /* unique Queue ID - currently used only by PMD flow */; 1635 __le16 same_as_last_id /* Unique Same-As-Last Resource ID - improves performance for same-as-last packets per connection (range 0..ETH_TX_NUM_SAME_AS_LAST_ENTRIES-1 IDs available) */; 1636 __le16 reserved[3]; 1637 struct regpair pbl_base_addr /* address of the pbl page */; 1638 struct regpair bd_cons_address /* BD consumer address in host - for PMD queues */; 1639 }; 1640 1641 /* 1642 * Ramrod data for tx queue stop ramrod 1643 */ 1644 struct tx_queue_stop_ramrod_data 1645 { 1646 __le16 reserved[4]; 1647 }; 1648 1649 /* 1650 * Ramrod data for tx queue update ramrod 1651 */ 1652 struct tx_queue_update_ramrod_data 1653 { 1654 __le16 update_qm_pq_id_flg /* Flag to Update QM PQ ID */; 1655 __le16 qm_pq_id /* Updated QM PQ ID */; 1656 __le32 reserved0; 1657 struct regpair reserved1[5]; 1658 }; 1659 1660 /* 1661 * Ramrod data for vport update ramrod 1662 */ 1663 struct vport_filter_update_ramrod_data 1664 { 1665 struct eth_filter_cmd_header filter_cmd_hdr /* Header for Filter Commands (RX/TX, Add/Remove/Replace, etc) */; 1666 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT] /* Filter Commands */; 1667 }; 1668 1669 /* 1670 * Ramrod data for vport start ramrod 1671 */ 1672 struct vport_start_ramrod_data 1673 { 1674 u8 vport_id; 1675 u8 sw_fid; 1676 __le16 mtu; 1677 u8 drop_ttl0_en /* if set, drop packet with ttl=0 */; 1678 u8 inner_vlan_removal_en; 1679 struct eth_vport_rx_mode rx_mode /* Rx filter data */; 1680 struct eth_vport_tx_mode tx_mode /* Tx filter data */; 1681 struct eth_vport_tpa_param tpa_param /* TPA configuration parameters */; 1682 __le16 default_vlan /* Default Vlan value to be forced by FW */; 1683 u8 tx_switching_en /* Tx switching is enabled for current Vport */; 1684 u8 anti_spoofing_en /* Anti-spoofing verification is set for current Vport */; 1685 u8 default_vlan_en /* If set, the default Vlan value is forced by the FW */; 1686 u8 handle_ptp_pkts /* If set, the vport handles PTP Timesync Packets */; 1687 u8 silent_vlan_removal_en /* If enable then innerVlan will be striped and not written to cqe */; 1688 u8 untagged /* If set untagged filter (vlan0) is added to current Vport, otherwise port is marked as any-vlan */; 1689 struct eth_tx_err_vals tx_err_behav /* Desired behavior per TX error type */; 1690 u8 zero_placement_offset /* If set, ETH header padding will not inserted. placement_offset will be zero. */; 1691 u8 ctl_frame_mac_check_en /* If set, control frames will be filtered according to MAC check. */; 1692 u8 ctl_frame_ethtype_check_en /* If set, control frames will be filtered according to ethtype check. */; 1693 u8 reserved[1]; 1694 }; 1695 1696 /* 1697 * Ramrod data for vport stop ramrod 1698 */ 1699 struct vport_stop_ramrod_data 1700 { 1701 u8 vport_id; 1702 u8 reserved[7]; 1703 }; 1704 1705 /* 1706 * Ramrod data for vport update ramrod 1707 */ 1708 struct vport_update_ramrod_data_cmn 1709 { 1710 u8 vport_id; 1711 u8 update_rx_active_flg /* set if rx active flag should be handled */; 1712 u8 rx_active_flg /* rx active flag value */; 1713 u8 update_tx_active_flg /* set if tx active flag should be handled */; 1714 u8 tx_active_flg /* tx active flag value */; 1715 u8 update_rx_mode_flg /* set if rx state data should be handled */; 1716 u8 update_tx_mode_flg /* set if tx state data should be handled */; 1717 u8 update_approx_mcast_flg /* set if approx. mcast data should be handled */; 1718 u8 update_rss_flg /* set if rss data should be handled */; 1719 u8 update_inner_vlan_removal_en_flg /* set if inner_vlan_removal_en should be handled */; 1720 u8 inner_vlan_removal_en; 1721 u8 update_tpa_param_flg /* set if tpa parameters should be handled, TPA must be disable before */; 1722 u8 update_tpa_en_flg /* set if tpa enable changes */; 1723 u8 update_tx_switching_en_flg /* set if tx switching en flag should be handled */; 1724 u8 tx_switching_en /* tx switching en value */; 1725 u8 update_anti_spoofing_en_flg /* set if anti spoofing flag should be handled */; 1726 u8 anti_spoofing_en /* Anti-spoofing verification en value */; 1727 u8 update_handle_ptp_pkts /* set if handle_ptp_pkts should be handled. */; 1728 u8 handle_ptp_pkts /* If set, the vport handles PTP Timesync Packets */; 1729 u8 update_default_vlan_en_flg /* If set, the default Vlan enable flag is updated */; 1730 u8 default_vlan_en /* If set, the default Vlan value is forced by the FW */; 1731 u8 update_default_vlan_flg /* If set, the default Vlan value is updated */; 1732 __le16 default_vlan /* Default Vlan value to be forced by FW */; 1733 u8 update_accept_any_vlan_flg /* set if accept_any_vlan should be handled */; 1734 u8 accept_any_vlan /* accept_any_vlan updated value */; 1735 u8 silent_vlan_removal_en /* Set to remove vlan silently, update_inner_vlan_removal_en_flg must be enabled as well. If Rx is in noSgl mode send rx_queue_update_ramrod_data */; 1736 u8 update_mtu_flg /* If set, MTU will be updated. Vport must be not active. */; 1737 __le16 mtu /* New MTU value. Used if update_mtu_flg are set */; 1738 u8 update_ctl_frame_checks_en_flg /* If set, ctl_frame_mac_check_en and ctl_frame_ethtype_check_en will be updated */; 1739 u8 ctl_frame_mac_check_en /* If set, control frames will be filtered according to MAC check. */; 1740 u8 ctl_frame_ethtype_check_en /* If set, control frames will be filtered according to ethtype check. */; 1741 u8 reserved[15]; 1742 }; 1743 1744 struct vport_update_ramrod_mcast 1745 { 1746 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS] /* multicast bins */; 1747 }; 1748 1749 /* 1750 * Ramrod data for vport update ramrod 1751 */ 1752 struct vport_update_ramrod_data 1753 { 1754 struct vport_update_ramrod_data_cmn common /* Common data for all vport update ramrods */; 1755 struct eth_vport_rx_mode rx_mode /* vport rx mode bitmap */; 1756 struct eth_vport_tx_mode tx_mode /* vport tx mode bitmap */; 1757 __le32 reserved[3]; 1758 struct eth_vport_tpa_param tpa_param /* TPA configuration parameters */; 1759 struct vport_update_ramrod_mcast approx_mcast; 1760 struct eth_vport_rss_config rss_config /* rss config data */; 1761 }; 1762 1763 struct E4XstormEthConnAgCtxDqExtLdPart 1764 { 1765 u8 reserved0 /* cdu_validation */; 1766 u8 state /* state */; 1767 u8 flags0; 1768 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1769 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 1770 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 1771 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1 1772 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 1773 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2 1774 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 1775 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 1776 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1 /* bit4 */ 1777 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4 1778 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1 /* cf_array_active */ 1779 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5 1780 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1 /* bit6 */ 1781 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6 1782 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1 /* bit7 */ 1783 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7 1784 u8 flags1; 1785 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1 /* bit8 */ 1786 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0 1787 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1 /* bit9 */ 1788 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1 1789 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1 /* bit10 */ 1790 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2 1791 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 /* bit11 */ 1792 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 1793 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_MASK 0x1 /* bit12 */ 1794 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_SHIFT 4 1795 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_MASK 0x1 /* bit13 */ 1796 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_SHIFT 5 1797 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 1798 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6 1799 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 1800 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7 1801 u8 flags2; 1802 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3 /* timer0cf */ 1803 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0 1804 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3 /* timer1cf */ 1805 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2 1806 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3 /* timer2cf */ 1807 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4 1808 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3 /* timer_stop_all */ 1809 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6 1810 u8 flags3; 1811 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3 /* cf4 */ 1812 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0 1813 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3 /* cf5 */ 1814 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2 1815 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3 /* cf6 */ 1816 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4 1817 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3 /* cf7 */ 1818 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6 1819 u8 flags4; 1820 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3 /* cf8 */ 1821 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0 1822 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3 /* cf9 */ 1823 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2 1824 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3 /* cf10 */ 1825 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4 1826 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3 /* cf11 */ 1827 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6 1828 u8 flags5; 1829 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3 /* cf12 */ 1830 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0 1831 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3 /* cf13 */ 1832 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2 1833 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3 /* cf14 */ 1834 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4 1835 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3 /* cf15 */ 1836 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6 1837 u8 flags6; 1838 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 1839 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0 1840 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3 /* cf_array_cf */ 1841 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2 1842 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3 /* cf18 */ 1843 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4 1844 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3 /* cf19 */ 1845 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6 1846 u8 flags7; 1847 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3 /* cf20 */ 1848 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0 1849 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3 /* cf21 */ 1850 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2 1851 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 /* cf22 */ 1852 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 1853 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 /* cf0en */ 1854 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 1855 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 /* cf1en */ 1856 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 1857 u8 flags8; 1858 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 /* cf2en */ 1859 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 1860 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 /* cf3en */ 1861 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 1862 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 /* cf4en */ 1863 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 1864 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 /* cf5en */ 1865 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 1866 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 /* cf6en */ 1867 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 1868 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1 /* cf7en */ 1869 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5 1870 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 /* cf8en */ 1871 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 1872 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 /* cf9en */ 1873 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 1874 u8 flags9; 1875 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 /* cf10en */ 1876 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 1877 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 /* cf11en */ 1878 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 1879 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 /* cf12en */ 1880 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 1881 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 /* cf13en */ 1882 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 1883 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 /* cf14en */ 1884 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 1885 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 /* cf15en */ 1886 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 1887 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 1888 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6 1889 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1 /* cf_array_cf_en */ 1890 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7 1891 u8 flags10; 1892 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1 /* cf18en */ 1893 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0 1894 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 1895 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1 1896 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 1897 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2 1898 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1 /* cf21en */ 1899 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3 1900 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1901 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 1902 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 1903 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5 1904 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1 /* rule0en */ 1905 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6 1906 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1 /* rule1en */ 1907 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7 1908 u8 flags11; 1909 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1 /* rule2en */ 1910 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0 1911 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1 /* rule3en */ 1912 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1 1913 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 1914 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2 1915 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 /* rule5en */ 1916 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 1917 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 /* rule6en */ 1918 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 1919 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 /* rule7en */ 1920 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 1921 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 /* rule8en */ 1922 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 1923 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 /* rule9en */ 1924 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 1925 u8 flags12; 1926 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 /* rule10en */ 1927 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 1928 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 /* rule11en */ 1929 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 1930 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 /* rule12en */ 1931 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 1932 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 /* rule13en */ 1933 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 1934 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 /* rule14en */ 1935 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 1936 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 /* rule15en */ 1937 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 1938 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 /* rule16en */ 1939 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 1940 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 /* rule17en */ 1941 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 1942 u8 flags13; 1943 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 /* rule18en */ 1944 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 1945 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 /* rule19en */ 1946 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 1947 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 /* rule20en */ 1948 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 1949 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 /* rule21en */ 1950 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 1951 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 /* rule22en */ 1952 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 1953 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 /* rule23en */ 1954 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 1955 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 /* rule24en */ 1956 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 1957 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 /* rule25en */ 1958 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 1959 u8 flags14; 1960 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 1961 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0 1962 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 1963 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1 1964 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 1965 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2 1966 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 1967 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3 1968 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 1969 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4 1970 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 1971 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 1972 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3 /* cf23 */ 1973 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6 1974 u8 edpm_event_id /* byte2 */; 1975 __le16 physical_q0 /* physical_q0 */; 1976 __le16 e5_reserved1 /* physical_q1 */; 1977 __le16 edpm_num_bds /* physical_q2 */; 1978 __le16 tx_bd_cons /* word3 */; 1979 __le16 tx_bd_prod /* word4 */; 1980 __le16 tx_class /* word5 */; 1981 __le16 conn_dpi /* conn_dpi */; 1982 u8 byte3 /* byte3 */; 1983 u8 byte4 /* byte4 */; 1984 u8 byte5 /* byte5 */; 1985 u8 byte6 /* byte6 */; 1986 __le32 reg0 /* reg0 */; 1987 __le32 reg1 /* reg1 */; 1988 __le32 reg2 /* reg2 */; 1989 __le32 reg3 /* reg3 */; 1990 __le32 reg4 /* reg4 */; 1991 }; 1992 1993 struct e4_mstorm_eth_conn_ag_ctx 1994 { 1995 u8 byte0 /* cdu_validation */; 1996 u8 byte1 /* state */; 1997 u8 flags0; 1998 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1999 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 2000 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2001 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 2002 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2003 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2 2004 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2005 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4 2006 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2007 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 2008 u8 flags1; 2009 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2010 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0 2011 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2012 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1 2013 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2014 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 2015 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2016 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 2017 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2018 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 2019 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2020 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 2021 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2022 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 2023 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2024 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 2025 __le16 word0 /* word0 */; 2026 __le16 word1 /* word1 */; 2027 __le32 reg0 /* reg0 */; 2028 __le32 reg1 /* reg1 */; 2029 }; 2030 2031 struct e4_xstorm_eth_hw_conn_ag_ctx 2032 { 2033 u8 reserved0 /* cdu_validation */; 2034 u8 state /* state */; 2035 u8 flags0; 2036 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2037 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 2038 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 2039 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1 2040 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 2041 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2 2042 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 2043 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 2044 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 2045 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4 2046 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 2047 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5 2048 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 2049 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6 2050 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 2051 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7 2052 u8 flags1; 2053 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 2054 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0 2055 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 2056 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1 2057 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 2058 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2 2059 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 2060 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3 2061 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 /* bit12 */ 2062 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 2063 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 /* bit13 */ 2064 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 2065 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 2066 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 2067 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 2068 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 2069 u8 flags2; 2070 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2071 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0 2072 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2073 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2 2074 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2075 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4 2076 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2077 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6 2078 u8 flags3; 2079 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 2080 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0 2081 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 2082 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2 2083 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 2084 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4 2085 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 2086 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6 2087 u8 flags4; 2088 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 2089 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0 2090 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 2091 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2 2092 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 2093 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4 2094 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 2095 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6 2096 u8 flags5; 2097 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 2098 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0 2099 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 2100 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2 2101 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 2102 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4 2103 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 2104 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6 2105 u8 flags6; 2106 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 2107 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 2108 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 /* cf_array_cf */ 2109 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 2110 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 2111 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4 2112 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 2113 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 2114 u8 flags7; 2115 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 2116 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 2117 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 2118 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2 2119 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 2120 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4 2121 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2122 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6 2123 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2124 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7 2125 u8 flags8; 2126 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2127 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0 2128 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2129 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1 2130 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 2131 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2 2132 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 2133 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3 2134 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 2135 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4 2136 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 2137 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5 2138 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 2139 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6 2140 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 2141 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7 2142 u8 flags9; 2143 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 2144 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0 2145 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 2146 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1 2147 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 2148 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2 2149 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 2150 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3 2151 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 2152 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4 2153 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 2154 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5 2155 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 2156 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 2157 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 /* cf_array_cf_en */ 2158 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 2159 u8 flags10; 2160 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 2161 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 2162 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 2163 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 2164 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 2165 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 2166 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 2167 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3 2168 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 2169 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 2170 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 2171 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 2172 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 2173 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6 2174 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 2175 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7 2176 u8 flags11; 2177 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 2178 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0 2179 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 2180 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1 2181 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 2182 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 2183 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2184 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3 2185 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2186 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4 2187 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2188 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5 2189 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 2190 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 2191 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 2192 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7 2193 u8 flags12; 2194 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 2195 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0 2196 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 2197 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1 2198 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 2199 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 2200 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 2201 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 2202 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 2203 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4 2204 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 2205 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5 2206 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 2207 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6 2208 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 2209 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7 2210 u8 flags13; 2211 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 2212 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0 2213 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 2214 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1 2215 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 2216 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 2217 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 2218 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 2219 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 2220 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 2221 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 2222 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 2223 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 2224 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 2225 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 2226 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 2227 u8 flags14; 2228 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 2229 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 2230 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 2231 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 2232 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 2233 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 2234 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 2235 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 2236 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 2237 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 2238 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 2239 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 2240 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */ 2241 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 2242 u8 edpm_event_id /* byte2 */; 2243 __le16 physical_q0 /* physical_q0 */; 2244 __le16 e5_reserved1 /* physical_q1 */; 2245 __le16 edpm_num_bds /* physical_q2 */; 2246 __le16 tx_bd_cons /* word3 */; 2247 __le16 tx_bd_prod /* word4 */; 2248 __le16 tx_class /* word5 */; 2249 __le16 conn_dpi /* conn_dpi */; 2250 }; 2251 2252 struct E5XstormEthConnAgCtxDqExtLdPart 2253 { 2254 u8 reserved0 /* cdu_validation */; 2255 u8 state_and_core_id /* state_and_core_id */; 2256 u8 flags0; 2257 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2258 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 2259 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 2260 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1 2261 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 2262 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2 2263 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 2264 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 2265 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1 /* bit4 */ 2266 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4 2267 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1 /* cf_array_active */ 2268 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5 2269 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1 /* bit6 */ 2270 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6 2271 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1 /* bit7 */ 2272 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7 2273 u8 flags1; 2274 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1 /* bit8 */ 2275 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0 2276 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1 /* bit9 */ 2277 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1 2278 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1 /* bit10 */ 2279 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2 2280 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 /* bit11 */ 2281 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 2282 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_COPY_CONDITION_LO_MASK 0x1 /* bit12 */ 2283 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_COPY_CONDITION_LO_SHIFT 4 2284 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_COPY_CONDITION_HI_MASK 0x1 /* bit13 */ 2285 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_COPY_CONDITION_HI_SHIFT 5 2286 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 2287 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6 2288 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 2289 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7 2290 u8 flags2; 2291 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3 /* timer0cf */ 2292 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0 2293 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3 /* timer1cf */ 2294 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2 2295 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3 /* timer2cf */ 2296 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4 2297 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3 /* timer_stop_all */ 2298 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6 2299 u8 flags3; 2300 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3 /* cf4 */ 2301 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0 2302 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3 /* cf5 */ 2303 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2 2304 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3 /* cf6 */ 2305 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4 2306 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3 /* cf7 */ 2307 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6 2308 u8 flags4; 2309 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3 /* cf8 */ 2310 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0 2311 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3 /* cf9 */ 2312 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2 2313 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3 /* cf10 */ 2314 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4 2315 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3 /* cf11 */ 2316 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6 2317 u8 flags5; 2318 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3 /* cf12 */ 2319 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0 2320 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3 /* cf13 */ 2321 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2 2322 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3 /* cf14 */ 2323 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4 2324 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3 /* cf15 */ 2325 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6 2326 u8 flags6; 2327 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 2328 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0 2329 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3 /* cf_array_cf */ 2330 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2 2331 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3 /* cf18 */ 2332 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4 2333 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3 /* cf19 */ 2334 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6 2335 u8 flags7; 2336 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3 /* cf20 */ 2337 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0 2338 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3 /* cf21 */ 2339 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2 2340 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 /* cf22 */ 2341 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 2342 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 /* cf0en */ 2343 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 2344 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 /* cf1en */ 2345 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 2346 u8 flags8; 2347 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 /* cf2en */ 2348 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 2349 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 /* cf3en */ 2350 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 2351 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 /* cf4en */ 2352 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 2353 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 /* cf5en */ 2354 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 2355 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 /* cf6en */ 2356 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 2357 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1 /* cf7en */ 2358 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5 2359 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 /* cf8en */ 2360 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 2361 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 /* cf9en */ 2362 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 2363 u8 flags9; 2364 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 /* cf10en */ 2365 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 2366 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 /* cf11en */ 2367 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 2368 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 /* cf12en */ 2369 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 2370 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 /* cf13en */ 2371 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 2372 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 /* cf14en */ 2373 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 2374 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 /* cf15en */ 2375 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 2376 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 2377 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6 2378 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1 /* cf_array_cf_en */ 2379 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7 2380 u8 flags10; 2381 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1 /* cf18en */ 2382 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0 2383 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 2384 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1 2385 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 2386 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2 2387 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1 /* cf21en */ 2388 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3 2389 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 2390 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 2391 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 2392 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5 2393 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1 /* rule0en */ 2394 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6 2395 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1 /* rule1en */ 2396 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7 2397 u8 flags11; 2398 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1 /* rule2en */ 2399 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0 2400 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1 /* rule3en */ 2401 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1 2402 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 2403 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2 2404 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 /* rule5en */ 2405 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 2406 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 /* rule6en */ 2407 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 2408 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 /* rule7en */ 2409 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 2410 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 /* rule8en */ 2411 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 2412 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 /* rule9en */ 2413 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 2414 u8 flags12; 2415 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 /* rule10en */ 2416 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 2417 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 /* rule11en */ 2418 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 2419 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 /* rule12en */ 2420 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 2421 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 /* rule13en */ 2422 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 2423 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 /* rule14en */ 2424 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 2425 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 /* rule15en */ 2426 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 2427 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 /* rule16en */ 2428 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 2429 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 /* rule17en */ 2430 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 2431 u8 flags13; 2432 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 /* rule18en */ 2433 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 2434 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 /* rule19en */ 2435 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 2436 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 /* rule20en */ 2437 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 2438 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 /* rule21en */ 2439 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 2440 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 /* rule22en */ 2441 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 2442 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 /* rule23en */ 2443 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 2444 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 /* rule24en */ 2445 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 2446 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 /* rule25en */ 2447 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 2448 u8 flags14; 2449 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 2450 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0 2451 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 2452 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1 2453 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 2454 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2 2455 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 2456 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3 2457 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 2458 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4 2459 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 2460 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 2461 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3 /* cf23 */ 2462 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6 2463 u8 edpm_vport /* byte2 */; 2464 __le16 physical_q0 /* physical_q0 */; 2465 __le16 tx_l2_edpm_usg_cnt /* physical_q1 */; 2466 __le16 edpm_num_bds /* physical_q2 */; 2467 __le16 tx_bd_cons /* word3 */; 2468 __le16 tx_bd_prod /* word4 */; 2469 __le16 tx_class /* word5 */; 2470 __le16 conn_dpi /* conn_dpi */; 2471 u8 byte3 /* byte3 */; 2472 u8 byte4 /* byte4 */; 2473 u8 byte5 /* byte5 */; 2474 u8 byte6 /* byte6 */; 2475 __le32 reg0 /* reg0 */; 2476 __le32 reg1 /* reg1 */; 2477 __le32 reg2 /* reg2 */; 2478 __le32 reg3 /* reg3 */; 2479 __le32 reg4 /* reg4 */; 2480 }; 2481 2482 struct e5_mstorm_eth_conn_ag_ctx 2483 { 2484 u8 byte0 /* cdu_validation */; 2485 u8 byte1 /* state_and_core_id */; 2486 u8 flags0; 2487 #define E5_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2488 #define E5_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 2489 #define E5_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2490 #define E5_MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 2491 #define E5_MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2492 #define E5_MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2 2493 #define E5_MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2494 #define E5_MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4 2495 #define E5_MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2496 #define E5_MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 2497 u8 flags1; 2498 #define E5_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2499 #define E5_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0 2500 #define E5_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2501 #define E5_MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1 2502 #define E5_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2503 #define E5_MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 2504 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2505 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 2506 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2507 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 2508 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2509 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 2510 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2511 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 2512 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2513 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 2514 __le16 word0 /* word0 */; 2515 __le16 word1 /* word1 */; 2516 __le32 reg0 /* reg0 */; 2517 __le32 reg1 /* reg1 */; 2518 }; 2519 2520 struct e5_xstorm_eth_hw_conn_ag_ctx 2521 { 2522 u8 reserved0 /* cdu_validation */; 2523 u8 state_and_core_id /* state_and_core_id */; 2524 u8 flags0; 2525 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2526 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 2527 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 2528 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1 2529 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 2530 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2 2531 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 2532 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 2533 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 2534 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4 2535 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 2536 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5 2537 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 2538 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6 2539 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 2540 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7 2541 u8 flags1; 2542 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 2543 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0 2544 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 2545 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1 2546 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 2547 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2 2548 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 2549 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3 2550 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_COPY_CONDITION_LO_MASK 0x1 /* bit12 */ 2551 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_COPY_CONDITION_LO_SHIFT 4 2552 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_COPY_CONDITION_HI_MASK 0x1 /* bit13 */ 2553 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_COPY_CONDITION_HI_SHIFT 5 2554 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 2555 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 2556 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 2557 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 2558 u8 flags2; 2559 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2560 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0 2561 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2562 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2 2563 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2564 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4 2565 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2566 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6 2567 u8 flags3; 2568 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 2569 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0 2570 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 2571 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2 2572 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 2573 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4 2574 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 2575 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6 2576 u8 flags4; 2577 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 2578 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0 2579 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 2580 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2 2581 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 2582 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4 2583 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 2584 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6 2585 u8 flags5; 2586 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 2587 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0 2588 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 2589 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2 2590 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 2591 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4 2592 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 2593 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6 2594 u8 flags6; 2595 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 2596 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 2597 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 /* cf_array_cf */ 2598 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 2599 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 2600 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4 2601 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 2602 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 2603 u8 flags7; 2604 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 2605 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 2606 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 2607 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2 2608 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 2609 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4 2610 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2611 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6 2612 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2613 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7 2614 u8 flags8; 2615 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2616 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0 2617 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2618 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1 2619 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 2620 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2 2621 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 2622 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3 2623 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 2624 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4 2625 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 2626 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5 2627 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 2628 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6 2629 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 2630 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7 2631 u8 flags9; 2632 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 2633 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0 2634 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 2635 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1 2636 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 2637 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2 2638 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 2639 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3 2640 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 2641 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4 2642 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 2643 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5 2644 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 2645 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 2646 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 /* cf_array_cf_en */ 2647 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 2648 u8 flags10; 2649 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 2650 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 2651 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 2652 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 2653 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 2654 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 2655 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 2656 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3 2657 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 2658 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 2659 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 2660 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 2661 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 2662 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6 2663 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 2664 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7 2665 u8 flags11; 2666 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 2667 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0 2668 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 2669 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1 2670 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 2671 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 2672 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2673 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3 2674 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2675 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4 2676 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2677 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5 2678 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 2679 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 2680 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 2681 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7 2682 u8 flags12; 2683 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 2684 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0 2685 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 2686 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1 2687 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 2688 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 2689 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 2690 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 2691 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 2692 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4 2693 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 2694 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5 2695 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 2696 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6 2697 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 2698 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7 2699 u8 flags13; 2700 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 2701 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0 2702 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 2703 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1 2704 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 2705 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 2706 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 2707 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 2708 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 2709 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 2710 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 2711 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 2712 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 2713 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 2714 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 2715 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 2716 u8 flags14; 2717 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 2718 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 2719 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 2720 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 2721 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 2722 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 2723 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 2724 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 2725 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 2726 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 2727 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 2728 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 2729 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */ 2730 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 2731 u8 edpm_vport /* byte2 */; 2732 __le16 physical_q0 /* physical_q0 */; 2733 __le16 tx_l2_edpm_usg_cnt /* physical_q1 */; 2734 __le16 edpm_num_bds /* physical_q2 */; 2735 __le16 tx_bd_cons /* word3 */; 2736 __le16 tx_bd_prod /* word4 */; 2737 __le16 tx_class /* word5 */; 2738 __le16 conn_dpi /* conn_dpi */; 2739 }; 2740 2741 /* 2742 * GFT CAM line struct 2743 */ 2744 struct gft_cam_line 2745 { 2746 __le32 camline; 2747 #define GFT_CAM_LINE_VALID_MASK 0x1 /* Indication if the line is valid. */ 2748 #define GFT_CAM_LINE_VALID_SHIFT 0 2749 #define GFT_CAM_LINE_DATA_MASK 0x3FFF /* Data bits, the word that compared with the profile key */ 2750 #define GFT_CAM_LINE_DATA_SHIFT 1 2751 #define GFT_CAM_LINE_MASK_BITS_MASK 0x3FFF /* Mask bits, indicate the bits in the data that are Dont-Care */ 2752 #define GFT_CAM_LINE_MASK_BITS_SHIFT 15 2753 #define GFT_CAM_LINE_RESERVED1_MASK 0x7 2754 #define GFT_CAM_LINE_RESERVED1_SHIFT 29 2755 }; 2756 2757 /* 2758 * GFT CAM line struct with fields breakout 2759 */ 2760 struct gft_cam_line_mapped 2761 { 2762 __le32 camline; 2763 #define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1 /* Indication if the line is valid. */ 2764 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0 2765 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1 /* (use enum gft_profile_ip_version) */ 2766 #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT 1 2767 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1 /* (use enum gft_profile_ip_version) */ 2768 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT 2 2769 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF /* (use enum gft_profile_upper_protocol_type) */ 2770 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT 3 2771 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF /* (use enum gft_profile_tunnel_type) */ 2772 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT 7 2773 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF 2774 #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT 11 2775 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1 2776 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT 15 2777 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1 2778 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT 16 2779 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF 2780 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17 2781 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF 2782 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT 21 2783 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF 2784 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT 25 2785 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7 2786 #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29 2787 }; 2788 2789 union gft_cam_line_union 2790 { 2791 struct gft_cam_line cam_line; 2792 struct gft_cam_line_mapped cam_line_mapped; 2793 }; 2794 2795 /* 2796 * Used in gft_profile_key: Indication for ip version 2797 */ 2798 enum gft_profile_ip_version 2799 { 2800 GFT_PROFILE_IPV4=0, 2801 GFT_PROFILE_IPV6=1, 2802 MAX_GFT_PROFILE_IP_VERSION 2803 }; 2804 2805 /* 2806 * Profile key stucr fot GFT logic in Prs 2807 */ 2808 struct gft_profile_key 2809 { 2810 __le16 profile_key; 2811 #define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */ 2812 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0 2813 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */ 2814 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1 2815 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF /* use enum gft_profile_upper_protocol_type (use enum gft_profile_upper_protocol_type) */ 2816 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2 2817 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */ 2818 #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6 2819 #define GFT_PROFILE_KEY_PF_ID_MASK 0xF 2820 #define GFT_PROFILE_KEY_PF_ID_SHIFT 10 2821 #define GFT_PROFILE_KEY_RESERVED0_MASK 0x3 2822 #define GFT_PROFILE_KEY_RESERVED0_SHIFT 14 2823 }; 2824 2825 /* 2826 * Used in gft_profile_key: Indication for tunnel type 2827 */ 2828 enum gft_profile_tunnel_type 2829 { 2830 GFT_PROFILE_NO_TUNNEL=0, 2831 GFT_PROFILE_VXLAN_TUNNEL=1, 2832 GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL=2, 2833 GFT_PROFILE_GRE_IP_TUNNEL=3, 2834 GFT_PROFILE_GENEVE_MAC_TUNNEL=4, 2835 GFT_PROFILE_GENEVE_IP_TUNNEL=5, 2836 MAX_GFT_PROFILE_TUNNEL_TYPE 2837 }; 2838 2839 /* 2840 * Used in gft_profile_key: Indication for protocol type 2841 */ 2842 enum gft_profile_upper_protocol_type 2843 { 2844 GFT_PROFILE_ROCE_PROTOCOL=0, 2845 GFT_PROFILE_RROCE_PROTOCOL=1, 2846 GFT_PROFILE_FCOE_PROTOCOL=2, 2847 GFT_PROFILE_ICMP_PROTOCOL=3, 2848 GFT_PROFILE_ARP_PROTOCOL=4, 2849 GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER=5, 2850 GFT_PROFILE_USER_TCP_DST_PORT_1_INNER=6, 2851 GFT_PROFILE_TCP_PROTOCOL=7, 2852 GFT_PROFILE_USER_UDP_DST_PORT_1_INNER=8, 2853 GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER=9, 2854 GFT_PROFILE_UDP_PROTOCOL=10, 2855 GFT_PROFILE_USER_IP_1_INNER=11, 2856 GFT_PROFILE_USER_IP_2_OUTER=12, 2857 GFT_PROFILE_USER_ETH_1_INNER=13, 2858 GFT_PROFILE_USER_ETH_2_OUTER=14, 2859 GFT_PROFILE_RAW=15, 2860 MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE 2861 }; 2862 2863 /* 2864 * GFT RAM line struct 2865 */ 2866 struct gft_ram_line 2867 { 2868 __le32 lo; 2869 #define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3 /* (use enum gft_vlan_select) */ 2870 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0 2871 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1 2872 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT 2 2873 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1 2874 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT 3 2875 #define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1 2876 #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT 4 2877 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1 2878 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT 5 2879 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1 2880 #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT 6 2881 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1 2882 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT 7 2883 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1 2884 #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT 8 2885 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1 2886 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT 9 2887 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1 2888 #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT 10 2889 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1 2890 #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT 11 2891 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1 2892 #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT 12 2893 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1 2894 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT 13 2895 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1 2896 #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT 14 2897 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1 2898 #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT 15 2899 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1 2900 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT 16 2901 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1 2902 #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT 17 2903 #define GFT_RAM_LINE_TTL_MASK 0x1 2904 #define GFT_RAM_LINE_TTL_SHIFT 18 2905 #define GFT_RAM_LINE_ETHERTYPE_MASK 0x1 2906 #define GFT_RAM_LINE_ETHERTYPE_SHIFT 19 2907 #define GFT_RAM_LINE_RESERVED0_MASK 0x1 2908 #define GFT_RAM_LINE_RESERVED0_SHIFT 20 2909 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1 2910 #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT 21 2911 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1 2912 #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT 22 2913 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1 2914 #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT 23 2915 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1 2916 #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT 24 2917 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1 2918 #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT 25 2919 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1 2920 #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT 26 2921 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1 2922 #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT 27 2923 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1 2924 #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT 28 2925 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1 2926 #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT 29 2927 #define GFT_RAM_LINE_DST_PORT_MASK 0x1 2928 #define GFT_RAM_LINE_DST_PORT_SHIFT 30 2929 #define GFT_RAM_LINE_SRC_PORT_MASK 0x1 2930 #define GFT_RAM_LINE_SRC_PORT_SHIFT 31 2931 __le32 hi; 2932 #define GFT_RAM_LINE_DSCP_MASK 0x1 2933 #define GFT_RAM_LINE_DSCP_SHIFT 0 2934 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1 2935 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT 1 2936 #define GFT_RAM_LINE_DST_IP_MASK 0x1 2937 #define GFT_RAM_LINE_DST_IP_SHIFT 2 2938 #define GFT_RAM_LINE_SRC_IP_MASK 0x1 2939 #define GFT_RAM_LINE_SRC_IP_SHIFT 3 2940 #define GFT_RAM_LINE_PRIORITY_MASK 0x1 2941 #define GFT_RAM_LINE_PRIORITY_SHIFT 4 2942 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1 2943 #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT 5 2944 #define GFT_RAM_LINE_VLAN_MASK 0x1 2945 #define GFT_RAM_LINE_VLAN_SHIFT 6 2946 #define GFT_RAM_LINE_DST_MAC_MASK 0x1 2947 #define GFT_RAM_LINE_DST_MAC_SHIFT 7 2948 #define GFT_RAM_LINE_SRC_MAC_MASK 0x1 2949 #define GFT_RAM_LINE_SRC_MAC_SHIFT 8 2950 #define GFT_RAM_LINE_TENANT_ID_MASK 0x1 2951 #define GFT_RAM_LINE_TENANT_ID_SHIFT 9 2952 #define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF 2953 #define GFT_RAM_LINE_RESERVED1_SHIFT 10 2954 }; 2955 2956 /* 2957 * Used in the first 2 bits for gft_ram_line: Indication for vlan mask 2958 */ 2959 enum gft_vlan_select 2960 { 2961 INNER_PROVIDER_VLAN=0, 2962 INNER_VLAN=1, 2963 OUTER_PROVIDER_VLAN=2, 2964 OUTER_VLAN=3, 2965 MAX_GFT_VLAN_SELECT 2966 }; 2967 2968 #endif /* __ECORE_HSI_ETH__ */ 2969