xref: /illumos-gate/usr/src/uts/sun/io/eri/eri_mac.h (revision 297a64e7779d7bd7140d1f3f2fa5db171aa21569)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_ERI_MAC_H
27 #define	_SYS_ERI_MAC_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #ifdef	__cplusplus
32 extern "C" {
33 #endif
34 
35 /*
36  * HOST MEMORY DATA STRUCTURES
37  * Transmit and Receive Descriptor Rings
38  */
39 
40 /* The Descriptor Ring base Addresses must be 2K-byte aligned */
41 
42 #define	ERI_GMDALIGN	(2048)
43 
44 /*
45  * The transmit and receiver Descriptor Rings are organized as "wrap-around
46  * descriptors and are of programmable size.
47  * Each descriptor consists of two double-word entries: a control/status entry
48  * and a pointer to a data buffer.
49  * The no. of entries is programmable in binary increments, from 32 to 8192.
50  * TBD: Even though the Receive Desriptor ring size is 8k, provide for a user
51  * configurable variable to specify the max.no. of Rx buffers posted.
52  */
53 
54 #define	ERI_TMDMAX	(4096)	/* Transmit descriptor ring size */
55 #define	ERI_RMDMAX	(4096)	/* Receive descriptor ring size */
56 
57 /*
58  * -----------------------------
59  * Transmit descriptor structure
60  * -----------------------------
61  */
62 
63 struct eri_tmd {
64 	uint64_t	tmd_flags;	/* INTME, SOP, EOP, cksum, bufsize */
65 	uint64_t	tmd_addr;	/* buffer address */
66 };
67 
68 /* fields in the tmd_flags */
69 
70 #define	ERI_TMD_BUFSIZE	(0x7fff << 0)	/* 0-14 : Tx Data buffer size */
71 					/* valid values in range 0 - 17k */
72 #define	ERI_TMD_CSSTART	(0x3f << 15)	/* 15-20 : Checksum start offset */
73 					/* value must be even */
74 #define	ERI_TMD_CSSTUFF	(0xff << 21)	/* 21-28 : Checksum stuff offset */
75 					/* value must be even */
76 #define	ERI_TMD_CSENABL	(1 << 29)	/* 29 : Enable checksum computation */
77 #define	ERI_TMD_EOP	(1 << 30)	/* 30 : End Of Packet flag */
78 #define	ERI_TMD_SOP	((uint64_t)1 << 31)	/* 31 : Packet Start flag */
79 #define	ERI_TMD_INTME	((uint64_t)1 << 32)	/* 32 : Interrupt me now */
80 #define	ERI_TMD_NOCRC	((uint64_t)1 << 33)	/* 33 : Do not insert CRC */
81 
82 #define	ERI_TMD_CSSTART_SHIFT 15	/* checksum start bit position */
83 #define	ERI_TMD_CSSTUFF_SHIFT 21	/* checksum stuff bit position */
84 
85 /*
86  * TCP Header offset within Ethernet Packet:
87  * 14 Bytes Ethernet Header + 20 IP Header.
88  */
89 
90 #define	ERI_TCPHDR_OFFSET	34
91 #define	ERI_IPHDR_OFFSET 	20
92 
93 /*
94  * TCP Checksum stuff offset within Ethernet packet:
95  * 34 Bytes up to TCP Header + 16 Bytes within TCP header
96  */
97 
98 #define	ERI_TCPCSUM_OFFSET	50
99 #define	ERI_TMDCSUM_CTL		(ERI_TMD_CSENABL | \
100 				(ERI_TCPHDR_OFFSET << ERI_TMD_CSSTART_SHIFT) | \
101 				(ERI_TCPCSUM_OFFSET << ERI_TMD_CSSTUFF_SHIFT))
102 /*
103  *	Programming Notes:
104  *
105  *	1. TX Kick Register is used to hand over TX descriptors to the hardware.
106  *	TX Completion Register is used by hardware to handover TX descriptors
107  *	back to the software.
108  *
109  *	2. ERI never writes back TX descriptors.
110  *
111  *	2. If a packet resides in more than one buffer, the Checksum_Enable,
112  *	Checksum_Stuff_Offset, Checksum_Start_Offset and Int_me fields need to
113  *	be set only in the first descriptor for the packet.
114  *
115  *	3. The hardware implementation relies on the fact that if a buffer
116  *	starts at an "odd" boundary, the DMA state machine can "rewind"
117  *	to the nearest burst boundary and execute a full DVMA burst Read.
118  *
119  *	There is no other alignment restriction for the transmit data buffer.
120  */
121 
122 /*
123  * -----------------------------
124  * Receive Descriptor structure
125  * ----------------------------
126  */
127 
128 struct rmd {
129 	uint64_t	rmd_flags;
130 		/* hash_val, hash_pass, bad, OWN, buf/data size, cksum */
131 	uint64_t	rmd_addr;	/* 8-byte aligned buffer address */
132 };
133 
134 /*
135  * fields in the rmd_flags
136  */
137 #define	ERI_RMD_CKSUM	(0xffff << 0)	/* 0-15 : checksum computed */
138 #define	ERI_RMD_BUFSIZE	(0x7fff << 16)	/* 16-30 : buffer/frame size */
139 #define	ERI_RMD_OWN	((uint64_t)1 << 31)	/* 31 : Ownership flag */
140 					/* 0 - owned by software */
141 					/* 1 - owned by hardware */
142 #define	ERI_RMD_RESERVED1	((uint64_t)0xfff << 32)	/* 32-43 : Reserved */
143 #define	ERI_RMD_HASHVAL	((uint64_t)0xffff << 44)	/* 44-59 : hash value */
144 #define	ERI_RMD_HASHPASS ((uint64_t)1 << 60)	/* 60 : pass hash filter */
145 #define	ERI_RMD_ALTERNATE	((uint64_t)1 << 61)
146 					/* 61 : matched alternate MAC adrs */
147 #define	ERI_RMD_BAD	((uint64_t)1 << 62)	/* 62 : bad CRC frame */
148 #define	ERI_RMD_RESERVED2	((uint64_t)1 << 63)	/* 63 : Reserved */
149 
150 #define	ERI_RMD_BUFSIZE_SHIFT 16	/* buffer/data size bit position */
151 
152 #define	ERI__RMD_BUFALIGN	8
153 
154 /*
155  * ERI REGISTER SPACE
156  * The comments are in the following format:
157  * Addres_Offset R/W Default Actual_size(bits) Description
158  */
159 
160 /*
161  * Global Register Space : Paritally Modified for ERI
162  */
163 struct global {
164     uint32_t seb_state;	/* 0x0000 RO   0x00000000 03 SEB State Register */
165     uint32_t config;	/* 0x0004 RW   0x00000000 17 Configuration Register */
166     uint32_t reserved2;	/* 0x0008 */
167     uint32_t status;	/* 0x000C R-AC 0x00000000 25 Int. Status Register */
168     uint32_t intmask;	/* 0x0010 RW   0xFFFFFFFF 12 Interrupt Mask Reg */
169     uint32_t intack;	/* 0x0014 WO   0x00000000 06 Interrupt Ack Register */
170     uint32_t reserved3;	/* 0x0018 */
171     uint32_t status_alias; /* 0x001C RO   0x00000000 25 Int. Stat Reg Alias */
172     uint32_t reserved4[1016];	/* To skip to 0x1000 */
173     uint32_t err_status; /* 0x1000 R-AC 0x00000000 03 PCI Error Status Reg. */
174     uint32_t reset;	/* 0x1010 RW-AC 0x00	  3  Software Reset Reg */
175 };
176 
177 /*
178  *
179  * SBus IO configuration (RW)
180  * To configure parameters that define the DMA burst and internal arbitration.
181  */
182 #define	ERI_SIOCFG_BSIZE32	(0x1 << 0) /* 32 byte burst sizeb state */
183 #define	ERI_SIOCFG_BSIZE64	(0x1 << 1) /* 64 byte burst sizeb state */
184 #define	ERI_SIOCFG_BSIZE128	(0x1 << 2) /* 128 byte burst sizeb state */
185 #define	ERI_SIOCFG_BMODE64	(0x1 << 3) /* Sbus 64 bit mode */
186 #define	ERI_SIOCFG_PARITY	(0x1 << 9) /* Sbus Parity enabled. */
187 
188 /*
189  * SEB State Register (RO)
190  * Reflects the internal state of the arbitration between TX and RX
191  * DMA Channels. Used for diagnostics only
192  */
193 #define	ERI_SEB_ARBSTS	(0x2 << 0)	/* Arbiter state */
194 #define	ERI_SEB_RXWON	(1 << 2)	/* RX won the arbitration */
195 
196 /*
197  * Global Configuration Register (RW)
198  * To configure parameters that define the DMA burst and internal arbitration.
199  * TX/RX_DMA_LIMIT: No. of data transfers in 64-byte multiples
200  *			0 - peririty changes at packet boundaries
201  * default:	0x042
202  */
203 #define	ERI_G_CONFIG_BURST_SIZE	(0x1 << 0)	/* 0:infinite/64-byte burst */
204 #define	ERI_G_CONFIG_TX_DMA_LIM	(0x1f << 1)	/* 5-1: TX_DMA_Limit */
205 #define	ERI_G_CONFIG_RX_DMA_LIM	(0x1f << 6)	/* 10-6: RX_DMA_Limit */
206 
207 #define	ERI_G_CONFIG_BURST_64	0x0	/* max burst size 64 */
208 #define	ERI_G_CONFIG_BURST_INF	0x1	/* infinite burst for whole pkt len */
209 
210 #define	ERI_G_CONFIG_TX_DMA_LIM_SHIFT	1
211 #define	ERI_G_CONFIG_RX_DMA_LIM_SHIFT	6
212 
213 /*
214  * Global Interrupt Status Register (R-AC)
215  * size:	32 bits: 0-31
216  * default:	0x00000000
217  * This is the top level register used to communicate to the software events
218  * that were detected by the hardware.
219  * Top level bits 0-6 are automatically cleared to 0 when the Status Register
220  * is read.
221  * Second level interrupts reported by bits 13-18 are cleared at the source.
222  * The value of the TX Completion Register is replicated in bits 19-31.
223  */
224 #define	ERI_G_STATUS_TX_INT_ME	(1 << 0)
225 	/* 0 - set when a frame with INT_ME bit set is transferred to FIFO */
226 #define	ERI_G_STATUS_TX_ALL	(1 << 1)	/* 1 - TX desc. ring empty */
227 #define	ERI_G_STATUS_TX_DONE	(1 << 2)	/* 2 - from host to TX FIFO */
228 #define	ERI_G_STATUS_RES1	(1 << 3)	/* 3 - reserved */
229 #define	ERI_G_STATUS_RX_DONE	(1 << 4)	/* 4 - from RXFIFO to host */
230 #define	ERI_G_STATUS_RX_NO_BUF	(1 << 5)	/* 5 - no RX buff available */
231 #define	ERI_G_STATUS_RX_TAG_ERR	(1 << 6)	/* 6 - RX tag error */
232 #define	ERI_G_STATUS_PERR_INT	(1 << 7)	/* 7 - Parity Err sts reg */
233 #define	ERI_G_STATUS_RES2	(0x3f << 7)	/* 7-12 : reserved */
234 #define	ERI_G_STATUS_PCS_INT	(1 << 13)	/* 13 - PCS Interrupt */
235 #define	ERI_G_STATUS_TX_MAC_INT	(1 << 14)	/* 14 - TX MAC stat reg set */
236 #define	ERI_G_STATUS_RX_MAC_INT	(1 << 15)	/* 15 - RX MAC stat reg set */
237 #define	ERI_G_STATUS_MAC_CTRL_INT	(1 << 16) /* 16 - MAC control reg  */
238 #define	ERI_G_STATUS_MIF_INT	(1 << 17)	/* 17 - MIF status reg set */
239 #define	ERI_G_STATUS_BUS_ERR_INT	(1 << 18) /* 18 - BUS Err sts reg */
240 #define	ERI_G_STATUS_TX_COMPL	(0xfff80000)	/* 19-31: TX Completion reg */
241 
242 #define	ERI_G_STATUS_INTR	(0xffffffff & ~(ERI_G_STATUS_TX_DONE |\
243 	ERI_G_STATUS_TX_ALL |\
244 	ERI_G_STATUS_MAC_CTRL_INT | ERI_G_STATUS_TX_COMPL))
245 
246 #define	ERI_G_STATUS_TX_INT	(ERI_G_STATUS_TX_DONE | ERI_G_STATUS_TX_ALL)
247 #define	ERI_G_STATUS_RX_INT	(~ERI_G_STATUS_TX_COMPL & ~ERI_G_STATUS_TX_INT)
248 
249 #define	ERI_G_STATUS_FATAL_ERR		(ERI_G_STATUS_RX_TAG_ERR | \
250 					ERI_G_STATUS_PERR_INT | \
251 					ERI_G_STATUS_BUS_ERR_INT)
252 
253 #define	ERI_G_STATUS_NONFATAL_ERR	(ERI_G_STATUS_TX_MAC_INT | \
254 					ERI_G_STATUS_RX_MAC_INT | \
255 					ERI_G_STATUS_MAC_CTRL_INT)
256 
257 #define	ERI_G_STATUS_TX_COMPL_SHIFT	19
258 #define	ERI_G_STATUS_TX_COMPL_MASK	0x1fff
259 
260 /*
261  * Global Interrupt Mask register (RW)
262  * size:	32 bits
263  * default:	0xFFFFFFFF
264  * There is one-to-one correspondence between the bits in this register and
265  * the Global Status register.
266  * If a mask bit is 0, the corresponding event causes an interrupt.
267  */
268 
269 
270 #define	ERI_G_MASK_TX_INT_ME	(1 << 0)
271 	/* 0 - set when a frame with INT_ME bit set is transferred to FIFO */
272 #define	ERI_G_MASK_TX_ALL	(1 << 1)	/* 1 - TX desc. ring empty */
273 #define	ERI_G_MASK_TX_DONE	(1 << 2)	/* 2 - from host to TX FIFO */
274 #define	ERI_G_MASK_RES1		(1 << 3)	/* 3 - reserved */
275 #define	ERI_G_MASK_RX_DONE	(1 << 4)	/* 4 - from RXFIFO to host */
276 #define	ERI_G_MASK_RX_NO_BUF	(1 << 5)	/* 5 - no RX bufer available */
277 #define	ERI_G_MASK_RX_TAG_ERR	(1 << 6)	/* 6 - RX tag error */
278 #define	ERI_G_MASK_RES2		(0x3f << 7)	/* 7-13 : reserved */
279 #define	ERI_G_MASK_PCS_INT	(1 << 13)	/* 13 - PCS Interrupt */
280 #define	ERI_G_MASK_TX_MAC_INT	(1 << 14)	/* 14 - TX MAC status reg set */
281 #define	ERI_G_MASK_RX_MAC_INT	(1 << 15)	/* 15 - RX MAC status reg set */
282 #define	ERI_G_MASK_MAC_CTRL_INT	(1 << 16)	/* 16 - MAC control reg set */
283 #define	ERI_G_MASK_MIF_INT	(1 << 17)	/* 17 - MIF status reg set */
284 #define	ERI_G_MASK_BUS_ERR_INT	(1 << 18)	/* 18 - BUS Error sts reg set */
285 
286 #define	ERI_G_MASK_INTR		(~ERI_G_STATUS_INTR | ERI_G_MASK_PCS_INT)
287 #define	ERI_G_MASK_ALL		(0xffffffffu)
288 
289 
290 /*
291  * Interrupt Ack Register (WO)
292  * Its layout corresponds to the layout of the top level bits of the Interrupt
293  * Status register.
294  * Bit positions written high will be cleared, while bit positions written low
295  * have no effect on the Interrupt Status Register.
296  */
297 
298 /*
299  * Status Register Alias (RO)
300  * This location presents the same view as the Interrupt Status Register, except
301  * that reading from this location does not automatically clear any of the
302  * register bits.
303  */
304 
305 /*
306  * PCI Error Status Register (R-AC)
307  * Other PCI bus errors : The specific error may be read from
308  * the PCI Status Register in PCI Configuration space
309  */
310 #define	ERI_G_STS_BADACK	(1 << 0)	/* no ACK64# during ABS64 */
311 #define	ERI_G_STS_DTRTO		(1 << 1)	/* Delayed trans timeout */
312 #define	ERI_G_STS_OTHERS	(1 << 2)
313 
314 /*
315  * PCI Error Mask Register (RW)
316  * size: 	32 bits
317  * default:	0xffffffff
318  * Same layout as the PCI Error Status Register
319  */
320 #define	ERI_G_PCI_ERROR_MASK	0x00
321 
322 /*
323  * BIF Configuration Register
324  * default: 0x0
325  * Used to configure specific system information for the BIF block to optimize.
326  * Default values indicate no special knowledge is assumed by BIF.
327  * M66EN is RO bit.
328  * 66 MHz operation (RO) May be used by the driver to sense
329  * whether ERI is operating in a 66MHz or 33 MHz PCI segment
330  */
331 #define	ERI_G_BIFCFG_SLOWCLK	(1 << 0)	/* for parity error timing */
332 #define	ERI_G_BIFCFG_HOST_64	(1 << 1)	/* 64-bit host */
333 #define	ERI_G_BIFCFG_B64D_DIS	(1 << 2)	/* no 64-bit wide data */
334 #define	ERI_G_BIFCFG_M66EN	(1 << 3)
335 
336 /*
337  * BIF Diagnostic register (RW)
338  * TBD
339  */
340 
341 /*
342  * Global Software Reset Register - RW-AC
343  * The lower 2bits are used to perform an individual Software Reset to the
344  * TX or RX functions (when the corresponding bit is set), or
345  * a Global Software Reset to the ERI (when both bits are set).
346  * These bits become "self cleared" after the corresponding reset command
347  * has been executed. After a reset, the software must poll this register
348  * till both the bits are read as 0's.
349  * The third bit (RSTOUT) is not self clearing and is used to activate
350  * the RSTOUT# pin, when set. When clear, RSTOUT# follows the level of the
351  * PCI reset input pin.
352  */
353 #define	ERI_G_RESET_ETX	(1 << 0)	/* Reset ETX */
354 #define	ERI_G_RESET_ERX	(1 << 1)	/* Reset ERX */
355 #define	ERI_G_RESET_RSTOUT (1 << 2)	/* force the RSTOUT# pin active */
356 #define	ERI_G_CACHE_BIT	16
357 #define	ERI_G_CACHE_LINE_SIZE_16 16	/* cache line size of 64 bytes  */
358 #define	ERI_G_CACHE_LINE_SIZE_32 32	/* cache line size of 128 bytes  */
359 #define	ERI_G_CACHE_16 (ERI_G_CACHE_LINE_SIZE_16 << ERI_G_CACHE_BIT)
360 #define	ERI_G_CACHE_32 (ERI_G_CACHE_LINE_SIZE_32 << ERI_G_CACHE_BIT)
361 
362 #define	ERI_G_RESET_GLOBAL (ERI_G_RESET_ETX | ERI_G_RESET_ERX)
363 
364 /*
365  * Transmit DMA Register set
366  * tx_kick and tx_completion registers are set to 0 when ETX is reset.
367  */
368 
369 struct etx {
370     uint32_t tx_kick;		/* 0x2000 RW Transmit Kick Register */
371     uint32_t config;		/* 0x2004 RW ETX Configuration Register */
372     uint32_t txring_lo;		/* 0x2008 RW Transmit Descriptor Base Low */
373     uint32_t txring_hi;		/* 0x200C RW Transmit Descriptor Base Low */
374     uint32_t reserved1;		/* 0x2010 */
375     uint32_t txfifo_wr_ptr;	/* 0x2014 RW TxFIFO Write Pointer */
376     uint32_t txfifo_sdwr_ptr;	/* 0x2018 RW TxFIFO Shadow Write Pointer */
377     uint32_t txfifo_rd_ptr;	/* 0x201C RW TxFIFO Read Pointer */
378     uint32_t txfifo_sdrd_ptr;	/* 0x2020 RW TxFIFO Shadow Read Pointer */
379     uint32_t txfifo_pkt_cnt;	/* 0x2024 RO TxFIFO Packet Counter */
380     uint32_t state_mach;	/* 0x2028 RO ETX State Machine Reg */
381     uint32_t reserved2;		/* 0x202C */
382     uint32_t txdata_ptr_lo;	/* 0x2030 RO ETX State Machine Register */
383     uint32_t txdata_ptr_hi;	/* 0x2034 RO ETX State Machine Register */
384     uint32_t reserved3[50];	/* 0x2038 - 0x20FC */
385 
386     uint32_t tx_completion;	/* 0x2100 RO ETX Completion Register */
387     uint32_t txfifo_adrs;	/* 0x2104 RW ETX FIFO address */
388     uint32_t txfifo_tag;	/* 0x2108 RO ETX FIFO tag */
389     uint32_t txfifo_data_lo;	/* 0x210C RW ETX FIFO data low */
390     uint32_t txfifo_data_hi_T1;	/* 0x2110 RW ETX FIFO data high T1 */
391     uint32_t txfifo_data_hi_T0;	/* 0x2114 RW ETX FIFO data high T0 */
392     uint32_t txfifo_size;	/* 0x2118 RO ETX FIFO size */
393 
394     uint32_t reserved4[964];	/* 0x211C - 0x3024 */
395 
396     uint32_t txdebug;		/* 0x3028 RW ETX Debug Register */
397 };
398 
399 
400 /*
401  * TX Kick Register (RW)
402  * size:	13-bits
403  * default:	0x0
404  * Written by the host CPU with the descriptor value that follows the last
405  * valid Transmit descriptor.
406  */
407 
408 /*
409  * TX Completion Register
410  * size:	13-bits
411  * default:	0x0
412  * This register stores the descriptor value that follows the last descriptor
413  * already processed by ERI.
414  *
415  */
416 #define	ETX_COMPLETION_MASK	0x1fff
417 
418 /*
419  * ETX Configuration Register
420  * default: 0x118010
421  * This register stores parameters that control the operation of the transmit
422  * DMA channel.
423  * If the desire is to buffer an entire standard Ethernet frame before its
424  * transmission is enabled, the Tx-FIFO-Threshold field has to be programmed
425  * to a value = > 0xC8. (CHECK). Default value is 0x460.
426  * Matewos: Changed the above to 0x400. Getting FIFO Underflow in the
427  * case if Giga bit speed.
428  * Bit 21 is used to modify the functionality of the Tx_All interrupt.
429  * If it is 0, Tx_All interrupt is generated after processing the last
430  * transmit descriptor.
431  * If it is 1, Tx_All interrupt is generated only after the entire
432  * Transmit FIFO has been drained.
433  */
434 
435 #define	GET_CONFIG_TXDMA_EN	(1 << 0)	/* 0 - Enable Tx DMA */
436 #define	GET_CONFIG_TXRING_SZ	(0xf << 1)	/* 1-4:Tx desc ring size */
437 #define	GET_CONFIG_RESERVED	(0x1f << 5)	/* 5-9: Reserved */
438 #define	GET_CONFIG_TXFIFOTH	(0x7ff << 10)	/* 10-20 :TX FIFO Threshold */
439 /*
440  * RIO specific value: TXFIFO threshold needs to be set to 1518/8.
441  *			It was set to (0x4FF << 10) for GEM.
442  *			set it back to 0x4ff.
443  *			set it to 190 receive TXMAC underrun and hang
444  *			try 0x100
445  *			try 0x4ff
446  *			try 0x100
447  */
448 #define	ETX_ERI_THRESHOLD	0x100
449 #define	ETX_CONFIG_THRESHOLD	(ETX_ERI_THRESHOLD << 10)
450 
451 #define	GET_CONFIG_PACED_MODE	(1 << 21)	/* 21 - TX_all_int mod */
452 
453 #define	GET_CONFIG_THRESHOLD	(0x400 << 10)	/* For Ethernet Packets */
454 #define	GET_CONFIG_RINGSZ	(ERI_TMDMAX << 1) /* for 2048 descriptors */
455 /*
456  * ETX TX ring size
457  * This is a 4-bit value to determine the no. of descriptor entries in the
458  * TX-ring. The number of entries can vary from 32 through 8192 in multiples
459  * of 2.
460  */
461 #define	ERI_TX_RINGSZ_SHIFT	1
462 
463 #define	ETX_RINGSZ_32	0
464 #define	ETX_RINGSZ_64	1
465 #define	ETX_RINGSZ_128	2
466 #define	ETX_RINGSZ_256	3
467 #define	ETX_RINGSZ_512	4
468 #define	ETX_RINGSZ_1024	5
469 #define	ETX_RINGSZ_2048	6
470 #define	ETX_RINGSZ_4096	7
471 #define	ETX_RINGSZ_8192	8
472 /* values 9-15 are reserved. */
473 
474 /*
475  * Transmit Descriptor Base Low and High (RW)
476  * The 53 most significant bits are used as the base address for the TX
477  * descriptor ring. The 11 least significant bits are not stored and assumed
478  * to be 0.
479  * This register should be initialized to a 2KByte-aligned value after power-on
480  * or Software Reset.
481  */
482 
483 
484 /*
485  * TX FIFO size (RO)
486  * This 11-bit RO register indicates the size, in 64 byte multiples, of the
487  * TX FIFO.
488  * The value of this register is 0x90, indicating a 9Kbyte TX FIFO.
489  */
490 
491 
492 /*
493  * ERX Register Set
494  */
495 
496 struct erx {
497     uint32_t config;		/* 0x4000 RW ERX Configuration Register */
498     uint32_t rxring_lo;		/* 0x4004 RW Receive Descriptor Base low */
499     uint32_t rxring_hi;		/* 0x4008 RW Receive Descriptor Base high */
500     uint32_t rxfifo_wr_ptr;	/* 0x400C RW RxFIFO Write Pointer */
501     uint32_t rxfifo_sdwr_ptr;	/* 0x4010 RW RxFIFO Shadow Write Pointer */
502     uint32_t rxfifo_rd_ptr;	/* 0x4014 RW RxFIFO Read pointer */
503     uint32_t rxfifo_pkt_cnt;	/* 0x4018 RO RxFIFO Packet Counter */
504     uint32_t state_mach;	/* 0x401C RO ERX State Machine Register */
505     uint32_t rx_pause_threshold; /* 0x4020 RW ERX Pause thresholds */
506     uint32_t rxdata_ptr_lo;	/* 0x4024 RO ERX Data Pointer low */
507     uint32_t rxdata_ptr_hi;	/* 0x4028 RO ERX Data Pointer high */
508     uint32_t reserved1[53];	/* 0x402C - 0x40FC */
509 
510     uint32_t rx_kick;		/* 0x4100 RW ERX Kick Register */
511     uint32_t rx_completion;	/* 0x4104 RO ERX Completion Register */
512     uint32_t rx_blanking;	/* 0x4108 RO ERX Blanking Register */
513     uint32_t rxfifo_adrs;	/* 0x410C RW ERX FIFO address */
514     uint32_t rxfifo_tag;	/* 0x4110 RO ERX FIFO tag */
515     uint32_t rxfifo_data_lo;	/* 0x4114 RW ERX FIFO data low */
516     uint32_t rxfifo_data_hi_T0;	/* 0x4118 RW ERX FIFO data high T0 */
517     uint32_t rxfifo_data_hi_T1;	/* 0x411C RW ERX FIFO data high T1 */
518     uint32_t rxfifo_size;	/* 0x4120 RW ERX FIFO size */
519 };
520 
521 /*
522  * ERX Configuration Register - RW
523  * This 27-bit register determines the ERX-specific parameters that control the
524  * operation of the receive DMA channel.
525  * Default : 0x1000010
526  */
527 
528 #define	GET_CONFIG_RXDMA_EN	(1 << 0)	/* 0 : Enable Rx DMA */
529 #define	ERI_RX_CONFIG_RXRING_SZ	(0xf << 1)	/* 1-4 : RX ring size */
530 #define	ERI_RX_CONFIG_BATDIS	(1 << 5)	/* Disable RX desc batching */
531 #define	ERI_RX_CONFIG_RES1	(0xf << 6)	/* 6-9 : reserverd */
532 #define	ERI_RX_CONFIG_FBOFFSET	(0x7 << 10)	/* 10-12 : 1st Byte Offset */
533 #define	ERI_RX_CONFIG_RX_CSSTART (0x7f << 13)	/* 13-19:cksum start offset */
534 #define	ERI_RX_CONFIG_RES2	(0xf << 20)	/* 20-23 : reserve */
535 #define	ERI_RX_CONFIG_RXFIFOTH	(0x7 << 24)	/* 24-26:RX DMA threshold */
536 
537 #define	ERI_RX_RINGSZ_SHIFT	1
538 #define	ERI_RX_CONFIG_FBO_SHIFT	10
539 #define	ERI_RX_CONFIG_RX_CSSTART_SHIFT	13
540 #define	ERI_RX_CONFIG_RXFIFOTH_SHIFT	24
541 
542 #define	ERX_RINGSZ_32	0
543 #define	ERX_RINGSZ_64	1
544 #define	ERX_RINGSZ_128	2
545 #define	ERX_RINGSZ_256	3
546 #define	ERX_RINGSZ_512	4
547 #define	ERX_RINGSZ_1024	5
548 #define	ERX_RINGSZ_2048	6
549 #define	ERX_RINGSZ_4096	7
550 #define	ERX_RINGSZ_8192	8
551 /* values 9-15 are reserved. */
552 
553 
554 #define	ERI_RX_FIFOTH_64	0
555 #define	ERI_RX_FIFOTH_128	1
556 #define	ERI_RX_FIFOTH_256	2
557 #define	ERI_RX_FIFOTH_512	3
558 #define	ERI_RX_FIFOTH_1024	4
559 #define	ERI_RX_FIFOTH_2048	5
560 /* 6 & 7 are reserved values */
561 
562 /*
563  * Receive Descriptor Base Low and High (RW)
564  * The 53 most significant bits are used as the base address for the RX
565  * descriptor ring. The 11 least significant bits are not stored and assumed
566  * to be 0.
567  * This register should be initialized to a 2KByte-aligned value after power-on
568  * or Software Reset.
569  */
570 
571 
572 /*
573  * Pause Thresholds Register (RW)
574  * default: 0x000f8
575  * Two PAUSE thresholds are used to define when PAUSE flow control frames are
576  * emitted by ERI. The granularity of these thresholds is in 64 byte increments.
577  * XOFF PAUSE frames use the pause_time value pre-programmed in the
578  * Send PAUSE MAC Register.
579  * XON PAUSE frames use a pause_time of 0.
580  */
581 
582 #define	ERI_RX_PTH_OFFTH	(0x1ff << 0)
583 			/*
584 			 * 0-8: XOFF PAUSE emitted when RX FIFO
585 			 * occupancy rises above this value (times 64 bytes)
586 			 */
587 #define	ERI_RX_PTH_RES	(0x7 << 9)	/* 9-11: reserved */
588 #define	ERI_RX_PTH_ONTH	(0x1ff << 12)
589 			/*
590 			 * 12-20: XON PAUSE emitted when RX FIFO
591 			 * occupancy falls below this value (times 64 bytes)
592 			 */
593 
594 #define	ERI_RX_PTH_ONTH_SHIFT	12
595 
596 /*
597  * ------------------------------------------------------------------------
598  * RX Kick Register (RW)
599  * This is a 13-bit register written by the host CPU.
600  * The last valid RX descriptor is the one right before the value of the
601  * register.
602  * Initially set to 0 on reset.
603  * RX descriptors must be posted in multiples of 4.
604  * The first descriptor should be cache-line aligned for best performance.
605  * -------------------------------------------------------------------------
606  */
607 
608 /*
609  * RX Completion Register (RO)
610  * This 13-bit register indicates which descriptors are already used by ERI
611  * for receive frames.
612  * All descriptors upto but excluding the register value are ready to be
613  * processed by the host.
614  */
615 
616 /*
617  * RX Blanking Register (RW)
618  * Defines the values used for receive interrupt blanking.
619  * For INTR_TIME field, every count is 2048 PCI clock time. For 66 Mhz, each
620  * count is about 16 us.
621  */
622 #define	ERI_RX_BLNK_INTR_PACKETS	(0x1ff << 0)
623 			/*
624 			 * 0-8:no.of pkts to be recvd since the last RX_DONE
625 			 * interrupt, before a new interrupt
626 			 */
627 #define	ERI_RX_BLNK_RESERVED	(0x7 << 9)	/* 9-11 : reserved */
628 #define	ERI_RX_BLNK_INTR_TIME	(0xff << 12)
629 			/*
630 			 * 12-19 : no. of clocks to be counted since the last
631 			 * RX_DONE interrupt, before a new interrupt
632 			 */
633 
634 #define	ERI_RX_BLNK_INTR_TIME_SHIFT	12
635 
636 /*
637  * RX FIFO Size (RO)
638  * This 11-bit RO register indicates the size, in 64-bit multiples, of the
639  * RX FIFO. Software should use it to properly configure the PAUSE thresholds.
640  * The value read is 0x140, indicating a 20kbyte RX FIFO.
641  */
642 
643 
644 /*
645  * Declarations and definitions specific to the ERI MAC functional block.
646  *
647  * The ERI MAC block will provide the MAC functons for 10 or 100 Mbps or
648  * 1 Gbps CSMA/CD-protocol-based or full-duplex interface.
649  */
650 
651 /*
652  * ERI MAC Register Set.
653  * ERI MAC addresses map on a word boundry. So all registers are
654  * declared for a size of 32 bits. Registers that use fewer than 32
655  * bits will return 0 in the bits not used.
656  * TBD: Define the constant values which should be used for initializing
657  * these registers.
658  */
659 struct	bmac {
660 	uint32_t	txrst;	/* 0x6000 tx software reset (RW) */
661 	uint32_t	rxrst;	/* 0x6004 rx software reset Reg (RW) */
662 	uint32_t	spcmd;	/* 0x6008 Send Pause Command Reg (RW) */
663 	uint32_t	res1;	/* 0x600C reserved */
664 	uint32_t	txsts;	/* 0x6010 tx MAC status reg (R-AC) */
665 	uint32_t	rxsts;	/* 0x6014 rx MAC status reg (R-AC) */
666 	uint32_t	macctl_sts; /* 0x6018 MAC Control Stat Reg (R-AC) */
667 	uint32_t	res2;	/* 0x601C reserved */
668 	uint32_t	txmask;	/* 0x6020 tx MAC Mask Register (RW) */
669 	uint32_t	rxmask;	/* 0x6024 rx MAC Mask register (RW) */
670 	uint32_t	macctl_mask; /* 0x6028 MAC Control Mask Reg (RW) */
671 	uint32_t	res3;	/* 0x602C reserved */
672 	uint32_t	txcfg;	/* 0x6030 tx config reg [8-0] (RW) */
673 	uint32_t	rxcfg;	/* 0x6034 rx config reg [7-0] (RW) */
674 	uint32_t	macctl_cfg; /* 0x6038 MAC Control Config Reg (RW) */
675 	uint32_t	xifc;	/* 0x603C XIF Config. reg [7-0] (RW) */
676 	uint32_t	ipg0;	/* 0x6040 Inter pkt Gap 0 [7-0] (RW) */
677 	uint32_t	ipg1;	/* 0x6044 Inter pkt Gap 1 [7-0] (RW) */
678 	uint32_t	ipg2;	/* 0x6048 Inter pkt Gap 2 [7-0] (RW) */
679 	uint32_t	slot;	/* 0x604C slot time reg [7-0] (RW) */
680 	uint32_t	macmin;	/* 0x6050 MAC min frame sze [9-0](RW) */
681 	uint32_t	macmax;	/* 0x6054 MAC max pkt sze [14-0] (RW) */
682 	uint32_t	palen;	/* 0x6058 preamble len reg [9-0] (RW) */
683 	uint32_t	jam;	/* 0x605C jam size reg [3-0] (RW) */
684 	uint32_t	alimit;	/* 0x6060 attempt limit reg [7-0](RW) */
685 	uint32_t	macctl_type; /* 0x6064 MAC Control Type Reg (RW) */
686 	uint32_t	res4[6]; /* reserved 0x6068 - 0x607C	*/
687 	uint32_t	madd0;	/* 0x6080 Norm MAC adrs 0 [15-0] (RW) */
688 	uint32_t	madd1;	/* 0x6084 Norm MAC adrs 1 [31-16](RW) */
689 	uint32_t	madd2;	/* 0x6088 Norm MAC adrs 2 [47-32](RW) */
690 	uint32_t	madd3;	/* 0x608C Alt. MAC adrs 0 [15-0](RW) */
691 	uint32_t	madd4;	/* 0x6090 Alt. MAC adrs 1 [31-16](RW) */
692 	uint32_t	madd5;	/* 0x6094 Alt. MAC adrs 2 [47-32](RW) */
693 	uint32_t	madd6;	/* 0x6098 Control MAC adrs 0 [15-0](RW) */
694 	uint32_t	madd7;	/* 0x609C Control MAC adrs 1 [31-16](RW) */
695 	uint32_t	madd8;	/* 0x60A0 Control MAC adrs 2 [47-32](RW) */
696 	uint32_t	afr0;	/* 0x60A4 addr filt reg 0_0 [15-0](RW) */
697 	uint32_t	afr1;	/* 0x60A8 addr filt reg 0_1 [15-0](RW) */
698 	uint32_t	afr2;	/* 0x60AC addr filt reg 0_2 [15-0](RW) */
699 	uint32_t	afmr1_2; /* 0x60B0 addr filt msk reg 1,2 [8-0](RW) */
700 	uint32_t	afmr0;	/* 0x60B4 addr filt msk reg 0 [15-0](RW) */
701 	uint32_t	res5[2]; /* 0x60B8 - 0x60BC Reserved	*/
702 	uint32_t	hash0;	/* 0x60C0 h-table 0 [15-0] (RW) */
703 	uint32_t	hash1;	/* 0x60C4 h-table 1 [31-16] (RW) */
704 	uint32_t	hash2;	/* 0x60C8 h-table 2 [47-32] (RW) */
705 	uint32_t	hash3;	/* 0x60CC h-table 3 [63-48] (RW) */
706 	uint32_t	hash4;	/* 0x60D0 h-table  4 [79-64] (RW) */
707 	uint32_t	hash5;	/* 0x60D4 h-table  5 [95-80] (RW) */
708 	uint32_t	hash6;	/* 0x60D8 h-table  6 [111-96] (RW) */
709 	uint32_t	hash7;	/* 0x60DC h-table  7 [127-112] (RW) */
710 	uint32_t	hash8;	/* 0x60E0 h-table  8 [143-128] (RW) */
711 	uint32_t	hash9;	/* 0x60E4 h-table  9 [159-144] (RW) */
712 	uint32_t	hash10;	/* 0x60E8 h-table 10 [175-160] (RW) */
713 	uint32_t	hash11;	/* 0x60EC h-table 11 [191-176] (RW) */
714 	uint32_t	hash12;	/* 0x60F0 h-table 12 [207-192] (RW) */
715 	uint32_t	hash13;	/* 0x60F4 h-table 13 [223-208] (RW) */
716 	uint32_t	hash14;	/* 0x60F8 h-table 14 [239-224] (RW) */
717 	uint32_t	hash15;	/* 0x60FC h-table 15 [255-240] (RW) */
718 	uint32_t	nccnt;	/* 0x6100 normal coll cnt [15-0] (RW) */
719 	uint32_t	fccnt;	/* 0x6104 1st succes coll [15-0] (RW) */
720 	uint32_t	excnt;	/* 0x6108 excess coll cnt[15-0] (RW) */
721 	uint32_t	ltcnt;	/* 0x610C late coll cnt [15-0] (RW) */
722 	uint32_t	dcnt;	/* 0x6110 defer timer cnt [15-0] (RW) */
723 	uint32_t	pattempts; /* 0x6114 peak attempt reg [7-0] (RW) */
724 	uint32_t	frcnt;	/* 0x6118 rcv frame cnt [15-0] (RW) */
725 	uint32_t	lecnt;	/* 0x611C rx len err cnt [15-0] (RW) */
726 	uint32_t	aecnt;	/* 0x6120 rx align err cnt[15-0] (RW) */
727 	uint32_t	fecnt;	/* 0x6124 rcv crc err cnt [15-0] (RW) */
728 	uint32_t	rxcv;	/* 0x6128 rx code viol reg [15-0](RW) */
729 	uint32_t	res6;	/* 0x612C Reserved */
730 	uint32_t	rseed;	/* 0x6130 random num seed [9-0] (RW) */
731 	uint32_t	macsm;	/* 0x6134 MAC state mach reg [7-0](R) */
732 };
733 
734 #define	BMAC_OVERFLOW_STATE	0x03800000
735 
736 /*
737  * Constants used for initializing the MAC registers
738  */
739 
740 #define	BMAC_SEND_PAUSE_CMD	0x1BF0
741 #define	BMAC_IPG0		0x00
742 #define	BMAC_IPG1		0x08
743 #define	BMAC_IPG2		0x04
744 #define	BMAC_SLOT_TIME		0x40
745 #define	BMAC_EXT_SLOT_TIME	0x200
746 #define	BMAC_MIN_FRAME_SIZE	0x40
747 #define	BMAC_MAX_FRAME_SIZE	(ETHERMTU + 18 + 4)	/* enet + vlan */
748 
749 /*
750  *	Hardware bug: set MAC_FRAME_SIZE to 0x7fff to
751  *	get around the problem of tag errors
752  */
753 #ifdef	ERI_RX_TAG_ERROR_WORKAROUND
754 #define	BMAC_MAX_FRAME_SIZE_TAG	0x7fff
755 #endif
756 
757 #define	BMAC_MAX_BURST		(0x2000 << 16)
758 #define	BMAC_PREAMBLE_SIZE	0x07
759 #define	BMAC_JAM_SIZE		0x04
760 #define	BMAC_ATTEMPT_LIMIT	0x10
761 #define	BMAC_CONTROL_TYPE	0x8808
762 #define	BMAC_ADDRESS_3		0x0000
763 #define	BMAC_ADDRESS_4		0x0000
764 #define	BMAC_ADDRESS_5		0x0000
765 #define	BMAC_ADDRESS_6		0x0001
766 #define	BMAC_ADDRESS_7		0xC200
767 #define	BMAC_ADDRESS_8		0x0180
768 #define	BMAC_AF_0		0x0000
769 #define	BMAC_AF_1		0x0000
770 #define	BMAC_AF_2		0x0000
771 #define	BMAC_AF21_MASK		0x00
772 #define	BMAC_AF0_MASK		0x0000
773 #define	BMAC_COUNTER		0x0000	/* for all MAC Counters */
774 
775 /*
776  * ERI MAC Register Bit Masks.
777  */
778 
779 /*
780  * TX_MAC Software Reset Command Register (RW)
781  * This bit is set to 1 when a PIO write is done. This bit becomes self-cleared.
782  * after the command has been executed.
783  */
784 
785 #define	BMAC_TX_RESET		(1 << 0)	/* TX_MAC Reset Command */
786 
787 
788 /*
789  * RX_MAC Software Reset Command Register (RW)
790  * This bit is set to 1 when a PIO write is done. This bit becomes self-cleared.
791  * after the command has been executed.
792  */
793 
794 #define	BMAC_RX_RESET		(1 << 0)	/* RX_MAC Reset Command */
795 
796 /*
797  * Send Pause Command Register (RW)
798  * This command register executes a Pause Flow Control frame transmission.
799  * Pause_Time_Sent field indicates to the MAC the value of the pause_time
800  * operand that should be sent on the network using either the Send_Pause
801  * Command bit or the flow control handshake on the RxDMA < - > MAC interface.
802  * The pause-time is interpreted in terms of Slot times.
803  */
804 
805 /*
806  * 0-15: value of pause_time operand
807  * in terms of slot time
808  */
809 
810 #define	ERI_MCTLSP_TIME	(0xffff << 0)
811 #define	ERI_MCTLSP_SEND	(1 << 16)	/* send Pause flow control frame */
812 
813 
814 /*
815  * TX_MAC Status Register (R-AC)
816  */
817 
818 #define	BMAC_TXSTS_XMIT_DONE	(1 << 0)	/* Frame transmitted */
819 #define	BMAC_TXSTS_TX_URUN	(1 << 1)	/* TX MAC Underrun */
820 #define	BMAC_TXSTS_MAXPKT_ERR	(1 << 2)	/* packet len exceeds max len */
821 #define	BMAC_TXSTS_NCC_EXP	(1 << 3)	/* Normal Collision cnt exp */
822 #define	BMAC_TXSTS_ECC_EXP	(1 << 4)	/* Excess Collision cnt exp */
823 #define	BMAC_TXSTS_LCC_EXP	(1 << 5)	/* Late Collision cnt exp */
824 #define	BMAC_TXSTS_FCC_EXP	(1 << 6)	/* First Collision cnt exp */
825 #define	BMAC_TXSTS_DEFER_EXP	(1 << 7)	/* Defer Timer exp */
826 #define	BMAC_TXSTS_PEAK_EXP	(1 << 8)	/* Peak attempts cnt exp */
827 
828 /*
829  * TX_MAC Mask Register (RW)
830  */
831 
832 #define	BMAC_TXMASK_XMIT_DONE	(1 << 0)	/* Frame transmitted */
833 #define	BMAC_TXMASK_TX_URUN	(1 << 1)	/* TX MAC Underrun */
834 #define	BMAC_TXMASK_MAXPKT_ERR	(1 << 2)	/* packet len exceeds max len */
835 #define	BMAC_TXMASK_NCC_EXP	(1 << 3)	/* Normal Collision cnt exp */
836 #define	BMAC_TXMASK_ECC_EXP	(1 << 4)	/* Excess Collision cnt exp */
837 #define	BMAC_TXMASK_LCC_EXP	(1 << 5)	/* Late Collision cnt exp */
838 #define	BMAC_TXMASK_FCC_EXP	(1 << 6)	/* First Collision cnt exp */
839 #define	BMAC_TXMASK_DEFER_EXP	(1 << 7)	/* Defer Timer exp */
840 #define	BMAC_TXMASK_PEAK_EXP	(1 << 8)	/* Peak attempts cnt exp */
841 /* Matewos added defer counter */
842 #define	BMAC_TXINTR_MASK	(BMAC_TXMASK_XMIT_DONE | BMAC_TXMASK_DEFER_EXP)
843 
844 /*
845  * RX_MAC Status Register (R-AC)
846  */
847 #define	BMAC_RXSTS_RX_DONE	(1 << 0)	/* Frame Received */
848 #define	BMAC_RXSTS_RX_OVF	(1 << 1)	/* RX MAC data path overflow */
849 #define	BMAC_RXSTS_FRMCNT_EXP	(1 << 2)	/* RX Frame counter exp */
850 #define	BMAC_RXSTS_ALE_EXP	(1 << 3)	/* RX Alignment error cnt exp */
851 #define	BMAC_RXSTS_CRC_EXP	(1 << 4)	/* RX CRC error cnt exp */
852 #define	BMAC_RXSTS_LEN_EXP	(1 << 5)	/* RX Length error cnt exp */
853 #define	BMAC_RXSTS_CVI_EXP	(1 << 6)    /* RX Code violate err cnt exp */
854 
855 /*
856  * RX_MAC Mask Register (R-AC)
857  */
858 #define	BMAC_RXMASK_RX_DONE	(1 << 0)	/* Frame Received */
859 #define	BMAC_RXMASK_RX_OVF	(1 << 1)	/* RX MAC data path overflow */
860 #define	BMAC_RXMASK_FRMCNT_EXP	(1 << 2)	/* RX Frame counter exp */
861 #define	BMAC_RXMASK_ALE_EXP	(1 << 3)	/* RX Alignment error cnt exp */
862 #define	BMAC_RXMASK_CRC_EXP	(1 << 4)	/* RX CRC error cnt exp */
863 #define	BMAC_RXMASK_LEN_EXP	(1 << 5)	/* RX Length error cnt exp */
864 #define	BMAC_RXMASK_CVI_EXP	(1 << 6)    /* RX Code violate err cnt exp */
865 
866 #define	BMAC_RXINTR_MASK	(BMAC_RXMASK_RX_DONE | BMAC_RXMASK_FRMCNT_EXP)
867 
868 /*
869  * MAC Control Status Register (R-AC)
870  */
871 #define	ERI_MCTLSTS_PAUSE_RCVD	(1 << 0)	/* PAUSE received */
872 #define	ERI_MCTLSTS_PAUSE_STATE	(1 << 1)	/* transition to PAUSE state */
873 #define	ERI_MCTLSTS_NONPAUSE	(1 << 2)	/* change to non-PAUSE state */
874 #define	ERI_MCTLSTS_RESERVED	(0x1fff << 3)	/* 3-15: reserved */
875 #define	ERI_MCTLSTS_PAUSE_TIME	(0xffff0000)	/* 16-31: Pause time recvd */
876 
877 #define	ERI_MCTLSTS_PAUSE_TIME_SHIFT	16
878 
879 /*
880  * MAC Control Mask Register (RW)
881  * pause time is in slot-time units.
882  */
883 #define	ERI_MCTLMASK_PAUSE_RCVD	(1 << 0)	/* PAUSE received */
884 #define	ERI_MCTLMASK_PAUSE_STATE (1 << 1)	/* transition to PAUSE state */
885 #define	ERI_MCTLMASK_NONPAUSE	(1 << 2)	/* change to non-PAUSE state */
886 #define	ERI_MCTLMASK_RESERVED	(0x1fff << 3)	/* 3-15: reserved */
887 #define	ERI_MCTLMASK_PAUSE_TIME	(0xffff << 16)	/* 16-31: Pause time recvd */
888 
889 #define	ERI_MACCTL_INTR_MASK	0x00000000
890 
891 /*
892  * XIF Configuration Register
893  * This register determines the parameters that control the operation of the
894  * transceiver interface.
895  * The Disable-echo bit should be 0 for full-duplex mode.
896  * Default: 0x00
897  */
898 
899 #define	BMAC_XIFC_TX_MII_OE	(1 << 0)	/* Enable XIF output drivers */
900 #define	BMAC_XIFC_MIILPBK	(1 << 1)	/* Enable MII Loopback mode */
901 #define	BMAC_XIFC_DIS_ECHO	(1 << 2)	/* Disable echo */
902 #define	BMAC_XIFC_MII_MODE	(1 << 3)	/* Selects GMII/MII mode */
903 #define	BMAC_XIFC_MIIBUF_OE	(1 << 4)	/* Enable MII Recv Buffers */
904 #define	BMAC_XIFC_LINK_LED	(1 << 5)	/* force LINKLED# active */
905 #define	BMAC_XIFC_FDPLX_LED	(1 << 6)	/* force FDPLXLED# active */
906 
907 /*
908  * TX_MAC Configuration Register
909  * Ignore_Carrier_Sense should be set to 1 for full-duplex operation and
910  * cleared to 0 for half-duplex operation..
911  * Ignore_collisions should be set to 1 for full-duplex operation and cleared
912  * to 0 for half-duplex operation..
913  * To Ensure proper operation of the TX_MAC, the TX_MAC_Enable bit must always
914  * be cleared to 0 and a delay imposed before a PIO write to any of the other
915  * bits in the TX_MAC Configuration register or any of the MAC parameter
916  * registers is done.
917  * The amount of delay required depends on the time required to transmit a max.
918  * size frame.
919  * Default: TBD
920  */
921 
922 #define	BMACTXRSTDELAY		(125)		/* 125 us wait period */
923 /* CHECK */
924 
925 #define	BMAC_TXCFG_ENAB		(1 << 0)	/* tx enable */
926 #define	BMAC_TXCFG_IGNCS	(1 << 1)	/* Ignore carrier sense */
927 #define	BMAC_TXCFG_IGCOLL	(1 << 2)	/* Ignore collisions */
928 #define	BMAC_TXCFG_ENIPG0	(1 << 3)	/* Extend Rx-to-Tx IPG */
929 #define	BMAC_TXCFG_NGU		(1 << 4)	/* Never Give Up */
930 #define	BMAC_TXCFG_NGU_LIMIT	(1 << 5)	/* Never Give Up limit */
931 #define	BMAC_TXCFG_NBKOFF	(1 << 6)	/* No Backoff */
932 #define	BMAC_TXCFG_SLOWDOWN	(1 << 7)	/* Slow down */
933 #define	BMAC_TXCFG_NFCS		(1 << 8)	/* no FCS will be generated */
934 #define	BMAC_TXCFG_CARR_EXT	(1 << 9)
935 			/*
936 			 * Enable TX Carrier Extension Carrier Extension is
937 			 * required for half-duplex operation at Gbps
938 			 */
939 
940 #define	BMAC_TXCFG_FDX	(BMAC_TXCFG_IGNCS | BMAC_TXCFG_IGCOLL)
941 
942 /*
943  * RX_MAC Configuration Register
944  * A delay of 3.2 ms should be allowed after clearing Rx_MAC_Enable or
945  * Hash_Filter_enable or Address_Filter_Enable bits.
946  * Default: TBD
947  */
948 /* CHECK 3ms or us */
949 /* GEM specification: 3.2msec (3200 usec) */
950 
951 #define	BMACRXRSTDELAY		(3200)		/* 3.2 ms wait period */
952 
953 #define	BMAC_RXCFG_ENAB		(1 << 0)	/* rx enable */
954 #define	BMAC_RXCFG_STRIP_PAD	(1 << 1)	/* rx strip pad bytes */
955 #define	BMAC_RXCFG_STRIP_CRC	(1 << 2)	/* rx enable CRC stripping */
956 #define	BMAC_RXCFG_PROMIS	(1 << 3)	/* rx enable promiscous */
957 #define	BMAC_RXCFG_GRPROM	(1 << 4)	/* rx promiscuous group mode */
958 #define	BMAC_RXCFG_HASH		(1 << 5)	/* rx enable hash filter */
959 #define	BMAC_RXCFG_ADDR		(1 << 6)	/* rx enable address filter */
960 #define	BMAC_RXCFG_ERR		(1 << 7)	/* rx disable error checking */
961 #define	BMAC_RXCFG_CARR_EXT	(1 << 8)
962 			/*
963 			 * Enable RX Carrier Extension.
964 			 * Enables the reception of packet bursts
965 			 * generated by Carrier Extension with
966 			 * packet bursting senders
967 			 */
968 
969 /*
970  * MAC Control Configuration Register (RW)
971  * Default: 0x00
972  */
973 
974 #define	ERI_MCTLCFG_TXPAUSE	(1 << 0)	/* Send_PAUSE Enable */
975 #define	ERI_MCTLCFG_RXPAUSE	(1 << 1)	/* Receive_PAUSE Enable */
976 #define	ERI_MCTLCFG_PASSPAUSE	(1 << 2)	/* Pass PAUSE up */
977 
978 /*
979  * MAC Control Type Register (RW)
980  * This 16-bit register specifies the "type" field for the MAC Control frame.
981  * Default: 0x8808
982  */
983 
984 
985 /*
986  * MAC Address Registers 0, 1, 2
987  * Station's Normal peririty MAC address which must be a unicast address.
988  * 0 - [15:0], 1 - [31:16], 2 - [47:32]
989  */
990 
991 /*
992  * MAC Address Registers 3, 4, 5
993  * Station's Alternate MAC address which may be a unicast or multicast address.
994  * 3 - [15:0], 4 - [31:16], 5 - [47:32]
995  */
996 
997 /*
998  * MAC Address Registers 6, 7, 8
999  * Station's Control MAC address which must be the reserved multicast
1000  * address for MAC Control frames.
1001  * 6 - [15:0], 7 - [31:16], 8 - [47:32]
1002  */
1003 
1004 /*
1005  * MII Transceiver Interface
1006  *
1007  * The Management Interface (MIF) allows the host to program and collect status
1008  * from two transceivers connected to the MII. MIF supports three modes of
1009  * operation:
1010  *	1. Bit-Bang Mode
1011  *	   This mode is imlemented using three 1-bit registers: data, clock,
1012  *	   and output_enable.
1013  *
1014  *	2. Frame Mode
1015  *	   This mode is supported using one 32-bit register: Frame register.
1016  *	   The software loads the Frame Register with avalid instaruction
1017  *	   ("frame"), and polls the Valid Bit for completion.
1018  *
1019  *	3. Polling Mode
1020  *	   The Polling mechanism is used for detecting a status change in the
1021  *	   transceiver. When this mode is enabled, the MIF will continuously
1022  *	   poll a specified transceiver register and generate a maskable
1023  *	   interrupt when a status change is detected. This mode of operation
1024  *	   can only be used when the MIF is in the "Frame mode".
1025  *
1026  */
1027 
1028 struct mif {
1029 	uint32_t mif_bbclk;	/* 0x6200 (RW) MIF Bit Bang Clock */
1030 	uint32_t mif_bbdata;	/* 0x6204 (RW) MIF Bit Bang Data */
1031 	uint32_t mif_bbopenb;	/* 0x6208 (RW) MIF Bit Bang Output Enable */
1032 	uint32_t mif_frame;	/* 0x620C (RW) MIF Frame - ctl and data */
1033 	uint32_t mif_cfg;	/* 0x6210 (RW) MIF Configuration */
1034 	uint32_t mif_imask;	/* 0x6214 (RW) MIF Interrupt mask */
1035 	uint32_t mif_bsts;	/* 0x6218 (R-AC) MIF Basic/Status register */
1036 	uint32_t mif_fsm;	/* 0x621C (RO) MIF State machine register */
1037 };
1038 
1039 /*
1040  * mif_bbclk - Bit Bang Clock register
1041  */
1042 #define	ERI_MIF_BBCLK	(1 << 0);	/* Bit Babg Clock */
1043 
1044 #define	ERI_BBCLK_LOW 0
1045 #define	ERI_BBCLK_HIGH 1
1046 
1047 /* mif_bbdata - bit Bang Data register */
1048 #define	ERI_MIF_BBDATA	(1 << 0);	/* Bit Bang Data */
1049 
1050 /* mif_bbopenb - Bit Bang oOutput Enable register */
1051 #define	ERI_MIF_BBOPENB	(1 << 0);	/* Bit Bang output Enable */
1052 
1053 /*
1054  * Management Frame Structure:
1055  * <IDLE> <ST><OP><PHYAD><REGAD><TA>	 <DATA>		   <IDLE>
1056  * READ:  <01><10><AAAAA><RRRRR><Z0><DDDDDDDDDDDDDDDD>
1057  * WRITE: <01><01><AAAAA><RRRRR><10><DDDDDDDDDDDDDDDD>
1058  */
1059 
1060 /*
1061  * mif_frame - MIF control and data register
1062  */
1063 #define	ERI_MIF_FRDATA	(0xffff << 0)	/* 0-15 : data bits */
1064 #define	ERI_MIF_FRTA0	(0x1 << 16)	/* 16 : TA bit, 1 for completion */
1065 #define	ERI_MIF_FRTA1	(0x1 << 17)	/* 16-17 : TA bits */
1066 #define	ERI_MIF_FRREGAD	(0x1f << 18)	/* 18-22 : register address bits */
1067 #define	ERI_MIF_FRPHYAD	(0x1f << 23)	/* 23-27 : PHY ad, should be 0 */
1068 #define	ERI_MIF_FROP	(0x3 << 28)	/* 28-29 : Operation - Write/Read */
1069 #define	ERI_MIF_FRST	(0xc0000000)	/* 30-31 : START bits */
1070 
1071 #define	ERI_MIF_FRREGAD_SHIFT	18
1072 #define	ERI_MIF_FRPHYAD_SHIFT	23
1073 #define	ERI_MIF_FRREAD		0x60020000
1074 #define	ERI_MIF_FRWRITE		0x50020000
1075 
1076 /*
1077  * maximum delay for MIF Register Read/Write operation
1078  */
1079 #define	ERI_MAX_MIF_DELAY	(100)
1080 
1081 /*
1082  * maximum delay for Transceiver Reset
1083  */
1084 #define	ERI_PHYRST_MAXDELAY	(500)
1085 #define	ERI_PCS_PHYRST_MAXDELAY	(500)
1086 
1087 /*
1088  * mif_cfg - MIF Configuration Register
1089  */
1090 #define	ERI_MIF_CFGPS	(1 << 0)	/* PHY Select */
1091 #define	ERI_MIF_CFGPE	(1 << 1)	/* Poll Enable */
1092 #define	ERI_MIF_CFGBB	(1 << 2)	/* Bit Bang Enable */
1093 #define	ERI_MIF_CFGPR	(0x1f << 3)	/* Poll Register address */
1094 #define	ERI_MIF_CFGM0	(1 << 8)	/* MDIO_0 Data / MDIO_0 attached */
1095 #define	ERI_MIF_CFGM1	(1 << 9)	/* MDIO_1 Data / MDIO_1 attached */
1096 #define	ERI_MIF_CFGPD	(0x1f << 10)	/* Poll Device PHY address */
1097 
1098 #define	ERI_MIF_CFGPR_SHIFT	3
1099 #define	ERI_MIF_CFGPD_SHIFT	10
1100 #define	ERI_MIF_POLL_DELAY	200
1101 
1102 /*
1103  * MDIO_0 corresponds to the On Board Transceiver.
1104  * MDIO_1 corresponds to the External Transceiver.
1105  * The PHYAD for both is 0.
1106  */
1107 #define	ERI_INTERNAL_PHYAD	1	/* PHY address for int. transceiver */
1108 #define	ERI_EXTERNAL_PHYAD	0	/* PHY address for ext. transceiver */
1109 #define	ERI_NOXCVR_PHYAD	99	/* PHY address for no   transceiver */
1110 
1111 
1112 /* mif_imask - MIF Interrupt Mask Register */
1113 /*
1114  * This register is bit-to-bit same as Basic/Status Register
1115  */
1116 #define	ERI_MIF_INTMASK	(0xffff << 0)	/* 0-15 : Interrupt mask */
1117 
1118 /* mif_bassts - MIF Basic - Status register */
1119 /*
1120  * The Basic portion of this register indicates the last value of the register
1121  * read indicated in the POLL REG field of the Configuration Register.
1122  * The Status portion indicates bit(s) that have changed.
1123  * The MIF Mask register is corresponding to this register in terms of the
1124  * bit(s) that need to be masked for generating interrupt on the MIF Interrupt
1125  * Bit of the Global Status Rgister.
1126  */
1127 
1128 #define	ERI_MIF_STATUS	(0xffff << 0)	/* 0-15 : Status */
1129 #define	ERI_MIF_BASIC	(0xffff << 16)	/* 16-31 : Basic register */
1130 
1131 /* mif_fsm - MIF State Machine register */
1132 
1133 #define	ERI_MIF_FSM	(0x3ff << 0)  /* 0-9 : MIF state */
1134 
1135 /*
1136  * ERI PCS/Serial-Link
1137  */
1138 struct pcslink {
1139 	uint32_t pcs_ctl;	/* 0x9000 (RW) PCS MII Control Reg */
1140 	uint32_t pcs_sts;	/* 0x9004 (RO) PCS MII Status Register */
1141 	uint32_t pcs_anar;	/* 0x9008 (RW) PCS MII Avertisement Reg */
1142 	uint32_t pcs_anlpar;    /* 0x900C (RW) PCS MII LP Ability Reg */
1143 	uint32_t pcs_cfg;	/* 0x9010 (RW) PCS Configuration Register */
1144 	uint32_t pcs_smr;	/* 0x9014 (RW) PCS State Machine Reg */
1145 	uint32_t pcs_intsts;    /* 0x9018 (R-AC) PCS Interrupt Status Reg */
1146 	uint32_t res1[13];	/* 0x901C - 0x904C Reserved */
1147 	uint32_t pcs_dmode;	/* 0x9050 (RW) Datapath mode register */
1148 	uint32_t slink_ctl;	/* 0x9054 (RW) Serial Link Control register */
1149 	uint32_t pcs_opsel;	/* 0x9058 (RW) Shared Output Select register */
1150 	uint32_t slink_sts;	/* 0x905C (RO) Serial Link Status register */
1151 };
1152 
1153 /*
1154  *  PCS MII	 Basic Mode Control Register
1155  * Auto-Negotiation should always be used for 802.3z 8B/10B
1156  * link configuration. May be cleared for diagnostic purposes, or
1157  * as a workaround for possible early product interoperability problems.
1158  */
1159 
1160 #define	PCS_BMCR_RESET	(1 << 15)	/* Resets the PCS when set */
1161 #define	PCS_BMCR_LPBK	(1 << 14)	/* Loopback of the 10-bit i/f */
1162 #define	PCS_BMCR_1000M	(1 << 13)	/* Speed selection, always 0 */
1163 #define	PCS_BMCR_ANE	(1 << 12)	/* Auto Negotiation Enabled when set */
1164 #define	PCS_BMCR_PWRDN	(1 << 11)	/* Power down, always 0 */
1165 #define	PCS_BMCR_ISOLATE (1 << 10)	/* Isolate PHY from MII, always 0 */
1166 #define	PCS_BMCR_RAN	(1 << 9)	/* Set to Restart Auto Negotiation */
1167 #define	PCS_BMCR_FDX	(1 << 8)	/* Full Duplex, always 0 */
1168 #define	PCS_BMCR_COLTST	(1 << 7)	/* Collision Test */
1169 #define	PCS_BMCR_RES1	(0x7f << 0)	/* 0-6 Reserved */
1170 
1171 #define	PCS_AUTONEG_DISABLE	0
1172 
1173 /*
1174  * ------------------------------------------------------------------------
1175  * PCS MII	 Basic Mode Status Register
1176  * -------------------------------------------------------------------------
1177  */
1178 
1179 
1180 #define	PCS_BMSR_RES2	(0x1f << 11)	/* 11-15 reserved, always 0 */
1181 #define	PCS_BMSR_GBFDX	(1 << 10)	/* PCS able to perform GBit FDX */
1182 #define	PCS_BMSR_GBHDX	(1 << 9)	/* PCS able to perform Gbit HDX */
1183 #define	PCS_BMSR_RES1	(0x7 << 6)	/* 6-8 reserved */
1184 #define	PCS_BMSR_ANC	(1 << 5)	/* Auto Negotiation Completed */
1185 #define	PCS_BMSR_REMFLT	(1 << 4)	/* Remote Fault detected */
1186 #define	PCS_BMSR_ACFG	(1 << 3)	/* Able to do Auto Link Negotiation,1 */
1187 #define	PCS_BMSR_LNKSTS	(1 << 2)	/* Link Status */
1188 #define	PCS_BMSR_JABDET	(1 << 1)	/* Jabber Condition Detected, 0 */
1189 #define	PCS_BMSR_EXTCAP	(1 << 0)	/* Extended Register Capability, 0 */
1190 
1191 #define	PCS_CAPABILITY_MASK (PCS_BMSR_GBFDX | PCS_BMSR_GBHDX)
1192 
1193 
1194 /*
1195  * ------------------------------------------------------------------------
1196  * PCS MII	Auto-Negotiation Advertisement Register (nway1Reg)
1197  * This register will hold the different modes of operation to be advertised to
1198  * the far-end PHY.
1199  * -------------------------------------------------------------------------
1200  */
1201 
1202 #define	PCS_ANAR_NP	(1 << 15)	/* Next Page bit, RO, always 0 */
1203 #define	PCS_ANAR_ACK	(1 << 14)	/* Acks reception of Link Partner */
1204 					/* Capability word  */
1205 #define	PCS_ANAR_RF	(0x2 << 12)	/* Advertise Remote Fault det. cap. */
1206 #define	PCS_ANAR_RES1	(0x7 << 9)	/* 9-11 reserved */
1207 #define	PCS_ANAR_PTX	(1 << 8)	/* Pause TX */
1208 #define	PCS_ANAR_PRX	(1 << 7)	/* Pause RX */
1209 #define	PCS_ANAR_PAUSE	(1 << 7)	/* Pause  */
1210 #define	PCS_ANAR_ASM_DIR	(1 << 8)	/* Asymetric Direction */
1211 #define	PCS_ANAR_GBFDX	(1 << 5)	/* Advertise Gbit FDX Capability */
1212 #define	PCS_ANAR_GBHDX	(1 << 6)	/* Advertise Gbit HDX Capability */
1213 #define	PCS_ANAR_RES	(0x1f << 0)	/* 0-5 Reserved */
1214 
1215 
1216 /* ************************************************************************ */
1217 /*
1218  * PCS MII	 Auto-Negotiation Link Partner Ability Reg
1219  * This register contains the Link Partners capabilities after NWay
1220  * Auto-Negotiation is complete.
1221  */
1222 
1223 #define	PCS_ANLPAR_NP	(1 << 15)	/* Next Page bit, RO, always 0 */
1224 #define	PCS_ANLPAR_ACK	(1 << 14)	/* Acks reception of Link Partner */
1225 					/* Capability word  */
1226 #define	PCS_ANLPAR_RF	(0x2 << 12)	/* Advertise Remote Fault det. cap. */
1227 #define	PCS_ANLPAR_RES1	(0x7 << 9)	/* 9-11 reserved */
1228 #define	PCS_ANLPAR_PTX	(1 << 8)	/* Pause TX */
1229 #define	PCS_ANLPAR_PRX	(1 << 7)	/* Pause RX */
1230 #define	PCS_ANLPAR_GBFDX (1 << 5)	/* Advertise Gbit FDX Capability */
1231 #define	PCS_ANLPAR_GBHDX (1 << 6)	/* Advertise Gbit HDX Capability */
1232 #define	PCS_ANLPAR_RES	(0x1f << 0)	/* 0-5 Reserved */
1233 
1234 
1235 /*
1236  * ------------------------------------------------------------------------
1237  * PCS Configuration Register
1238  * Default = 0x8
1239  * -------------------------------------------------------------------------
1240  */
1241 
1242 #define	PCS_CFG_RES	(0xfff << 4)	/* 4-15 Reserved */
1243 #define	PCS_CFG_TIMER	(0x7 << 1)
1244 	/* Timer values used for the 802.3z Clause 36 Link Monitor s/m timers */
1245 #define	PCS_CFG_ENABLE	(1 << 0)	/* Enable PCS, when set to 1 */
1246 
1247 
1248 /*
1249  * ------------------------------------------------------------------------
1250  * PCS Interrupt State Register
1251  * Presently only one bit is implemented, reflecting transitions on the link
1252  * status. Note that there is no mask register at this level.
1253  * THe PCS_INT bit may be masked at the Interrupt Status Register level.
1254  * -------------------------------------------------------------------------
1255  */
1256 
1257 #define	PCS_STS_LNKSTS	2	/* Link Status Change */
1258 
1259 
1260 /*
1261  * ------------------------------------------------------------------------
1262  * Datapath Mode Register (RW)
1263  * This register controls which network interface is used.
1264  * Only one bit should be set in this register.
1265  * Default: 0x1
1266  * -------------------------------------------------------------------------
1267  */
1268 /*
1269  * Select MII/GMII and not PCS.
1270  * Selection between MII and GMII is
1271  * controlled by the XIF register
1272  */
1273 #define	ERI_PCS_MII	(1 << 2)
1274 /*
1275  * Applicable only in Serial Mode
1276  * When set, makes the 10-bit Xmit data
1277  * visible at the GMII
1278  */
1279 #define	ERI_PCS_GMIIOUTEN (1 << 3)
1280 
1281 
1282 /*
1283  * ------------------------------------------------------------------------
1284  * Serial Link Control register (RW)
1285  * This register controls the Serial link
1286  * Default: 0x000
1287  * -------------------------------------------------------------------------
1288  */
1289 #define	ERI_SLC_LOOPBACK (1 << 0)	/* Enables loopback at the SL o/p */
1290 #define	ERI_SLC_ENSYNCDT (1 << 1)	/* Enable Sync char detection */
1291 #define	ERI_SLC_LOCKREF	(1 << 2)	/* Lock to reference clock */
1292 #define	ERI_SLC_EMP	(0x2 << 3)	/* Control o/p driver emphasis */
1293 #define	ERI_SLC_RES	(1 << 5)	/* Reserved */
1294 #define	ERI_SLC_SELFTEST (0x7 << 6)	/* To select built-in self tests */
1295 #define	ERI_SLC_SW_PDOWN (1 << 9)	/* Power down Serial link block */
1296 
1297 /*
1298  * ------------------------------------------------------------------------
1299  * Shared Output Select Register (RW)
1300  * Default: 0x00
1301  * -------------------------------------------------------------------------
1302  */
1303 
1304 /*
1305  * ------------------------------------------------------------------------
1306  * Serial Link State Register (RO)
1307  * Indicates the progress of the Serial link boot up
1308  * 00 - Undergoing test
1309  * 01 - Waiting 500us while lockrefn is asserted
1310  * 10 - Waiting for comma detect
1311  * 11 - Receive Data is synchronized
1312  * -------------------------------------------------------------------------
1313  */
1314 #define	ERI_SLS_STATE	(0x2 << 0)	/* state */
1315 
1316 
1317 
1318 /* ************************************************************************ */
1319 /*
1320  * Definition for the time required to wait after a software
1321  * reset has been issued.
1322  */
1323 #define	ERI_MAX_RST_DELAY	(200)
1324 #define	ERI_PERIOD	(20)	/* period to wait */
1325 #define	ERI_WAITPERIOD	ERI_PERIOD
1326 
1327 #define	ERI_DELAY(c, n) \
1328 	{ \
1329 		register int N = n / ERI_WAITPERIOD; \
1330 		while (--N > 0) { \
1331 			if (c) \
1332 				break; \
1333 			drv_usecwait(ERI_WAITPERIOD); \
1334 		} \
1335 	}
1336 
1337 #define	MIF_ERIDELAY(n, phyad, regad) \
1338 	{ \
1339 		register int N = n / ERI_WAITPERIOD; \
1340 		PUT_MIFREG(mif_frame, \
1341 			(ERI_MIF_FRREAD | (phyad << ERI_MIF_FRPHYAD_SHIFT) | \
1342 			(regad << ERI_MIF_FRREGAD_SHIFT))); \
1343 		while (--N > 0) { \
1344 			if (GET_MIFREG(mif_frame) & ERI_MIF_FRTA0) \
1345 				break; \
1346 			drv_usecwait(ERI_WAITPERIOD); \
1347 		} \
1348 	}
1349 
1350 
1351 #ifdef	__cplusplus
1352 }
1353 #endif
1354 
1355 #endif	/* _SYS_ERI_MAC_H */
1356