xref: /titanic_41/usr/src/uts/sun4u/sys/envctrl_ue250.h (revision 29949e866e40b95795203f3ee46f44a197c946e4)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 1998 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef	_SYS_ENVCTRL_UE250_H
28 #define	_SYS_ENVCTRL_UE250_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 #ifdef	__cplusplus
33 extern "C" {
34 #endif
35 
36 /*
37  * envctrl_ue250.h
38  *
39  * This header file contains environmental control definitions specific
40  * to the UltraEnterprise-250 platform.
41  */
42 
43 #define	ENVCTRL_UE250_OVERTEMP_TIMEOUT_USEC	60 * MICROSEC
44 #define	ENVCTRL_UE250_BLINK_TIMEOUT_USEC	500 * (MICROSEC / MILLISEC)
45 
46 /* Keyswitch Definitions */
47 #define	ENVCTRL_UE250_FSP_KEYMASK	0xC0
48 #define	ENVCTRL_UE250_FSP_POMASK	0x20
49 #define	ENVCTRL_UE250_FSP_KEYLOCKED	0x00
50 #define	ENVCTRL_UE250_FSP_KEYOFF	0xC0
51 #define	ENVCTRL_UE250_FSP_KEYDIAG	0x80
52 #define	ENVCTRL_UE250_FSP_KEYON		0x40
53 
54 /* Front Status Panel Definitions */
55 #define	ENVCTRL_UE250_FSP_DISK_ERR	0x01
56 #define	ENVCTRL_UE250_FSP_PS_ERR	0x02
57 #define	ENVCTRL_UE250_FSP_TEMP_ERR	0x04
58 #define	ENVCTRL_UE250_FSP_GEN_ERR	0x08
59 #define	ENVCTRL_UE250_FSP_ACTIVE	0x10
60 #define	ENVCTRL_UE250_FSP_POWER	0x20
61 #define	ENVCTRL_UE250_FSP_USRMASK		\
62 	(ENVCTRL_UE250_FSP_DISK_ERR | ENVCTRL_UE250_FSP_GEN_ERR)
63 
64 #define	ENVCTRL_UE250_FSP_OFF		0x4F
65 
66 #define	ENVCTRL_UE250_MAX_DISKS		6
67 #define	ENVCTRL_UE250_MAXPS 		0x02	/* 0 based array */
68 
69 #define	ENVCTRL_UE250_PDB_TEMP_DEV	0x94
70 #define	ENVCTRL_UE250_CPU_TEMP_DEV	0x9E
71 #define	ENVCTRL_UE250_CPU0_PORT		0
72 #define	ENVCTRL_UE250_CPU1_PORT		1
73 #define	ENVCTRL_UE250_MB0_PORT		2
74 #define	ENVCTRL_UE250_MB1_PORT		3
75 #define	ENVCTRL_UE250_PDB_TEMP_PORT	0
76 #define	ENVCTRL_UE250_SCSI_TEMP_PORT	3
77 
78 #define	ENVCTRL_UE250_CPU0_SENSOR	0
79 #define	ENVCTRL_UE250_CPU1_SENSOR	1
80 #define	ENVCTRL_UE250_MB0_SENSOR	2
81 #define	ENVCTRL_UE250_MB1_SENSOR	3
82 #define	ENVCTRL_UE250_PDB_SENSOR	4
83 #define	ENVCTRL_UE250_SCSI_SENSOR	5
84 
85 #define	ENVCTRL_UE250_MAX_CPU_TEMP	80
86 
87 #define	ENVCTRL_UE250_PCF8591_BASE_ADDR		0x90
88 #define	ENVCTRL_UE250_PCF8574A_BASE_ADDR	0x70
89 #define	ENVCTRL_UE250_PCF8574_BASE_ADDR		0x40
90 
91 #define	ENVCTRL_UE250_DFLOP_INIT0		0x77
92 #define	ENVCTRL_UE250_DFLOP_INIT1		0x7F
93 #define	ENVCTRL_UE250_DEVINTR_INIT0		0xF7
94 #define	ENVCTRL_UE250_DEVINTR_INIT1		0xFF
95 #define	ENVCTRL_UE250_INTR_LATCH_CLR		0xFE
96 
97 #ifdef	__cplusplus
98 }
99 #endif
100 
101 #endif	/* _SYS_ENVCTRL_UE250_H */
102