xref: /linux/drivers/gpu/drm/amd/display/dc/dc_dp_types.h (revision 2c1ed907520c50326b8f604907a8478b27881a2e)
1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef DC_DP_TYPES_H
27 #define DC_DP_TYPES_H
28 
29 #include "os_types.h"
30 #include "dc_ddc_types.h"
31 
32 enum dc_lane_count {
33 	LANE_COUNT_UNKNOWN = 0,
34 	LANE_COUNT_ONE = 1,
35 	LANE_COUNT_TWO = 2,
36 	LANE_COUNT_FOUR = 4,
37 	LANE_COUNT_EIGHT = 8,
38 	LANE_COUNT_DP_MAX = LANE_COUNT_FOUR
39 };
40 
41 /* This is actually a reference clock (27MHz) multiplier
42  * 162MBps bandwidth for 1.62GHz like rate,
43  * 270MBps for 2.70GHz,
44  * 324MBps for 3.24Ghz,
45  * 540MBps for 5.40GHz
46  * 810MBps for 8.10GHz
47  */
48 enum dc_link_rate {
49 	LINK_RATE_UNKNOWN = 0,
50 	LINK_RATE_LOW = 0x06,		// Rate_1 (RBR)  - 1.62 Gbps/Lane
51 	LINK_RATE_RATE_2 = 0x08,	// Rate_2        - 2.16 Gbps/Lane
52 	LINK_RATE_RATE_3 = 0x09,	// Rate_3        - 2.43 Gbps/Lane
53 	LINK_RATE_HIGH = 0x0A,		// Rate_4 (HBR)  - 2.70 Gbps/Lane
54 	LINK_RATE_RBR2 = 0x0C,		// Rate_5 (RBR2) - 3.24 Gbps/Lane
55 	LINK_RATE_RATE_6 = 0x10,	// Rate_6        - 4.32 Gbps/Lane
56 	LINK_RATE_HIGH2 = 0x14,		// Rate_7 (HBR2) - 5.40 Gbps/Lane
57 	LINK_RATE_RATE_8 = 0x19,	// Rate_8        - 6.75 Gbps/Lane
58 	LINK_RATE_HIGH3 = 0x1E,		// Rate_9 (HBR3) - 8.10 Gbps/Lane
59 	/* Starting from DP2.0 link rate enum directly represents actual
60 	 * link rate value in unit of 10 mbps
61 	 */
62 	LINK_RATE_UHBR10 = 1000,	// UHBR10 - 10.0 Gbps/Lane
63 	LINK_RATE_UHBR13_5 = 1350,	// UHBR13.5 - 13.5 Gbps/Lane
64 	LINK_RATE_UHBR20 = 2000,	// UHBR20 - 20.0 Gbps/Lane
65 };
66 
67 enum dc_link_spread {
68 	LINK_SPREAD_DISABLED = 0x00,
69 	/* 0.5 % downspread 30 kHz */
70 	LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10,
71 	/* 0.5 % downspread 33 kHz */
72 	LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11
73 };
74 
75 enum dc_voltage_swing {
76 	VOLTAGE_SWING_LEVEL0 = 0,	/* direct HW translation! */
77 	VOLTAGE_SWING_LEVEL1,
78 	VOLTAGE_SWING_LEVEL2,
79 	VOLTAGE_SWING_LEVEL3,
80 	VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3
81 };
82 
83 enum dc_pre_emphasis {
84 	PRE_EMPHASIS_DISABLED = 0,	/* direct HW translation! */
85 	PRE_EMPHASIS_LEVEL1,
86 	PRE_EMPHASIS_LEVEL2,
87 	PRE_EMPHASIS_LEVEL3,
88 	PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3
89 };
90 /* Post Cursor 2 is optional for transmitter
91  * and it applies only to the main link operating at HBR2
92  */
93 enum dc_post_cursor2 {
94 	POST_CURSOR2_DISABLED = 0,	/* direct HW translation! */
95 	POST_CURSOR2_LEVEL1,
96 	POST_CURSOR2_LEVEL2,
97 	POST_CURSOR2_LEVEL3,
98 	POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3,
99 };
100 
101 enum dc_dp_ffe_preset_level {
102 	DP_FFE_PRESET_LEVEL0 = 0,
103 	DP_FFE_PRESET_LEVEL1,
104 	DP_FFE_PRESET_LEVEL2,
105 	DP_FFE_PRESET_LEVEL3,
106 	DP_FFE_PRESET_LEVEL4,
107 	DP_FFE_PRESET_LEVEL5,
108 	DP_FFE_PRESET_LEVEL6,
109 	DP_FFE_PRESET_LEVEL7,
110 	DP_FFE_PRESET_LEVEL8,
111 	DP_FFE_PRESET_LEVEL9,
112 	DP_FFE_PRESET_LEVEL10,
113 	DP_FFE_PRESET_LEVEL11,
114 	DP_FFE_PRESET_LEVEL12,
115 	DP_FFE_PRESET_LEVEL13,
116 	DP_FFE_PRESET_LEVEL14,
117 	DP_FFE_PRESET_LEVEL15,
118 	DP_FFE_PRESET_MAX_LEVEL = DP_FFE_PRESET_LEVEL15,
119 };
120 
121 enum dc_dp_training_pattern {
122 	DP_TRAINING_PATTERN_SEQUENCE_1 = 0,
123 	DP_TRAINING_PATTERN_SEQUENCE_2,
124 	DP_TRAINING_PATTERN_SEQUENCE_3,
125 	DP_TRAINING_PATTERN_SEQUENCE_4,
126 	DP_TRAINING_PATTERN_VIDEOIDLE,
127 	DP_128b_132b_TPS1,
128 	DP_128b_132b_TPS2,
129 	DP_128b_132b_TPS2_CDS,
130 };
131 
132 enum dp_link_encoding {
133 	DP_UNKNOWN_ENCODING = 0,
134 	DP_8b_10b_ENCODING = 1,
135 	DP_128b_132b_ENCODING = 2,
136 };
137 
138 enum dp_test_link_rate {
139 	DP_TEST_LINK_RATE_RBR		= 0x06,
140 	DP_TEST_LINK_RATE_RATE_2    = 0x08,	// Rate_2        - 2.16 Gbps/Lane
141 	DP_TEST_LINK_RATE_RATE_3    = 0x09,	// Rate_3        - 2.43 Gbps/Lane
142 	DP_TEST_LINK_RATE_HBR		= 0x0A,
143 	DP_TEST_LINK_RATE_RBR2      = 0x0C,	// Rate_5 (RBR2) - 3.24 Gbps/Lane
144 	DP_TEST_LINK_RATE_RATE_6    = 0x10,	// Rate_6        - 4.32 Gbps/Lane
145 	DP_TEST_LINK_RATE_HBR2		= 0x14,
146 	DP_TEST_LINK_RATE_RATE_8    = 0x19,	// Rate_8        - 6.75 Gbps/Lane
147 	DP_TEST_LINK_RATE_HBR3		= 0x1E,
148 	DP_TEST_LINK_RATE_UHBR10	= 0x01,
149 	DP_TEST_LINK_RATE_UHBR20	= 0x02,
150 	DP_TEST_LINK_RATE_UHBR13_5_LEGACY	= 0x03, /* For backward compatibility*/
151 	DP_TEST_LINK_RATE_UHBR13_5	= 0x04,
152 };
153 
154 struct dc_link_settings {
155 	enum dc_lane_count lane_count;
156 	enum dc_link_rate link_rate;
157 	enum dc_link_spread link_spread;
158 	bool use_link_rate_set;
159 	uint8_t link_rate_set;
160 };
161 
162 union dc_dp_ffe_preset {
163 	struct {
164 		uint8_t level		: 4;
165 		uint8_t reserved	: 1;
166 		uint8_t no_preshoot	: 1;
167 		uint8_t no_deemphasis	: 1;
168 		uint8_t method2		: 1;
169 	} settings;
170 	uint8_t raw;
171 };
172 
173 struct dc_lane_settings {
174 	enum dc_voltage_swing VOLTAGE_SWING;
175 	enum dc_pre_emphasis PRE_EMPHASIS;
176 	enum dc_post_cursor2 POST_CURSOR2;
177 	union dc_dp_ffe_preset FFE_PRESET;
178 };
179 
180 struct dc_link_training_overrides {
181 	enum dc_voltage_swing *voltage_swing;
182 	enum dc_pre_emphasis *pre_emphasis;
183 	enum dc_post_cursor2 *post_cursor2;
184 	union dc_dp_ffe_preset *ffe_preset;
185 
186 	uint16_t *cr_pattern_time;
187 	uint16_t *eq_pattern_time;
188 	enum dc_dp_training_pattern *pattern_for_cr;
189 	enum dc_dp_training_pattern *pattern_for_eq;
190 
191 	enum dc_link_spread *downspread;
192 	bool *alternate_scrambler_reset;
193 	bool *enhanced_framing;
194 	bool *mst_enable;
195 	bool *fec_enable;
196 };
197 
198 union payload_table_update_status {
199 	struct {
200 		uint8_t  VC_PAYLOAD_TABLE_UPDATED:1;
201 		uint8_t  ACT_HANDLED:1;
202 	} bits;
203 	uint8_t  raw;
204 };
205 
206 union dpcd_rev {
207 	struct {
208 		uint8_t MINOR:4;
209 		uint8_t MAJOR:4;
210 	} bits;
211 	uint8_t raw;
212 };
213 
214 union max_lane_count {
215 	struct {
216 		uint8_t MAX_LANE_COUNT:5;
217 		uint8_t POST_LT_ADJ_REQ_SUPPORTED:1;
218 		uint8_t TPS3_SUPPORTED:1;
219 		uint8_t ENHANCED_FRAME_CAP:1;
220 	} bits;
221 	uint8_t raw;
222 };
223 
224 union max_down_spread {
225 	struct {
226 		uint8_t MAX_DOWN_SPREAD:1;
227 		uint8_t RESERVED:5;
228 		uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1;
229 		uint8_t TPS4_SUPPORTED:1;
230 	} bits;
231 	uint8_t raw;
232 };
233 
234 union mstm_cap {
235 	struct {
236 		uint8_t MST_CAP:1;
237 		uint8_t RESERVED:7;
238 	} bits;
239 	uint8_t raw;
240 };
241 
242 union lane_count_set {
243 	struct {
244 		uint8_t LANE_COUNT_SET:5;
245 		uint8_t POST_LT_ADJ_REQ_GRANTED:1;
246 		uint8_t RESERVED:1;
247 		uint8_t ENHANCED_FRAMING:1;
248 	} bits;
249 	uint8_t raw;
250 };
251 
252 union lane_status {
253 	struct {
254 		uint8_t CR_DONE_0:1;
255 		uint8_t CHANNEL_EQ_DONE_0:1;
256 		uint8_t SYMBOL_LOCKED_0:1;
257 		uint8_t RESERVED0:1;
258 		uint8_t CR_DONE_1:1;
259 		uint8_t CHANNEL_EQ_DONE_1:1;
260 		uint8_t SYMBOL_LOCKED_1:1;
261 		uint8_t RESERVED_1:1;
262 	} bits;
263 	uint8_t raw;
264 };
265 
266 union device_service_irq {
267 	struct {
268 		uint8_t REMOTE_CONTROL_CMD_PENDING:1;
269 		uint8_t AUTOMATED_TEST:1;
270 		uint8_t CP_IRQ:1;
271 		uint8_t MCCS_IRQ:1;
272 		uint8_t DOWN_REP_MSG_RDY:1;
273 		uint8_t UP_REQ_MSG_RDY:1;
274 		uint8_t SINK_SPECIFIC:1;
275 		uint8_t reserved:1;
276 	} bits;
277 	uint8_t raw;
278 };
279 
280 union sink_count {
281 	struct {
282 		uint8_t SINK_COUNT:6;
283 		uint8_t CPREADY:1;
284 		uint8_t RESERVED:1;
285 	} bits;
286 	uint8_t raw;
287 };
288 
289 union lane_align_status_updated {
290 	struct {
291 		uint8_t INTERLANE_ALIGN_DONE:1;
292 		uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1;
293 		uint8_t EQ_INTERLANE_ALIGN_DONE_128b_132b:1;
294 		uint8_t CDS_INTERLANE_ALIGN_DONE_128b_132b:1;
295 		uint8_t LT_FAILED_128b_132b:1;
296 		uint8_t RESERVED:1;
297 		uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1;
298 		uint8_t LINK_STATUS_UPDATED:1;
299 	} bits;
300 	uint8_t raw;
301 };
302 
303 union lane_adjust {
304 	struct {
305 		uint8_t VOLTAGE_SWING_LANE:2;
306 		uint8_t PRE_EMPHASIS_LANE:2;
307 		uint8_t RESERVED:4;
308 	} bits;
309 	struct {
310 		uint8_t PRESET_VALUE	:4;
311 		uint8_t RESERVED	:4;
312 	} tx_ffe;
313 	uint8_t raw;
314 };
315 
316 union dpcd_training_pattern {
317 	struct {
318 		uint8_t TRAINING_PATTERN_SET:4;
319 		uint8_t RECOVERED_CLOCK_OUT_EN:1;
320 		uint8_t SCRAMBLING_DISABLE:1;
321 		uint8_t SYMBOL_ERROR_COUNT_SEL:2;
322 	} v1_4;
323 	struct {
324 		uint8_t TRAINING_PATTERN_SET:2;
325 		uint8_t LINK_QUAL_PATTERN_SET:2;
326 		uint8_t RESERVED:4;
327 	} v1_3;
328 	uint8_t raw;
329 };
330 
331 /* Training Lane is used to configure downstream DP device's voltage swing
332 and pre-emphasis levels*/
333 /* The DPCD addresses are from 0x103 to 0x106*/
334 union dpcd_training_lane {
335 	struct {
336 		uint8_t VOLTAGE_SWING_SET:2;
337 		uint8_t MAX_SWING_REACHED:1;
338 		uint8_t PRE_EMPHASIS_SET:2;
339 		uint8_t MAX_PRE_EMPHASIS_REACHED:1;
340 		uint8_t RESERVED:2;
341 	} bits;
342 	struct {
343 		uint8_t PRESET_VALUE	:4;
344 		uint8_t RESERVED	:4;
345 	} tx_ffe;
346 	uint8_t raw;
347 };
348 
349 /* TMDS-converter related */
350 union dwnstream_port_caps_byte0 {
351 	struct {
352 		uint8_t DWN_STRM_PORTX_TYPE:3;
353 		uint8_t DWN_STRM_PORTX_HPD:1;
354 		uint8_t RESERVERD:4;
355 	} bits;
356 	uint8_t raw;
357 };
358 
359 /* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/
360 enum dpcd_downstream_port_detailed_type {
361 	DOWN_STREAM_DETAILED_DP = 0,
362 	DOWN_STREAM_DETAILED_VGA,
363 	DOWN_STREAM_DETAILED_DVI,
364 	DOWN_STREAM_DETAILED_HDMI,
365 	DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/
366 	DOWN_STREAM_DETAILED_DP_PLUS_PLUS
367 };
368 
369 union dwnstream_port_caps_byte2 {
370 	struct {
371 		uint8_t MAX_BITS_PER_COLOR_COMPONENT:2;
372 		uint8_t MAX_ENCODED_LINK_BW_SUPPORT:3;
373 		uint8_t SOURCE_CONTROL_MODE_SUPPORT:1;
374 		uint8_t CONCURRENT_LINK_BRING_UP_SEQ_SUPPORT:1;
375 		uint8_t RESERVED:1;
376 	} bits;
377 	uint8_t raw;
378 };
379 
380 union dp_downstream_port_present {
381 	uint8_t byte;
382 	struct {
383 		uint8_t PORT_PRESENT:1;
384 		uint8_t PORT_TYPE:2;
385 		uint8_t FMT_CONVERSION:1;
386 		uint8_t DETAILED_CAPS:1;
387 		uint8_t RESERVED:3;
388 	} fields;
389 };
390 
391 union dwnstream_port_caps_byte3_dvi {
392 	struct {
393 		uint8_t RESERVED1:1;
394 		uint8_t DUAL_LINK:1;
395 		uint8_t HIGH_COLOR_DEPTH:1;
396 		uint8_t RESERVED2:5;
397 	} bits;
398 	uint8_t raw;
399 };
400 
401 union dwnstream_port_caps_byte3_hdmi {
402 	struct {
403 		uint8_t FRAME_SEQ_TO_FRAME_PACK:1;
404 		uint8_t YCrCr422_PASS_THROUGH:1;
405 		uint8_t YCrCr420_PASS_THROUGH:1;
406 		uint8_t YCrCr422_CONVERSION:1;
407 		uint8_t YCrCr420_CONVERSION:1;
408 		uint8_t RESERVED:3;
409 	} bits;
410 	uint8_t raw;
411 };
412 
413 union hdmi_sink_encoded_link_bw_support {
414 	struct {
415 		uint8_t HDMI_SINK_ENCODED_LINK_BW_SUPPORT:3;
416 		uint8_t RESERVED:5;
417 	} bits;
418 	uint8_t raw;
419 };
420 
421 union hdmi_encoded_link_bw {
422 	struct {
423 		uint8_t FRL_MODE:1; // Bit 0
424 		uint8_t BW_9Gbps:1;
425 		uint8_t BW_18Gbps:1;
426 		uint8_t BW_24Gbps:1;
427 		uint8_t BW_32Gbps:1;
428 		uint8_t BW_40Gbps:1;
429 		uint8_t BW_48Gbps:1;
430 		uint8_t RESERVED:1; // Bit 7
431 	} bits;
432 	uint8_t raw;
433 };
434 
435 /*4-byte structure for detailed capabilities of a down-stream port
436 (DP-to-TMDS converter).*/
437 union dwnstream_portxcaps {
438 	struct {
439 		union dwnstream_port_caps_byte0 byte0;
440 		unsigned char max_TMDS_clock;   //byte1
441 		union dwnstream_port_caps_byte2 byte2;
442 
443 		union {
444 			union dwnstream_port_caps_byte3_dvi byteDVI;
445 			union dwnstream_port_caps_byte3_hdmi byteHDMI;
446 		} byte3;
447 	} bytes;
448 
449 	unsigned char raw[4];
450 };
451 
452 union downstream_port {
453 	struct {
454 		unsigned char   present:1;
455 		unsigned char   type:2;
456 		unsigned char   format_conv:1;
457 		unsigned char   detailed_caps:1;
458 		unsigned char   reserved:3;
459 	} bits;
460 	unsigned char raw;
461 };
462 
463 
464 union sink_status {
465 	struct {
466 		uint8_t RX_PORT0_STATUS:1;
467 		uint8_t RX_PORT1_STATUS:1;
468 		uint8_t RESERVED:6;
469 	} bits;
470 	uint8_t raw;
471 };
472 
473 /*6-byte structure corresponding to 6 registers (200h-205h)
474 read during handling of HPD-IRQ*/
475 union hpd_irq_data {
476 	struct {
477 		union sink_count sink_cnt;/* 200h */
478 		union device_service_irq device_service_irq;/* 201h */
479 		union lane_status lane01_status;/* 202h */
480 		union lane_status lane23_status;/* 203h */
481 		union lane_align_status_updated lane_status_updated;/* 204h */
482 		union sink_status sink_status;
483 	} bytes;
484 	uint8_t raw[6];
485 };
486 
487 union down_stream_port_count {
488 	struct {
489 		uint8_t DOWN_STR_PORT_COUNT:4;
490 		uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/
491 		/*Bit 6 = MSA_TIMING_PAR_IGNORED
492 		0 = Sink device requires the MSA timing parameters
493 		1 = Sink device is capable of rendering incoming video
494 		 stream without MSA timing parameters*/
495 		uint8_t IGNORE_MSA_TIMING_PARAM:1;
496 		/*Bit 7 = OUI Support
497 		0 = OUI not supported
498 		1 = OUI supported
499 		(OUI and Device Identification mandatory for DP 1.2)*/
500 		uint8_t OUI_SUPPORT:1;
501 	} bits;
502 	uint8_t raw;
503 };
504 
505 union down_spread_ctrl {
506 	struct {
507 		uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/
508 	/* Bits 4 = SPREAD_AMP. Spreading amplitude
509 	0 = Main link signal is not downspread
510 	1 = Main link signal is downspread <= 0.5%
511 	with frequency in the range of 30kHz ~ 33kHz*/
512 		uint8_t SPREAD_AMP:1;
513 		uint8_t RESERVED2:1;/*Bit 5 = RESERVED. Read all 0s*/
514 	/* Bit 6 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE.
515 	0 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE is not enabled by the Source device (default)
516 	1 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE is enabled by Source device */
517 		uint8_t FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE:1;
518 	/*Bit 7 = MSA_TIMING_PAR_IGNORE_EN
519 	0 = Source device will send valid data for the MSA Timing Params
520 	1 = Source device may send invalid data for these MSA Timing Params*/
521 		uint8_t IGNORE_MSA_TIMING_PARAM:1;
522 	} bits;
523 	uint8_t raw;
524 };
525 
526 union dpcd_edp_config {
527 	struct {
528 		uint8_t PANEL_MODE_EDP:1;
529 		uint8_t FRAMING_CHANGE_ENABLE:1;
530 		uint8_t RESERVED:5;
531 		uint8_t PANEL_SELF_TEST_ENABLE:1;
532 	} bits;
533 	uint8_t raw;
534 };
535 
536 struct dp_device_vendor_id {
537 	uint8_t ieee_oui[3];/*24-bit IEEE OUI*/
538 	uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/
539 };
540 
541 struct dp_sink_hw_fw_revision {
542 	uint8_t ieee_hw_rev;
543 	uint8_t ieee_fw_rev[2];
544 };
545 
546 struct dpcd_vendor_signature {
547 	bool is_valid;
548 
549 	union dpcd_ieee_vendor_signature {
550 		struct {
551 			uint8_t ieee_oui[3];/*24-bit IEEE OUI*/
552 			uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/
553 			uint8_t ieee_hw_rev;
554 			uint8_t ieee_fw_rev[2];
555 		};
556 		uint8_t raw[12];
557 	} data;
558 };
559 
560 struct dpcd_amd_signature {
561 	uint8_t AMD_IEEE_TxSignature_byte1;
562 	uint8_t AMD_IEEE_TxSignature_byte2;
563 	uint8_t AMD_IEEE_TxSignature_byte3;
564 };
565 
566 struct dpcd_amd_device_id {
567 	uint8_t device_id_byte1;
568 	uint8_t device_id_byte2;
569 	uint8_t zero[4];
570 	uint8_t dce_version;
571 	uint8_t dal_version_byte1;
572 	uint8_t dal_version_byte2;
573 };
574 
575 struct target_luminance_value {
576 	uint8_t byte0;
577 	uint8_t byte1;
578 	uint8_t byte2;
579 };
580 
581 struct dpcd_source_backlight_set {
582 	struct  {
583 		uint8_t byte0;
584 		uint8_t byte1;
585 		uint8_t byte2;
586 		uint8_t byte3;
587 	} backlight_level_millinits;
588 
589 	struct  {
590 		uint8_t byte0;
591 		uint8_t byte1;
592 	} backlight_transition_time_ms;
593 };
594 
595 union dpcd_source_backlight_get {
596 	struct {
597 		uint32_t backlight_millinits_peak; /* 326h */
598 		uint32_t backlight_millinits_avg; /* 32Ah */
599 	} bytes;
600 	uint8_t raw[8];
601 };
602 
603 /*DPCD register of DP receiver capability field bits-*/
604 union edp_configuration_cap {
605 	struct {
606 		uint8_t ALT_SCRAMBLER_RESET:1;
607 		uint8_t FRAMING_CHANGE:1;
608 		uint8_t RESERVED:1;
609 		uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1;
610 		uint8_t RESERVED2:4;
611 	} bits;
612 	uint8_t raw;
613 };
614 
615 union dprx_feature {
616 	struct {
617 		uint8_t GTC_CAP:1;                             // bit 0: DP 1.3+
618 		uint8_t SST_SPLIT_SDP_CAP:1;                   // bit 1: DP 1.4
619 		uint8_t AV_SYNC_CAP:1;                         // bit 2: DP 1.3+
620 		uint8_t VSC_SDP_COLORIMETRY_SUPPORTED:1;       // bit 3: DP 1.3+
621 		uint8_t VSC_EXT_VESA_SDP_SUPPORTED:1;          // bit 4: DP 1.4
622 		uint8_t VSC_EXT_VESA_SDP_CHAINING_SUPPORTED:1; // bit 5: DP 1.4
623 		uint8_t VSC_EXT_CEA_SDP_SUPPORTED:1;           // bit 6: DP 1.4
624 		uint8_t VSC_EXT_CEA_SDP_CHAINING_SUPPORTED:1;  // bit 7: DP 1.4
625 	} bits;
626 	uint8_t raw;
627 };
628 
629 union training_aux_rd_interval {
630 	struct {
631 		uint8_t TRAINIG_AUX_RD_INTERVAL:7;
632 		uint8_t EXT_RECEIVER_CAP_FIELD_PRESENT:1;
633 	} bits;
634 	uint8_t raw;
635 };
636 
637 /* Automated test structures */
638 union test_request {
639 	struct {
640 	uint8_t LINK_TRAINING                :1;
641 	uint8_t LINK_TEST_PATTRN             :1;
642 	uint8_t EDID_READ                    :1;
643 	uint8_t PHY_TEST_PATTERN             :1;
644 	uint8_t PHY_TEST_CHANNEL_CODING_TYPE :2;
645 	uint8_t AUDIO_TEST_PATTERN           :1;
646 	uint8_t TEST_AUDIO_DISABLED_VIDEO    :1;
647 	} bits;
648 	uint8_t raw;
649 };
650 
651 union test_response {
652 	struct {
653 		uint8_t ACK         :1;
654 		uint8_t NO_ACK      :1;
655 		uint8_t EDID_CHECKSUM_WRITE:1;
656 		uint8_t RESERVED    :5;
657 	} bits;
658 	uint8_t raw;
659 };
660 
661 union phy_test_pattern {
662 	struct {
663 		/* This field is 7 bits for DP2.0 */
664 		uint8_t PATTERN     :7;
665 		uint8_t RESERVED    :1;
666 	} bits;
667 	uint8_t raw;
668 };
669 
670 /* States of Compliance Test Specification (CTS DP1.2). */
671 union compliance_test_state {
672 	struct {
673 		unsigned char STEREO_3D_RUNNING        : 1;
674 		unsigned char RESERVED                 : 7;
675 	} bits;
676 	unsigned char raw;
677 };
678 
679 union link_test_pattern {
680 	struct {
681 		/* dpcd_link_test_patterns */
682 		unsigned char PATTERN :2;
683 		unsigned char RESERVED:6;
684 	} bits;
685 	unsigned char raw;
686 };
687 
688 union test_misc {
689 	struct dpcd_test_misc_bits {
690 		unsigned char SYNC_CLOCK  :1;
691 		/* dpcd_test_color_format */
692 		unsigned char CLR_FORMAT  :2;
693 		/* dpcd_test_dyn_range */
694 		unsigned char DYN_RANGE   :1;
695 		unsigned char YCBCR_COEFS :1;
696 		/* dpcd_test_bit_depth */
697 		unsigned char BPC         :3;
698 	} bits;
699 	unsigned char raw;
700 };
701 
702 union audio_test_mode {
703 	struct {
704 		unsigned char sampling_rate   :4;
705 		unsigned char channel_count   :4;
706 	} bits;
707 	unsigned char raw;
708 };
709 
710 union audio_test_pattern_period {
711 	struct {
712 		unsigned char pattern_period   :4;
713 		unsigned char reserved         :4;
714 	} bits;
715 	unsigned char raw;
716 };
717 
718 struct audio_test_pattern_type {
719 	unsigned char value;
720 };
721 
722 struct dp_audio_test_data_flags {
723 	uint8_t test_requested  :1;
724 	uint8_t disable_video   :1;
725 };
726 
727 struct dp_audio_test_data {
728 
729 	struct dp_audio_test_data_flags flags;
730 	uint8_t sampling_rate;
731 	uint8_t channel_count;
732 	uint8_t pattern_type;
733 	uint8_t pattern_period[8];
734 };
735 
736 /* FEC capability DPCD register field bits-*/
737 union dpcd_fec_capability {
738 	struct {
739 		uint8_t FEC_CAPABLE:1;
740 		uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1;
741 		uint8_t CORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1;
742 		uint8_t BIT_ERROR_COUNT_CAPABLE:1;
743 		uint8_t PARITY_BLOCK_ERROR_COUNT_CAPABLE:1;
744 		uint8_t ARITY_BIT_ERROR_COUNT_CAPABLE:1;
745 		uint8_t FEC_RUNNING_INDICATOR_SUPPORTED:1;
746 		uint8_t FEC_ERROR_REPORTING_POLICY_SUPPORTED:1;
747 	} bits;
748 	uint8_t raw;
749 };
750 
751 /* DSC capability DPCD register field bits-*/
752 struct dpcd_dsc_support {
753 	uint8_t DSC_SUPPORT		:1;
754 	uint8_t DSC_PASSTHROUGH_SUPPORT	:1;
755 	uint8_t RESERVED		:6;
756 };
757 
758 struct dpcd_dsc_algorithm_revision {
759 	uint8_t DSC_VERSION_MAJOR	:4;
760 	uint8_t DSC_VERSION_MINOR	:4;
761 };
762 
763 struct dpcd_dsc_rc_buffer_block_size {
764 	uint8_t RC_BLOCK_BUFFER_SIZE	:2;
765 	uint8_t RESERVED		:6;
766 };
767 
768 struct dpcd_dsc_slice_capability1 {
769 	uint8_t ONE_SLICE_PER_DP_DSC_SINK_DEVICE	:1;
770 	uint8_t TWO_SLICES_PER_DP_DSC_SINK_DEVICE	:1;
771 	uint8_t RESERVED				:1;
772 	uint8_t FOUR_SLICES_PER_DP_DSC_SINK_DEVICE	:1;
773 	uint8_t SIX_SLICES_PER_DP_DSC_SINK_DEVICE	:1;
774 	uint8_t EIGHT_SLICES_PER_DP_DSC_SINK_DEVICE	:1;
775 	uint8_t TEN_SLICES_PER_DP_DSC_SINK_DEVICE	:1;
776 	uint8_t TWELVE_SLICES_PER_DP_DSC_SINK_DEVICE	:1;
777 };
778 
779 struct dpcd_dsc_line_buffer_bit_depth {
780 	uint8_t LINE_BUFFER_BIT_DEPTH	:4;
781 	uint8_t RESERVED		:4;
782 };
783 
784 struct dpcd_dsc_block_prediction_support {
785 	uint8_t BLOCK_PREDICTION_SUPPORT:1;
786 	uint8_t RESERVED		:7;
787 };
788 
789 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor {
790 	uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_LOW	:7;
791 	uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_HIGH	:7;
792 	uint8_t RESERVED							:2;
793 };
794 
795 struct dpcd_dsc_decoder_color_format_capabilities {
796 	uint8_t RGB_SUPPORT			:1;
797 	uint8_t Y_CB_CR_444_SUPPORT		:1;
798 	uint8_t Y_CB_CR_SIMPLE_422_SUPPORT	:1;
799 	uint8_t Y_CB_CR_NATIVE_422_SUPPORT	:1;
800 	uint8_t Y_CB_CR_NATIVE_420_SUPPORT	:1;
801 	uint8_t RESERVED			:3;
802 };
803 
804 struct dpcd_dsc_decoder_color_depth_capabilities {
805 	uint8_t RESERVED0			:1;
806 	uint8_t EIGHT_BITS_PER_COLOR_SUPPORT	:1;
807 	uint8_t TEN_BITS_PER_COLOR_SUPPORT	:1;
808 	uint8_t TWELVE_BITS_PER_COLOR_SUPPORT	:1;
809 	uint8_t RESERVED1			:4;
810 };
811 
812 struct dpcd_peak_dsc_throughput_dsc_sink {
813 	uint8_t THROUGHPUT_MODE_0:4;
814 	uint8_t THROUGHPUT_MODE_1:4;
815 };
816 
817 struct dpcd_dsc_slice_capabilities_2 {
818 	uint8_t SIXTEEN_SLICES_PER_DSC_SINK_DEVICE	:1;
819 	uint8_t TWENTY_SLICES_PER_DSC_SINK_DEVICE	:1;
820 	uint8_t TWENTYFOUR_SLICES_PER_DSC_SINK_DEVICE	:1;
821 	uint8_t RESERVED				:5;
822 };
823 
824 struct dpcd_bits_per_pixel_increment{
825 	uint8_t INCREMENT_OF_BITS_PER_PIXEL_SUPPORTED	:3;
826 	uint8_t RESERVED				:5;
827 };
828 union dpcd_dsc_basic_capabilities {
829 	struct {
830 		struct dpcd_dsc_support dsc_support;
831 		struct dpcd_dsc_algorithm_revision dsc_algorithm_revision;
832 		struct dpcd_dsc_rc_buffer_block_size dsc_rc_buffer_block_size;
833 		uint8_t dsc_rc_buffer_size;
834 		struct dpcd_dsc_slice_capability1 dsc_slice_capabilities_1;
835 		struct dpcd_dsc_line_buffer_bit_depth dsc_line_buffer_bit_depth;
836 		struct dpcd_dsc_block_prediction_support dsc_block_prediction_support;
837 		struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor maximum_bits_per_pixel_supported_by_the_decompressor;
838 		struct dpcd_dsc_decoder_color_format_capabilities dsc_decoder_color_format_capabilities;
839 		struct dpcd_dsc_decoder_color_depth_capabilities dsc_decoder_color_depth_capabilities;
840 		struct dpcd_peak_dsc_throughput_dsc_sink peak_dsc_throughput_dsc_sink;
841 		uint8_t dsc_maximum_slice_width;
842 		struct dpcd_dsc_slice_capabilities_2 dsc_slice_capabilities_2;
843 		uint8_t reserved;
844 		struct dpcd_bits_per_pixel_increment bits_per_pixel_increment;
845 	} fields;
846 	uint8_t raw[16];
847 };
848 
849 union dpcd_dsc_branch_decoder_capabilities {
850 	struct {
851 		uint8_t BRANCH_OVERALL_THROUGHPUT_0;
852 		uint8_t BRANCH_OVERALL_THROUGHPUT_1;
853 		uint8_t BRANCH_MAX_LINE_WIDTH;
854 	} fields;
855 	uint8_t raw[3];
856 };
857 
858 struct dpcd_dsc_capabilities {
859 	union dpcd_dsc_basic_capabilities dsc_basic_caps;
860 	union dpcd_dsc_branch_decoder_capabilities dsc_branch_decoder_caps;
861 };
862 
863 /* These parameters are from PSR capabilities reported by Sink DPCD */
864 struct psr_caps {
865 	unsigned char psr_version;
866 	unsigned int psr_rfb_setup_time;
867 	bool psr_exit_link_training_required;
868 	unsigned char edp_revision;
869 	unsigned char support_ver;
870 	bool su_granularity_required;
871 	bool y_coordinate_required;
872 	uint8_t su_y_granularity;
873 	bool alpm_cap;
874 	bool standby_support;
875 	uint8_t rate_control_caps;
876 	unsigned int psr_power_opt_flag;
877 };
878 
879 union dpcd_dprx_feature_enumeration_list_cont_1 {
880 	struct {
881 		uint8_t ADAPTIVE_SYNC_SDP_SUPPORT:1;
882 		uint8_t AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED: 1;
883 		uint8_t RESERVED0: 2;
884 		uint8_t VSC_EXT_SDP_VER1_SUPPORT: 1;
885 		uint8_t RESERVED1: 3;
886 	} bits;
887 	uint8_t raw;
888 };
889 
890 struct adaptive_sync_caps {
891 	union dpcd_dprx_feature_enumeration_list_cont_1 dp_adap_sync_caps;
892 };
893 
894 /* Length of router topology ID read from DPCD in bytes. */
895 #define DPCD_USB4_TOPOLOGY_ID_LEN 5
896 
897 /* DPCD[0xE000D] DP_TUNNELING_CAPABILITIES SUPPORT register. */
898 union dp_tun_cap_support {
899 	struct {
900 		uint8_t dp_tunneling :1;
901 		uint8_t rsvd :5;
902 		uint8_t panel_replay_tun_opt :1;
903 		uint8_t dpia_bw_alloc :1;
904 	} bits;
905 	uint8_t raw;
906 };
907 
908 /* DPCD[0xE000E] DP_IN_ADAPTER_INFO register. */
909 union dpia_info {
910 	struct {
911 		uint8_t dpia_num :5;
912 		uint8_t rsvd :3;
913 	} bits;
914 	uint8_t raw;
915 };
916 
917 /* DP Tunneling over USB4 */
918 struct dpcd_usb4_dp_tunneling_info {
919 	union dp_tun_cap_support dp_tun_cap;
920 	union dpia_info dpia_info;
921 	uint8_t usb4_driver_id;
922 	uint8_t usb4_topology_id[DPCD_USB4_TOPOLOGY_ID_LEN];
923 };
924 
925 union dp_main_line_channel_coding_cap {
926 	struct {
927 		uint8_t DP_8b_10b_SUPPORTED	:1;
928 		uint8_t DP_128b_132b_SUPPORTED	:1;
929 		uint8_t RESERVED		:6;
930 	} bits;
931 	uint8_t raw;
932 };
933 
934 union dp_main_link_channel_coding_lttpr_cap {
935 	struct {
936 		uint8_t DP_128b_132b_SUPPORTED	:1;
937 		uint8_t RESERVED		:7;
938 	} bits;
939 	uint8_t raw;
940 };
941 
942 union dp_128b_132b_supported_link_rates {
943 	struct {
944 		uint8_t UHBR10	:1;
945 		uint8_t UHBR20	:1;
946 		uint8_t UHBR13_5:1;
947 		uint8_t RESERVED:5;
948 	} bits;
949 	uint8_t raw;
950 };
951 
952 union dp_128b_132b_supported_lttpr_link_rates {
953 	struct {
954 		uint8_t UHBR10	:1;
955 		uint8_t UHBR20	:1;
956 		uint8_t UHBR13_5:1;
957 		uint8_t RESERVED:5;
958 	} bits;
959 	uint8_t raw;
960 };
961 
962 union dp_sink_video_fallback_formats {
963 	struct {
964 		uint8_t dp_1024x768_60Hz_24bpp_support	:1;
965 		uint8_t dp_1280x720_60Hz_24bpp_support	:1;
966 		uint8_t dp_1920x1080_60Hz_24bpp_support	:1;
967 		uint8_t RESERVED			:5;
968 	} bits;
969 	uint8_t raw;
970 };
971 
972 union dp_receive_port0_cap {
973 	struct {
974 		uint8_t RESERVED					:1;
975 		uint8_t LOCAL_EDID_PRESENT			:1;
976 		uint8_t ASSOCIATED_TO_PRECEDING_PORT:1;
977 		uint8_t HBLANK_EXPANSION_CAPABLE	:1;
978 		uint8_t BUFFER_SIZE_UNIT			:1;
979 		uint8_t BUFFER_SIZE_PER_PORT		:1;
980 		uint8_t HBLANK_REDUCTION_CAPABLE	:1;
981 		uint8_t RESERVED2:1;
982 		uint8_t BUFFER_SIZE:8;
983 	} bits;
984 	uint8_t raw[2];
985 };
986 
987 union dpcd_max_uncompressed_pixel_rate_cap {
988 	struct {
989 		uint16_t max_uncompressed_pixel_rate_cap	:15;
990 		uint16_t valid			:1;
991 	} bits;
992 	uint8_t raw[2];
993 };
994 
995 union dp_fec_capability1 {
996 	struct {
997 		uint8_t AGGREGATED_ERROR_COUNTERS_CAPABLE	:1;
998 		uint8_t RESERVED				:7;
999 	} bits;
1000 	uint8_t raw;
1001 };
1002 
1003 union dp_cable_id {
1004 	struct {
1005 		uint8_t UHBR10_20_CAPABILITY	:2;
1006 		uint8_t UHBR13_5_CAPABILITY	:1;
1007 		uint8_t CABLE_TYPE		:3;
1008 		uint8_t RESERVED		:2;
1009 	} bits;
1010 	uint8_t raw;
1011 };
1012 
1013 struct dp_color_depth_caps {
1014 	uint8_t support_6bpc	:1;
1015 	uint8_t support_8bpc	:1;
1016 	uint8_t support_10bpc	:1;
1017 	uint8_t support_12bpc	:1;
1018 	uint8_t support_16bpc	:1;
1019 	uint8_t RESERVED	:3;
1020 };
1021 
1022 struct dp_encoding_format_caps {
1023 	uint8_t support_rgb	:1;
1024 	uint8_t support_ycbcr444:1;
1025 	uint8_t support_ycbcr422:1;
1026 	uint8_t support_ycbcr420:1;
1027 	uint8_t RESERVED	:4;
1028 };
1029 
1030 union dp_dfp_cap_ext {
1031 	struct {
1032 		uint8_t supported;
1033 		uint8_t max_pixel_rate_in_mps[2];
1034 		uint8_t max_video_h_active_width[2];
1035 		uint8_t max_video_v_active_height[2];
1036 		struct dp_encoding_format_caps encoding_format_caps;
1037 		struct dp_color_depth_caps rgb_color_depth_caps;
1038 		struct dp_color_depth_caps ycbcr444_color_depth_caps;
1039 		struct dp_color_depth_caps ycbcr422_color_depth_caps;
1040 		struct dp_color_depth_caps ycbcr420_color_depth_caps;
1041 	} fields;
1042 	uint8_t raw[12];
1043 };
1044 
1045 union dp_128b_132b_training_aux_rd_interval {
1046 	struct {
1047 		uint8_t VALUE	:7;
1048 		uint8_t UNIT	:1;
1049 	} bits;
1050 	uint8_t raw;
1051 };
1052 
1053 union edp_alpm_caps {
1054 	struct {
1055 		uint8_t AUX_WAKE_ALPM_CAP       :1;
1056 		uint8_t PM_STATE_2A_SUPPORT     :1;
1057 		uint8_t AUX_LESS_ALPM_CAP       :1;
1058 		uint8_t RESERVED                :5;
1059 	} bits;
1060 	uint8_t raw;
1061 };
1062 
1063 union edp_psr_dpcd_caps {
1064 	struct {
1065 		uint8_t LINK_TRAINING_ON_EXIT_NOT_REQUIRED      :1;
1066 		uint8_t PSR_SETUP_TIME  :3;
1067 		uint8_t Y_COORDINATE_REQUIRED   :1;
1068 		uint8_t SU_GRANULARITY_REQUIRED :1;
1069 		uint8_t FRAME_SYNC_IS_NOT_NEEDED_FOR_SU :1;
1070 		uint8_t RESERVED                :1;
1071 	} bits;
1072 	uint8_t raw;
1073 };
1074 
1075 struct edp_psr_info {
1076 	uint8_t psr_version;
1077 	union edp_psr_dpcd_caps psr_dpcd_caps;
1078 	uint8_t psr2_su_y_granularity_cap;
1079 	uint8_t force_psrsu_cap;
1080 };
1081 
1082 struct replay_info {
1083 	uint8_t pixel_deviation_per_line;
1084 	uint8_t max_deviation_line;
1085 };
1086 
1087 struct dprx_states {
1088 	bool cable_id_written;
1089 };
1090 
1091 enum dpcd_downstream_port_max_bpc {
1092 	DOWN_STREAM_MAX_8BPC = 0,
1093 	DOWN_STREAM_MAX_10BPC,
1094 	DOWN_STREAM_MAX_12BPC,
1095 	DOWN_STREAM_MAX_16BPC
1096 };
1097 
1098 enum link_training_offset {
1099 	DPRX                = 0,
1100 	LTTPR_PHY_REPEATER1 = 1,
1101 	LTTPR_PHY_REPEATER2 = 2,
1102 	LTTPR_PHY_REPEATER3 = 3,
1103 	LTTPR_PHY_REPEATER4 = 4,
1104 	LTTPR_PHY_REPEATER5 = 5,
1105 	LTTPR_PHY_REPEATER6 = 6,
1106 	LTTPR_PHY_REPEATER7 = 7,
1107 	LTTPR_PHY_REPEATER8 = 8
1108 };
1109 
1110 #define MAX_REPEATER_CNT 8
1111 
1112 struct dc_lttpr_caps {
1113 	union dpcd_rev revision;
1114 	uint8_t mode;
1115 	uint8_t max_lane_count;
1116 	uint8_t max_link_rate;
1117 	uint8_t phy_repeater_cnt;
1118 	uint8_t max_ext_timeout;
1119 	union dp_main_link_channel_coding_lttpr_cap main_link_channel_coding;
1120 	union dp_128b_132b_supported_lttpr_link_rates supported_128b_132b_rates;
1121 	uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1];
1122 };
1123 
1124 struct dc_dongle_dfp_cap_ext {
1125 	bool supported;
1126 	uint16_t max_pixel_rate_in_mps;
1127 	uint16_t max_video_h_active_width;
1128 	uint16_t max_video_v_active_height;
1129 	struct dp_encoding_format_caps encoding_format_caps;
1130 	struct dp_color_depth_caps rgb_color_depth_caps;
1131 	struct dp_color_depth_caps ycbcr444_color_depth_caps;
1132 	struct dp_color_depth_caps ycbcr422_color_depth_caps;
1133 	struct dp_color_depth_caps ycbcr420_color_depth_caps;
1134 };
1135 
1136 struct dc_dongle_caps {
1137 	/* dongle type (DP converter, CV smart dongle) */
1138 	enum display_dongle_type dongle_type;
1139 	bool extendedCapValid;
1140 	/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
1141 	indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
1142 	bool is_dp_hdmi_s3d_converter;
1143 	bool is_dp_hdmi_ycbcr422_pass_through;
1144 	bool is_dp_hdmi_ycbcr420_pass_through;
1145 	bool is_dp_hdmi_ycbcr422_converter;
1146 	bool is_dp_hdmi_ycbcr420_converter;
1147 	uint32_t dp_hdmi_max_bpc;
1148 	uint32_t dp_hdmi_max_pixel_clk_in_khz;
1149 	uint32_t dp_hdmi_frl_max_link_bw_in_kbps;
1150 	struct dc_dongle_dfp_cap_ext dfp_cap_ext;
1151 };
1152 
1153 struct dpcd_caps {
1154 	union dpcd_rev dpcd_rev;
1155 	union max_lane_count max_ln_count;
1156 	union max_down_spread max_down_spread;
1157 	union dprx_feature dprx_feature;
1158 
1159 	/* valid only for eDP v1.4 or higher*/
1160 	uint8_t edp_supported_link_rates_count;
1161 	enum dc_link_rate edp_supported_link_rates[8];
1162 
1163 	/* dongle type (DP converter, CV smart dongle) */
1164 	enum display_dongle_type dongle_type;
1165 	bool is_dongle_type_one;
1166 	/* branch device or sink device */
1167 	bool is_branch_dev;
1168 	/* Dongle's downstream count. */
1169 	union sink_count sink_count;
1170 	bool is_mst_capable;
1171 	/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
1172 	indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
1173 	struct dc_dongle_caps dongle_caps;
1174 
1175 	uint32_t sink_dev_id;
1176 	int8_t sink_dev_id_str[6];
1177 	int8_t sink_hw_revision;
1178 	int8_t sink_fw_revision[2];
1179 
1180 	uint32_t branch_dev_id;
1181 	int8_t branch_dev_name[6];
1182 	int8_t branch_hw_revision;
1183 	int8_t branch_fw_revision[2];
1184 	int8_t branch_vendor_specific_data[4];
1185 
1186 	bool allow_invalid_MSA_timing_param;
1187 	bool panel_mode_edp;
1188 	bool dpcd_display_control_capable;
1189 	bool ext_receiver_cap_field_present;
1190 	bool set_power_state_capable_edp;
1191 	bool dynamic_backlight_capable_edp;
1192 	union dpcd_fec_capability fec_cap;
1193 	struct dpcd_dsc_capabilities dsc_caps;
1194 	struct dc_lttpr_caps lttpr_caps;
1195 	struct adaptive_sync_caps adaptive_sync_caps;
1196 	struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info;
1197 	union dpcd_max_uncompressed_pixel_rate_cap max_uncompressed_pixel_rate_cap;
1198 
1199 	union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates;
1200 	union dp_main_line_channel_coding_cap channel_coding_cap;
1201 	union dp_sink_video_fallback_formats fallback_formats;
1202 	union dp_fec_capability1 fec_cap1;
1203 	bool panel_luminance_control;
1204 	union dp_cable_id cable_id;
1205 	uint8_t edp_rev;
1206 	union edp_alpm_caps alpm_caps;
1207 	struct edp_psr_info psr_info;
1208 
1209 	struct replay_info pr_info;
1210 	uint16_t edp_oled_emission_rate;
1211 	union dp_receive_port0_cap receive_port0_cap;
1212 };
1213 
1214 union dpcd_sink_ext_caps {
1215 	struct {
1216 		/* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode
1217 		 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode.
1218 		 */
1219 		uint8_t sdr_aux_backlight_control : 1;
1220 		uint8_t hdr_aux_backlight_control : 1;
1221 		uint8_t reserved_1 : 2;
1222 		uint8_t oled : 1;
1223 		uint8_t reserved_2 : 1;
1224 		uint8_t miniled : 1;
1225 		uint8_t emission_output : 1;
1226 	} bits;
1227 	uint8_t raw;
1228 };
1229 
1230 enum dc_link_fec_state {
1231 	dc_link_fec_not_ready,
1232 	dc_link_fec_ready,
1233 	dc_link_fec_enabled
1234 };
1235 
1236 union dpcd_psr_configuration {
1237 	struct {
1238 		unsigned char ENABLE                    : 1;
1239 		unsigned char TRANSMITTER_ACTIVE_IN_PSR : 1;
1240 		unsigned char CRC_VERIFICATION          : 1;
1241 		unsigned char FRAME_CAPTURE_INDICATION  : 1;
1242 		/* For eDP 1.4, PSR v2*/
1243 		unsigned char LINE_CAPTURE_INDICATION   : 1;
1244 		/* For eDP 1.4, PSR v2*/
1245 		unsigned char IRQ_HPD_WITH_CRC_ERROR    : 1;
1246 		unsigned char ENABLE_PSR2               : 1;
1247 		unsigned char EARLY_TRANSPORT_ENABLE    : 1;
1248 	} bits;
1249 	unsigned char raw;
1250 };
1251 
1252 union replay_enable_and_configuration {
1253 	struct {
1254 		unsigned char FREESYNC_PANEL_REPLAY_MODE              :1;
1255 		unsigned char TIMING_DESYNC_ERROR_VERIFICATION        :1;
1256 		unsigned char STATE_TRANSITION_ERROR_DETECTION        :1;
1257 		unsigned char RESERVED                                :5;
1258 	} bits;
1259 	unsigned char raw;
1260 };
1261 
1262 union dpcd_replay_configuration {
1263 	struct {
1264 		unsigned char STATE_TRANSITION_ERROR_STATUS    : 1;
1265 		unsigned char DESYNC_ERROR_STATUS              : 1;
1266 		unsigned char SINK_DEVICE_REPLAY_STATUS        : 3;
1267 		unsigned char SINK_FRAME_LOCKED                : 2;
1268 		unsigned char RESERVED                         : 1;
1269 	} bits;
1270 	unsigned char raw;
1271 };
1272 
1273 union dpcd_alpm_configuration {
1274 	struct {
1275 		unsigned char ENABLE                    : 1;
1276 		unsigned char IRQ_HPD_ENABLE            : 1;
1277 		unsigned char RESERVED                  : 6;
1278 	} bits;
1279 	unsigned char raw;
1280 };
1281 
1282 union dpcd_sink_active_vtotal_control_mode {
1283 	struct {
1284 		unsigned char ENABLE                    : 1;
1285 		unsigned char RESERVED                  : 7;
1286 	} bits;
1287 	unsigned char raw;
1288 };
1289 
1290 union psr_error_status {
1291 	struct {
1292 		unsigned char LINK_CRC_ERROR        :1;
1293 		unsigned char RFB_STORAGE_ERROR     :1;
1294 		unsigned char VSC_SDP_ERROR         :1;
1295 		unsigned char RESERVED              :5;
1296 	} bits;
1297 	unsigned char raw;
1298 };
1299 
1300 union psr_sink_psr_status {
1301 	struct {
1302 	unsigned char SINK_SELF_REFRESH_STATUS  :3;
1303 	unsigned char RESERVED                  :5;
1304 	} bits;
1305 	unsigned char raw;
1306 };
1307 
1308 struct edp_trace_power_timestamps {
1309 	uint64_t poweroff;
1310 	uint64_t poweron;
1311 };
1312 
1313 struct dp_trace_lt_counts {
1314 	unsigned int total;
1315 	unsigned int fail;
1316 };
1317 
1318 enum link_training_result {
1319 	LINK_TRAINING_SUCCESS,
1320 	LINK_TRAINING_CR_FAIL_LANE0,
1321 	LINK_TRAINING_CR_FAIL_LANE1,
1322 	LINK_TRAINING_CR_FAIL_LANE23,
1323 	/* CR DONE bit is cleared during EQ step */
1324 	LINK_TRAINING_EQ_FAIL_CR,
1325 	/* CR DONE bit is cleared but LANE0_CR_DONE is set during EQ step */
1326 	LINK_TRAINING_EQ_FAIL_CR_PARTIAL,
1327 	/* other failure during EQ step */
1328 	LINK_TRAINING_EQ_FAIL_EQ,
1329 	LINK_TRAINING_LQA_FAIL,
1330 	/* one of the CR,EQ or symbol lock is dropped */
1331 	LINK_TRAINING_LINK_LOSS,
1332 	/* Abort link training (because sink unplugged) */
1333 	LINK_TRAINING_ABORT,
1334 	DP_128b_132b_LT_FAILED,
1335 	DP_128b_132b_MAX_LOOP_COUNT_REACHED,
1336 	DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT,
1337 	DP_128b_132b_CDS_DONE_TIMEOUT,
1338 };
1339 
1340 struct dp_trace_lt {
1341 	struct dp_trace_lt_counts counts;
1342 	struct dp_trace_timestamps {
1343 		unsigned long long start;
1344 		unsigned long long end;
1345 	} timestamps;
1346 	enum link_training_result result;
1347 	bool is_logged;
1348 };
1349 
1350 struct dp_trace {
1351 	struct dp_trace_lt detect_lt_trace;
1352 	struct dp_trace_lt commit_lt_trace;
1353 	unsigned int link_loss_count;
1354 	bool is_initialized;
1355 	struct edp_trace_power_timestamps edp_trace_power_timestamps;
1356 };
1357 
1358 /* TODO - This is a temporary location for any new DPCD definitions.
1359  * We should move these to drm_dp header.
1360  */
1361 #ifndef DP_LINK_SQUARE_PATTERN
1362 #define DP_LINK_SQUARE_PATTERN				0x10F
1363 #endif
1364 #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX
1365 #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX		0x2217
1366 #endif
1367 #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX
1368 #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX		0x110
1369 #endif
1370 #ifndef DPCD_MAX_UNCOMPRESSED_PIXEL_RATE_CAP
1371 #define DPCD_MAX_UNCOMPRESSED_PIXEL_RATE_CAP    0x221c
1372 #endif
1373 #ifndef DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE
1374 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE	0x50
1375 #endif
1376 #ifndef DP_TUNNELING_IRQ
1377 #define DP_TUNNELING_IRQ				(1 << 5)
1378 #endif
1379 #ifndef DP_BRANCH_VENDOR_SPECIFIC_START
1380 #define DP_BRANCH_VENDOR_SPECIFIC_START     0x50C
1381 #endif
1382 /** USB4 DPCD BW Allocation Registers Chapter 10.7 **/
1383 #ifndef DP_TUNNELING_CAPABILITIES
1384 #define DP_TUNNELING_CAPABILITIES			0xE000D /* 1.4a */
1385 #endif
1386 #ifndef USB4_DRIVER_ID
1387 #define USB4_DRIVER_ID					0xE000F /* 1.4a */
1388 #endif
1389 #ifndef USB4_DRIVER_BW_CAPABILITY
1390 #define USB4_DRIVER_BW_CAPABILITY			0xE0020 /* 1.4a */
1391 #endif
1392 #ifndef DP_IN_ADAPTER_TUNNEL_INFO
1393 #define DP_IN_ADAPTER_TUNNEL_INFO			0xE0021 /* 1.4a */
1394 #endif
1395 #ifndef DP_BW_GRANULALITY
1396 #define DP_BW_GRANULALITY				0xE0022 /* 1.4a */
1397 #endif
1398 #ifndef ESTIMATED_BW
1399 #define ESTIMATED_BW					0xE0023 /* 1.4a */
1400 #endif
1401 #ifndef ALLOCATED_BW
1402 #define ALLOCATED_BW					0xE0024 /* 1.4a */
1403 #endif
1404 #ifndef DP_TUNNELING_STATUS
1405 #define DP_TUNNELING_STATUS				0xE0025 /* 1.4a */
1406 #endif
1407 #ifndef DP_TUNNELING_MAX_LINK_RATE
1408 #define DP_TUNNELING_MAX_LINK_RATE			0xE0028 /* 1.4a */
1409 #endif
1410 #ifndef DP_TUNNELING_MAX_LANE_COUNT
1411 #define DP_TUNNELING_MAX_LANE_COUNT			0xE0029 /* 1.4a */
1412 #endif
1413 #ifndef DPTX_BW_ALLOCATION_MODE_CONTROL
1414 #define DPTX_BW_ALLOCATION_MODE_CONTROL			0xE0030 /* 1.4a */
1415 #endif
1416 #ifndef REQUESTED_BW
1417 #define REQUESTED_BW					0xE0031 /* 1.4a */
1418 #endif
1419 #endif /* DC_DP_TYPES_H */
1420