1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2001-2024, Intel Corporation 5 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 6 * Copyright (c) 2024 Kevin Bowling <kbowling@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 31 #ifndef _EM_H_DEFINED_ 32 #define _EM_H_DEFINED_ 33 34 #include "opt_ddb.h" 35 #include "opt_inet.h" 36 #include "opt_inet6.h" 37 #include "opt_rss.h" 38 39 #ifdef HAVE_KERNEL_OPTION_HEADERS 40 #include "opt_device_polling.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #ifdef DDB 46 #include <sys/types.h> 47 #include <ddb/ddb.h> 48 #endif 49 #include <sys/buf_ring.h> 50 #include <sys/bus.h> 51 #include <sys/endian.h> 52 #include <sys/kernel.h> 53 #include <sys/kthread.h> 54 #include <sys/malloc.h> 55 #include <sys/mbuf.h> 56 #include <sys/module.h> 57 #include <sys/rman.h> 58 #include <sys/smp.h> 59 #include <sys/socket.h> 60 #include <sys/sockio.h> 61 #include <sys/sysctl.h> 62 #include <sys/taskqueue.h> 63 #include <sys/eventhandler.h> 64 #include <machine/bus.h> 65 #include <machine/resource.h> 66 67 #include <net/bpf.h> 68 #include <net/ethernet.h> 69 #include <net/if.h> 70 #include <net/if_var.h> 71 #include <net/if_arp.h> 72 #include <net/if_dl.h> 73 #include <net/if_media.h> 74 #include <net/iflib.h> 75 #include <net/rss_config.h> 76 #include <netinet/in_rss.h> 77 78 #include <net/if_types.h> 79 #include <net/if_vlan_var.h> 80 81 #include <netinet/in_systm.h> 82 #include <netinet/in.h> 83 #include <netinet/if_ether.h> 84 #include <netinet/ip.h> 85 #include <netinet/ip6.h> 86 #include <netinet/tcp.h> 87 #include <netinet/udp.h> 88 89 #include <machine/in_cksum.h> 90 #include <dev/led/led.h> 91 #include <dev/pci/pcivar.h> 92 #include <dev/pci/pcireg.h> 93 94 #include "e1000_api.h" 95 #include "e1000_82571.h" 96 #include "ifdi_if.h" 97 98 /* Tunables */ 99 100 /* 101 * EM_MAX_TXD: Maximum number of Transmit Descriptors 102 * Valid Range: 80-256 for 82542 and 82543-based adapters 103 * 80-4096 for others 104 * Default Value: 1024 105 * This value is the number of transmit descriptors allocated by the driver. 106 * Increasing this value allows the driver to queue more transmits. Each 107 * descriptor is 16 bytes. 108 * Since TDLEN should be multiple of 128bytes, the number of transmit 109 * desscriptors should meet the following condition. 110 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 111 */ 112 #define EM_MIN_TXD 128 113 #define EM_MAX_TXD 4096 114 #define EM_DEFAULT_TXD 1024 115 #define EM_DEFAULT_MULTI_TXD 4096 116 #define IGB_MAX_TXD 4096 117 118 /* 119 * EM_MAX_RXD - Maximum number of receive Descriptors 120 * Valid Range: 80-256 for 82542 and 82543-based adapters 121 * 80-4096 for others 122 * Default Value: 1024 123 * This value is the number of receive descriptors allocated by the driver. 124 * Increasing this value allows the driver to buffer more incoming packets. 125 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 126 * descriptor. The maximum MTU size is 16110. 127 * Since TDLEN should be multiple of 128bytes, the number of transmit 128 * desscriptors should meet the following condition. 129 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 130 */ 131 #define EM_MIN_RXD 128 132 #define EM_MAX_RXD 4096 133 #define EM_DEFAULT_RXD 1024 134 #define EM_DEFAULT_MULTI_RXD 4096 135 #define IGB_MAX_RXD 4096 136 137 /* 138 * EM_TIDV - Transmit Interrupt Delay Value 139 * Valid Range: 0-65535 (0=off) 140 * Default Value: 64 141 * This value delays the generation of transmit interrupts in units of 142 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 143 * efficiency if properly tuned for specific network traffic. If the 144 * system is reporting dropped transmits, this value may be set too high 145 * causing the driver to run out of available transmit descriptors. 146 */ 147 #define EM_TIDV 64 148 149 /* 150 * EM_TADV - Transmit Absolute Interrupt Delay Value 151 * (Not valid for 82542/82543/82544) 152 * Valid Range: 0-65535 (0=off) 153 * Default Value: 64 154 * This value, in units of 1.024 microseconds, limits the delay in which a 155 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 156 * this value ensures that an interrupt is generated after the initial 157 * packet is sent on the wire within the set amount of time. Proper tuning, 158 * along with EM_TIDV, may improve traffic throughput in specific 159 * network conditions. 160 */ 161 #define EM_TADV 64 162 163 /* 164 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 165 * Valid Range: 0-65535 (0=off) 166 * Default Value: 0 167 * This value delays the generation of receive interrupts in units of 1.024 168 * microseconds. Receive interrupt reduction can improve CPU efficiency if 169 * properly tuned for specific network traffic. Increasing this value adds 170 * extra latency to frame reception and can end up decreasing the throughput 171 * of TCP traffic. If the system is reporting dropped receives, this value 172 * may be set too high, causing the driver to run out of available receive 173 * descriptors. 174 * 175 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 176 * may hang (stop transmitting) under certain network conditions. 177 * If this occurs a WATCHDOG message is logged in the system 178 * event log. In addition, the controller is automatically reset, 179 * restoring the network connection. To eliminate the potential 180 * for the hang ensure that EM_RDTR is set to 0. 181 */ 182 #define EM_RDTR 0 183 184 /* 185 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 186 * Valid Range: 0-65535 (0=off) 187 * Default Value: 64 188 * This value, in units of 1.024 microseconds, limits the delay in which a 189 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 190 * this value ensures that an interrupt is generated after the initial 191 * packet is received within the set amount of time. Proper tuning, 192 * along with EM_RDTR, may improve traffic throughput in specific network 193 * conditions. 194 */ 195 #define EM_RADV 64 196 197 /* 198 * This parameter controls whether or not autonegotiation is enabled. 199 * 0 - Disable autonegotiation 200 * 1 - Enable autonegotiation 201 */ 202 #define DO_AUTO_NEG 1 203 204 /* 205 * This parameter control whether or not the driver will wait for 206 * autonegotiation to complete. 207 * 1 - Wait for autonegotiation to complete 208 * 0 - Don't wait for autonegotiation to complete 209 */ 210 #define WAIT_FOR_AUTO_NEG_DEFAULT 0 211 212 /* Tunables -- End */ 213 214 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 215 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 216 ADVERTISE_1000_FULL) 217 218 #define AUTO_ALL_MODES 0 219 220 /* PHY master/slave setting */ 221 #define EM_MASTER_SLAVE e1000_ms_hw_default 222 223 /* 224 * Miscellaneous constants 225 */ 226 #define EM_VENDOR_ID 0x8086 227 #define EM_FLASH 0x0014 228 229 #define EM_JUMBO_PBA 0x00000028 230 #define EM_DEFAULT_PBA 0x00000030 231 #define EM_SMARTSPEED_DOWNSHIFT 3 232 #define EM_SMARTSPEED_MAX 15 233 #define EM_MAX_LOOP 10 234 235 #define MAX_NUM_MULTICAST_ADDRESSES 128 236 #define PCI_ANY_ID (~0U) 237 #define ETHER_ALIGN 2 238 #define EM_FC_PAUSE_TIME 0x0680 239 #define EM_EEPROM_APME 0x400; 240 #define EM_82544_APME 0x0004; 241 242 /* Support AutoMediaDetect for Marvell M88 PHY in i354 */ 243 #define IGB_MEDIA_RESET (1 << 0) 244 245 /* Define the interrupt rates and ITR helpers */ 246 #define EM_INTS_4K 4000 247 #define EM_INTS_20K 20000 248 #define EM_INTS_70K 70000 249 #define EM_INTS_DEFAULT 8000 250 #define EM_INTS_MULTIPLIER 256 251 #define EM_ITR_DIVIDEND 1000000000 252 #define EM_INTS_TO_ITR(i) (EM_ITR_DIVIDEND/(i * EM_INTS_MULTIPLIER)) 253 #define IGB_EITR_DIVIDEND 1000000 254 #define IGB_EITR_SHIFT 2 255 #define IGB_QVECTOR_MASK 0x7FFC 256 #define IGB_INTS_TO_EITR(i) (((IGB_EITR_DIVIDEND/i) & IGB_QVECTOR_MASK) << \ 257 IGB_EITR_SHIFT) 258 259 #define IGB_LINK_ITR 2000 260 #define I210_LINK_DELAY 1000 261 262 #define IGB_TXPBSIZE 20408 263 #define IGB_HDR_BUF 128 264 #define IGB_PKTTYPE_MASK 0x0000FFF0 265 #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ 266 267 /* 268 * Driver state logic for the detection of a hung state 269 * in hardware. Set TX_HUNG whenever a TX packet is used 270 * (data is sent) and clear it when txeof() is invoked if 271 * any descriptors from the ring are cleaned/reclaimed. 272 * Increment internal counter if no descriptors are cleaned 273 * and compare to TX_MAXTRIES. When counter > TX_MAXTRIES, 274 * reset adapter. 275 */ 276 #define EM_TX_IDLE 0x00000000 277 #define EM_TX_BUSY 0x00000001 278 #define EM_TX_HUNG 0x80000000 279 #define EM_TX_MAXTRIES 10 280 281 #define PCICFG_DESC_RING_STATUS 0xe4 282 #define FLUSH_DESC_REQUIRED 0x100 283 284 285 #define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : \ 286 ((hw->mac.type <= e1000_82576) ? 16 : 8)) 287 #define IGB_RX_HTHRESH 8 288 #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ 289 (sc->intr_type == IFLIB_INTR_MSIX)) ? 1 : 4) 290 291 #define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) 292 #define IGB_TX_HTHRESH 1 293 #define IGB_TX_WTHRESH ((hw->mac.type != e1000_82575 && \ 294 sc->intr_type == IFLIB_INTR_MSIX) ? 1 : 16) 295 296 /* 297 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 298 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 299 * also optimize cache line size effect. H/W supports up to cache line size 128. 300 */ 301 #define EM_DBA_ALIGN 128 302 303 /* 304 * See Intel 82574 Driver Programming Interface Manual, Section 10.2.6.9 305 */ 306 #define TARC_COMPENSATION_MODE (1 << 7) /* Compensation Mode */ 307 #define TARC_SPEED_MODE_BIT (1 << 21) /* On PCI-E MACs only */ 308 #define TARC_MQ_FIX (1 << 23) | \ 309 (1 << 24) | \ 310 (1 << 25) /* Handle errata in MQ mode */ 311 #define TARC_ERRATA_BIT (1 << 26) /* Note from errata on 82574 */ 312 313 /* PCI Config defines */ 314 #define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 315 #define EM_BAR_TYPE_MASK 0x00000001 316 #define EM_BAR_TYPE_MMEM 0x00000000 317 #define EM_BAR_TYPE_IO 0x00000001 318 #define EM_BAR_TYPE_FLASH 0x0014 319 #define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 320 #define EM_BAR_MEM_TYPE_MASK 0x00000006 321 #define EM_BAR_MEM_TYPE_32BIT 0x00000000 322 #define EM_BAR_MEM_TYPE_64BIT 0x00000004 323 324 /* Defines for printing debug information */ 325 #define DEBUG_INIT 0 326 #define DEBUG_IOCTL 0 327 #define DEBUG_HW 0 328 329 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 330 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 331 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 332 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 333 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 334 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 335 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 336 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 337 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 338 339 #define EM_MAX_SCATTER 40 340 #define EM_VFTA_SIZE 128 341 #define EM_TSO_SIZE 65535 342 #define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ 343 #define ETH_ZLEN 60 344 345 /* Offload bits in mbuf flag */ 346 #define EM_CSUM_OFFLOAD (CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | \ 347 CSUM_IP6_UDP | CSUM_IP6_TCP) 348 #define IGB_CSUM_OFFLOAD (CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | \ 349 CSUM_IP_SCTP | CSUM_IP6_UDP | CSUM_IP6_TCP | \ 350 CSUM_IP6_SCTP) 351 352 #define IGB_PKTTYPE_MASK 0x0000FFF0 353 #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ 354 355 /* 356 * 82574 has a nonstandard address for EIAC 357 * and since its only used in MSI-X, and in 358 * the em driver only 82574 uses MSI-X we can 359 * solve it just using this define. 360 */ 361 #define EM_EIAC 0x000DC 362 /* 363 * 82574 only reports 3 MSI-X vectors by default; 364 * defines assisting with making it report 5 are 365 * located here. 366 */ 367 #define EM_NVM_PCIE_CTRL 0x1B 368 #define EM_NVM_MSIX_N_MASK (0x7 << EM_NVM_MSIX_N_SHIFT) 369 #define EM_NVM_MSIX_N_SHIFT 7 370 371 /* 372 * VFs use 32-bit counter that rolls over. 373 */ 374 #define UPDATE_VF_REG(reg, last, cur) \ 375 do { \ 376 u32 new = E1000_READ_REG(&sc->hw, reg); \ 377 if (new < last) \ 378 cur += 0x100000000LL; \ 379 last = new; \ 380 cur &= 0xFFFFFFFF00000000LL; \ 381 cur |= new; \ 382 } while (0) 383 384 struct e1000_softc; 385 386 struct em_int_delay_info { 387 struct e1000_softc *sc; /* Back-pointer to the sc struct */ 388 int offset; /* Register offset to read/write */ 389 int value; /* Current value in usecs */ 390 }; 391 392 /* 393 * The transmit ring, one per tx queue 394 */ 395 struct tx_ring { 396 struct e1000_softc *sc; 397 struct e1000_tx_desc *tx_base; 398 uint64_t tx_paddr; 399 qidx_t *tx_rsq; 400 bool tx_tso; /* last tx was tso */ 401 uint8_t me; 402 qidx_t tx_rs_cidx; 403 qidx_t tx_rs_pidx; 404 qidx_t tx_cidx_processed; 405 /* Interrupt resources */ 406 void *tag; 407 struct resource *res; 408 409 /* Soft stats */ 410 unsigned long tx_irq; 411 unsigned long tx_packets; 412 unsigned long tx_bytes; 413 414 /* Saved csum offloading context information */ 415 int csum_flags; 416 int csum_lhlen; 417 int csum_iphlen; 418 419 int csum_thlen; 420 int csum_mss; 421 int csum_pktlen; 422 423 uint32_t csum_txd_upper; 424 uint32_t csum_txd_lower; /* last field */ 425 }; 426 427 /* 428 * The Receive ring, one per rx queue 429 */ 430 struct rx_ring { 431 struct e1000_softc *sc; 432 struct em_rx_queue *que; 433 u32 me; 434 u32 payload; 435 union e1000_rx_desc_extended *rx_base; 436 uint64_t rx_paddr; 437 438 /* Interrupt resources */ 439 void *tag; 440 struct resource *res; 441 bool discard; 442 443 /* Soft stats */ 444 unsigned long rx_irq; 445 unsigned long rx_discarded; 446 unsigned long rx_packets; 447 unsigned long rx_bytes; 448 449 /* Next requested ITR latency */ 450 u8 rx_nextlatency; 451 }; 452 453 struct em_tx_queue { 454 struct e1000_softc *sc; 455 u32 msix; 456 u32 eims; /* This queue's EIMS bit */ 457 u32 me; 458 struct tx_ring txr; 459 }; 460 461 struct em_rx_queue { 462 struct e1000_softc *sc; 463 u32 me; 464 u32 msix; 465 u32 eims; 466 u32 itr_setting; 467 struct rx_ring rxr; 468 u64 irqs; 469 struct if_irq que_irq; 470 }; 471 472 /* Our softc structure */ 473 struct e1000_softc { 474 struct e1000_hw hw; 475 476 if_softc_ctx_t shared; 477 if_ctx_t ctx; 478 #define tx_num_queues shared->isc_ntxqsets 479 #define rx_num_queues shared->isc_nrxqsets 480 #define intr_type shared->isc_intr 481 /* FreeBSD operating-system-specific structures. */ 482 struct e1000_osdep osdep; 483 device_t dev; 484 struct cdev *led_dev; 485 486 struct em_tx_queue *tx_queues; 487 struct em_rx_queue *rx_queues; 488 struct if_irq irq; 489 490 struct resource *memory; 491 struct resource *flash; 492 struct resource *ioport; 493 494 struct resource *res; 495 void *tag; 496 u32 linkvec; 497 u32 ivars; 498 499 struct ifmedia *media; 500 int msix; 501 int if_flags; 502 int em_insert_vlan_header; 503 u32 ims; 504 bool in_detach; 505 506 u32 flags; 507 /* Task for FAST handling */ 508 struct grouptask link_task; 509 510 u16 num_vlans; 511 u32 txd_cmd; 512 513 u32 rx_mbuf_sz; 514 515 int enable_aim; 516 /* Management and WOL features */ 517 u32 wol; 518 bool has_manage; 519 bool has_amt; 520 521 /* Multicast array memory */ 522 u8 *mta; 523 524 /* 525 ** Shadow VFTA table, this is needed because 526 ** the real vlan filter table gets cleared during 527 ** a soft reset and the driver needs to be able 528 ** to repopulate it. 529 */ 530 u32 shadow_vfta[EM_VFTA_SIZE]; 531 532 /* Info about the interface */ 533 u16 link_active; 534 u16 fc; 535 u16 link_speed; 536 u16 link_duplex; 537 u32 smartspeed; 538 u32 dmac; 539 u32 pba; 540 int link_mask; 541 int tso_automasked; 542 543 u64 que_mask; 544 545 /* We need to store this at attach due to e1000 hw/sw locking model */ 546 struct e1000_fw_version fw_ver; 547 548 struct em_int_delay_info tx_int_delay; 549 struct em_int_delay_info tx_abs_int_delay; 550 struct em_int_delay_info rx_int_delay; 551 struct em_int_delay_info rx_abs_int_delay; 552 struct em_int_delay_info tx_itr; 553 554 /* Misc stats maintained by the driver */ 555 unsigned long dropped_pkts; 556 unsigned long link_irq; 557 unsigned long rx_overruns; 558 unsigned long watchdog_events; 559 560 union { 561 struct e1000_hw_stats stats; /* !sc->vf_ifp */ 562 struct e1000_vf_stats vf_stats; /* sc->vf_ifp */ 563 } ustats; 564 565 u16 vf_ifp; 566 }; 567 568 /******************************************************************************** 569 * vendor_info_array 570 * 571 * This array contains the list of Subvendor/Subdevice IDs on which the driver 572 * should load. 573 * 574 ********************************************************************************/ 575 typedef struct _em_vendor_info_t { 576 unsigned int vendor_id; 577 unsigned int device_id; 578 unsigned int subvendor_id; 579 unsigned int subdevice_id; 580 unsigned int index; 581 } em_vendor_info_t; 582 583 void em_dump_rs(struct e1000_softc *); 584 585 #define EM_RSSRK_SIZE 4 586 #define EM_RSSRK_VAL(key, i) (key[(i) * EM_RSSRK_SIZE] | \ 587 key[(i) * EM_RSSRK_SIZE + 1] << 8 | \ 588 key[(i) * EM_RSSRK_SIZE + 2] << 16 | \ 589 key[(i) * EM_RSSRK_SIZE + 3] << 24) 590 #endif /* _EM_H_DEFINED_ */ 591