xref: /freebsd/sys/arm/allwinner/if_awg.c (revision 62e8ccc3a489434af379c7f47da71545bc1e14ee)
1 /*-
2  * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
20  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
21  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  */
25 
26 /*
27  * Allwinner Gigabit Ethernet MAC (EMAC) controller
28  */
29 
30 #include "opt_device_polling.h"
31 
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/rman.h>
36 #include <sys/kernel.h>
37 #include <sys/endian.h>
38 #include <sys/mbuf.h>
39 #include <sys/socket.h>
40 #include <sys/sockio.h>
41 #include <sys/module.h>
42 #include <sys/gpio.h>
43 
44 #include <net/bpf.h>
45 #include <net/if.h>
46 #include <net/ethernet.h>
47 #include <net/if_dl.h>
48 #include <net/if_media.h>
49 #include <net/if_types.h>
50 #include <net/if_var.h>
51 
52 #include <machine/bus.h>
53 
54 #include <dev/ofw/ofw_bus.h>
55 #include <dev/ofw/ofw_bus_subr.h>
56 
57 #include <arm/allwinner/if_awgreg.h>
58 #include <arm/allwinner/aw_sid.h>
59 #include <dev/mii/mii.h>
60 #include <dev/mii/miivar.h>
61 
62 #include <dev/clk/clk.h>
63 #include <dev/hwreset/hwreset.h>
64 #include <dev/regulator/regulator.h>
65 #include <dev/syscon/syscon.h>
66 
67 #include "syscon_if.h"
68 #include "miibus_if.h"
69 #include "gpio_if.h"
70 
71 #define	RD4(sc, reg)		bus_read_4((sc)->res[_RES_EMAC], (reg))
72 #define	WR4(sc, reg, val)	bus_write_4((sc)->res[_RES_EMAC], (reg), (val))
73 
74 #define	AWG_LOCK(sc)		mtx_lock(&(sc)->mtx)
75 #define	AWG_UNLOCK(sc)		mtx_unlock(&(sc)->mtx);
76 #define	AWG_ASSERT_LOCKED(sc)	mtx_assert(&(sc)->mtx, MA_OWNED)
77 #define	AWG_ASSERT_UNLOCKED(sc)	mtx_assert(&(sc)->mtx, MA_NOTOWNED)
78 
79 #define	DESC_ALIGN		4
80 #define	TX_DESC_COUNT		1024
81 #define	TX_DESC_SIZE		(sizeof(struct emac_desc) * TX_DESC_COUNT)
82 #define	RX_DESC_COUNT		256
83 #define	RX_DESC_SIZE		(sizeof(struct emac_desc) * RX_DESC_COUNT)
84 
85 #define	DESC_OFF(n)		((n) * sizeof(struct emac_desc))
86 #define	TX_NEXT(n)		(((n) + 1) & (TX_DESC_COUNT - 1))
87 #define	TX_SKIP(n, o)		(((n) + (o)) & (TX_DESC_COUNT - 1))
88 #define	RX_NEXT(n)		(((n) + 1) & (RX_DESC_COUNT - 1))
89 
90 #define	TX_MAX_SEGS		20
91 
92 #define	SOFT_RST_RETRY		1000
93 #define	MII_BUSY_RETRY		1000
94 #define	MDIO_FREQ		2500000
95 
96 #define	BURST_LEN_DEFAULT	8
97 #define	RX_TX_PRI_DEFAULT	0
98 #define	PAUSE_TIME_DEFAULT	0x400
99 #define	TX_INTERVAL_DEFAULT	64
100 #define	RX_BATCH_DEFAULT	64
101 
102 /* syscon EMAC clock register */
103 #define	EMAC_CLK_REG		0x30
104 #define	EMAC_CLK_EPHY_ADDR	(0x1f << 20)	/* H3 */
105 #define	EMAC_CLK_EPHY_ADDR_SHIFT 20
106 #define	EMAC_CLK_EPHY_LED_POL	(1 << 17)	/* H3 */
107 #define	EMAC_CLK_EPHY_SHUTDOWN	(1 << 16)	/* H3 */
108 #define	EMAC_CLK_EPHY_SELECT	(1 << 15)	/* H3 */
109 #define	EMAC_CLK_RMII_EN	(1 << 13)
110 #define	EMAC_CLK_ETXDC		(0x7 << 10)
111 #define	EMAC_CLK_ETXDC_SHIFT	10
112 #define	EMAC_CLK_ERXDC		(0x1f << 5)
113 #define	EMAC_CLK_ERXDC_SHIFT	5
114 #define	EMAC_CLK_PIT		(0x1 << 2)
115 #define	 EMAC_CLK_PIT_MII	(0 << 2)
116 #define	 EMAC_CLK_PIT_RGMII	(1 << 2)
117 #define	EMAC_CLK_SRC		(0x3 << 0)
118 #define	 EMAC_CLK_SRC_MII	(0 << 0)
119 #define	 EMAC_CLK_SRC_EXT_RGMII	(1 << 0)
120 #define	 EMAC_CLK_SRC_RGMII	(2 << 0)
121 
122 /* Burst length of RX and TX DMA transfers */
123 static int awg_burst_len = BURST_LEN_DEFAULT;
124 TUNABLE_INT("hw.awg.burst_len", &awg_burst_len);
125 
126 /* RX / TX DMA priority. If 1, RX DMA has priority over TX DMA. */
127 static int awg_rx_tx_pri = RX_TX_PRI_DEFAULT;
128 TUNABLE_INT("hw.awg.rx_tx_pri", &awg_rx_tx_pri);
129 
130 /* Pause time field in the transmitted control frame */
131 static int awg_pause_time = PAUSE_TIME_DEFAULT;
132 TUNABLE_INT("hw.awg.pause_time", &awg_pause_time);
133 
134 /* Request a TX interrupt every <n> descriptors */
135 static int awg_tx_interval = TX_INTERVAL_DEFAULT;
136 TUNABLE_INT("hw.awg.tx_interval", &awg_tx_interval);
137 
138 /* Maximum number of mbufs to send to if_input */
139 static int awg_rx_batch = RX_BATCH_DEFAULT;
140 TUNABLE_INT("hw.awg.rx_batch", &awg_rx_batch);
141 
142 enum awg_type {
143 	EMAC_A83T = 1,
144 	EMAC_H3,
145 	EMAC_A64,
146 };
147 
148 static struct ofw_compat_data compat_data[] = {
149 	{ "allwinner,sun8i-a83t-emac",		EMAC_A83T },
150 	{ "allwinner,sun8i-h3-emac",		EMAC_H3 },
151 	{ "allwinner,sun50i-a64-emac",		EMAC_A64 },
152 	{ NULL,					0 }
153 };
154 
155 struct awg_bufmap {
156 	bus_dmamap_t		map;
157 	struct mbuf		*mbuf;
158 };
159 
160 struct awg_txring {
161 	bus_dma_tag_t		desc_tag;
162 	bus_dmamap_t		desc_map;
163 	struct emac_desc	*desc_ring;
164 	bus_addr_t		desc_ring_paddr;
165 	bus_dma_tag_t		buf_tag;
166 	struct awg_bufmap	buf_map[TX_DESC_COUNT];
167 	u_int			cur, next, queued;
168 	u_int			segs;
169 };
170 
171 struct awg_rxring {
172 	bus_dma_tag_t		desc_tag;
173 	bus_dmamap_t		desc_map;
174 	struct emac_desc	*desc_ring;
175 	bus_addr_t		desc_ring_paddr;
176 	bus_dma_tag_t		buf_tag;
177 	struct awg_bufmap	buf_map[RX_DESC_COUNT];
178 	bus_dmamap_t		buf_spare_map;
179 	u_int			cur;
180 };
181 
182 enum {
183 	_RES_EMAC,
184 	_RES_IRQ,
185 	_RES_SYSCON,
186 	_RES_NITEMS
187 };
188 
189 struct awg_softc {
190 	struct resource		*res[_RES_NITEMS];
191 	struct mtx		mtx;
192 	if_t			ifp;
193 	device_t		dev;
194 	device_t		miibus;
195 	struct callout		stat_ch;
196 	void			*ih;
197 	u_int			mdc_div_ratio_m;
198 	int			link;
199 	int			if_flags;
200 	enum awg_type		type;
201 	struct syscon		*syscon;
202 
203 	struct awg_txring	tx;
204 	struct awg_rxring	rx;
205 };
206 
207 static struct resource_spec awg_spec[] = {
208 	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
209 	{ SYS_RES_IRQ,		0,	RF_ACTIVE },
210 	{ SYS_RES_MEMORY,	1,	RF_ACTIVE | RF_OPTIONAL },
211 	{ -1, 0 }
212 };
213 
214 static void awg_txeof(struct awg_softc *sc);
215 static void awg_start_locked(struct awg_softc *sc);
216 
217 static void awg_tick(void *softc);
218 
219 static int awg_parse_delay(device_t dev, uint32_t *tx_delay,
220     uint32_t *rx_delay);
221 static uint32_t syscon_read_emac_clk_reg(device_t dev);
222 static void syscon_write_emac_clk_reg(device_t dev, uint32_t val);
223 static phandle_t awg_get_phy_node(device_t dev);
224 static bool awg_has_internal_phy(device_t dev);
225 
226 /*
227  * MII functions
228  */
229 
230 static int
awg_miibus_readreg(device_t dev,int phy,int reg)231 awg_miibus_readreg(device_t dev, int phy, int reg)
232 {
233 	struct awg_softc *sc;
234 	int retry, val;
235 
236 	sc = device_get_softc(dev);
237 	val = 0;
238 
239 	WR4(sc, EMAC_MII_CMD,
240 	    (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) |
241 	    (phy << PHY_ADDR_SHIFT) |
242 	    (reg << PHY_REG_ADDR_SHIFT) |
243 	    MII_BUSY);
244 	for (retry = MII_BUSY_RETRY; retry > 0; retry--) {
245 		if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) {
246 			val = RD4(sc, EMAC_MII_DATA);
247 			break;
248 		}
249 		DELAY(10);
250 	}
251 
252 	if (retry == 0)
253 		device_printf(dev, "phy read timeout, phy=%d reg=%d\n",
254 		    phy, reg);
255 
256 	return (val);
257 }
258 
259 static int
awg_miibus_writereg(device_t dev,int phy,int reg,int val)260 awg_miibus_writereg(device_t dev, int phy, int reg, int val)
261 {
262 	struct awg_softc *sc;
263 	int retry;
264 
265 	sc = device_get_softc(dev);
266 
267 	WR4(sc, EMAC_MII_DATA, val);
268 	WR4(sc, EMAC_MII_CMD,
269 	    (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) |
270 	    (phy << PHY_ADDR_SHIFT) |
271 	    (reg << PHY_REG_ADDR_SHIFT) |
272 	    MII_WR | MII_BUSY);
273 	for (retry = MII_BUSY_RETRY; retry > 0; retry--) {
274 		if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0)
275 			break;
276 		DELAY(10);
277 	}
278 
279 	if (retry == 0)
280 		device_printf(dev, "phy write timeout, phy=%d reg=%d\n",
281 		    phy, reg);
282 
283 	return (0);
284 }
285 
286 static void
awg_miibus_statchg(device_t dev)287 awg_miibus_statchg(device_t dev)
288 {
289 	struct awg_softc *sc;
290 	struct mii_data *mii;
291 	uint32_t val;
292 
293 	sc = device_get_softc(dev);
294 
295 	AWG_ASSERT_LOCKED(sc);
296 
297 	if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) == 0)
298 		return;
299 	mii = device_get_softc(sc->miibus);
300 
301 	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
302 	    (IFM_ACTIVE | IFM_AVALID)) {
303 		switch (IFM_SUBTYPE(mii->mii_media_active)) {
304 		case IFM_1000_T:
305 		case IFM_1000_SX:
306 		case IFM_100_TX:
307 		case IFM_10_T:
308 			sc->link = 1;
309 			break;
310 		default:
311 			sc->link = 0;
312 			break;
313 		}
314 	} else
315 		sc->link = 0;
316 
317 	if (sc->link == 0)
318 		return;
319 
320 	val = RD4(sc, EMAC_BASIC_CTL_0);
321 	val &= ~(BASIC_CTL_SPEED | BASIC_CTL_DUPLEX);
322 
323 	if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
324 	    IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
325 		val |= BASIC_CTL_SPEED_1000 << BASIC_CTL_SPEED_SHIFT;
326 	else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX)
327 		val |= BASIC_CTL_SPEED_100 << BASIC_CTL_SPEED_SHIFT;
328 	else
329 		val |= BASIC_CTL_SPEED_10 << BASIC_CTL_SPEED_SHIFT;
330 
331 	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
332 		val |= BASIC_CTL_DUPLEX;
333 
334 	WR4(sc, EMAC_BASIC_CTL_0, val);
335 
336 	val = RD4(sc, EMAC_RX_CTL_0);
337 	val &= ~RX_FLOW_CTL_EN;
338 	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
339 		val |= RX_FLOW_CTL_EN;
340 	WR4(sc, EMAC_RX_CTL_0, val);
341 
342 	val = RD4(sc, EMAC_TX_FLOW_CTL);
343 	val &= ~(PAUSE_TIME|TX_FLOW_CTL_EN);
344 	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
345 		val |= TX_FLOW_CTL_EN;
346 	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
347 		val |= awg_pause_time << PAUSE_TIME_SHIFT;
348 	WR4(sc, EMAC_TX_FLOW_CTL, val);
349 }
350 
351 /*
352  * Media functions
353  */
354 
355 static void
awg_media_status(if_t ifp,struct ifmediareq * ifmr)356 awg_media_status(if_t ifp, struct ifmediareq *ifmr)
357 {
358 	struct awg_softc *sc;
359 	struct mii_data *mii;
360 
361 	sc = if_getsoftc(ifp);
362 	mii = device_get_softc(sc->miibus);
363 
364 	AWG_LOCK(sc);
365 	mii_pollstat(mii);
366 	ifmr->ifm_active = mii->mii_media_active;
367 	ifmr->ifm_status = mii->mii_media_status;
368 	AWG_UNLOCK(sc);
369 }
370 
371 static int
awg_media_change(if_t ifp)372 awg_media_change(if_t ifp)
373 {
374 	struct awg_softc *sc;
375 	struct mii_data *mii;
376 	int error;
377 
378 	sc = if_getsoftc(ifp);
379 	mii = device_get_softc(sc->miibus);
380 
381 	AWG_LOCK(sc);
382 	error = mii_mediachg(mii);
383 	AWG_UNLOCK(sc);
384 
385 	return (error);
386 }
387 
388 /*
389  * Core functions
390  */
391 
392 /* Bit Reversal - http://aggregate.org/MAGIC/#Bit%20Reversal */
393 static uint32_t
bitrev32(uint32_t x)394 bitrev32(uint32_t x)
395 {
396 	x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1));
397 	x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2));
398 	x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4));
399 	x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8));
400 
401 	return (x >> 16) | (x << 16);
402 }
403 
404 static u_int
awg_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)405 awg_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
406 {
407 	uint32_t crc, hashreg, hashbit, *hash = arg;
408 
409 	crc = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN) & 0x7f;
410 	crc = bitrev32(~crc) >> 26;
411 	hashreg = (crc >> 5);
412 	hashbit = (crc & 0x1f);
413 	hash[hashreg] |= (1 << hashbit);
414 
415 	return (1);
416 }
417 
418 static void
awg_setup_rxfilter(struct awg_softc * sc)419 awg_setup_rxfilter(struct awg_softc *sc)
420 {
421 	uint32_t val, hash[2], machi, maclo;
422 	uint8_t *eaddr;
423 	if_t ifp;
424 
425 	AWG_ASSERT_LOCKED(sc);
426 
427 	ifp = sc->ifp;
428 	val = 0;
429 	hash[0] = hash[1] = 0;
430 
431 	if (if_getflags(ifp) & IFF_PROMISC)
432 		val |= DIS_ADDR_FILTER;
433 	else if (if_getflags(ifp) & IFF_ALLMULTI) {
434 		val |= RX_ALL_MULTICAST;
435 		hash[0] = hash[1] = ~0;
436 	} else if (if_foreach_llmaddr(ifp, awg_hash_maddr, hash) > 0)
437 		val |= HASH_MULTICAST;
438 
439 	/* Write our unicast address */
440 	eaddr = if_getlladdr(ifp);
441 	machi = (eaddr[5] << 8) | eaddr[4];
442 	maclo = (eaddr[3] << 24) | (eaddr[2] << 16) | (eaddr[1] << 8) |
443 	   (eaddr[0] << 0);
444 	WR4(sc, EMAC_ADDR_HIGH(0), machi);
445 	WR4(sc, EMAC_ADDR_LOW(0), maclo);
446 
447 	/* Multicast hash filters */
448 	WR4(sc, EMAC_RX_HASH_0, hash[1]);
449 	WR4(sc, EMAC_RX_HASH_1, hash[0]);
450 
451 	/* RX frame filter config */
452 	WR4(sc, EMAC_RX_FRM_FLT, val);
453 }
454 
455 static void
awg_setup_core(struct awg_softc * sc)456 awg_setup_core(struct awg_softc *sc)
457 {
458 	uint32_t val;
459 
460 	AWG_ASSERT_LOCKED(sc);
461 	/* Configure DMA burst length and priorities */
462 	val = awg_burst_len << BASIC_CTL_BURST_LEN_SHIFT;
463 	if (awg_rx_tx_pri)
464 		val |= BASIC_CTL_RX_TX_PRI;
465 	WR4(sc, EMAC_BASIC_CTL_1, val);
466 
467 }
468 
469 static void
awg_enable_mac(struct awg_softc * sc,bool enable)470 awg_enable_mac(struct awg_softc *sc, bool enable)
471 {
472 	uint32_t tx, rx;
473 
474 	AWG_ASSERT_LOCKED(sc);
475 
476 	tx = RD4(sc, EMAC_TX_CTL_0);
477 	rx = RD4(sc, EMAC_RX_CTL_0);
478 	if (enable) {
479 		tx |= TX_EN;
480 		rx |= RX_EN | CHECK_CRC;
481 	} else {
482 		tx &= ~TX_EN;
483 		rx &= ~(RX_EN | CHECK_CRC);
484 	}
485 
486 	WR4(sc, EMAC_TX_CTL_0, tx);
487 	WR4(sc, EMAC_RX_CTL_0, rx);
488 }
489 
490 static void
awg_get_eaddr(device_t dev,uint8_t * eaddr)491 awg_get_eaddr(device_t dev, uint8_t *eaddr)
492 {
493 	struct awg_softc *sc;
494 	uint32_t maclo, machi, rnd;
495 	u_char rootkey[16];
496 	uint32_t rootkey_size;
497 
498 	sc = device_get_softc(dev);
499 
500 	machi = RD4(sc, EMAC_ADDR_HIGH(0)) & 0xffff;
501 	maclo = RD4(sc, EMAC_ADDR_LOW(0));
502 
503 	rootkey_size = sizeof(rootkey);
504 	if (maclo == 0xffffffff && machi == 0xffff) {
505 		/* MAC address in hardware is invalid, create one */
506 		if (aw_sid_get_fuse(AW_SID_FUSE_ROOTKEY, rootkey,
507 		    &rootkey_size) == 0 &&
508 		    (rootkey[3] | rootkey[12] | rootkey[13] | rootkey[14] |
509 		     rootkey[15]) != 0) {
510 			/* MAC address is derived from the root key in SID */
511 			maclo = (rootkey[13] << 24) | (rootkey[12] << 16) |
512 				(rootkey[3] << 8) | 0x02;
513 			machi = (rootkey[15] << 8) | rootkey[14];
514 		} else {
515 			/* Create one */
516 			rnd = arc4random();
517 			maclo = 0x00f2 | (rnd & 0xffff0000);
518 			machi = rnd & 0xffff;
519 		}
520 	}
521 
522 	eaddr[0] = maclo & 0xff;
523 	eaddr[1] = (maclo >> 8) & 0xff;
524 	eaddr[2] = (maclo >> 16) & 0xff;
525 	eaddr[3] = (maclo >> 24) & 0xff;
526 	eaddr[4] = machi & 0xff;
527 	eaddr[5] = (machi >> 8) & 0xff;
528 }
529 
530 /*
531  * DMA functions
532  */
533 
534 static void
awg_enable_dma_intr(struct awg_softc * sc)535 awg_enable_dma_intr(struct awg_softc *sc)
536 {
537 	/* Enable interrupts */
538 	WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN);
539 }
540 
541 static void
awg_disable_dma_intr(struct awg_softc * sc)542 awg_disable_dma_intr(struct awg_softc *sc)
543 {
544 	/* Disable interrupts */
545 	WR4(sc, EMAC_INT_EN, 0);
546 }
547 
548 static void
awg_init_dma(struct awg_softc * sc)549 awg_init_dma(struct awg_softc *sc)
550 {
551 	uint32_t val;
552 
553 	AWG_ASSERT_LOCKED(sc);
554 
555 	/* Enable interrupts */
556 #ifdef DEVICE_POLLING
557 	if ((if_getcapenable(sc->ifp) & IFCAP_POLLING) == 0)
558 		awg_enable_dma_intr(sc);
559 	else
560 		awg_disable_dma_intr(sc);
561 #else
562 	awg_enable_dma_intr(sc);
563 #endif
564 
565 	/* Enable transmit DMA */
566 	val = RD4(sc, EMAC_TX_CTL_1);
567 	WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD | TX_NEXT_FRAME);
568 
569 	/* Enable receive DMA */
570 	val = RD4(sc, EMAC_RX_CTL_1);
571 	WR4(sc, EMAC_RX_CTL_1, val | RX_DMA_EN | RX_MD);
572 }
573 
574 static void
awg_stop_dma(struct awg_softc * sc)575 awg_stop_dma(struct awg_softc *sc)
576 {
577 	uint32_t val;
578 
579 	AWG_ASSERT_LOCKED(sc);
580 
581 	/* Stop transmit DMA and flush data in the TX FIFO */
582 	val = RD4(sc, EMAC_TX_CTL_1);
583 	val &= ~TX_DMA_EN;
584 	val |= FLUSH_TX_FIFO;
585 	WR4(sc, EMAC_TX_CTL_1, val);
586 
587 	/* Disable interrupts */
588 	awg_disable_dma_intr(sc);
589 
590 	/* Disable transmit DMA */
591 	val = RD4(sc, EMAC_TX_CTL_1);
592 	WR4(sc, EMAC_TX_CTL_1, val & ~TX_DMA_EN);
593 
594 	/* Disable receive DMA */
595 	val = RD4(sc, EMAC_RX_CTL_1);
596 	WR4(sc, EMAC_RX_CTL_1, val & ~RX_DMA_EN);
597 }
598 
599 static int
awg_encap(struct awg_softc * sc,struct mbuf ** mp)600 awg_encap(struct awg_softc *sc, struct mbuf **mp)
601 {
602 	bus_dmamap_t map;
603 	bus_dma_segment_t segs[TX_MAX_SEGS];
604 	int error, nsegs, cur, first, last, i;
605 	u_int csum_flags;
606 	uint32_t flags, status;
607 	struct mbuf *m;
608 
609 	cur = first = sc->tx.cur;
610 	map = sc->tx.buf_map[first].map;
611 
612 	m = *mp;
613 	error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, map, m, segs,
614 	    &nsegs, BUS_DMA_NOWAIT);
615 	if (error == EFBIG) {
616 		m = m_collapse(m, M_NOWAIT, TX_MAX_SEGS);
617 		if (m == NULL) {
618 			device_printf(sc->dev, "awg_encap: m_collapse failed\n");
619 			m_freem(*mp);
620 			*mp = NULL;
621 			return (ENOMEM);
622 		}
623 		*mp = m;
624 		error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, map, m,
625 		    segs, &nsegs, BUS_DMA_NOWAIT);
626 		if (error != 0) {
627 			m_freem(*mp);
628 			*mp = NULL;
629 		}
630 	}
631 	if (error != 0) {
632 		device_printf(sc->dev, "awg_encap: bus_dmamap_load_mbuf_sg failed\n");
633 		return (error);
634 	}
635 	if (nsegs == 0) {
636 		m_freem(*mp);
637 		*mp = NULL;
638 		return (EIO);
639 	}
640 
641 	if (sc->tx.queued + nsegs > TX_DESC_COUNT) {
642 		bus_dmamap_unload(sc->tx.buf_tag, map);
643 		return (ENOBUFS);
644 	}
645 
646 	bus_dmamap_sync(sc->tx.buf_tag, map, BUS_DMASYNC_PREWRITE);
647 
648 	flags = TX_FIR_DESC;
649 	status = 0;
650 	if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) {
651 		if ((m->m_pkthdr.csum_flags & (CSUM_TCP|CSUM_UDP)) != 0)
652 			csum_flags = TX_CHECKSUM_CTL_FULL;
653 		else
654 			csum_flags = TX_CHECKSUM_CTL_IP;
655 		flags |= (csum_flags << TX_CHECKSUM_CTL_SHIFT);
656 	}
657 
658 	for (i = 0; i < nsegs; i++) {
659 		sc->tx.segs++;
660 		if (i == nsegs - 1) {
661 			flags |= TX_LAST_DESC;
662 			/*
663 			 * Can only request TX completion
664 			 * interrupt on last descriptor.
665 			 */
666 			if (sc->tx.segs >= awg_tx_interval) {
667 				sc->tx.segs = 0;
668 				flags |= TX_INT_CTL;
669 			}
670 		}
671 
672 		sc->tx.desc_ring[cur].addr = htole32((uint32_t)segs[i].ds_addr);
673 		sc->tx.desc_ring[cur].size = htole32(flags | segs[i].ds_len);
674 		sc->tx.desc_ring[cur].status = htole32(status);
675 
676 		flags &= ~TX_FIR_DESC;
677 		/*
678 		 * Setting of the valid bit in the first descriptor is
679 		 * deferred until the whole chain is fully set up.
680 		 */
681 		status = TX_DESC_CTL;
682 
683 		++sc->tx.queued;
684 		cur = TX_NEXT(cur);
685 	}
686 
687 	sc->tx.cur = cur;
688 
689 	/* Store mapping and mbuf in the last segment */
690 	last = TX_SKIP(cur, TX_DESC_COUNT - 1);
691 	sc->tx.buf_map[first].map = sc->tx.buf_map[last].map;
692 	sc->tx.buf_map[last].map = map;
693 	sc->tx.buf_map[last].mbuf = m;
694 
695 	/*
696 	 * The whole mbuf chain has been DMA mapped,
697 	 * fix the first descriptor.
698 	 */
699 	sc->tx.desc_ring[first].status = htole32(TX_DESC_CTL);
700 
701 	return (0);
702 }
703 
704 static void
awg_clean_txbuf(struct awg_softc * sc,int index)705 awg_clean_txbuf(struct awg_softc *sc, int index)
706 {
707 	struct awg_bufmap *bmap;
708 
709 	--sc->tx.queued;
710 
711 	bmap = &sc->tx.buf_map[index];
712 	if (bmap->mbuf != NULL) {
713 		bus_dmamap_sync(sc->tx.buf_tag, bmap->map,
714 		    BUS_DMASYNC_POSTWRITE);
715 		bus_dmamap_unload(sc->tx.buf_tag, bmap->map);
716 		m_freem(bmap->mbuf);
717 		bmap->mbuf = NULL;
718 	}
719 }
720 
721 static void
awg_setup_rxdesc(struct awg_softc * sc,int index,bus_addr_t paddr)722 awg_setup_rxdesc(struct awg_softc *sc, int index, bus_addr_t paddr)
723 {
724 	uint32_t status, size;
725 
726 	status = RX_DESC_CTL;
727 	size = MCLBYTES - 1;
728 
729 	sc->rx.desc_ring[index].addr = htole32((uint32_t)paddr);
730 	sc->rx.desc_ring[index].size = htole32(size);
731 	sc->rx.desc_ring[index].status = htole32(status);
732 }
733 
734 static void
awg_reuse_rxdesc(struct awg_softc * sc,int index)735 awg_reuse_rxdesc(struct awg_softc *sc, int index)
736 {
737 
738 	sc->rx.desc_ring[index].status = htole32(RX_DESC_CTL);
739 }
740 
741 static int
awg_newbuf_rx(struct awg_softc * sc,int index)742 awg_newbuf_rx(struct awg_softc *sc, int index)
743 {
744 	struct mbuf *m;
745 	bus_dma_segment_t seg;
746 	bus_dmamap_t map;
747 	int nsegs;
748 
749 	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
750 	if (m == NULL)
751 		return (ENOBUFS);
752 
753 	m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
754 	m_adj(m, ETHER_ALIGN);
755 
756 	if (bus_dmamap_load_mbuf_sg(sc->rx.buf_tag, sc->rx.buf_spare_map,
757 	    m, &seg, &nsegs, BUS_DMA_NOWAIT) != 0) {
758 		m_freem(m);
759 		return (ENOBUFS);
760 	}
761 
762 	if (sc->rx.buf_map[index].mbuf != NULL) {
763 		bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map,
764 		    BUS_DMASYNC_POSTREAD);
765 		bus_dmamap_unload(sc->rx.buf_tag, sc->rx.buf_map[index].map);
766 	}
767 	map = sc->rx.buf_map[index].map;
768 	sc->rx.buf_map[index].map = sc->rx.buf_spare_map;
769 	sc->rx.buf_spare_map = map;
770 	bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map,
771 	    BUS_DMASYNC_PREREAD);
772 
773 	sc->rx.buf_map[index].mbuf = m;
774 	awg_setup_rxdesc(sc, index, seg.ds_addr);
775 
776 	return (0);
777 }
778 
779 static void
awg_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nseg,int error)780 awg_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
781 {
782 	if (error != 0)
783 		return;
784 	*(bus_addr_t *)arg = segs[0].ds_addr;
785 }
786 
787 static int
awg_setup_dma(device_t dev)788 awg_setup_dma(device_t dev)
789 {
790 	struct awg_softc *sc;
791 	int error, i;
792 
793 	sc = device_get_softc(dev);
794 
795 	/* Setup TX ring */
796 	error = bus_dma_tag_create(
797 	    bus_get_dma_tag(dev),	/* Parent tag */
798 	    DESC_ALIGN, 0,		/* alignment, boundary */
799 	    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
800 	    BUS_SPACE_MAXADDR,		/* highaddr */
801 	    NULL, NULL,			/* filter, filterarg */
802 	    TX_DESC_SIZE, 1,		/* maxsize, nsegs */
803 	    TX_DESC_SIZE,		/* maxsegsize */
804 	    0,				/* flags */
805 	    NULL, NULL,			/* lockfunc, lockarg */
806 	    &sc->tx.desc_tag);
807 	if (error != 0) {
808 		device_printf(dev, "cannot create TX descriptor ring tag\n");
809 		return (error);
810 	}
811 
812 	error = bus_dmamem_alloc(sc->tx.desc_tag, (void **)&sc->tx.desc_ring,
813 	    BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->tx.desc_map);
814 	if (error != 0) {
815 		device_printf(dev, "cannot allocate TX descriptor ring\n");
816 		return (error);
817 	}
818 
819 	error = bus_dmamap_load(sc->tx.desc_tag, sc->tx.desc_map,
820 	    sc->tx.desc_ring, TX_DESC_SIZE, awg_dmamap_cb,
821 	    &sc->tx.desc_ring_paddr, 0);
822 	if (error != 0) {
823 		device_printf(dev, "cannot load TX descriptor ring\n");
824 		return (error);
825 	}
826 
827 	for (i = 0; i < TX_DESC_COUNT; i++)
828 		sc->tx.desc_ring[i].next =
829 		    htole32(sc->tx.desc_ring_paddr + DESC_OFF(TX_NEXT(i)));
830 
831 	error = bus_dma_tag_create(
832 	    bus_get_dma_tag(dev),	/* Parent tag */
833 	    1, 0,			/* alignment, boundary */
834 	    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
835 	    BUS_SPACE_MAXADDR,		/* highaddr */
836 	    NULL, NULL,			/* filter, filterarg */
837 	    MCLBYTES, TX_MAX_SEGS,	/* maxsize, nsegs */
838 	    MCLBYTES,			/* maxsegsize */
839 	    0,				/* flags */
840 	    NULL, NULL,			/* lockfunc, lockarg */
841 	    &sc->tx.buf_tag);
842 	if (error != 0) {
843 		device_printf(dev, "cannot create TX buffer tag\n");
844 		return (error);
845 	}
846 
847 	sc->tx.queued = 0;
848 	for (i = 0; i < TX_DESC_COUNT; i++) {
849 		error = bus_dmamap_create(sc->tx.buf_tag, 0,
850 		    &sc->tx.buf_map[i].map);
851 		if (error != 0) {
852 			device_printf(dev, "cannot create TX buffer map\n");
853 			return (error);
854 		}
855 	}
856 
857 	/* Setup RX ring */
858 	error = bus_dma_tag_create(
859 	    bus_get_dma_tag(dev),	/* Parent tag */
860 	    DESC_ALIGN, 0,		/* alignment, boundary */
861 	    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
862 	    BUS_SPACE_MAXADDR,		/* highaddr */
863 	    NULL, NULL,			/* filter, filterarg */
864 	    RX_DESC_SIZE, 1,		/* maxsize, nsegs */
865 	    RX_DESC_SIZE,		/* maxsegsize */
866 	    0,				/* flags */
867 	    NULL, NULL,			/* lockfunc, lockarg */
868 	    &sc->rx.desc_tag);
869 	if (error != 0) {
870 		device_printf(dev, "cannot create RX descriptor ring tag\n");
871 		return (error);
872 	}
873 
874 	error = bus_dmamem_alloc(sc->rx.desc_tag, (void **)&sc->rx.desc_ring,
875 	    BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rx.desc_map);
876 	if (error != 0) {
877 		device_printf(dev, "cannot allocate RX descriptor ring\n");
878 		return (error);
879 	}
880 
881 	error = bus_dmamap_load(sc->rx.desc_tag, sc->rx.desc_map,
882 	    sc->rx.desc_ring, RX_DESC_SIZE, awg_dmamap_cb,
883 	    &sc->rx.desc_ring_paddr, 0);
884 	if (error != 0) {
885 		device_printf(dev, "cannot load RX descriptor ring\n");
886 		return (error);
887 	}
888 
889 	error = bus_dma_tag_create(
890 	    bus_get_dma_tag(dev),	/* Parent tag */
891 	    1, 0,			/* alignment, boundary */
892 	    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
893 	    BUS_SPACE_MAXADDR,		/* highaddr */
894 	    NULL, NULL,			/* filter, filterarg */
895 	    MCLBYTES, 1,		/* maxsize, nsegs */
896 	    MCLBYTES,			/* maxsegsize */
897 	    0,				/* flags */
898 	    NULL, NULL,			/* lockfunc, lockarg */
899 	    &sc->rx.buf_tag);
900 	if (error != 0) {
901 		device_printf(dev, "cannot create RX buffer tag\n");
902 		return (error);
903 	}
904 
905 	error = bus_dmamap_create(sc->rx.buf_tag, 0, &sc->rx.buf_spare_map);
906 	if (error != 0) {
907 		device_printf(dev,
908 		    "cannot create RX buffer spare map\n");
909 		return (error);
910 	}
911 
912 	for (i = 0; i < RX_DESC_COUNT; i++) {
913 		sc->rx.desc_ring[i].next =
914 		    htole32(sc->rx.desc_ring_paddr + DESC_OFF(RX_NEXT(i)));
915 
916 		error = bus_dmamap_create(sc->rx.buf_tag, 0,
917 		    &sc->rx.buf_map[i].map);
918 		if (error != 0) {
919 			device_printf(dev, "cannot create RX buffer map\n");
920 			return (error);
921 		}
922 		sc->rx.buf_map[i].mbuf = NULL;
923 		error = awg_newbuf_rx(sc, i);
924 		if (error != 0) {
925 			device_printf(dev, "cannot create RX buffer\n");
926 			return (error);
927 		}
928 	}
929 	bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
930 	    BUS_DMASYNC_PREWRITE);
931 
932 	/* Write transmit and receive descriptor base address registers */
933 	WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr);
934 	WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr);
935 
936 	return (0);
937 }
938 
939 static void
awg_dma_start_tx(struct awg_softc * sc)940 awg_dma_start_tx(struct awg_softc *sc)
941 {
942 	uint32_t val;
943 
944 	AWG_ASSERT_LOCKED(sc);
945 
946 	/* Start and run TX DMA */
947 	val = RD4(sc, EMAC_TX_CTL_1);
948 	WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START);
949 }
950 
951 /*
952  * if_ functions
953  */
954 
955 static void
awg_start_locked(struct awg_softc * sc)956 awg_start_locked(struct awg_softc *sc)
957 {
958 	struct mbuf *m;
959 	if_t ifp;
960 	int cnt, err;
961 
962 	AWG_ASSERT_LOCKED(sc);
963 
964 	if (!sc->link)
965 		return;
966 
967 	ifp = sc->ifp;
968 
969 	if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) !=
970 	    IFF_DRV_RUNNING)
971 		return;
972 
973 	for (cnt = 0; ; cnt++) {
974 		m = if_dequeue(ifp);
975 		if (m == NULL)
976 			break;
977 
978 		err = awg_encap(sc, &m);
979 		if (err != 0) {
980 			if (err == ENOBUFS)
981 				if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
982 			if (m != NULL)
983 				if_sendq_prepend(ifp, m);
984 			break;
985 		}
986 		bpf_mtap_if(ifp, m);
987 	}
988 
989 	if (cnt != 0) {
990 		bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map,
991 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
992 
993 		awg_dma_start_tx(sc);
994 	}
995 }
996 
997 static void
awg_start(if_t ifp)998 awg_start(if_t ifp)
999 {
1000 	struct awg_softc *sc;
1001 
1002 	sc = if_getsoftc(ifp);
1003 
1004 	AWG_LOCK(sc);
1005 	awg_start_locked(sc);
1006 	AWG_UNLOCK(sc);
1007 }
1008 
1009 static void
awg_init_locked(struct awg_softc * sc)1010 awg_init_locked(struct awg_softc *sc)
1011 {
1012 	struct mii_data *mii;
1013 	if_t ifp;
1014 
1015 	mii = device_get_softc(sc->miibus);
1016 	ifp = sc->ifp;
1017 
1018 	AWG_ASSERT_LOCKED(sc);
1019 
1020 	if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1021 		return;
1022 
1023 	awg_setup_rxfilter(sc);
1024 	awg_setup_core(sc);
1025 	awg_enable_mac(sc, true);
1026 	awg_init_dma(sc);
1027 
1028 	if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
1029 
1030 	mii_mediachg(mii);
1031 	callout_reset(&sc->stat_ch, hz, awg_tick, sc);
1032 }
1033 
1034 static void
awg_init(void * softc)1035 awg_init(void *softc)
1036 {
1037 	struct awg_softc *sc;
1038 
1039 	sc = softc;
1040 
1041 	AWG_LOCK(sc);
1042 	awg_init_locked(sc);
1043 	AWG_UNLOCK(sc);
1044 }
1045 
1046 static void
awg_stop(struct awg_softc * sc)1047 awg_stop(struct awg_softc *sc)
1048 {
1049 	if_t ifp;
1050 	uint32_t val;
1051 	int i;
1052 
1053 	AWG_ASSERT_LOCKED(sc);
1054 
1055 	ifp = sc->ifp;
1056 
1057 	callout_stop(&sc->stat_ch);
1058 
1059 	awg_stop_dma(sc);
1060 	awg_enable_mac(sc, false);
1061 
1062 	sc->link = 0;
1063 
1064 	/* Finish handling transmitted buffers */
1065 	awg_txeof(sc);
1066 
1067 	/* Release any untransmitted buffers. */
1068 	for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) {
1069 		val = le32toh(sc->tx.desc_ring[i].status);
1070 		if ((val & TX_DESC_CTL) != 0)
1071 			break;
1072 		awg_clean_txbuf(sc, i);
1073 	}
1074 	sc->tx.next = i;
1075 	for (; sc->tx.queued > 0; i = TX_NEXT(i)) {
1076 		sc->tx.desc_ring[i].status = 0;
1077 		awg_clean_txbuf(sc, i);
1078 	}
1079 	sc->tx.cur = sc->tx.next;
1080 	bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map,
1081 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1082 
1083 	/* Setup RX buffers for reuse */
1084 	bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
1085 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1086 
1087 	for (i = sc->rx.cur; ; i = RX_NEXT(i)) {
1088 		val = le32toh(sc->rx.desc_ring[i].status);
1089 		if ((val & RX_DESC_CTL) != 0)
1090 			break;
1091 		awg_reuse_rxdesc(sc, i);
1092 	}
1093 	sc->rx.cur = i;
1094 	bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
1095 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1096 
1097 	if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1098 }
1099 
1100 static int
awg_ioctl(if_t ifp,u_long cmd,caddr_t data)1101 awg_ioctl(if_t ifp, u_long cmd, caddr_t data)
1102 {
1103 	struct awg_softc *sc;
1104 	struct mii_data *mii;
1105 	struct ifreq *ifr;
1106 	int flags, mask, error;
1107 
1108 	sc = if_getsoftc(ifp);
1109 	mii = device_get_softc(sc->miibus);
1110 	ifr = (struct ifreq *)data;
1111 	error = 0;
1112 
1113 	switch (cmd) {
1114 	case SIOCSIFFLAGS:
1115 		AWG_LOCK(sc);
1116 		if (if_getflags(ifp) & IFF_UP) {
1117 			if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1118 				flags = if_getflags(ifp) ^ sc->if_flags;
1119 				if ((flags & (IFF_PROMISC|IFF_ALLMULTI)) != 0)
1120 					awg_setup_rxfilter(sc);
1121 			} else
1122 				awg_init_locked(sc);
1123 		} else {
1124 			if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1125 				awg_stop(sc);
1126 		}
1127 		sc->if_flags = if_getflags(ifp);
1128 		AWG_UNLOCK(sc);
1129 		break;
1130 	case SIOCADDMULTI:
1131 	case SIOCDELMULTI:
1132 		if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1133 			AWG_LOCK(sc);
1134 			awg_setup_rxfilter(sc);
1135 			AWG_UNLOCK(sc);
1136 		}
1137 		break;
1138 	case SIOCSIFMEDIA:
1139 	case SIOCGIFMEDIA:
1140 		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1141 		break;
1142 	case SIOCSIFCAP:
1143 		mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1144 #ifdef DEVICE_POLLING
1145 		if (mask & IFCAP_POLLING) {
1146 			if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) {
1147 				error = ether_poll_register(awg_poll, ifp);
1148 				if (error != 0)
1149 					break;
1150 				AWG_LOCK(sc);
1151 				awg_disable_dma_intr(sc);
1152 				if_setcapenablebit(ifp, IFCAP_POLLING, 0);
1153 				AWG_UNLOCK(sc);
1154 			} else {
1155 				error = ether_poll_deregister(ifp);
1156 				AWG_LOCK(sc);
1157 				awg_enable_dma_intr(sc);
1158 				if_setcapenablebit(ifp, 0, IFCAP_POLLING);
1159 				AWG_UNLOCK(sc);
1160 			}
1161 		}
1162 #endif
1163 		if (mask & IFCAP_VLAN_MTU)
1164 			if_togglecapenable(ifp, IFCAP_VLAN_MTU);
1165 		if (mask & IFCAP_RXCSUM)
1166 			if_togglecapenable(ifp, IFCAP_RXCSUM);
1167 		if (mask & IFCAP_TXCSUM)
1168 			if_togglecapenable(ifp, IFCAP_TXCSUM);
1169 		if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
1170 			if_sethwassistbits(ifp, CSUM_IP | CSUM_UDP | CSUM_TCP, 0);
1171 		else
1172 			if_sethwassistbits(ifp, 0, CSUM_IP | CSUM_UDP | CSUM_TCP);
1173 		break;
1174 	default:
1175 		error = ether_ioctl(ifp, cmd, data);
1176 		break;
1177 	}
1178 
1179 	return (error);
1180 }
1181 
1182 /*
1183  * Interrupts functions
1184  */
1185 
1186 static int
awg_rxintr(struct awg_softc * sc)1187 awg_rxintr(struct awg_softc *sc)
1188 {
1189 	if_t ifp;
1190 	struct mbuf *m, *mh, *mt;
1191 	int error, index, len, cnt, npkt;
1192 	uint32_t status;
1193 
1194 	ifp = sc->ifp;
1195 	mh = mt = NULL;
1196 	cnt = 0;
1197 	npkt = 0;
1198 
1199 	bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
1200 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1201 
1202 	for (index = sc->rx.cur; ; index = RX_NEXT(index)) {
1203 		status = le32toh(sc->rx.desc_ring[index].status);
1204 		if ((status & RX_DESC_CTL) != 0)
1205 			break;
1206 
1207 		len = (status & RX_FRM_LEN) >> RX_FRM_LEN_SHIFT;
1208 
1209 		if (len == 0) {
1210 			if ((status & (RX_NO_ENOUGH_BUF_ERR | RX_OVERFLOW_ERR)) != 0)
1211 				if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1212 			awg_reuse_rxdesc(sc, index);
1213 			continue;
1214 		}
1215 
1216 		m = sc->rx.buf_map[index].mbuf;
1217 
1218 		error = awg_newbuf_rx(sc, index);
1219 		if (error != 0) {
1220 			if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1221 			awg_reuse_rxdesc(sc, index);
1222 			continue;
1223 		}
1224 
1225 		m->m_pkthdr.rcvif = ifp;
1226 		m->m_pkthdr.len = len;
1227 		m->m_len = len;
1228 		if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1229 
1230 		if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 &&
1231 		    (status & RX_FRM_TYPE) != 0) {
1232 			m->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
1233 			if ((status & RX_HEADER_ERR) == 0)
1234 				m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1235 			if ((status & RX_PAYLOAD_ERR) == 0) {
1236 				m->m_pkthdr.csum_flags |=
1237 				    CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1238 				m->m_pkthdr.csum_data = 0xffff;
1239 			}
1240 		}
1241 
1242 		m->m_nextpkt = NULL;
1243 		if (mh == NULL)
1244 			mh = m;
1245 		else
1246 			mt->m_nextpkt = m;
1247 		mt = m;
1248 		++cnt;
1249 		++npkt;
1250 
1251 		if (cnt == awg_rx_batch) {
1252 			AWG_UNLOCK(sc);
1253 			if_input(ifp, mh);
1254 			AWG_LOCK(sc);
1255 			mh = mt = NULL;
1256 			cnt = 0;
1257 		}
1258 	}
1259 
1260 	if (index != sc->rx.cur) {
1261 		bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
1262 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1263 	}
1264 
1265 	if (mh != NULL) {
1266 		AWG_UNLOCK(sc);
1267 		if_input(ifp, mh);
1268 		AWG_LOCK(sc);
1269 	}
1270 
1271 	sc->rx.cur = index;
1272 
1273 	return (npkt);
1274 }
1275 
1276 static void
awg_txeof(struct awg_softc * sc)1277 awg_txeof(struct awg_softc *sc)
1278 {
1279 	struct emac_desc *desc;
1280 	uint32_t status, size;
1281 	if_t ifp;
1282 	int i, prog;
1283 
1284 	AWG_ASSERT_LOCKED(sc);
1285 
1286 	bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map,
1287 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1288 
1289 	ifp = sc->ifp;
1290 
1291 	prog = 0;
1292 	for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) {
1293 		desc = &sc->tx.desc_ring[i];
1294 		status = le32toh(desc->status);
1295 		if ((status & TX_DESC_CTL) != 0)
1296 			break;
1297 		size = le32toh(desc->size);
1298 		if (size & TX_LAST_DESC) {
1299 			if ((status & (TX_HEADER_ERR | TX_PAYLOAD_ERR)) != 0)
1300 				if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1301 			else
1302 				if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1303 		}
1304 		prog++;
1305 		awg_clean_txbuf(sc, i);
1306 	}
1307 
1308 	if (prog > 0) {
1309 		sc->tx.next = i;
1310 		if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1311 	}
1312 }
1313 
1314 static void
awg_intr(void * arg)1315 awg_intr(void *arg)
1316 {
1317 	struct awg_softc *sc;
1318 	uint32_t val;
1319 
1320 	sc = arg;
1321 
1322 	AWG_LOCK(sc);
1323 	val = RD4(sc, EMAC_INT_STA);
1324 	WR4(sc, EMAC_INT_STA, val);
1325 
1326 	if (val & RX_INT)
1327 		awg_rxintr(sc);
1328 
1329 	if (val & TX_INT)
1330 		awg_txeof(sc);
1331 
1332 	if (val & (TX_INT | TX_BUF_UA_INT)) {
1333 		if (!if_sendq_empty(sc->ifp))
1334 			awg_start_locked(sc);
1335 	}
1336 
1337 	AWG_UNLOCK(sc);
1338 }
1339 
1340 #ifdef DEVICE_POLLING
1341 static int
awg_poll(if_t ifp,enum poll_cmd cmd,int count)1342 awg_poll(if_t ifp, enum poll_cmd cmd, int count)
1343 {
1344 	struct awg_softc *sc;
1345 	uint32_t val;
1346 	int rx_npkts;
1347 
1348 	sc = if_getsoftc(ifp);
1349 	rx_npkts = 0;
1350 
1351 	AWG_LOCK(sc);
1352 
1353 	if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
1354 		AWG_UNLOCK(sc);
1355 		return (0);
1356 	}
1357 
1358 	rx_npkts = awg_rxintr(sc);
1359 	awg_txeof(sc);
1360 	if (!if_sendq_empty(ifp))
1361 		awg_start_locked(sc);
1362 
1363 	if (cmd == POLL_AND_CHECK_STATUS) {
1364 		val = RD4(sc, EMAC_INT_STA);
1365 		if (val != 0)
1366 			WR4(sc, EMAC_INT_STA, val);
1367 	}
1368 
1369 	AWG_UNLOCK(sc);
1370 
1371 	return (rx_npkts);
1372 }
1373 #endif
1374 
1375 /*
1376  * syscon functions
1377  */
1378 static uint32_t
syscon_read_emac_clk_reg(device_t dev)1379 syscon_read_emac_clk_reg(device_t dev)
1380 {
1381 	struct awg_softc *sc;
1382 
1383 	sc = device_get_softc(dev);
1384 	if (sc->syscon != NULL)
1385 		return (SYSCON_READ_4(sc->syscon, EMAC_CLK_REG));
1386 	else if (sc->res[_RES_SYSCON] != NULL)
1387 		return (bus_read_4(sc->res[_RES_SYSCON], 0));
1388 
1389 	return (0);
1390 }
1391 
1392 static void
syscon_write_emac_clk_reg(device_t dev,uint32_t val)1393 syscon_write_emac_clk_reg(device_t dev, uint32_t val)
1394 {
1395 	struct awg_softc *sc;
1396 
1397 	sc = device_get_softc(dev);
1398 	if (sc->syscon != NULL)
1399 		SYSCON_WRITE_4(sc->syscon, EMAC_CLK_REG, val);
1400 	else if (sc->res[_RES_SYSCON] != NULL)
1401 		bus_write_4(sc->res[_RES_SYSCON], 0, val);
1402 }
1403 
1404 /*
1405  * PHY functions
1406  */
1407 
1408 static phandle_t
awg_get_phy_node(device_t dev)1409 awg_get_phy_node(device_t dev)
1410 {
1411 	phandle_t node;
1412 	pcell_t phy_handle;
1413 
1414 	node = ofw_bus_get_node(dev);
1415 	if (OF_getencprop(node, "phy-handle", (void *)&phy_handle,
1416 	    sizeof(phy_handle)) <= 0)
1417 		return (0);
1418 
1419 	return (OF_node_from_xref(phy_handle));
1420 }
1421 
1422 static bool
awg_has_internal_phy(device_t dev)1423 awg_has_internal_phy(device_t dev)
1424 {
1425 	phandle_t node, phy_node;
1426 
1427 	node = ofw_bus_get_node(dev);
1428 	/* Legacy binding */
1429 	if (OF_hasprop(node, "allwinner,use-internal-phy"))
1430 		return (true);
1431 
1432 	phy_node = awg_get_phy_node(dev);
1433 	return (phy_node != 0 && ofw_bus_node_is_compatible(OF_parent(phy_node),
1434 	    "allwinner,sun8i-h3-mdio-internal") != 0);
1435 }
1436 
1437 static int
awg_parse_delay(device_t dev,uint32_t * tx_delay,uint32_t * rx_delay)1438 awg_parse_delay(device_t dev, uint32_t *tx_delay, uint32_t *rx_delay)
1439 {
1440 	phandle_t node;
1441 	uint32_t delay;
1442 
1443 	if (tx_delay == NULL || rx_delay == NULL)
1444 		return (EINVAL);
1445 	*tx_delay = *rx_delay = 0;
1446 	node = ofw_bus_get_node(dev);
1447 
1448 	if (OF_getencprop(node, "tx-delay", &delay, sizeof(delay)) >= 0)
1449 		*tx_delay = delay;
1450 	else if (OF_getencprop(node, "allwinner,tx-delay-ps", &delay,
1451 	    sizeof(delay)) >= 0) {
1452 		if ((delay % 100) != 0) {
1453 			device_printf(dev, "tx-delay-ps is not a multiple of 100\n");
1454 			return (EDOM);
1455 		}
1456 		*tx_delay = delay / 100;
1457 	}
1458 	if (*tx_delay > 7) {
1459 		device_printf(dev, "tx-delay out of range\n");
1460 		return (ERANGE);
1461 	}
1462 
1463 	if (OF_getencprop(node, "rx-delay", &delay, sizeof(delay)) >= 0)
1464 		*rx_delay = delay;
1465 	else if (OF_getencprop(node, "allwinner,rx-delay-ps", &delay,
1466 	    sizeof(delay)) >= 0) {
1467 		if ((delay % 100) != 0) {
1468 			device_printf(dev, "rx-delay-ps is not within documented domain\n");
1469 			return (EDOM);
1470 		}
1471 		*rx_delay = delay / 100;
1472 	}
1473 	if (*rx_delay > 31) {
1474 		device_printf(dev, "rx-delay out of range\n");
1475 		return (ERANGE);
1476 	}
1477 
1478 	return (0);
1479 }
1480 
1481 static int
awg_setup_phy(device_t dev)1482 awg_setup_phy(device_t dev)
1483 {
1484 	struct awg_softc *sc;
1485 	clk_t clk_tx, clk_tx_parent;
1486 	const char *tx_parent_name;
1487 	char *phy_type;
1488 	phandle_t node;
1489 	uint32_t reg, tx_delay, rx_delay;
1490 	int error;
1491 	bool use_syscon;
1492 
1493 	sc = device_get_softc(dev);
1494 	node = ofw_bus_get_node(dev);
1495 	use_syscon = false;
1496 
1497 	if (OF_getprop_alloc(node, "phy-mode", (void **)&phy_type) == 0)
1498 		return (0);
1499 
1500 	if (sc->syscon != NULL || sc->res[_RES_SYSCON] != NULL)
1501 		use_syscon = true;
1502 
1503 	if (bootverbose)
1504 		device_printf(dev, "PHY type: %s, conf mode: %s\n", phy_type,
1505 		    use_syscon ? "reg" : "clk");
1506 
1507 	if (use_syscon) {
1508 		/*
1509 		 * Abstract away writing to syscon for devices like the pine64.
1510 		 * For the pine64, we get dtb from U-Boot and it still uses the
1511 		 * legacy setup of specifying syscon register in emac node
1512 		 * rather than as its own node and using an xref in emac.
1513 		 * These abstractions can go away once U-Boot dts is up-to-date.
1514 		 */
1515 		reg = syscon_read_emac_clk_reg(dev);
1516 		reg &= ~(EMAC_CLK_PIT | EMAC_CLK_SRC | EMAC_CLK_RMII_EN);
1517 		if (strncmp(phy_type, "rgmii", 5) == 0)
1518 			reg |= EMAC_CLK_PIT_RGMII | EMAC_CLK_SRC_RGMII;
1519 		else if (strcmp(phy_type, "rmii") == 0)
1520 			reg |= EMAC_CLK_RMII_EN;
1521 		else
1522 			reg |= EMAC_CLK_PIT_MII | EMAC_CLK_SRC_MII;
1523 
1524 		/*
1525 		 * Fail attach if we fail to parse either of the delay
1526 		 * parameters. If we don't have the proper delay to write to
1527 		 * syscon, then awg likely won't function properly anyways.
1528 		 * Lack of delay is not an error!
1529 		 */
1530 		error = awg_parse_delay(dev, &tx_delay, &rx_delay);
1531 		if (error != 0)
1532 			goto fail;
1533 
1534 		/* Default to 0 and we'll increase it if we need to. */
1535 		reg &= ~(EMAC_CLK_ETXDC | EMAC_CLK_ERXDC);
1536 		if (tx_delay > 0)
1537 			reg |= (tx_delay << EMAC_CLK_ETXDC_SHIFT);
1538 		if (rx_delay > 0)
1539 			reg |= (rx_delay << EMAC_CLK_ERXDC_SHIFT);
1540 
1541 		if (sc->type == EMAC_H3) {
1542 			if (awg_has_internal_phy(dev)) {
1543 				reg |= EMAC_CLK_EPHY_SELECT;
1544 				reg &= ~EMAC_CLK_EPHY_SHUTDOWN;
1545 				if (OF_hasprop(node,
1546 				    "allwinner,leds-active-low"))
1547 					reg |= EMAC_CLK_EPHY_LED_POL;
1548 				else
1549 					reg &= ~EMAC_CLK_EPHY_LED_POL;
1550 
1551 				/* Set internal PHY addr to 1 */
1552 				reg &= ~EMAC_CLK_EPHY_ADDR;
1553 				reg |= (1 << EMAC_CLK_EPHY_ADDR_SHIFT);
1554 			} else {
1555 				reg &= ~EMAC_CLK_EPHY_SELECT;
1556 			}
1557 		}
1558 
1559 		if (bootverbose)
1560 			device_printf(dev, "EMAC clock: 0x%08x\n", reg);
1561 		syscon_write_emac_clk_reg(dev, reg);
1562 	} else {
1563 		if (strncmp(phy_type, "rgmii", 5) == 0)
1564 			tx_parent_name = "emac_int_tx";
1565 		else
1566 			tx_parent_name = "mii_phy_tx";
1567 
1568 		/* Get the TX clock */
1569 		error = clk_get_by_ofw_name(dev, 0, "tx", &clk_tx);
1570 		if (error != 0) {
1571 			device_printf(dev, "cannot get tx clock\n");
1572 			goto fail;
1573 		}
1574 
1575 		/* Find the desired parent clock based on phy-mode property */
1576 		error = clk_get_by_name(dev, tx_parent_name, &clk_tx_parent);
1577 		if (error != 0) {
1578 			device_printf(dev, "cannot get clock '%s'\n",
1579 			    tx_parent_name);
1580 			goto fail;
1581 		}
1582 
1583 		/* Set TX clock parent */
1584 		error = clk_set_parent_by_clk(clk_tx, clk_tx_parent);
1585 		if (error != 0) {
1586 			device_printf(dev, "cannot set tx clock parent\n");
1587 			goto fail;
1588 		}
1589 
1590 		/* Enable TX clock */
1591 		error = clk_enable(clk_tx);
1592 		if (error != 0) {
1593 			device_printf(dev, "cannot enable tx clock\n");
1594 			goto fail;
1595 		}
1596 	}
1597 
1598 	error = 0;
1599 
1600 fail:
1601 	OF_prop_free(phy_type);
1602 	return (error);
1603 }
1604 
1605 static int
awg_setup_extres(device_t dev)1606 awg_setup_extres(device_t dev)
1607 {
1608 	struct awg_softc *sc;
1609 	phandle_t node, phy_node;
1610 	hwreset_t rst_ahb, rst_ephy;
1611 	clk_t clk_ahb, clk_ephy;
1612 	regulator_t reg;
1613 	uint64_t freq;
1614 	int error, div;
1615 
1616 	sc = device_get_softc(dev);
1617 	rst_ahb = rst_ephy = NULL;
1618 	clk_ahb = clk_ephy = NULL;
1619 	reg = NULL;
1620 	node = ofw_bus_get_node(dev);
1621 	phy_node = awg_get_phy_node(dev);
1622 
1623 	if (phy_node == 0 && OF_hasprop(node, "phy-handle")) {
1624 		error = ENXIO;
1625 		device_printf(dev, "cannot get phy handle\n");
1626 		goto fail;
1627 	}
1628 
1629 	/* Get AHB clock and reset resources */
1630 	error = hwreset_get_by_ofw_name(dev, 0, "stmmaceth", &rst_ahb);
1631 	if (error != 0)
1632 		error = hwreset_get_by_ofw_name(dev, 0, "ahb", &rst_ahb);
1633 	if (error != 0) {
1634 		device_printf(dev, "cannot get ahb reset\n");
1635 		goto fail;
1636 	}
1637 	if (hwreset_get_by_ofw_name(dev, 0, "ephy", &rst_ephy) != 0)
1638 		if (phy_node == 0 || hwreset_get_by_ofw_idx(dev, phy_node, 0,
1639 		    &rst_ephy) != 0)
1640 			rst_ephy = NULL;
1641 	error = clk_get_by_ofw_name(dev, 0, "stmmaceth", &clk_ahb);
1642 	if (error != 0)
1643 		error = clk_get_by_ofw_name(dev, 0, "ahb", &clk_ahb);
1644 	if (error != 0) {
1645 		device_printf(dev, "cannot get ahb clock\n");
1646 		goto fail;
1647 	}
1648 	if (clk_get_by_ofw_name(dev, 0, "ephy", &clk_ephy) != 0)
1649 		if (phy_node == 0 || clk_get_by_ofw_index(dev, phy_node, 0,
1650 		    &clk_ephy) != 0)
1651 			clk_ephy = NULL;
1652 
1653 	if (OF_hasprop(node, "syscon") && syscon_get_by_ofw_property(dev, node,
1654 	    "syscon", &sc->syscon) != 0) {
1655 		device_printf(dev, "cannot get syscon driver handle\n");
1656 		goto fail;
1657 	}
1658 
1659 	/* Configure PHY for MII or RGMII mode */
1660 	if (awg_setup_phy(dev) != 0)
1661 		goto fail;
1662 
1663 	/* Enable clocks */
1664 	error = clk_enable(clk_ahb);
1665 	if (error != 0) {
1666 		device_printf(dev, "cannot enable ahb clock\n");
1667 		goto fail;
1668 	}
1669 	if (clk_ephy != NULL) {
1670 		error = clk_enable(clk_ephy);
1671 		if (error != 0) {
1672 			device_printf(dev, "cannot enable ephy clock\n");
1673 			goto fail;
1674 		}
1675 	}
1676 
1677 	/* De-assert reset */
1678 	error = hwreset_deassert(rst_ahb);
1679 	if (error != 0) {
1680 		device_printf(dev, "cannot de-assert ahb reset\n");
1681 		goto fail;
1682 	}
1683 	if (rst_ephy != NULL) {
1684 		/*
1685 		 * The ephy reset is left de-asserted by U-Boot.  Assert it
1686 		 * here to make sure that we're in a known good state going
1687 		 * into the PHY reset.
1688 		 */
1689 		hwreset_assert(rst_ephy);
1690 		error = hwreset_deassert(rst_ephy);
1691 		if (error != 0) {
1692 			device_printf(dev, "cannot de-assert ephy reset\n");
1693 			goto fail;
1694 		}
1695 	}
1696 
1697 	/* Enable PHY regulator if applicable */
1698 	if (regulator_get_by_ofw_property(dev, 0, "phy-supply", &reg) == 0) {
1699 		error = regulator_enable(reg);
1700 		if (error != 0) {
1701 			device_printf(dev, "cannot enable PHY regulator\n");
1702 			goto fail;
1703 		}
1704 	}
1705 
1706 	/* Determine MDC clock divide ratio based on AHB clock */
1707 	error = clk_get_freq(clk_ahb, &freq);
1708 	if (error != 0) {
1709 		device_printf(dev, "cannot get AHB clock frequency\n");
1710 		goto fail;
1711 	}
1712 	div = freq / MDIO_FREQ;
1713 	if (div <= 16)
1714 		sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_16;
1715 	else if (div <= 32)
1716 		sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_32;
1717 	else if (div <= 64)
1718 		sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_64;
1719 	else if (div <= 128)
1720 		sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_128;
1721 	else {
1722 		device_printf(dev, "cannot determine MDC clock divide ratio\n");
1723 		error = ENXIO;
1724 		goto fail;
1725 	}
1726 
1727 	if (bootverbose)
1728 		device_printf(dev, "AHB frequency %ju Hz, MDC div: 0x%x\n",
1729 		    (uintmax_t)freq, sc->mdc_div_ratio_m);
1730 
1731 	return (0);
1732 
1733 fail:
1734 	if (reg != NULL)
1735 		regulator_release(reg);
1736 	if (clk_ephy != NULL)
1737 		clk_release(clk_ephy);
1738 	if (clk_ahb != NULL)
1739 		clk_release(clk_ahb);
1740 	if (rst_ephy != NULL)
1741 		hwreset_release(rst_ephy);
1742 	if (rst_ahb != NULL)
1743 		hwreset_release(rst_ahb);
1744 	return (error);
1745 }
1746 
1747 #ifdef AWG_DEBUG
1748 static void
awg_dump_regs(device_t dev)1749 awg_dump_regs(device_t dev)
1750 {
1751 	static const struct {
1752 		const char *name;
1753 		u_int reg;
1754 	} regs[] = {
1755 		{ "BASIC_CTL_0", EMAC_BASIC_CTL_0 },
1756 		{ "BASIC_CTL_1", EMAC_BASIC_CTL_1 },
1757 		{ "INT_STA", EMAC_INT_STA },
1758 		{ "INT_EN", EMAC_INT_EN },
1759 		{ "TX_CTL_0", EMAC_TX_CTL_0 },
1760 		{ "TX_CTL_1", EMAC_TX_CTL_1 },
1761 		{ "TX_FLOW_CTL", EMAC_TX_FLOW_CTL },
1762 		{ "TX_DMA_LIST", EMAC_TX_DMA_LIST },
1763 		{ "RX_CTL_0", EMAC_RX_CTL_0 },
1764 		{ "RX_CTL_1", EMAC_RX_CTL_1 },
1765 		{ "RX_DMA_LIST", EMAC_RX_DMA_LIST },
1766 		{ "RX_FRM_FLT", EMAC_RX_FRM_FLT },
1767 		{ "RX_HASH_0", EMAC_RX_HASH_0 },
1768 		{ "RX_HASH_1", EMAC_RX_HASH_1 },
1769 		{ "MII_CMD", EMAC_MII_CMD },
1770 		{ "ADDR_HIGH0", EMAC_ADDR_HIGH(0) },
1771 		{ "ADDR_LOW0", EMAC_ADDR_LOW(0) },
1772 		{ "TX_DMA_STA", EMAC_TX_DMA_STA },
1773 		{ "TX_DMA_CUR_DESC", EMAC_TX_DMA_CUR_DESC },
1774 		{ "TX_DMA_CUR_BUF", EMAC_TX_DMA_CUR_BUF },
1775 		{ "RX_DMA_STA", EMAC_RX_DMA_STA },
1776 		{ "RX_DMA_CUR_DESC", EMAC_RX_DMA_CUR_DESC },
1777 		{ "RX_DMA_CUR_BUF", EMAC_RX_DMA_CUR_BUF },
1778 		{ "RGMII_STA", EMAC_RGMII_STA },
1779 	};
1780 	struct awg_softc *sc;
1781 	unsigned int n;
1782 
1783 	sc = device_get_softc(dev);
1784 
1785 	for (n = 0; n < nitems(regs); n++)
1786 		device_printf(dev, "  %-20s %08x\n", regs[n].name,
1787 		    RD4(sc, regs[n].reg));
1788 }
1789 #endif
1790 
1791 #define	GPIO_ACTIVE_LOW		1
1792 
1793 static int
awg_phy_reset(device_t dev)1794 awg_phy_reset(device_t dev)
1795 {
1796 	pcell_t gpio_prop[4], delay_prop[3];
1797 	phandle_t node, gpio_node;
1798 	device_t gpio;
1799 	uint32_t pin, flags;
1800 	uint32_t pin_value;
1801 
1802 	node = ofw_bus_get_node(dev);
1803 	if (OF_getencprop(node, "allwinner,reset-gpio", gpio_prop,
1804 	    sizeof(gpio_prop)) <= 0)
1805 		return (0);
1806 
1807 	if (OF_getencprop(node, "allwinner,reset-delays-us", delay_prop,
1808 	    sizeof(delay_prop)) <= 0)
1809 		return (ENXIO);
1810 
1811 	gpio_node = OF_node_from_xref(gpio_prop[0]);
1812 	if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL)
1813 		return (ENXIO);
1814 
1815 	if (GPIO_MAP_GPIOS(gpio, node, gpio_node, nitems(gpio_prop) - 1,
1816 	    gpio_prop + 1, &pin, &flags) != 0)
1817 		return (ENXIO);
1818 
1819 	pin_value = GPIO_PIN_LOW;
1820 	if (OF_hasprop(node, "allwinner,reset-active-low"))
1821 		pin_value = GPIO_PIN_HIGH;
1822 
1823 	if (flags & GPIO_ACTIVE_LOW)
1824 		pin_value = !pin_value;
1825 
1826 	GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT);
1827 	GPIO_PIN_SET(gpio, pin, pin_value);
1828 	DELAY(delay_prop[0]);
1829 	GPIO_PIN_SET(gpio, pin, !pin_value);
1830 	DELAY(delay_prop[1]);
1831 	GPIO_PIN_SET(gpio, pin, pin_value);
1832 	DELAY(delay_prop[2]);
1833 
1834 	return (0);
1835 }
1836 
1837 static int
awg_reset(device_t dev)1838 awg_reset(device_t dev)
1839 {
1840 	struct awg_softc *sc;
1841 	int retry;
1842 
1843 	sc = device_get_softc(dev);
1844 
1845 	/* Reset PHY if necessary */
1846 	if (awg_phy_reset(dev) != 0) {
1847 		device_printf(dev, "failed to reset PHY\n");
1848 		return (ENXIO);
1849 	}
1850 
1851 	/* Soft reset all registers and logic */
1852 	WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST);
1853 
1854 	/* Wait for soft reset bit to self-clear */
1855 	for (retry = SOFT_RST_RETRY; retry > 0; retry--) {
1856 		if ((RD4(sc, EMAC_BASIC_CTL_1) & BASIC_CTL_SOFT_RST) == 0)
1857 			break;
1858 		DELAY(10);
1859 	}
1860 	if (retry == 0) {
1861 		device_printf(dev, "soft reset timed out\n");
1862 #ifdef AWG_DEBUG
1863 		awg_dump_regs(dev);
1864 #endif
1865 		return (ETIMEDOUT);
1866 	}
1867 
1868 	return (0);
1869 }
1870 
1871 /*
1872  * Stats
1873  */
1874 
1875 static void
awg_tick(void * softc)1876 awg_tick(void *softc)
1877 {
1878 	struct awg_softc *sc;
1879 	struct mii_data *mii;
1880 	if_t ifp;
1881 	int link;
1882 
1883 	sc = softc;
1884 	ifp = sc->ifp;
1885 	mii = device_get_softc(sc->miibus);
1886 
1887 	AWG_ASSERT_LOCKED(sc);
1888 
1889 	if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
1890 		return;
1891 
1892 	link = sc->link;
1893 	mii_tick(mii);
1894 	if (sc->link && !link)
1895 		awg_start_locked(sc);
1896 
1897 	callout_reset(&sc->stat_ch, hz, awg_tick, sc);
1898 }
1899 
1900 /*
1901  * Probe/attach functions
1902  */
1903 
1904 static int
awg_probe(device_t dev)1905 awg_probe(device_t dev)
1906 {
1907 	if (!ofw_bus_status_okay(dev))
1908 		return (ENXIO);
1909 
1910 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
1911 		return (ENXIO);
1912 
1913 	device_set_desc(dev, "Allwinner Gigabit Ethernet");
1914 	return (BUS_PROBE_DEFAULT);
1915 }
1916 
1917 static int
awg_attach(device_t dev)1918 awg_attach(device_t dev)
1919 {
1920 	uint8_t eaddr[ETHER_ADDR_LEN];
1921 	struct awg_softc *sc;
1922 	int error;
1923 
1924 	sc = device_get_softc(dev);
1925 	sc->dev = dev;
1926 	sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
1927 
1928 	if (bus_alloc_resources(dev, awg_spec, sc->res) != 0) {
1929 		device_printf(dev, "cannot allocate resources for device\n");
1930 		return (ENXIO);
1931 	}
1932 
1933 	mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF);
1934 	callout_init_mtx(&sc->stat_ch, &sc->mtx, 0);
1935 
1936 	/* Setup clocks and regulators */
1937 	error = awg_setup_extres(dev);
1938 	if (error != 0)
1939 		return (error);
1940 
1941 	/* Read MAC address before resetting the chip */
1942 	awg_get_eaddr(dev, eaddr);
1943 
1944 	/* Soft reset EMAC core */
1945 	error = awg_reset(dev);
1946 	if (error != 0)
1947 		return (error);
1948 
1949 	/* Setup DMA descriptors */
1950 	error = awg_setup_dma(dev);
1951 	if (error != 0)
1952 		return (error);
1953 
1954 	/* Install interrupt handler */
1955 	error = bus_setup_intr(dev, sc->res[_RES_IRQ],
1956 	    INTR_TYPE_NET | INTR_MPSAFE, NULL, awg_intr, sc, &sc->ih);
1957 	if (error != 0) {
1958 		device_printf(dev, "cannot setup interrupt handler\n");
1959 		return (error);
1960 	}
1961 
1962 	/* Setup ethernet interface */
1963 	sc->ifp = if_alloc(IFT_ETHER);
1964 	if_setsoftc(sc->ifp, sc);
1965 	if_initname(sc->ifp, device_get_name(dev), device_get_unit(dev));
1966 	if_setflags(sc->ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
1967 	if_setstartfn(sc->ifp, awg_start);
1968 	if_setioctlfn(sc->ifp, awg_ioctl);
1969 	if_setinitfn(sc->ifp, awg_init);
1970 	if_setsendqlen(sc->ifp, TX_DESC_COUNT - 1);
1971 	if_setsendqready(sc->ifp);
1972 	if_sethwassist(sc->ifp, CSUM_IP | CSUM_UDP | CSUM_TCP);
1973 	if_setcapabilities(sc->ifp, IFCAP_VLAN_MTU | IFCAP_HWCSUM);
1974 	if_setcapenable(sc->ifp, if_getcapabilities(sc->ifp));
1975 #ifdef DEVICE_POLLING
1976 	if_setcapabilitiesbit(sc->ifp, IFCAP_POLLING, 0);
1977 #endif
1978 
1979 	/* Attach MII driver */
1980 	error = mii_attach(dev, &sc->miibus, sc->ifp, awg_media_change,
1981 	    awg_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
1982 	    MIIF_DOPAUSE);
1983 	if (error != 0) {
1984 		device_printf(dev, "cannot attach PHY\n");
1985 		return (error);
1986 	}
1987 
1988 	/* Attach ethernet interface */
1989 	ether_ifattach(sc->ifp, eaddr);
1990 
1991 	return (0);
1992 }
1993 
1994 static device_method_t awg_methods[] = {
1995 	/* Device interface */
1996 	DEVMETHOD(device_probe,		awg_probe),
1997 	DEVMETHOD(device_attach,	awg_attach),
1998 
1999 	/* MII interface */
2000 	DEVMETHOD(miibus_readreg,	awg_miibus_readreg),
2001 	DEVMETHOD(miibus_writereg,	awg_miibus_writereg),
2002 	DEVMETHOD(miibus_statchg,	awg_miibus_statchg),
2003 
2004 	DEVMETHOD_END
2005 };
2006 
2007 static driver_t awg_driver = {
2008 	"awg",
2009 	awg_methods,
2010 	sizeof(struct awg_softc),
2011 };
2012 
2013 DRIVER_MODULE(awg, simplebus, awg_driver, 0, 0);
2014 DRIVER_MODULE(miibus, awg, miibus_driver, 0, 0);
2015 MODULE_DEPEND(awg, ether, 1, 1, 1);
2016 MODULE_DEPEND(awg, miibus, 1, 1, 1);
2017 MODULE_DEPEND(awg, aw_sid, 1, 1, 1);
2018 SIMPLEBUS_PNP_INFO(compat_data);
2019