1 2 3 #ifndef __ELINK_H 4 #define __ELINK_H 5 6 #if defined(_VBD_) 7 #include <SAL.h> 8 #include "debug.h" 9 #endif 10 11 #ifndef _In_ 12 #define _In_ 13 #endif 14 #ifndef _Out_ 15 #define _Out_ 16 #endif 17 18 /***********************************************************/ 19 /* CLC Call backs functions */ 20 /***********************************************************/ 21 /* CLC device structure */ 22 struct elink_dev; 23 24 extern u32 elink_cb_reg_read(struct elink_dev *cb, u32 reg_addr); 25 extern void elink_cb_reg_write(struct elink_dev *cb, u32 reg_addr, u32 val); 26 /* wb_write - pointer to 2 32 bits vars to be passed to the DMAE*/ 27 extern void elink_cb_reg_wb_write(struct elink_dev *cb, u32 offset, 28 u32 *wb_write, u16 len); 29 extern void elink_cb_reg_wb_read(struct elink_dev *cb, u32 offset, 30 u32 *wb_write, u16 len); 31 32 /* mode - 0( LOW ) /1(HIGH)*/ 33 extern u8 elink_cb_gpio_write(struct elink_dev *cb, 34 u16 gpio_num, 35 u8 mode, u8 port); 36 extern u8 elink_cb_gpio_mult_write(struct elink_dev *cb, 37 u8 pins, 38 u8 mode); 39 40 extern u32 elink_cb_gpio_read(struct elink_dev *cb, u16 gpio_num, u8 port); 41 extern u8 elink_cb_gpio_int_write(struct elink_dev *cb, 42 u16 gpio_num, 43 u8 mode, u8 port); 44 45 extern u32 elink_cb_fw_command(struct elink_dev *cb, u32 command, u32 param); 46 47 /* Delay */ 48 extern void elink_cb_udelay(struct elink_dev *cb, u32 microsecond); 49 50 /* This function is called every 1024 bytes downloading of phy firmware. 51 Driver can use it to print to screen indication for download progress */ 52 extern void elink_cb_download_progress(struct elink_dev *cb, u32 cur, u32 total); 53 54 /* Each log type has its own parameters */ 55 typedef enum elink_log_id { 56 ELINK_LOG_ID_UNQUAL_IO_MODULE = 0, /* u8 port, const char* vendor_name, const char* vendor_pn */ 57 ELINK_LOG_ID_OVER_CURRENT = 1, /* u8 port */ 58 ELINK_LOG_ID_PHY_UNINITIALIZED = 2, /* u8 port */ 59 ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT= 3, /* No params */ 60 ELINK_LOG_ID_NON_10G_MODULE = 4, /* u8 port */ 61 }elink_log_id_t; 62 63 typedef enum elink_status { 64 ELINK_STATUS_OK = 0, 65 ELINK_STATUS_ERROR, 66 ELINK_STATUS_TIMEOUT, 67 ELINK_STATUS_NO_LINK, 68 ELINK_STATUS_INVALID_IMAGE, 69 ELINK_OP_NOT_SUPPORTED = 122 70 } elink_status_t; 71 #ifndef EDEBUG 72 extern void elink_cb_event_log(struct elink_dev *cb, const elink_log_id_t log_id, ...); 73 #endif 74 extern void elink_cb_load_warpcore_microcode(void); 75 76 extern u8 elink_cb_path_id(struct elink_dev *cb); 77 78 extern void elink_cb_notify_link_changed(struct elink_dev *cb); 79 80 #define ELINK_EVENT_LOG_LEVEL_ERROR 1 81 #define ELINK_EVENT_LOG_LEVEL_WARNING 2 82 #define ELINK_EVENT_ID_SFP_UNQUALIFIED_MODULE 1 83 #define ELINK_EVENT_ID_SFP_POWER_FAULT 2 84 85 #ifdef ELINK_AUX_POWER 86 #define elink_cb_event_log(cb, level, ...) 87 #define elink_cb_get_friendly_name(cb) '' 88 #endif /*ELINK_AUX_POWER */ 89 #ifndef ARRAY_SIZE 90 #define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) 91 #endif 92 /* Debug prints */ 93 #ifdef ELINK_DEBUG 94 95 #if defined(_VBD_) 96 #define ELINK_DEBUG_P0(cb, fmt) DbgMessage(cb, WARNelink, fmt) 97 #define ELINK_DEBUG_P1(cb, fmt, arg1) DbgMessage(cb, WARNelink, fmt, arg1) 98 #define ELINK_DEBUG_P2(cb, fmt, arg1, arg2) DbgMessage(cb, WARNelink, fmt, arg1, arg2) 99 #define ELINK_DEBUG_P3(cb, fmt, arg1, arg2, arg3) \ 100 DbgMessage(cb, WARNelink, fmt, arg1, arg2, arg3) 101 #else 102 extern void elink_cb_dbg(struct elink_dev *cb, _In_ char *fmt); 103 extern void elink_cb_dbg1(struct elink_dev *cb, _In_ char *fmt, u32 arg1); 104 extern void elink_cb_dbg2(struct elink_dev *cb, _In_ char *fmt, u32 arg1, u32 arg2); 105 extern void elink_cb_dbg3(struct elink_dev *cb, _In_ char *fmt, u32 arg1, u32 arg2, 106 u32 arg3); 107 108 #define ELINK_DEBUG_P0(cb, fmt) elink_cb_dbg(cb, fmt) 109 #define ELINK_DEBUG_P1(cb, fmt, arg1) elink_cb_dbg1(cb, fmt, arg1) 110 #define ELINK_DEBUG_P2(cb, fmt, arg1, arg2) elink_cb_dbg2(cb, fmt, arg1, arg2) 111 #define ELINK_DEBUG_P3(cb, fmt, arg1, arg2, arg3) \ 112 elink_cb_dbg3(cb, fmt, arg1, arg2, arg3) 113 #endif // _VBD_ 114 115 #else 116 #define ELINK_DEBUG_P0(cb, fmt) 117 #define ELINK_DEBUG_P1(cb, fmt, arg1) 118 #define ELINK_DEBUG_P2(cb, fmt, arg1, arg2) 119 #define ELINK_DEBUG_P3(cb, fmt, arg1, arg2, arg3) 120 #endif 121 122 /***********************************************************/ 123 /* Defines */ 124 /***********************************************************/ 125 #define ELINK_DEFAULT_PHY_DEV_ADDR 3 126 #define ELINK_E2_DEFAULT_PHY_DEV_ADDR 5 127 128 129 #ifndef DUPLEX_FULL 130 #define DUPLEX_FULL 1 131 #endif 132 #ifndef DUPLEX_HALF 133 #define DUPLEX_HALF 2 134 #endif 135 136 #define ELINK_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO 137 #define ELINK_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX 138 #define ELINK_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX 139 #define ELINK_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH 140 #define ELINK_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE 141 142 #define ELINK_NET_SERDES_IF_XFI 1 143 #define ELINK_NET_SERDES_IF_SFI 2 144 #define ELINK_NET_SERDES_IF_KR 3 145 #define ELINK_NET_SERDES_IF_DXGXS 4 146 147 #define ELINK_SPEED_AUTO_NEG 0 148 #define ELINK_SPEED_10 10 149 #define ELINK_SPEED_100 100 150 #define ELINK_SPEED_1000 1000 151 #define ELINK_SPEED_2500 2500 152 #define ELINK_SPEED_10000 10000 153 #define ELINK_SPEED_20000 20000 154 155 #define ELINK_I2C_DEV_ADDR_A0 0xa0 156 #define ELINK_I2C_DEV_ADDR_A2 0xa2 157 158 #define ELINK_SFP_EEPROM_PAGE_SIZE 16 159 #define ELINK_SFP_EEPROM_VENDOR_NAME_ADDR 0x14 160 #define ELINK_SFP_EEPROM_VENDOR_NAME_SIZE 16 161 #define ELINK_SFP_EEPROM_VENDOR_OUI_ADDR 0x25 162 #define ELINK_SFP_EEPROM_VENDOR_OUI_SIZE 3 163 #define ELINK_SFP_EEPROM_PART_NO_ADDR 0x28 164 #define ELINK_SFP_EEPROM_PART_NO_SIZE 16 165 #define ELINK_SFP_EEPROM_REVISION_ADDR 0x38 166 #define ELINK_SFP_EEPROM_REVISION_SIZE 4 167 #define ELINK_SFP_EEPROM_SERIAL_ADDR 0x44 168 #define ELINK_SFP_EEPROM_SERIAL_SIZE 16 169 #define ELINK_SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */ 170 #define ELINK_SFP_EEPROM_DATE_SIZE 6 171 #define ELINK_SFP_EEPROM_DIAG_TYPE_ADDR 0x5c 172 #define ELINK_SFP_EEPROM_DIAG_TYPE_SIZE 1 173 #define ELINK_SFP_EEPROM_DIAG_ADDR_CHANGE_REQ (1<<2) 174 #define ELINK_SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e 175 #define ELINK_SFP_EEPROM_SFF_8472_COMP_SIZE 1 176 #define ELINK_SFP_EEPROM_VENDOR_SPECIFIC_ADDR 0x60 177 #define ELINK_SFP_EEPROM_VENDOR_SPECIFIC_SIZE 16 178 179 180 #define ELINK_SFP_EEPROM_A2_CHECKSUM_RANGE 0x5e 181 #define ELINK_SFP_EEPROM_A2_CC_DMI_ADDR 0x5f 182 183 #define ELINK_PWR_FLT_ERR_MSG_LEN 250 184 185 #define ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config) \ 186 ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) 187 #define ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config) \ 188 (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \ 189 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT) 190 #define ELINK_SERDES_EXT_PHY_TYPE(ext_phy_config) \ 191 ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) 192 193 /* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */ 194 #define ELINK_SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1) 195 /* Single Media board contains single external phy */ 196 #define ELINK_SINGLE_MEDIA(params) (params->num_phys == 2) 197 /* Dual Media board contains two external phy with different media */ 198 #define ELINK_DUAL_MEDIA(params) (params->num_phys == 3) 199 200 #define ELINK_FW_PARAM_PHY_ADDR_MASK 0x000000FF 201 #define ELINK_FW_PARAM_PHY_TYPE_MASK 0x0000FF00 202 #define ELINK_FW_PARAM_MDIO_CTRL_MASK 0xFFFF0000 203 #define ELINK_FW_PARAM_MDIO_CTRL_OFFSET 16 204 #define ELINK_FW_PARAM_PHY_ADDR(fw_param) (fw_param & \ 205 ELINK_FW_PARAM_PHY_ADDR_MASK) 206 #define ELINK_FW_PARAM_PHY_TYPE(fw_param) (fw_param & \ 207 ELINK_FW_PARAM_PHY_TYPE_MASK) 208 #define ELINK_FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \ 209 ELINK_FW_PARAM_MDIO_CTRL_MASK) >> \ 210 ELINK_FW_PARAM_MDIO_CTRL_OFFSET) 211 #define ELINK_FW_PARAM_SET(phy_addr, phy_type, mdio_access) \ 212 (phy_addr | phy_type | mdio_access << ELINK_FW_PARAM_MDIO_CTRL_OFFSET) 213 214 215 #define ELINK_PFC_BRB_FULL_LB_XOFF_THRESHOLD 170 216 #define ELINK_PFC_BRB_FULL_LB_XON_THRESHOLD 250 217 218 #define ELINK_MAXVAL(a, b) (((a) > (b)) ? (a) : (b)) 219 220 #define ELINK_BMAC_CONTROL_RX_ENABLE 2 221 /***********************************************************/ 222 /* Structs */ 223 /***********************************************************/ 224 #define ELINK_INT_PHY 0 225 #define ELINK_EXT_PHY1 1 226 #define ELINK_EXT_PHY2 2 227 #define ELINK_MAX_PHYS 3 228 229 /* Same configuration is shared between the XGXS and the first external phy */ 230 #define ELINK_LINK_CONFIG_SIZE (ELINK_MAX_PHYS - 1) 231 #define ELINK_LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == ELINK_INT_PHY) ? \ 232 0 : (_phy_idx - 1)) 233 /***********************************************************/ 234 /* elink_phy struct */ 235 /* Defines the required arguments and function per phy */ 236 /***********************************************************/ 237 struct elink_vars; 238 struct elink_params; 239 struct elink_phy; 240 241 typedef u8 (*config_init_t)(struct elink_phy *phy, struct elink_params *params, 242 struct elink_vars *vars); 243 typedef u8 (*read_status_t)(struct elink_phy *phy, struct elink_params *params, 244 struct elink_vars *vars); 245 typedef void (*link_reset_t)(struct elink_phy *phy, 246 struct elink_params *params); 247 typedef void (*config_loopback_t)(struct elink_phy *phy, 248 struct elink_params *params); 249 typedef u8 (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len); 250 typedef void (*hw_reset_t)(struct elink_phy *phy, struct elink_params *params); 251 typedef void (*set_link_led_t)(struct elink_phy *phy, 252 struct elink_params *params, u8 mode); 253 typedef void (*phy_specific_func_t)(struct elink_phy *phy, 254 struct elink_params *params, u32 action); 255 struct elink_reg_set { 256 u8 devad; 257 u16 reg; 258 u16 val; 259 }; 260 261 struct elink_phy { 262 u32 type; 263 264 /* Loaded during init */ 265 u8 addr; 266 u8 def_md_devad; 267 u16 flags; 268 /* No Over-Current detection */ 269 #define ELINK_FLAGS_NOC (1<<1) 270 /* Fan failure detection required */ 271 #define ELINK_FLAGS_FAN_FAILURE_DET_REQ (1<<2) 272 /* Initialize first the XGXS and only then the phy itself */ 273 #define ELINK_FLAGS_INIT_XGXS_FIRST (1<<3) 274 #define ELINK_FLAGS_WC_DUAL_MODE (1<<4) 275 #define ELINK_FLAGS_4_PORT_MODE (1<<5) 276 #define ELINK_FLAGS_REARM_LATCH_SIGNAL (1<<6) 277 #define ELINK_FLAGS_SFP_NOT_APPROVED (1<<7) 278 #define ELINK_FLAGS_MDC_MDIO_WA (1<<8) 279 #define ELINK_FLAGS_DUMMY_READ (1<<9) 280 #define ELINK_FLAGS_MDC_MDIO_WA_B0 (1<<10) 281 #define ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC (1<<11) 282 #define ELINK_FLAGS_TX_ERROR_CHECK (1<<12) 283 #define ELINK_FLAGS_EEE (1<<13) 284 #define ELINK_FLAGS_TEMPERATURE (1<<14) 285 #define ELINK_FLAGS_MDC_MDIO_WA_G (1<<15) 286 287 /* preemphasis values for the rx side */ 288 u16 rx_preemphasis[4]; 289 290 /* preemphasis values for the tx side */ 291 u16 tx_preemphasis[4]; 292 293 /* EMAC address for access MDIO */ 294 u32 mdio_ctrl; 295 296 u32 supported; 297 #define ELINK_SUPPORTED_10baseT_Half (1<<0) 298 #define ELINK_SUPPORTED_10baseT_Full (1<<1) 299 #define ELINK_SUPPORTED_100baseT_Half (1<<2) 300 #define ELINK_SUPPORTED_100baseT_Full (1<<3) 301 #define ELINK_SUPPORTED_1000baseT_Full (1<<4) 302 #define ELINK_SUPPORTED_2500baseX_Full (1<<5) 303 #define ELINK_SUPPORTED_10000baseT_Full (1<<6) 304 #define ELINK_SUPPORTED_TP (1<<7) 305 #define ELINK_SUPPORTED_FIBRE (1<<8) 306 #define ELINK_SUPPORTED_Autoneg (1<<9) 307 #define ELINK_SUPPORTED_Pause (1<<10) 308 #define ELINK_SUPPORTED_Asym_Pause (1<<11) 309 #define ELINK_SUPPORTED_20000baseMLD2_Full (1<<21) 310 #define ELINK_SUPPORTED_20000baseKR2_Full (1<<22) 311 312 u32 media_type; 313 #define ELINK_ETH_PHY_UNSPECIFIED 0x0 314 #define ELINK_ETH_PHY_SFPP_10G_FIBER 0x1 315 #define ELINK_ETH_PHY_XFP_FIBER 0x2 316 #define ELINK_ETH_PHY_DA_TWINAX 0x3 317 #define ELINK_ETH_PHY_BASE_T 0x4 318 #define ELINK_ETH_PHY_SFP_1G_FIBER 0x5 319 #define ELINK_ETH_PHY_KR 0xf0 320 #define ELINK_ETH_PHY_CX4 0xf1 321 #define ELINK_ETH_PHY_NOT_PRESENT 0xff 322 323 /* The address in which version is located*/ 324 u32 ver_addr; 325 326 u16 req_flow_ctrl; 327 328 u16 req_line_speed; 329 330 u32 speed_cap_mask; 331 332 u16 req_duplex; 333 u16 rsrv; 334 /* Called per phy/port init, and it configures LASI, speed, autoneg, 335 duplex, flow control negotiation, etc. */ 336 config_init_t config_init; 337 338 /* Called due to interrupt. It determines the link, speed */ 339 read_status_t read_status; 340 341 /* Called when driver is unloading. Should reset the phy */ 342 link_reset_t link_reset; 343 344 /* Set the loopback configuration for the phy */ 345 config_loopback_t config_loopback; 346 347 /* Format the given raw number into str up to len */ 348 format_fw_ver_t format_fw_ver; 349 350 /* Reset the phy (both ports) */ 351 hw_reset_t hw_reset; 352 353 /* Set link led mode (on/off/oper)*/ 354 set_link_led_t set_link_led; 355 356 /* PHY Specific tasks */ 357 phy_specific_func_t phy_specific_func; 358 #define ELINK_DISABLE_TX 1 359 #define ELINK_ENABLE_TX 2 360 #define ELINK_PHY_INIT 3 361 }; 362 363 /* Inputs parameters to the CLC */ 364 struct elink_params { 365 366 u8 port; 367 368 /* Default / User Configuration */ 369 u8 loopback_mode; 370 #define ELINK_LOOPBACK_NONE 0 371 #define ELINK_LOOPBACK_EMAC 1 372 #define ELINK_LOOPBACK_BMAC 2 373 #define ELINK_LOOPBACK_XGXS 3 374 #define ELINK_LOOPBACK_EXT_PHY 4 375 #define ELINK_LOOPBACK_EXT 5 376 #define ELINK_LOOPBACK_UMAC 6 377 #define ELINK_LOOPBACK_XMAC 7 378 379 /* Device parameters */ 380 u8 mac_addr[6]; 381 382 u16 req_duplex[ELINK_LINK_CONFIG_SIZE]; 383 u16 req_flow_ctrl[ELINK_LINK_CONFIG_SIZE]; 384 385 u16 req_line_speed[ELINK_LINK_CONFIG_SIZE]; /* Also determine AutoNeg */ 386 387 /* shmem parameters */ 388 u32 shmem_base; 389 u32 shmem2_base; 390 u32 speed_cap_mask[ELINK_LINK_CONFIG_SIZE]; 391 u32 switch_cfg; 392 #define ELINK_SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH 393 #define ELINK_SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH 394 #define ELINK_SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT 395 396 u32 lane_config; 397 398 /* Phy register parameter */ 399 u32 chip_id; 400 401 /* features */ 402 u32 feature_config_flags; 403 #define ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0) 404 #define ELINK_FEATURE_CONFIG_PFC_ENABLED (1<<1) 405 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2) 406 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3) 407 #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC (1<<4) 408 #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC (1<<5) 409 #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC (1<<6) 410 #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC (1<<7) 411 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX (1<<8) 412 #define ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED (1<<9) 413 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1<<10) 414 #define ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET (1<<11) 415 #define ELINK_FEATURE_CONFIG_IEEE_PHY_TEST (1<<12) 416 #define ELINK_FEATURE_CONFIG_MT_SUPPORT (1<<13) 417 #define ELINK_FEATURE_CONFIG_BOOT_FROM_SAN (1<<14) 418 419 /* Will be populated during common init */ 420 struct elink_phy phy[ELINK_MAX_PHYS]; 421 422 /* Will be populated during common init */ 423 u8 num_phys; 424 425 u8 rsrv; 426 427 /* Used to configure the EEE Tx LPI timer, has several modes of 428 * operation, according to bits 29:28 - 429 * 2'b00: Timer will be configured by nvram, output will be the value 430 * from nvram. 431 * 2'b01: Timer will be configured by nvram, output will be in 432 * microseconds. 433 * 2'b10: bits 1:0 contain an nvram value which will be used instead 434 * of the one located in the nvram. Output will be that value. 435 * 2'b11: bits 19:0 contain the idle timer in microseconds; output 436 * will be in microseconds. 437 * Bits 31:30 should be 2'b11 in order for EEE to be enabled. 438 */ 439 u32 eee_mode; 440 #define ELINK_EEE_MODE_NVRAM_BALANCED_TIME (0xa00) 441 #define ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME (0x100) 442 #define ELINK_EEE_MODE_NVRAM_LATENCY_TIME (0x6000) 443 #define ELINK_EEE_MODE_NVRAM_MASK (0x3) 444 #define ELINK_EEE_MODE_TIMER_MASK (0xfffff) 445 #define ELINK_EEE_MODE_OUTPUT_TIME (1<<28) 446 #define ELINK_EEE_MODE_OVERRIDE_NVRAM (1<<29) 447 #define ELINK_EEE_MODE_ENABLE_LPI (1<<30) 448 #define ELINK_EEE_MODE_ADV_LPI (1<<31) 449 450 u16 hw_led_mode; /* part of the hw_config read from the shmem */ 451 u32 multi_phy_config; 452 453 /* Device pointer passed to all callback functions */ 454 struct elink_dev *cb; 455 u16 req_fc_auto_adv; /* Should be set to TX / BOTH when 456 req_flow_ctrl is set to AUTO */ 457 u16 link_flags; 458 #define ELINK_LINK_FLAGS_INT_DISABLED (1<<0) 459 #define ELINK_PHY_INITIALIZED (1<<1) 460 u32 lfa_base; 461 462 /* The same definitions as the shmem2 parameter */ 463 u32 link_attr_sync; 464 }; 465 466 /* Output parameters */ 467 struct elink_vars { 468 u8 phy_flags; 469 #define PHY_XGXS_FLAG (1<<0) 470 #define PHY_SGMII_FLAG (1<<1) 471 #define PHY_PHYSICAL_LINK_FLAG (1<<2) 472 #define PHY_HALF_OPEN_CONN_FLAG (1<<3) 473 #define PHY_OVER_CURRENT_FLAG (1<<4) 474 #define PHY_SFP_TX_FAULT_FLAG (1<<5) 475 476 u8 mac_type; 477 #define ELINK_MAC_TYPE_NONE 0 478 #define ELINK_MAC_TYPE_EMAC 1 479 #define ELINK_MAC_TYPE_BMAC 2 480 #define ELINK_MAC_TYPE_UMAC 3 481 #define ELINK_MAC_TYPE_XMAC 4 482 483 u8 phy_link_up; /* internal phy link indication */ 484 u8 link_up; 485 486 u16 line_speed; 487 u16 duplex; 488 489 u16 flow_ctrl; 490 u16 ieee_fc; 491 492 /* The same definitions as the shmem parameter */ 493 u32 link_status; 494 u32 eee_status; 495 u8 fault_detected; 496 u8 check_kr2_recovery_cnt; 497 #define ELINK_CHECK_KR2_RECOVERY_CNT 5 498 u16 periodic_flags; 499 #define ELINK_PERIODIC_FLAGS_LINK_EVENT 0x0001 500 501 u32 aeu_int_mask; 502 u8 rx_tx_asic_rst; 503 u8 turn_to_run_wc_rt; 504 u16 rsrv2; 505 506 }; 507 508 /***********************************************************/ 509 /* Functions */ 510 /***********************************************************/ 511 elink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars); 512 513 #ifndef EXCLUDE_LINK_RESET 514 /* Reset the link. Should be called when driver or interface goes down 515 Before calling phy firmware upgrade, the reset_ext_phy should be set 516 to 0 */ 517 elink_status_t elink_link_reset(struct elink_params *params, struct elink_vars *vars, 518 u8 reset_ext_phy); 519 #endif 520 elink_status_t elink_lfa_reset(struct elink_params *params, struct elink_vars *vars); 521 /* elink_link_update should be called upon link interrupt */ 522 elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars); 523 524 /* use the following phy functions to read/write from external_phy 525 In order to use it to read/write internal phy registers, use 526 ELINK_DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as 527 the register */ 528 elink_status_t elink_phy_read(struct elink_params *params, u8 phy_addr, 529 u8 devad, u16 reg, u16 *ret_val); 530 531 elink_status_t elink_phy_write(struct elink_params *params, u8 phy_addr, 532 u8 devad, u16 reg, u16 val); 533 534 /* Reads the link_status from the shmem, 535 and update the link vars accordingly */ 536 void elink_link_status_update(struct elink_params *input, 537 struct elink_vars *output); 538 #ifdef ELINK_ENHANCEMENTS 539 /* returns string representing the fw_version of the external phy */ 540 elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params, u8 *version, 541 u16 len); 542 #endif 543 544 /* Set/Unset the led 545 Basically, the CLC takes care of the led for the link, but in case one needs 546 to set/unset the led unnaturally, set the "mode" to ELINK_LED_MODE_OPER to 547 blink the led, and ELINK_LED_MODE_OFF to set the led off.*/ 548 elink_status_t elink_set_led(struct elink_params *params, 549 struct elink_vars *vars, u8 mode, u32 speed); 550 #define ELINK_LED_MODE_OFF 0 551 #define ELINK_LED_MODE_ON 1 552 #define ELINK_LED_MODE_OPER 2 553 #define ELINK_LED_MODE_FRONT_PANEL_OFF 3 554 555 #ifdef ELINK_ENHANCEMENTS 556 /* elink_handle_module_detect_int should be called upon module detection 557 interrupt */ 558 void elink_handle_module_detect_int(struct elink_params *params); 559 560 /* Get the actual link status. In case it returns ELINK_STATUS_OK, link is up, 561 otherwise link is down*/ 562 elink_status_t elink_test_link(struct elink_params *params, struct elink_vars *vars, 563 u8 is_serdes); 564 565 #endif 566 567 /* One-time initialization for external phy after power up */ 568 elink_status_t elink_common_init_phy(struct elink_dev *cb, u32 shmem_base_path[], 569 u32 shmem2_base_path[], u32 chip_id, u8 one_port_enabled); 570 571 /* Reset the external PHY using GPIO */ 572 void elink_ext_phy_hw_reset(struct elink_dev *cb, u8 port); 573 574 #ifdef ELINK_ENHANCEMENTS 575 /* Reset the external of SFX7101 */ 576 void elink_sfx7101_sp_sw_reset(struct elink_dev *cb, struct elink_phy *phy); 577 #endif 578 579 /* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */ 580 elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy, 581 struct elink_params *params, u8 dev_addr, 582 u16 addr, u16 byte_cnt, u8 *o_buf); 583 584 void elink_hw_reset_phy(struct elink_params *params); 585 586 /* Check swap bit and adjust PHY order */ 587 u32 elink_phy_selection(struct elink_params *params); 588 589 #ifndef EXCLUDE_COMMON_INIT 590 /* Probe the phys on board, and populate them in "params" */ 591 elink_status_t elink_phy_probe(struct elink_params *params); 592 593 /* Checks if fan failure detection is required on one of the phys on board */ 594 u8 elink_fan_failure_det_req(struct elink_dev *cb, u32 shmem_base, 595 u32 shmem2_base, u8 port); 596 597 /* Open / close the gate between the NIG and the BRB */ 598 void elink_set_rx_filter(struct elink_params *params, u8 en); 599 #endif /* EXCLUDE_COMMON_INIT */ 600 601 /* DCBX structs */ 602 603 /* Number of maximum COS per chip */ 604 #define ELINK_DCBX_E2E3_MAX_NUM_COS (2) 605 #define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0 (6) 606 #define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 (3) 607 #define ELINK_DCBX_E3B0_MAX_NUM_COS ( \ 608 ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0, \ 609 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1)) 610 611 #define ELINK_DCBX_MAX_NUM_COS ( \ 612 ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS, \ 613 ELINK_DCBX_E2E3_MAX_NUM_COS)) 614 615 /* PFC port configuration params */ 616 struct elink_nig_brb_pfc_port_params { 617 /* NIG */ 618 u32 pause_enable; 619 u32 llfc_out_en; 620 u32 llfc_enable; 621 u32 pkt_priority_to_cos; 622 u8 num_of_rx_cos_priority_mask; 623 u32 rx_cos_priority_mask[ELINK_DCBX_MAX_NUM_COS]; 624 u32 llfc_high_priority_classes; 625 u32 llfc_low_priority_classes; 626 }; 627 628 629 /* ETS port configuration params */ 630 struct elink_ets_bw_params { 631 u8 bw; 632 }; 633 634 struct elink_ets_sp_params { 635 /** 636 * valid values are 0 - 5. 0 is highest strict priority. 637 * There can't be two COS's with the same pri. 638 */ 639 u8 pri; 640 }; 641 642 enum elink_cos_state { 643 elink_cos_state_strict = 0, 644 elink_cos_state_bw = 1, 645 }; 646 647 struct elink_ets_cos_params { 648 enum elink_cos_state state ; 649 union { 650 struct elink_ets_bw_params bw_params; 651 struct elink_ets_sp_params sp_params; 652 } params; 653 }; 654 655 struct elink_ets_params { 656 u8 num_of_cos; /* Number of valid COS entries*/ 657 struct elink_ets_cos_params cos[ELINK_DCBX_MAX_NUM_COS]; 658 }; 659 660 /* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB 661 * when link is already up 662 */ 663 elink_status_t elink_update_pfc(struct elink_params *params, 664 struct elink_vars *vars, 665 struct elink_nig_brb_pfc_port_params *pfc_params); 666 667 668 /* Used to configure the ETS to disable */ 669 elink_status_t elink_ets_disabled(struct elink_params *params, 670 struct elink_vars *vars); 671 672 /* Used to configure the ETS to BW limited */ 673 void elink_ets_bw_limit(const struct elink_params *params, const u32 cos0_bw, 674 const u32 cos1_bw); 675 676 /* Used to configure the ETS to strict */ 677 elink_status_t elink_ets_strict(const struct elink_params *params, const u8 strict_cos); 678 679 680 /* Configure the COS to ETS according to BW and SP settings.*/ 681 elink_status_t elink_ets_e3b0_config(const struct elink_params *params, 682 const struct elink_vars *vars, 683 struct elink_ets_params *ets_params); 684 /* Read pfc statistic*/ 685 #ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */ 686 void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars, 687 u32 pfc_frames_sent[2], 688 u32 pfc_frames_received[2]); 689 #endif 690 void elink_init_mod_abs_int(struct elink_dev *cb, struct elink_vars *vars, 691 u32 chip_id, u32 shmem_base, u32 shmem2_base, 692 u8 port); 693 #ifndef BNX2X_ADD /* ! BNX2X_ADD */ 694 elink_status_t elink_sfp_module_detection(struct elink_phy *phy, 695 struct elink_params *params); 696 #endif 697 698 void elink_period_func(struct elink_params *params, struct elink_vars *vars); 699 700 #ifndef BNX2X_ADD /* ! BNX2X_ADD */ 701 elink_status_t elink_check_half_open_conn(struct elink_params *params, 702 struct elink_vars *vars, u8 notify); 703 #endif 704 705 void elink_enable_pmd_tx(struct elink_params *params); 706 707 #ifndef EXCLUDE_FROM_BNX2X 708 elink_status_t elink_pre_init_phy(struct elink_dev *cb, 709 u32 shmem_base, 710 u32 shmem2_base, 711 u32 chip_id, 712 u8 port); 713 elink_status_t elink_validate_cc_dmi(u8 *sfp_a2_buf); 714 715 #endif /* EXCLUDE_FROM_BNX2X */ 716 #ifdef ELINK_AUX_POWER 717 void elink_adjust_phy_func_ptr(struct elink_params *params); 718 719 elink_status_t elink_get_phy_temperature(struct elink_params *params, 720 u32 *temp_reading, u8 path, u8 port); 721 722 u8 elink_phy_is_temperature_support(struct elink_params *params); 723 void set_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 val); 724 int get_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 *val); 725 int elink_warpcore_get_sigdet(struct elink_phy *phy, 726 struct elink_params *params); 727 void elink_force_link(struct elink_params *params, int enable); 728 #endif 729 730 #endif /* __ELINK_H */ 731 732