1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_USB_EHCI_H 27 #define _SYS_USB_EHCI_H 28 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* 35 * Enhanced Host Controller Driver (EHCI) 36 * 37 * The EHCI driver is a software driver which interfaces to the Universal 38 * Serial Bus layer (USBA) and the Host Controller (HC). The interface to 39 * the Host Controller is defined by the EHCI Host Controller Interface. 40 * 41 * This header file describes the registers and data structures shared by 42 * the EHCI USB controller (HC) and the EHCI Driver. 43 */ 44 45 #include <sys/types.h> 46 #include <sys/pci.h> 47 #include <sys/sunddi.h> 48 #include <sys/sunndi.h> 49 #include <sys/ndi_impldefs.h> 50 #include <sys/disp.h> 51 52 #include <sys/usb/usba.h> 53 54 #include <sys/usb/usba/hcdi.h> 55 56 #include <sys/usb/hubd/hub.h> 57 #include <sys/usb/usba/hubdi.h> 58 #include <sys/usb/hubd/hubdvar.h> 59 60 #include <sys/id32.h> 61 62 #define EHCI_MAX_RH_PORTS 31 /* Maximum root hub ports */ 63 64 65 /* 66 * Each EHCI buffer can hold upto 4k bytes of data. Hence there is a 67 * restriction of 4k alignment while allocating a dma buffer. 68 */ 69 #define EHCI_4K_ALIGN 0x1000 70 71 /* 72 * USB Host controller DMA scatter gather list defines for 73 * Sparc and non-sparc architectures. 74 */ 75 #if defined(__sparc) 76 #define EHCI_DMA_ATTR_MAX_XFER 0xffffffffull 77 #define EHCI_DMA_ATTR_COUNT_MAX 0xffffffffull 78 #define EHCI_DMA_ATTR_GRANULAR 512 79 #define EHCI_DMA_ATTR_ALIGNMENT EHCI_4K_ALIGN 80 #else 81 #define EHCI_DMA_ATTR_MAX_XFER 0x00ffffffull 82 #define EHCI_DMA_ATTR_COUNT_MAX 0x00ffffffull 83 #define EHCI_DMA_ATTR_GRANULAR 1 84 #define EHCI_DMA_ATTR_ALIGNMENT EHCI_4K_ALIGN 85 #endif 86 87 /* Set the default data structure (QTD,QH,SITD,ITD) to a 32 byte alignment */ 88 #define EHCI_DMA_ATTR_TD_QH_ALIGNMENT 0x0020 89 #define EHCI_DMA_ATTR_PFL_ALIGNMENT EHCI_4K_ALIGN 90 91 /* TW scatter/gatter list defines */ 92 #define EHCI_DMA_ATTR_TW_SGLLEN 0x7fffffff 93 94 /* 95 * EHCI Capability Registers 96 * 97 * The registers specify the limits, restrictions and capabilities of the 98 * specific EHCI Host Controller implementation. 99 */ 100 typedef volatile struct ehci_caps { 101 uint8_t ehci_caps_length; /* Capability register length */ 102 uint8_t ehci_pad; /* Reserved */ 103 uint16_t ehci_version; /* Interface version number */ 104 uint32_t ehci_hcs_params; /* Structural paramters */ 105 uint32_t ehci_hcc_params; /* Capability paramters */ 106 uint8_t ehci_port_route[8]; /* Companion port route */ 107 } ehci_caps_t; 108 109 /* 110 * EHCI revision 111 * 112 * EHCI driver supports EHCI host controllers compliant to 0.95 and higher 113 * revisions of EHCI specifications. 114 */ 115 #define EHCI_REVISION_0_95 0x95 /* Revision 0.95 */ 116 117 /* EHCI HCS Params Register Bits */ 118 #define EHCI_HCS_PORT_INDICATOR 0x00010000 /* Port indicator control */ 119 #define EHCI_HCS_NUM_COMP_CTRLS 0x0000F000 /* No of companion ctrls */ 120 #define EHCI_HCS_NUM_COMP_CTRL_SHIFT 12 121 #define EHCI_HCS_NUM_PORTS_CC 0x00000F00 /* Ports per classic ctrls */ 122 #define EHCI_HCS_NUM_PORTS_CC_SHIFT 8 123 #define EHCI_HCS_PORT_ROUTING_RULES 0x00000080 /* Port routing rules */ 124 #define EHCI_HCS_PORT_POWER_CONTROL 0x00000010 /* Port power control */ 125 #define EHCI_HCS_NUM_PORTS 0x0000000F /* No of root hub ports */ 126 127 /* EHCI HCC Params Register Bits */ 128 #define EHCI_HCC_EECP 0x0000FF00 /* Extended capbilities */ 129 #define EHCI_HCC_EECP_SHIFT 8 130 #define EHCI_HCC_EECP_MIN_OFFSET 0x00000040 /* Minimum valid offset */ 131 #define EHCI_HCC_ISOCH_SCHED_THRESHOLD 0x000000F0 /* Isoch sched threshold */ 132 #define EHCI_HCC_ASYNC_SCHED_PARK_CAP 0x00000004 /* Async schedule park cap */ 133 #define EHCI_HCC_PROG_FRAME_LIST_FLAG 0x00000002 /* Prog frame list flag */ 134 #define EHCI_HCC_64BIT_ADDR_CAP 0x00000001 /* 64bit addr capability */ 135 136 /* EHCI Port Route Register Bits */ 137 #define EHCI_PORT_ROUTE_EVEN 0x0F /* Classic even port route */ 138 #define EHCI_PORT_ROUTE_ODD 0xF0 /* Classic odd port route */ 139 #define EHCI_PORT_ROUTE_ODD_SHIFT 4 140 141 142 /* 143 * EHCI Operational Registers 144 * 145 * The EHCI Host Controller contains a set of on-chip operational registers 146 * which are mapped into a non-cacheable portion of the system addressable 147 * space. These registers are also used by the EHCI Host Controller Driver. 148 * This structure must be aligned to 32 byte boundary. 149 */ 150 typedef volatile struct ehci_regs { 151 /* Control and status registers */ 152 uint32_t ehci_command; /* USB commands */ 153 uint32_t ehci_status; /* USB status */ 154 uint32_t ehci_interrupt; /* Interrupt enable */ 155 uint32_t ehci_frame_index; /* Frame index */ 156 157 /* Memory pointer registers */ 158 uint32_t ehci_ctrl_segment; /* Control data segment */ 159 uint32_t ehci_periodic_list_base; /* Period frm list base addr */ 160 uint32_t ehci_async_list_addr; /* Async list base address */ 161 uint32_t ehci_pad[9]; /* Head of the bulk list */ 162 163 /* Root hub registers */ 164 uint32_t ehci_config_flag; /* Config Flag */ 165 uint32_t ehci_rh_port_status[EHCI_MAX_RH_PORTS]; 166 /* Root hub port status and control information */ 167 } ehci_regs_t; 168 169 /* EHCI Command Register Bits */ 170 #define EHCI_CMD_INTR_THRESHOLD 0x00FF0000 /* Intr threshold control */ 171 #define EHCI_CMD_INTR_SHIFT 16 172 #define EHCI_CMD_01_INTR 0x00010000 /* 01 micro-frame */ 173 #define EHCI_CMD_02_INTR 0x00020000 /* 02 micro-frames */ 174 #define EHCI_CMD_04_INTR 0x00040000 /* 04 micro-frames */ 175 #define EHCI_CMD_08_INTR 0x00080000 /* 08 micro-frames */ 176 #define EHCI_CMD_16_INTR 0x00100000 /* 16 micro-frames */ 177 #define EHCI_CMD_32_INTR 0x00200000 /* 32 micro-frames */ 178 #define EHCI_CMD_64_INTR 0x00400000 /* 64 micro-frames */ 179 180 #define EHCI_CMD_ASYNC_PARK_ENABLE 0x00000800 /* Async sched park enable */ 181 #define EHCI_CMD_ASYNC_PARK_COUNT 0x00000300 /* Async sched park count */ 182 #define EHCI_CMD_ASYNC_PARK_COUNT_1 0x00000100 /* Async sched park cnt 1 */ 183 #define EHCI_CMD_ASYNC_PARK_COUNT_2 0x00000200 /* Async sched park cnt 2 */ 184 #define EHCI_CMD_ASYNC_PARK_COUNT_3 0x00000300 /* Async sched park cnt 3 */ 185 #define EHCI_CMD_ASYNC_PARK_SHIFT 8 186 #define EHCI_CMD_LIGHT_HC_RESET 0x00000080 /* Light host ctrl reset */ 187 #define EHCI_CMD_INTR_ON_ASYNC_ADVANCE 0x00000040 /* Async advance doorbell */ 188 #define EHCI_CMD_ASYNC_SCHED_ENABLE 0x00000020 /* Async schedule enable */ 189 #define EHCI_CMD_PERIODIC_SCHED_ENABLE 0x00000010 /* Periodic sched enable */ 190 #define EHCI_CMD_FRAME_LIST_SIZE 0x0000000C /* Frame list size */ 191 #define EHCI_CMD_FRAME_LIST_SIZE_SHIFT 2 192 #define EHCI_CMD_FRAME_1024_SIZE 0x00000000 /* 1024 frame list size */ 193 #define EHCI_CMD_FRAME_512_SIZE 0x00000004 /* 512 frame list size */ 194 #define EHCI_CMD_FRAME_256_SIZE 0X00000008 /* 256 frame list size */ 195 #define EHCI_CMD_HOST_CTRL_RESET 0x00000002 /* Host controller reset */ 196 #define EHCI_CMD_HOST_CTRL_RS 0x00000001 /* Host ctrl run or stop */ 197 #define EHCI_CMD_HOST_CTRL_RUN 0x00000001 /* Host controller run */ 198 #define EHCI_CMD_HOST_CTRL_STOP 0x00000000 /* Host controller stop */ 199 200 /* EHCI Status Register Bits */ 201 #define EHCI_STS_ASYNC_SCHED_STATUS 0x00008000 /* Async schedule status */ 202 #define EHCI_STS_PERIODIC_SCHED_STATUS 0x00004000 /* Periodic sched status */ 203 #define EHCI_STS_EMPTY_ASYNC_SCHEDULE 0x00002000 /* Empty async schedule */ 204 #define EHCI_STS_HOST_CTRL_HALTED 0x00001000 /* Host controller Halted */ 205 #define EHCI_STS_ASYNC_ADVANCE_INTR 0x00000020 /* Intr on async advance */ 206 #define EHCI_STS_HOST_SYSTEM_ERROR_INTR 0x00000010 /* Host system error */ 207 #define EHCI_STS_FRM_LIST_ROLLOVER_INTR 0x00000008 /* Frame list rollover */ 208 #define EHCI_STS_RH_PORT_CHANGE_INTR 0x00000004 /* Port change detect */ 209 #define EHCI_STS_USB_ERROR_INTR 0x00000002 /* USB error interrupt */ 210 #define EHCI_STS_USB_INTR 0x00000001 /* USB interrupt */ 211 212 /* EHCI Interrupt Register Bits */ 213 #define EHCI_INTR_ASYNC_ADVANCE 0x00000020 /* Async advance interrupt */ 214 #define EHCI_INTR_HOST_SYSTEM_ERROR 0x00000010 /* Host system error intr */ 215 #define EHCI_INTR_FRAME_LIST_ROLLOVER 0x00000008 /* Framelist rollover intr */ 216 #define EHCI_INTR_RH_PORT_CHANGE 0x00000004 /* Port change interrupt */ 217 #define EHCI_INTR_USB_ERROR 0x00000002 /* USB error interrupt */ 218 #define EHCI_INTR_USB 0x00000001 /* USB interrupt */ 219 220 /* EHCI Frame Index Register Bits */ 221 #define EHCI_FRAME_INDEX 0x00003FFF /* Frame index */ 222 #define EHCI_FRAME_1024 0x00003FFF /* 1024 elements */ 223 #define EHCI_FRAME_0512 0x00001FFF /* 512 elements */ 224 #define EHCI_FRAME_0256 0x00000FFF /* 256 elements */ 225 226 /* EHCI Control Data Structure Segment Register Bits */ 227 /* Most significant 32 bits for all EHCI data structures in 64bit addressing */ 228 #define EHCI_CTRLD_SEGMENT 0xFFFFFFFF /* Control data segment */ 229 230 /* EHCI Periodic Frame List Base Address Register Bits */ 231 #define EHCI_PERIODIC_LIST_BASE 0xFFFFF000 /* Periodic framelist addr */ 232 #define EHCI_PERIODIC_LIST_BASE_SHIFT 12 233 234 /* EHCI Asynchronous List Address Register Bits */ 235 #define EHCI_ASYNC_LIST_ADDR 0xFFFFFFE0 /* Async list address */ 236 #define EHCI_ASYNC_LIST_ADDR_SHIFT 5 237 238 /* EHCI Config Flag Register Bits */ 239 #define EHCI_CONFIG_FLAG 0x00000001 /* Route host controllers */ 240 #define EHCI_CONFIG_FLAG_CLASSIC 0x00000000 /* Route to Classic ctrl */ 241 #define EHCI_CONFIG_FLAG_EHCI 0x00000001 /* Route to EHCI ctrl */ 242 243 /* EHCI Root Hub Port Status and Control Register Bits */ 244 #define EHCI_RH_PORT_OVER_CURENT_ENABLE 0x00400000 /* Over current enable */ 245 #define EHCI_RH_PORT_DISCONNECT_ENABLE 0x00200000 /* Disconnect enable */ 246 #define EHCI_RH_PORT_CONNECT_ENABLE 0x00100000 /* Connect enable */ 247 #define EHCI_RH_PORT_INDICATOR 0x0000C000 /* Port indicator control */ 248 #define EHCI_RH_PORT_IND_SHIFT 14 249 #define EHCI_RH_PORT_IND_OFF 0x00000000 /* Port indicators off */ 250 #define EHCI_RH_PORT_IND_AMBER 0x00004000 /* Amber port indicator */ 251 #define EHCI_RH_PORT_IND_GREEN 0x00008000 /* Green port indicator */ 252 #define EHCI_RH_PORT_OWNER 0x00002000 /* Port ownership */ 253 #define EHCI_RH_PORT_OWNER_CLASSIC 0x00002000 /* Classic port ownership */ 254 #define EHCI_RH_PORT_OWNER_EHCI 0x00000000 /* EHCI port ownership */ 255 #define EHCI_RH_PORT_POWER 0x00001000 /* Port power */ 256 #define EHCI_RH_PORT_LINE_STATUS 0x00000C00 /* USB speed line status */ 257 #define EHCI_RH_PORT_LOW_SPEED 0x00000400 /* Low speed */ 258 #define EHCI_RH_PORT_RESET 0x00000100 /* Port reset */ 259 #define EHCI_RH_PORT_SUSPEND 0x00000080 /* Port suspend */ 260 #define EHCI_RH_PORT_RESUME 0x00000040 /* Port resume */ 261 #define EHCI_RH_PORT_OVER_CURR_CHANGE 0x00000020 /* Over current change */ 262 #define EHCI_RH_PORT_OVER_CURR_ACTIVE 0x00000010 /* Over current active */ 263 #define EHCI_RH_PORT_ENABLE_CHANGE 0x00000008 /* Port enable change */ 264 #define EHCI_RH_PORT_ENABLE 0x00000004 /* Port enable */ 265 #define EHCI_RH_PORT_CONNECT_STS_CHANGE 0x00000002 /* Connect status change */ 266 #define EHCI_RH_PORT_CONNECT_STATUS 0x00000001 /* Connect status */ 267 268 /* Root hub port change bits mask */ 269 #define EHCI_RH_PORT_CLEAR_MASK 0x0000002A /* Clear bits mask */ 270 271 272 /* 273 * EHCI Extended Capability Registers 274 * 275 * Currently this register only specifies BIOS handoff information. 276 */ 277 #define EHCI_EX_CAP_SPECIFICS 0xFFFF0000 278 #define EHCI_EX_CAP_SPECIFICS_SHIFT 16 279 #define EHCI_EX_CAP_NEXT_PTR 0x0000FF00 280 #define EHCI_EX_CAP_NEXT_PTR_SHIFT 8 281 #define EHCI_EX_CAP_ID 0x000000FF 282 #define EHCI_EX_CAP_ID_SHIFT 0 283 #define EHCI_EX_CAP_ID_BIOS_HANDOFF 1 284 285 #define EHCI_LEGSUP_OS_OWNED_SEM 0x01000000 286 #define EHCI_LEGSUP_BIOS_OWNED_SEM 0x00010000 287 288 289 /* 290 * Host Controller Periodic Frame List Area 291 * 292 * The Host Controller Periodic Frame List Area is a 4K structre of system 293 * memory that is established by the Host Controller Driver (HCD) and this 294 * structre is used for communication between HCD and HC. The HCD maintains 295 * a pointer to this structure in the Host Controller (HC). This structure 296 * must be aligned to a 4K boundary. There are 1024 periodic frame list 297 * entries. 298 */ 299 300 #define EHCI_NUM_INTR_QH_LISTS 32 /* No of intr lists */ 301 #define EHCI_NUM_STATIC_NODES 63 /* No of static QHs */ 302 #define EHCI_NUM_PERIODIC_FRAME_LISTS 1024 /* No of entries */ 303 304 typedef volatile struct ehci_periodic_frame_list { 305 uint32_t ehci_periodic_frame_list_table[ 306 EHCI_NUM_PERIODIC_FRAME_LISTS]; /* 1024 lists */ 307 } ehci_periodic_frame_list_t; 308 309 310 /* 311 * Host Controller Queue Head 312 * 313 * An Queue Head (QH) is a memory structure that describes the information 314 * necessary for the Host Controller to communicate with a device endpoint 315 * except High Speed and Full Speed Isochronous's endpoints. An QH includes 316 * a Queue Element Transfer Descriptor (QTD) pointer. This structure must 317 * be aligned to a 32 byte boundary. 318 */ 319 typedef volatile struct ehci_qh { 320 /* Endpoint capabilities or characteristics */ 321 uint32_t qh_link_ptr; /* Next QH or ITD or SITD */ 322 uint32_t qh_ctrl; /* Generic control information */ 323 uint32_t qh_split_ctrl; /* Split transaction control info */ 324 uint32_t qh_curr_qtd; /* Current QTD */ 325 326 /* Tranfer overlay */ 327 uint32_t qh_next_qtd; /* Next QTD */ 328 uint32_t qh_alt_next_qtd; /* Next alternate QTD */ 329 uint32_t qh_status; /* Status of current QTD */ 330 uint32_t qh_buf[5]; /* Buffer pointers */ 331 uint32_t qh_buf_high[5]; /* For 64 bit addressing */ 332 333 /* HCD private fields */ 334 uint32_t qh_dummy_qtd; /* Current dummy qtd */ 335 uint32_t qh_prev; /* Prevous QH */ 336 uint32_t qh_state; /* QH's state */ 337 uint32_t qh_reclaim_next; /* Next QH on reclaim list */ 338 uint32_t qh_reclaim_frame; /* Reclaim usb frame number */ 339 uint8_t qh_pad[8]; /* Required padding */ 340 } ehci_qh_t; 341 342 /* 343 * qh_link_ptr control bits. 344 */ 345 #define EHCI_QH_LINK_PTR 0xFFFFFFE0 /* QH link ptr mask */ 346 #define EHCI_QH_LINK_REF 0x00000006 /* Ref to QH/ITD/SITD */ 347 #define EHCI_QH_LINK_REF_ITD 0x00000000 /* Isoch QTD pointer */ 348 #define EHCI_QH_LINK_REF_QH 0x00000002 /* QH pointer */ 349 #define EHCI_QH_LINK_REF_SITD 0x00000004 /* SIQTD pointer */ 350 #define EHCI_QH_LINK_REF_FSTN 0x00000006 /* FSTN pointer */ 351 #define EHCI_QH_LINK_PTR_VALID 0x00000001 /* Link ptr validity */ 352 353 /* 354 * qh_ctrl control bits. 355 */ 356 #define EHCI_QH_CTRL_NC_RL 0xF0000000 /* Nak count reload */ 357 #define EHCI_QH_CTRL_NC_RL_SHIFT 28 /* NC reload shift */ 358 #define EHCI_QH_CTRL_MAX_NC 0xF0000000 /* Max Nak counts */ 359 #define EHCI_QH_CTRL_CONTROL_ED_FLAG 0x08000000 /* Ctrl endpoint flag */ 360 #define EHCI_QH_CTRL_MAXPKTSZ 0x07FF0000 /* Max packet length */ 361 #define EHCI_QH_CTRL_MAXPKTSZ_SHIFT 16 /* Max packet shift */ 362 #define EHCI_QH_CTRL_RECLAIM_HEAD 0x00008000 /* Head reclaim list */ 363 #define EHCI_QH_CTRL_DATA_TOGGLE 0x00004000 /* Data toggle */ 364 #define EHCI_QH_CTRL_ED_SPEED 0x00003000 /* Endpoint speed */ 365 #define EHCI_QH_CTRL_ED_FULL_SPEED 0x00000000 /* FullSpeed endpoint */ 366 #define EHCI_QH_CTRL_ED_LOW_SPEED 0x00001000 /* LowSpeed endpoint */ 367 #define EHCI_QH_CTRL_ED_HIGH_SPEED 0x00002000 /* HighSpeed endpoint */ 368 #define EHCI_QH_CTRL_ED_SPEED_SHIFT 12 /* ED speed shift */ 369 #define EHCI_QH_CTRL_ED_NUMBER 0x00000F00 /* Endpoint number */ 370 #define EHCI_QH_CTRL_ED_NUMBER_SHIFT 8 /* ED number shift */ 371 #define EHCI_QH_CTRL_ED_INACTIVATE 0x00000080 /* Inctivate endpoint */ 372 #define EHCI_QH_CTRL_DEVICE_ADDRESS 0x0000007F /* Device address */ 373 374 /* 375 * q_split_ctrl control bits. 376 */ 377 #define EHCI_QH_SPLIT_CTRL_MULT 0xC0000000 /* HB multiplier */ 378 #define EHCI_QH_SPLIT_CTRL_MULT_SHIFT 30 /* HB mult Shift */ 379 #define EHCI_QH_SPLIT_CTRL_1_XACTS 0x40000000 /* 1 Xacts per uFrame */ 380 #define EHCI_QH_SPLIT_CTRL_2_XACTS 0x80000000 /* 2 Xacts per uFrame */ 381 #define EHCI_QH_SPLIT_CTRL_3_XACTS 0xC0000000 /* 3 Xacts per uFrame */ 382 #define EHCI_QH_SPLIT_CTRL_HUB_PORT 0x3F800000 /* HS hub port number */ 383 #define EHCI_QH_SPLIT_CTRL_HUB_PORT_SHIFT 23 /* HS hubport no shft */ 384 #define EHCI_QH_SPLIT_CTRL_HUB_ADDR 0x007F0000 /* HS hub address */ 385 #define EHCI_QH_SPLIT_CTRL_HUB_ADDR_SHIFT 16 /* HS hub addr mask */ 386 #define EHCI_QH_SPLIT_CTRL_COMP_MASK 0x0000FF00 /* Split comp mask */ 387 #define EHCI_QH_SPLIT_CTRL_COMP_SHIFT 8 /* Split comp shift */ 388 #define EHCI_QH_SPLIT_CTRL_INTR_MASK 0x000000FF /* Intr schedule mask */ 389 390 /* 391 * qh_curr_qtd control bits. 392 */ 393 #define EHCI_QH_CURR_QTD_PTR 0xFFFFFFE0 /* Curr element QTD */ 394 395 /* 396 * qh_next_qtd control bits. 397 */ 398 #define EHCI_QH_NEXT_QTD_PTR 0xFFFFFFE0 /* Next QTD */ 399 #define EHCI_QH_NEXT_QTD_PTR_VALID 0x00000001 /* Next QTD validity */ 400 401 /* 402 * qh_alt_next_qtd control bits. 403 */ 404 #define EHCI_QH_ALT_NEXT_QTD_PTR 0xFFFFFFE0 /* Alternate next QTD */ 405 #define EHCI_QH_ALT_NEXT_QTD_PTR_VALID 0x00000001 /* Alt QTD validity */ 406 #define EHCI_QH_ALT_NEXT_QTD_NAKCNT 0x0000001E /* NAK counter */ 407 408 /* 409 * qh_status control bits. 410 */ 411 #define EHCI_QH_STS_DATA_TOGGLE 0x80000000 /* Data toggle */ 412 #define EHCI_QH_STS_BYTES_TO_XFER 0x7FFF0000 /* Bytes to transfer */ 413 #define EHCI_QH_STS_BYTES_TO_XFER_SHIFT 16 /* Bytes to xfer mask */ 414 #define EHCI_QH_STS_INTR_ON_COMPLETE 0x00008000 /* Intr on complete */ 415 #define EHCI_QH_STS_C_PAGE 0x00007000 /* C page */ 416 #define EHCI_QH_STS_ERROR_COUNTER 0x00000C00 /* Error counter */ 417 #define EHCI_QH_STS_ERROR_COUNT_MASK 0x00000C00 /* Error count mask */ 418 #define EHCI_QH_STS_PID_CODE 0x00000300 /* PID code */ 419 #define EHCI_QH_STS_XACT_STATUS 0x000000FF /* Xact Status */ 420 #define EHCI_QH_STS_HS_XACT_STATUS 0x000000F8 /* HS Xact status */ 421 #define EHCI_QH_STS_NON_HS_XACT_STATUS 0x000000FD /* Non HS Xact status */ 422 #define EHCI_QH_STS_NO_ERROR 0x00000000 /* No error */ 423 #define EHCI_QH_STS_ACTIVE 0x00000080 /* Active */ 424 #define EHCI_QH_STS_HALTED 0x00000040 /* Halted */ 425 #define EHCI_QH_STS_DATA_BUFFER_ERR 0x00000020 /* Data buffer error */ 426 #define EHCI_QH_STS_BABBLE_DETECTED 0x00000010 /* Babble detected */ 427 #define EHCI_QH_STS_XACT_ERROR 0x00000008 /* Transaction error */ 428 #define EHCI_QH_STS_MISSED_uFRAME 0x00000004 /* Missed micro frame */ 429 #define EHCI_QH_STS_SPLIT_XSTATE 0x00000002 /* Split xact state */ 430 #define EHCI_QH_STS_DO_START_SPLIT 0x00000000 /* Do start split */ 431 #define EHCI_QH_STS_DO_COMPLETE_SPLIT 0x00000002 /* Do complete split */ 432 #define EHCI_QH_STS_PING_STATE 0x00000001 /* Ping state */ 433 #define EHCI_QH_STS_DO_OUT 0x00000000 /* Do OUT */ 434 #define EHCI_QH_STS_DO_PING 0x00000001 /* Do PING */ 435 #define EHCI_QH_STS_PRD_SPLIT_XACT_ERR 0x00000001 /* Periodic split err */ 436 437 /* 438 * qh_buf[X] control bits. 439 */ 440 #define EHCI_QH_BUF_PTR 0xFFFFF000 /* Buffer pointer */ 441 #define EHCI_QH_BUF_CURR_OFFSET 0x00000FFF /* Current offset */ 442 #define EHCI_QH_BUF_CPROG_MASK 0x000000FF /* Split progress */ 443 #define EHCI_QH_BUF_SBYTES 0x00000FE0 /* Software S bytes */ 444 #define EHCI_QH_BUF_FRAME_TAG 0x0000001F /* Split xct frametag */ 445 446 /* 447 * qh_buf_high[X] control bits. 448 */ 449 #define EHCI_QH_BUF_HIGH_PTR 0xFFFFFFFF /* For 64 addressing */ 450 451 /* 452 * qh_state 453 * 454 * QH States 455 */ 456 #define EHCI_QH_FREE 1 /* Free QH */ 457 #define EHCI_QH_STATIC 2 /* Static QH */ 458 #define EHCI_QH_ACTIVE 3 /* Active QH */ 459 460 461 /* 462 * Host Controller Queue Element Transfer Descriptor 463 * 464 * A Queue Element Transfer Descriptor (QTD) is a memory structure that 465 * describes the information necessary for the Host Controller (HC) to 466 * transfer a block of data to or from a device endpoint except High 467 * Speed and Full Speed Isochronous's endpoints. These QTD's will be 468 * attached to a Queue Head (QH). This structure must be aligned to a 469 * 32 byte boundary. 470 */ 471 typedef volatile struct ehci_qtd { 472 uint32_t qtd_next_qtd; /* Next QTD */ 473 uint32_t qtd_alt_next_qtd; /* Next alternate QTD */ 474 uint32_t qtd_ctrl; /* Control information */ 475 uint32_t qtd_buf[5]; /* Buffer pointers */ 476 uint32_t qtd_buf_high[5]; /* For 64 bit addressing */ 477 478 /* HCD private fields */ 479 uint32_t qtd_trans_wrapper; /* Transfer wrapper */ 480 uint32_t qtd_tw_next_qtd; /* Next qtd on TW */ 481 uint32_t qtd_active_qtd_next; /* Next QTD on active list */ 482 uint32_t qtd_active_qtd_prev; /* Prev QTD on active list */ 483 uint32_t qtd_state; /* QTD state */ 484 uint32_t qtd_ctrl_phase; /* Control xfer phase info */ 485 uint32_t qtd_xfer_offs; /* Starting buffer offset */ 486 uint32_t qtd_xfer_len; /* Transfer length */ 487 uint8_t qtd_pad[12]; /* Required padding */ 488 } ehci_qtd_t; 489 490 /* 491 * qtd_next_qtd control bits. 492 */ 493 #define EHCI_QTD_NEXT_QTD_PTR 0xFFFFFFE0 /* Next QTD pointer */ 494 #define EHCI_QTD_NEXT_QTD_PTR_VALID 0x00000001 /* Next QTD validity */ 495 496 /* 497 * qtd_alt_next_qtd control bits. 498 */ 499 #define EHCI_QTD_ALT_NEXT_QTD_PTR 0xFFFFFFE0 /* Alt QTD pointer */ 500 #define EHCI_QTD_ALT_NEXT_QTD_PTR_VALID 0x00000001 /* Alt QTD validity */ 501 502 /* 503 * qtd_ctrl control bits. 504 */ 505 #define EHCI_QTD_CTRL_DATA_TOGGLE 0x80000000 /* Data toggle */ 506 #define EHCI_QTD_CTRL_DATA_TOGGLE_0 0x00000000 /* Data toggle 0 */ 507 #define EHCI_QTD_CTRL_DATA_TOGGLE_1 0x80000000 /* Data toggle 1 */ 508 #define EHCI_QTD_CTRL_BYTES_TO_XFER 0x7FFF0000 /* Bytes to xfer */ 509 #define EHCI_QTD_CTRL_BYTES_TO_XFER_SHIFT 16 /* Bytes xfer mask */ 510 #define EHCI_QTD_CTRL_INTR_ON_COMPLETE 0x00008000 /* Intr on complete */ 511 #define EHCI_QTD_CTRL_C_PAGE 0x00007000 /* Current page */ 512 #define EHCI_QTD_CTRL_MAX_ERR_COUNTS 0x00000C00 /* Max error counts */ 513 #define EHCI_QTD_CTRL_PID_CODE 0x00000300 /* PID code */ 514 #define EHCI_QTD_CTRL_OUT_PID 0x00000000 /* OUT token */ 515 #define EHCI_QTD_CTRL_IN_PID 0x00000100 /* IN token */ 516 #define EHCI_QTD_CTRL_SETUP_PID 0x00000200 /* SETUP token */ 517 #define EHCI_QTD_CTRL_XACT_STATUS 0x000000FF /* Xact status */ 518 #define EHCI_QTD_CTRL_HS_XACT_STATUS 0x000000F8 /* HS Xact status */ 519 #define EHCI_QTD_CTRL_NON_HS_XACT_STATUS 0x000000FD /* Non HS Xact status */ 520 #define EHCI_QTD_CTRL_NO_ERROR 0x00000000 /* No error */ 521 #define EHCI_QTD_CTRL_ACTIVE_XACT 0x00000080 /* Active xact */ 522 #define EHCI_QTD_CTRL_HALTED_XACT 0x00000040 /* Halted due to err */ 523 #define EHCI_QTD_CTRL_DATA_BUFFER_ERROR 0x00000020 /* Data buffer error */ 524 #define EHCI_QTD_CTRL_ERR_COUNT_MASK 0x00000C00 /* Error count */ 525 #define EHCI_QTD_CTRL_BABBLE_DETECTED 0x00000010 /* Babble detected */ 526 #define EHCI_QTD_CTRL_XACT_ERROR 0x00000008 /* Transaction error */ 527 #define EHCI_QTD_CTRL_MISSED_uFRAME 0x00000004 /* Missed uFrame */ 528 #define EHCI_QTD_CTRL_SPLIT_XACT_STATE 0x00000002 /* Split xact state */ 529 #define EHCI_QTD_CTRL_DO_START_SPLIT 0x00000000 /* Do start split */ 530 #define EHCI_QTD_CTRL_DO_COMPLETE_SPLIT 0x00000002 /* Do complete split */ 531 #define EHCI_QTD_CTRL_PING_STATE 0x00000001 /* Ping state */ 532 #define EHCI_QTD_CTRL_DO_OUT 0x00000000 /* Do OUT */ 533 #define EHCI_QTD_CTRL_DO_PING 0x00000001 /* Do PING */ 534 #define EHCI_QTD_CTRL_PRD_SPLIT_XACT_ERR 0x00000001 /* Periodic split err */ 535 536 /* 537 * qtd_buf[X] control bits. 538 */ 539 #define EHCI_QTD_BUF_PTR 0xFFFFF000 /* Buffer pointer */ 540 #define EHCI_QTD_BUF_CURR_OFFSET 0x00000FFF /* Current offset */ 541 542 /* 543 * qtd_buf_high[X] control bits. 544 */ 545 #define EHCI_QTD_BUF_HIGH_PTR 0xFFFFFFFF /* 64 bit addressing */ 546 547 /* 548 * qtd_state 549 * 550 * QTD States 551 */ 552 #define EHCI_QTD_FREE 1 /* Free QTD */ 553 #define EHCI_QTD_DUMMY 2 /* Dummy QTD */ 554 #define EHCI_QTD_ACTIVE 3 /* Active QTD */ 555 #define EHCI_QTD_RECLAIM 4 /* Reclaim QTD */ 556 557 /* 558 * qtd_ctrl_phase 559 * 560 * Control Transfer Phase information 561 */ 562 #define EHCI_CTRL_SETUP_PHASE 1 /* Setup phase */ 563 #define EHCI_CTRL_DATA_PHASE 2 /* Data phase */ 564 #define EHCI_CTRL_STATUS_PHASE 3 /* Status phase */ 565 566 /* 567 * Host Controller Split Isochronous Transfer Descripter 568 * 569 * iTD/siTD is a memory structure that describes the information necessary for 570 * the Host Controller (HC) to transfer a block of data to or from a 571 * 1.1 isochronous device end point. The iTD/siTD will be inserted between 572 * the periodic frame list and the interrupt tree lattice. This structure 573 * must be aligned to a 32 byte boundary. 574 */ 575 typedef volatile struct ehci_itd { 576 uint32_t itd_link_ptr; /* Next TD */ 577 uint32_t itd_body[15]; /* iTD and siTD body */ 578 uint32_t itd_body_high[7]; /* For 64 bit addressing */ 579 580 /* Padding required */ 581 uint32_t itd_pad; 582 583 /* HCD private fields */ 584 uint32_t itd_trans_wrapper; /* Transfer wrapper */ 585 uint32_t itd_itw_next_itd; /* Next iTD on TW */ 586 uint32_t itd_next_active_itd; /* Next iTD in active list */ 587 uint32_t itd_state; /* iTD state */ 588 uint32_t itd_index[8]; /* iTD index */ 589 uint64_t itd_frame_number; /* Frame iTD exists */ 590 uint64_t itd_reclaim_number; /* Frame iTD is reclaimed */ 591 } ehci_itd_t; 592 593 /* 594 * Generic Link Ptr Bits 595 * EHCI_TD_LINK_PTR : Points to the next data object to be processed 596 * EHCI_TD_LINK_PTR_TYPE : Type of reference this descriptor is 597 * EHCI_TD_LINK_PTR_VALID : Is this link pointer valid 598 */ 599 #define EHCI_ITD_LINK_PTR 0xFFFFFFE0 /* TD link ptr mask */ 600 #define EHCI_ITD_LINK_REF 0x00000006 /* Ref to TD/ITD/SITD */ 601 #define EHCI_ITD_LINK_REF_ITD 0x00000000 /* ITD pointer */ 602 #define EHCI_ITD_LINK_REF_QH 0x00000002 /* QH pointer */ 603 #define EHCI_ITD_LINK_REF_SITD 0x00000004 /* SITD pointer */ 604 #define EHCI_ITD_LINK_REF_FSTN 0x00000006 /* FSTN pointer */ 605 #define EHCI_ITD_LINK_PTR_INVALID 0x00000001 /* Link ptr validity */ 606 607 #define EHCI_ITD_CTRL_LIST_SIZE 8 608 #define EHCI_ITD_BUFFER_LIST_SIZE 7 609 #define EHCI_ITD_CTRL0 0 /* Status and Ctrl List */ 610 #define EHCI_ITD_CTRL1 1 611 #define EHCI_ITD_CTRL2 2 612 #define EHCI_ITD_CTRL3 3 613 #define EHCI_ITD_CTRL4 4 614 #define EHCI_ITD_CTRL5 5 615 #define EHCI_ITD_CTRL6 6 616 #define EHCI_ITD_CTRL7 7 617 #define EHCI_ITD_BUFFER0 8 /* Buffer Page Ptr List */ 618 #define EHCI_ITD_BUFFER1 9 619 #define EHCI_ITD_BUFFER2 10 620 #define EHCI_ITD_BUFFER3 11 621 #define EHCI_ITD_BUFFER4 12 622 #define EHCI_ITD_BUFFER5 13 623 #define EHCI_ITD_BUFFER6 14 624 625 /* 626 * iTD Transaction Status and Control bits 627 */ 628 #define EHCI_ITD_XFER_STATUS_MASK 0xF0000000 629 #define EHCI_ITD_XFER_STATUS_SHIFT 28 630 #define EHCI_ITD_XFER_ACTIVE 0x80000000 631 #define EHCI_ITD_XFER_DATA_BUFFER_ERR 0x40000000 632 #define EHCI_ITD_XFER_BABBLE 0x20000000 633 #define EHCI_ITD_XFER_ERROR 0x10000000 634 #define EHCI_ITD_XFER_LENGTH 0x0FFF0000 635 #define EHCI_ITD_XFER_IOC 0x00008000 636 #define EHCI_ITD_XFER_IOC_ON 0x00008000 637 #define EHCI_ITD_XFER_IOC_OFF 0x00000000 638 #define EHCI_ITD_XFER_PAGE_SELECT 0x00007000 639 #define EHCI_ITD_XFER_OFFSET 0x00000FFF 640 641 /* 642 * iTD Buffer Page Pointer bits 643 */ 644 #define EHCI_ITD_CTRL_BUFFER_MASK 0xFFFFF000 645 #define EHCI_ITD_CTRL_ENDPT_MASK 0x00000F00 646 #define EHCI_ITD_CTRL_DEVICE_MASK 0x0000007F 647 #define EHCI_ITD_CTRL_DIR 0x00000800 648 #define EHCI_ITD_CTRL_DIR_IN 0x00000800 649 #define EHCI_ITD_CTRL_DIR_OUT 0x00000000 650 #define EHCI_ITD_CTRL_MAX_PACKET_MASK 0x000007FF 651 #define EHCI_ITD_CTRL_MULTI_MASK 0x00000003 652 #define EHCI_ITD_CTRL_ONE_XACT 0x00000001 653 #define EHCI_ITD_CTRL_TWO_XACT 0x00000002 654 #define EHCI_ITD_CTRL_THREE_XACT 0x00000003 655 656 /* Unused iTD index */ 657 #define EHCI_ITD_UNUSED_INDEX 0xFFFFFFFF 658 659 #define EHCI_SITD_CTRL 0 660 #define EHCI_SITD_UFRAME_SCHED 1 661 #define EHCI_SITD_XFER_STATE 2 662 #define EHCI_SITD_BUFFER0 3 663 #define EHCI_SITD_BUFFER1 4 664 #define EHCI_SITD_PREV_SITD 5 665 666 /* 667 * sitd_ctrl bits 668 * EHCI_SITD_CTRL_DIR : Direction of transaction 669 * EHCI_SITD_CTRL_PORT_MASK : Port # of recipient transaction translator(TT) 670 * EHCI_SITD_CTRL_HUB_MASK : Device address of the TT's hub 671 * EHCI_SITD_CTRL_END_PT_MASK : Endpoint # on device serving as data source/sink 672 * EHCI_SITD_CTRL_DEVICE_MASK : Address of device serving as data source/sink 673 */ 674 #define EHCI_SITD_CTRL_DIR 0x80000000 675 #define EHCI_SITD_CTRL_DIR_IN 0x80000000 676 #define EHCI_SITD_CTRL_DIR_OUT 0x00000000 677 #define EHCI_SITD_CTRL_PORT_MASK 0x7F000000 678 #define EHCI_SITD_CTRL_PORT_SHIFT 24 679 #define EHCI_SITD_CTRL_HUB_MASK 0x007F0000 680 #define EHCI_SITD_CTRL_HUB_SHIFT 16 681 #define EHCI_SITD_CTRL_END_PT_MASK 0x00000F00 682 #define EHCI_SITD_CTRL_END_PT_SHIFT 8 683 #define EHCI_SITD_CTRL_DEVICE_MASK 0x0000007F 684 #define EHCI_SITD_CTRL_DEVICE_SHIFT 0 685 686 /* 687 * sitd_uframe_sched bits 688 * EHCI_SITD_UFRAME_CMASK_MASK : Determines which uFrame the HC executes CSplit 689 * EHCI_SITD_UFRAME_SMASK_MASK : Determines which uFrame the HC executes SSplit 690 */ 691 #define EHCI_SITD_UFRAME_CMASK_MASK 0x0000FF00 692 #define EHCI_SITD_UFRAME_CMASK_SHIFT 8 693 #define EHCI_SITD_UFRAME_SMASK_MASK 0x000000FF 694 #define EHCI_SITD_UFRAME_SMASK_SHIFT 0 695 696 /* 697 * sitd_xfer_state bits 698 * EHCI_SITD_XFER_IOC_MASK : Interrupt when transaction is complete. 699 * EHCI_SITD_XFER_PAGE_MASK : Which data page pointer should be concatenated 700 * with the CurrentOffset to construct a data 701 * buffer pointer 702 * EHCI_SITD_XFER_TOTAL_MASK : Total number of bytes expected in xfer(1023 Max). 703 * EHCI_SITD_XFER_CPROG_MASK : HC tracks which CSplit has been executed. 704 * EHCI_SITD_XFER_STATUS_MASK : Status of xfer 705 */ 706 #define EHCI_SITD_XFER_IOC_MASK 0x80000000 707 #define EHCI_SITD_XFER_IOC_ON 0x80000000 708 #define EHCI_SITD_XFER_IOC_OFF 0x00000000 709 #define EHCI_SITD_XFER_PAGE_MASK 0x40000000 710 #define EHCI_SITD_XFER_PAGE_0 0x00000000 711 #define EHCI_SITD_XFER_PAGE_1 0x40000000 712 #define EHCI_SITD_XFER_TOTAL_MASK 0x03FF0000 713 #define EHCI_SITD_XFER_TOTAL_SHIFT 16 714 #define EHCI_SITD_XFER_CPROG_MASK 0x0000FF00 715 #define EHCI_SITD_XFER_CPROG_SHIFT 8 716 #define EHCI_SITD_XFER_STATUS_MASK 0x000000FF 717 #define EHCI_SITD_XFER_STATUS_SHIFT 0 718 #define EHCI_SITD_XFER_ACTIVE 0x80 719 #define EHCI_SITD_XFER_ERROR 0x40 720 #define EHCI_SITD_XFER_DATA_BUFFER_ERR 0x20 721 #define EHCI_SITD_XFER_BABBLE 0x10 722 #define EHCI_SITD_XFER_XACT_ERROR 0x08 723 #define EHCI_SITD_XFER_MISSED_UFRAME 0x04 724 #define EHCI_SITD_XFER_SPLIT_XACT_STATE 0x02 725 #define EHCI_SITD_XFER_SSPLIT_STATE 0x00 726 #define EHCI_SITD_XFER_CSPLIT_STATE 0x02 727 728 /* 729 * sitd_xfer_buffer0/1 730 * EHCI_SITD_XFER_BUFFER_MASK : Buffer Pointer List 731 * EHCI_SITD_XFER_OFFSET_MASK : Current byte offset 732 * EHCI_SITD_XFER_TP_MASK : Transaction position 733 * EHCI_SITD_XFER_TCOUNT_MASK : Transaction count 734 */ 735 #define EHCI_SITD_XFER_BUFFER_MASK 0xFFFFF000 736 #define EHCI_SITD_XFER_BUFFER_SHIFT 12 737 #define EHCI_SITD_XFER_OFFSET_MASK 0x00000FFF 738 #define EHCI_SITD_XFER_OFFSET_SHIFT 0 739 #define EHCI_SITD_XFER_TP_MASK 0x00000018 740 #define EHCI_SITD_XFER_TP_ALL 0x0 741 #define EHCI_SITD_XFER_TP_BEGIN 0x1 742 #define EHCI_SITD_XFER_TP_MID 0x2 743 #define EHCI_SITD_XFER_TP_END 0x3 744 #define EHCI_SITD_XFER_TCOUNT_MASK 0x00000007 745 #define EHCI_SITD_XFER_TCOUNT_SHIFT 0 746 747 /* 748 * qtd_state 749 * 750 * ITD States 751 */ 752 #define EHCI_ITD_FREE 1 /* Free ITD */ 753 #define EHCI_ITD_DUMMY 2 /* Dummy ITD */ 754 #define EHCI_ITD_ACTIVE 3 /* Active ITD */ 755 #define EHCI_ITD_RECLAIM 4 /* Reclaim ITD */ 756 757 #ifdef __cplusplus 758 } 759 #endif 760 761 #endif /* _SYS_USB_EHCI_H */ 762