xref: /illumos-gate/usr/src/uts/common/io/sfxge/common/efx.h (revision 49ef7e0638c8b771d8a136eae78b1c0f99acc8e0)
1 /*
2  * Copyright (c) 2006-2015 Solarflare Communications Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  *    this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright notice,
11  *    this list of conditions and the following disclaimer in the documentation
12  *    and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  *
26  * The views and conclusions contained in the software and documentation are
27  * those of the authors and should not be interpreted as representing official
28  * policies, either expressed or implied, of the FreeBSD Project.
29  */
30 
31 #ifndef	_SYS_EFX_H
32 #define	_SYS_EFX_H
33 
34 #include "efsys.h"
35 #include "efx_check.h"
36 #include "efx_phy_ids.h"
37 
38 #ifdef	__cplusplus
39 extern "C" {
40 #endif
41 
42 #define	EFX_STATIC_ASSERT(_cond)		\
43 	((void)sizeof(char[(_cond) ? 1 : -1]))
44 
45 #define	EFX_ARRAY_SIZE(_array)			\
46 	(sizeof(_array) / sizeof((_array)[0]))
47 
48 #define	EFX_FIELD_OFFSET(_type, _field)		\
49 	((size_t) &(((_type *)0)->_field))
50 
51 /* Return codes */
52 
53 typedef __success(return == 0) int efx_rc_t;
54 
55 
56 /* Chip families */
57 
58 typedef enum efx_family_e {
59 	EFX_FAMILY_INVALID,
60 	EFX_FAMILY_FALCON,	/* Obsolete and not supported */
61 	EFX_FAMILY_SIENA,
62 	EFX_FAMILY_HUNTINGTON,
63 	EFX_FAMILY_MEDFORD,
64 	EFX_FAMILY_NTYPES
65 } efx_family_t;
66 
67 extern	__checkReturn	efx_rc_t
68 efx_family(
69 	__in		uint16_t venid,
70 	__in		uint16_t devid,
71 	__out		efx_family_t *efp);
72 
73 
74 #define	EFX_PCI_VENID_SFC			0x1924
75 
76 #define	EFX_PCI_DEVID_FALCON			0x0710	/* SFC4000 */
77 
78 #define	EFX_PCI_DEVID_BETHPAGE			0x0803	/* SFC9020 */
79 #define	EFX_PCI_DEVID_SIENA			0x0813	/* SFL9021 */
80 #define	EFX_PCI_DEVID_SIENA_F1_UNINIT		0x0810
81 
82 #define	EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT	0x0901
83 #define	EFX_PCI_DEVID_FARMINGDALE		0x0903	/* SFC9120 PF */
84 #define	EFX_PCI_DEVID_GREENPORT			0x0923	/* SFC9140 PF */
85 
86 #define	EFX_PCI_DEVID_FARMINGDALE_VF		0x1903	/* SFC9120 VF */
87 #define	EFX_PCI_DEVID_GREENPORT_VF		0x1923	/* SFC9140 VF */
88 
89 #define	EFX_PCI_DEVID_MEDFORD_PF_UNINIT		0x0913
90 #define	EFX_PCI_DEVID_MEDFORD			0x0A03	/* SFC9240 PF */
91 #define	EFX_PCI_DEVID_MEDFORD_VF		0x1A03	/* SFC9240 VF */
92 
93 #define	EFX_MEM_BAR	2
94 
95 /* Error codes */
96 
97 enum {
98 	EFX_ERR_INVALID,
99 	EFX_ERR_SRAM_OOB,
100 	EFX_ERR_BUFID_DC_OOB,
101 	EFX_ERR_MEM_PERR,
102 	EFX_ERR_RBUF_OWN,
103 	EFX_ERR_TBUF_OWN,
104 	EFX_ERR_RDESQ_OWN,
105 	EFX_ERR_TDESQ_OWN,
106 	EFX_ERR_EVQ_OWN,
107 	EFX_ERR_EVFF_OFLO,
108 	EFX_ERR_ILL_ADDR,
109 	EFX_ERR_SRAM_PERR,
110 	EFX_ERR_NCODES
111 };
112 
113 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
114 extern	__checkReturn		uint32_t
115 efx_crc32_calculate(
116 	__in			uint32_t crc_init,
117 	__in_ecount(length)	uint8_t const *input,
118 	__in			int length);
119 
120 
121 /* Type prototypes */
122 
123 typedef struct efx_rxq_s	efx_rxq_t;
124 
125 /* NIC */
126 
127 typedef struct efx_nic_s	efx_nic_t;
128 
129 #define	EFX_NIC_FUNC_PRIMARY	0x00000001
130 #define	EFX_NIC_FUNC_LINKCTRL	0x00000002
131 #define	EFX_NIC_FUNC_TRUSTED	0x00000004
132 
133 
134 extern	__checkReturn	efx_rc_t
135 efx_nic_create(
136 	__in		efx_family_t family,
137 	__in		efsys_identifier_t *esip,
138 	__in		efsys_bar_t *esbp,
139 	__in		efsys_lock_t *eslp,
140 	__deref_out	efx_nic_t **enpp);
141 
142 extern	__checkReturn	efx_rc_t
143 efx_nic_probe(
144 	__in		efx_nic_t *enp);
145 
146 extern	__checkReturn	efx_rc_t
147 efx_nic_init(
148 	__in		efx_nic_t *enp);
149 
150 extern	__checkReturn	efx_rc_t
151 efx_nic_reset(
152 	__in		efx_nic_t *enp);
153 
154 #if EFSYS_OPT_DIAG
155 
156 extern	__checkReturn	efx_rc_t
157 efx_nic_register_test(
158 	__in		efx_nic_t *enp);
159 
160 #endif	/* EFSYS_OPT_DIAG */
161 
162 extern		void
163 efx_nic_fini(
164 	__in		efx_nic_t *enp);
165 
166 extern		void
167 efx_nic_unprobe(
168 	__in		efx_nic_t *enp);
169 
170 extern 		void
171 efx_nic_destroy(
172 	__in	efx_nic_t *enp);
173 
174 #if EFSYS_OPT_MCDI
175 
176 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
177 /* Huntington and Medford require MCDIv2 commands */
178 #define	WITH_MCDI_V2 1
179 #endif
180 
181 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
182 
183 typedef enum efx_mcdi_exception_e {
184 	EFX_MCDI_EXCEPTION_MC_REBOOT,
185 	EFX_MCDI_EXCEPTION_MC_BADASSERT,
186 } efx_mcdi_exception_t;
187 
188 #if EFSYS_OPT_MCDI_LOGGING
189 typedef enum efx_log_msg_e
190 {
191 	EFX_LOG_INVALID,
192 	EFX_LOG_MCDI_REQUEST,
193 	EFX_LOG_MCDI_RESPONSE,
194 } efx_log_msg_t;
195 #endif /* EFSYS_OPT_MCDI_LOGGING */
196 
197 typedef struct efx_mcdi_transport_s {
198 	void		*emt_context;
199 	efsys_mem_t	*emt_dma_mem;
200 	void		(*emt_execute)(void *, efx_mcdi_req_t *);
201 	void		(*emt_ev_cpl)(void *);
202 	void		(*emt_exception)(void *, efx_mcdi_exception_t);
203 #if EFSYS_OPT_MCDI_LOGGING
204 	void		(*emt_logger)(void *, efx_log_msg_t,
205 					void *, size_t, void *, size_t);
206 #endif /* EFSYS_OPT_MCDI_LOGGING */
207 #if EFSYS_OPT_MCDI_PROXY_AUTH
208 	void		(*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
209 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
210 } efx_mcdi_transport_t;
211 
212 extern	__checkReturn	efx_rc_t
213 efx_mcdi_init(
214 	__in		efx_nic_t *enp,
215 	__in		const efx_mcdi_transport_t *mtp);
216 
217 extern	__checkReturn	efx_rc_t
218 efx_mcdi_reboot(
219 	__in		efx_nic_t *enp);
220 
221 			void
222 efx_mcdi_new_epoch(
223 	__in		efx_nic_t *enp);
224 
225 extern			void
226 efx_mcdi_request_start(
227 	__in		efx_nic_t *enp,
228 	__in		efx_mcdi_req_t *emrp,
229 	__in		boolean_t ev_cpl);
230 
231 extern	__checkReturn	boolean_t
232 efx_mcdi_request_poll(
233 	__in		efx_nic_t *enp);
234 
235 extern	__checkReturn	boolean_t
236 efx_mcdi_request_abort(
237 	__in		efx_nic_t *enp);
238 
239 extern			void
240 efx_mcdi_fini(
241 	__in		efx_nic_t *enp);
242 
243 #endif	/* EFSYS_OPT_MCDI */
244 
245 /* INTR */
246 
247 #define	EFX_NINTR_SIENA 1024
248 
249 typedef enum efx_intr_type_e {
250 	EFX_INTR_INVALID = 0,
251 	EFX_INTR_LINE,
252 	EFX_INTR_MESSAGE,
253 	EFX_INTR_NTYPES
254 } efx_intr_type_t;
255 
256 #define	EFX_INTR_SIZE	(sizeof (efx_oword_t))
257 
258 extern	__checkReturn	efx_rc_t
259 efx_intr_init(
260 	__in		efx_nic_t *enp,
261 	__in		efx_intr_type_t type,
262 	__in		efsys_mem_t *esmp);
263 
264 extern 			void
265 efx_intr_enable(
266 	__in		efx_nic_t *enp);
267 
268 extern 			void
269 efx_intr_disable(
270 	__in		efx_nic_t *enp);
271 
272 extern 			void
273 efx_intr_disable_unlocked(
274 	__in		efx_nic_t *enp);
275 
276 #define	EFX_INTR_NEVQS	32
277 
278 extern __checkReturn	efx_rc_t
279 efx_intr_trigger(
280 	__in		efx_nic_t *enp,
281 	__in		unsigned int level);
282 
283 extern			void
284 efx_intr_status_line(
285 	__in		efx_nic_t *enp,
286 	__out		boolean_t *fatalp,
287 	__out		uint32_t *maskp);
288 
289 extern			void
290 efx_intr_status_message(
291 	__in		efx_nic_t *enp,
292 	__in		unsigned int message,
293 	__out		boolean_t *fatalp);
294 
295 extern			void
296 efx_intr_fatal(
297 	__in		efx_nic_t *enp);
298 
299 extern			void
300 efx_intr_fini(
301 	__in		efx_nic_t *enp);
302 
303 /* MAC */
304 
305 #if EFSYS_OPT_MAC_STATS
306 
307 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
308 typedef enum efx_mac_stat_e {
309 	EFX_MAC_RX_OCTETS,
310 	EFX_MAC_RX_PKTS,
311 	EFX_MAC_RX_UNICST_PKTS,
312 	EFX_MAC_RX_MULTICST_PKTS,
313 	EFX_MAC_RX_BRDCST_PKTS,
314 	EFX_MAC_RX_PAUSE_PKTS,
315 	EFX_MAC_RX_LE_64_PKTS,
316 	EFX_MAC_RX_65_TO_127_PKTS,
317 	EFX_MAC_RX_128_TO_255_PKTS,
318 	EFX_MAC_RX_256_TO_511_PKTS,
319 	EFX_MAC_RX_512_TO_1023_PKTS,
320 	EFX_MAC_RX_1024_TO_15XX_PKTS,
321 	EFX_MAC_RX_GE_15XX_PKTS,
322 	EFX_MAC_RX_ERRORS,
323 	EFX_MAC_RX_FCS_ERRORS,
324 	EFX_MAC_RX_DROP_EVENTS,
325 	EFX_MAC_RX_FALSE_CARRIER_ERRORS,
326 	EFX_MAC_RX_SYMBOL_ERRORS,
327 	EFX_MAC_RX_ALIGN_ERRORS,
328 	EFX_MAC_RX_INTERNAL_ERRORS,
329 	EFX_MAC_RX_JABBER_PKTS,
330 	EFX_MAC_RX_LANE0_CHAR_ERR,
331 	EFX_MAC_RX_LANE1_CHAR_ERR,
332 	EFX_MAC_RX_LANE2_CHAR_ERR,
333 	EFX_MAC_RX_LANE3_CHAR_ERR,
334 	EFX_MAC_RX_LANE0_DISP_ERR,
335 	EFX_MAC_RX_LANE1_DISP_ERR,
336 	EFX_MAC_RX_LANE2_DISP_ERR,
337 	EFX_MAC_RX_LANE3_DISP_ERR,
338 	EFX_MAC_RX_MATCH_FAULT,
339 	EFX_MAC_RX_NODESC_DROP_CNT,
340 	EFX_MAC_TX_OCTETS,
341 	EFX_MAC_TX_PKTS,
342 	EFX_MAC_TX_UNICST_PKTS,
343 	EFX_MAC_TX_MULTICST_PKTS,
344 	EFX_MAC_TX_BRDCST_PKTS,
345 	EFX_MAC_TX_PAUSE_PKTS,
346 	EFX_MAC_TX_LE_64_PKTS,
347 	EFX_MAC_TX_65_TO_127_PKTS,
348 	EFX_MAC_TX_128_TO_255_PKTS,
349 	EFX_MAC_TX_256_TO_511_PKTS,
350 	EFX_MAC_TX_512_TO_1023_PKTS,
351 	EFX_MAC_TX_1024_TO_15XX_PKTS,
352 	EFX_MAC_TX_GE_15XX_PKTS,
353 	EFX_MAC_TX_ERRORS,
354 	EFX_MAC_TX_SGL_COL_PKTS,
355 	EFX_MAC_TX_MULT_COL_PKTS,
356 	EFX_MAC_TX_EX_COL_PKTS,
357 	EFX_MAC_TX_LATE_COL_PKTS,
358 	EFX_MAC_TX_DEF_PKTS,
359 	EFX_MAC_TX_EX_DEF_PKTS,
360 	EFX_MAC_PM_TRUNC_BB_OVERFLOW,
361 	EFX_MAC_PM_DISCARD_BB_OVERFLOW,
362 	EFX_MAC_PM_TRUNC_VFIFO_FULL,
363 	EFX_MAC_PM_DISCARD_VFIFO_FULL,
364 	EFX_MAC_PM_TRUNC_QBB,
365 	EFX_MAC_PM_DISCARD_QBB,
366 	EFX_MAC_PM_DISCARD_MAPPING,
367 	EFX_MAC_RXDP_Q_DISABLED_PKTS,
368 	EFX_MAC_RXDP_DI_DROPPED_PKTS,
369 	EFX_MAC_RXDP_STREAMING_PKTS,
370 	EFX_MAC_RXDP_HLB_FETCH,
371 	EFX_MAC_RXDP_HLB_WAIT,
372 	EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
373 	EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
374 	EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
375 	EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
376 	EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
377 	EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
378 	EFX_MAC_VADAPTER_RX_BAD_PACKETS,
379 	EFX_MAC_VADAPTER_RX_BAD_BYTES,
380 	EFX_MAC_VADAPTER_RX_OVERFLOW,
381 	EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
382 	EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
383 	EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
384 	EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
385 	EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
386 	EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
387 	EFX_MAC_VADAPTER_TX_BAD_PACKETS,
388 	EFX_MAC_VADAPTER_TX_BAD_BYTES,
389 	EFX_MAC_VADAPTER_TX_OVERFLOW,
390 	EFX_MAC_NSTATS
391 } efx_mac_stat_t;
392 
393 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
394 
395 #endif	/* EFSYS_OPT_MAC_STATS */
396 
397 typedef enum efx_link_mode_e {
398 	EFX_LINK_UNKNOWN = 0,
399 	EFX_LINK_DOWN,
400 	EFX_LINK_10HDX,
401 	EFX_LINK_10FDX,
402 	EFX_LINK_100HDX,
403 	EFX_LINK_100FDX,
404 	EFX_LINK_1000HDX,
405 	EFX_LINK_1000FDX,
406 	EFX_LINK_10000FDX,
407 	EFX_LINK_40000FDX,
408 	EFX_LINK_NMODES
409 } efx_link_mode_t;
410 
411 #define	EFX_MAC_ADDR_LEN 6
412 
413 #define	EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t*)_address)[0] & 0x01)
414 
415 #define	EFX_MAC_MULTICAST_LIST_MAX	256
416 
417 #define	EFX_MAC_SDU_MAX	9202
418 
419 #define	EFX_MAC_PDU(_sdu) 				\
420 	P2ROUNDUP(((_sdu)				\
421 		    + /* EtherII */ 14			\
422 		    + /* VLAN */ 4			\
423 		    + /* CRC */ 4			\
424 		    + /* bug16011 */ 16),		\
425 		    (1 << 3))
426 
427 #define	EFX_MAC_PDU_MIN	60
428 #define	EFX_MAC_PDU_MAX	EFX_MAC_PDU(EFX_MAC_SDU_MAX)
429 
430 extern	__checkReturn	efx_rc_t
431 efx_mac_pdu_set(
432 	__in		efx_nic_t *enp,
433 	__in		size_t pdu);
434 
435 extern	__checkReturn	efx_rc_t
436 efx_mac_addr_set(
437 	__in		efx_nic_t *enp,
438 	__in		uint8_t *addr);
439 
440 extern	__checkReturn			efx_rc_t
441 efx_mac_filter_set(
442 	__in				efx_nic_t *enp,
443 	__in				boolean_t all_unicst,
444 	__in				boolean_t mulcst,
445 	__in				boolean_t all_mulcst,
446 	__in				boolean_t brdcst);
447 
448 extern	__checkReturn	efx_rc_t
449 efx_mac_multicast_list_set(
450 	__in				efx_nic_t *enp,
451 	__in_ecount(6*count)		uint8_t const *addrs,
452 	__in				int count);
453 
454 extern	__checkReturn	efx_rc_t
455 efx_mac_filter_default_rxq_set(
456 	__in		efx_nic_t *enp,
457 	__in		efx_rxq_t *erp,
458 	__in		boolean_t using_rss);
459 
460 extern			void
461 efx_mac_filter_default_rxq_clear(
462 	__in		efx_nic_t *enp);
463 
464 extern	__checkReturn	efx_rc_t
465 efx_mac_drain(
466 	__in		efx_nic_t *enp,
467 	__in		boolean_t enabled);
468 
469 extern	__checkReturn	efx_rc_t
470 efx_mac_up(
471 	__in		efx_nic_t *enp,
472 	__out		boolean_t *mac_upp);
473 
474 #define	EFX_FCNTL_RESPOND	0x00000001
475 #define	EFX_FCNTL_GENERATE	0x00000002
476 
477 extern	__checkReturn	efx_rc_t
478 efx_mac_fcntl_set(
479 	__in		efx_nic_t *enp,
480 	__in		unsigned int fcntl,
481 	__in		boolean_t autoneg);
482 
483 extern			void
484 efx_mac_fcntl_get(
485 	__in		efx_nic_t *enp,
486 	__out		unsigned int *fcntl_wantedp,
487 	__out		unsigned int *fcntl_linkp);
488 
489 
490 #if EFSYS_OPT_MAC_STATS
491 
492 #if EFSYS_OPT_NAMES
493 
494 extern	__checkReturn			const char *
495 efx_mac_stat_name(
496 	__in				efx_nic_t *enp,
497 	__in				unsigned int id);
498 
499 #endif	/* EFSYS_OPT_NAMES */
500 
501 #define	EFX_MAC_STATS_SIZE 0x400
502 
503 /*
504  * Upload mac statistics supported by the hardware into the given buffer.
505  *
506  * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
507  * and page aligned.
508  *
509  * The hardware will only DMA statistics that it understands (of course).
510  * Drivers should not make any assumptions about which statistics are
511  * supported, especially when the statistics are generated by firmware.
512  *
513  * Thus, drivers should zero this buffer before use, so that not-understood
514  * statistics read back as zero.
515  */
516 extern	__checkReturn			efx_rc_t
517 efx_mac_stats_upload(
518 	__in				efx_nic_t *enp,
519 	__in				efsys_mem_t *esmp);
520 
521 extern	__checkReturn			efx_rc_t
522 efx_mac_stats_periodic(
523 	__in				efx_nic_t *enp,
524 	__in				efsys_mem_t *esmp,
525 	__in				uint16_t period_ms,
526 	__in				boolean_t events);
527 
528 extern	__checkReturn			efx_rc_t
529 efx_mac_stats_update(
530 	__in				efx_nic_t *enp,
531 	__in				efsys_mem_t *esmp,
532 	__inout_ecount(EFX_MAC_NSTATS)	efsys_stat_t *stat,
533 	__inout_opt			uint32_t *generationp);
534 
535 #endif	/* EFSYS_OPT_MAC_STATS */
536 
537 /* MON */
538 
539 typedef enum efx_mon_type_e {
540 	EFX_MON_INVALID = 0,
541 	EFX_MON_SFC90X0,
542 	EFX_MON_SFC91X0,
543 	EFX_MON_SFC92X0,
544 	EFX_MON_NTYPES
545 } efx_mon_type_t;
546 
547 #if EFSYS_OPT_NAMES
548 
549 extern		const char *
550 efx_mon_name(
551 	__in	efx_nic_t *enp);
552 
553 #endif	/* EFSYS_OPT_NAMES */
554 
555 extern	__checkReturn	efx_rc_t
556 efx_mon_init(
557 	__in		efx_nic_t *enp);
558 
559 #if EFSYS_OPT_MON_STATS
560 
561 #define	EFX_MON_STATS_PAGE_SIZE 0x100
562 #define	EFX_MON_MASK_ELEMENT_SIZE 32
563 
564 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 5d4ee5185e419abe */
565 typedef enum efx_mon_stat_e {
566 	EFX_MON_STAT_2_5V,
567 	EFX_MON_STAT_VCCP1,
568 	EFX_MON_STAT_VCC,
569 	EFX_MON_STAT_5V,
570 	EFX_MON_STAT_12V,
571 	EFX_MON_STAT_VCCP2,
572 	EFX_MON_STAT_EXT_TEMP,
573 	EFX_MON_STAT_INT_TEMP,
574 	EFX_MON_STAT_AIN1,
575 	EFX_MON_STAT_AIN2,
576 	EFX_MON_STAT_INT_COOLING,
577 	EFX_MON_STAT_EXT_COOLING,
578 	EFX_MON_STAT_1V,
579 	EFX_MON_STAT_1_2V,
580 	EFX_MON_STAT_1_8V,
581 	EFX_MON_STAT_3_3V,
582 	EFX_MON_STAT_1_2VA,
583 	EFX_MON_STAT_VREF,
584 	EFX_MON_STAT_VAOE,
585 	EFX_MON_STAT_AOE_TEMP,
586 	EFX_MON_STAT_PSU_AOE_TEMP,
587 	EFX_MON_STAT_PSU_TEMP,
588 	EFX_MON_STAT_FAN0,
589 	EFX_MON_STAT_FAN1,
590 	EFX_MON_STAT_FAN2,
591 	EFX_MON_STAT_FAN3,
592 	EFX_MON_STAT_FAN4,
593 	EFX_MON_STAT_VAOE_IN,
594 	EFX_MON_STAT_IAOE,
595 	EFX_MON_STAT_IAOE_IN,
596 	EFX_MON_STAT_NIC_POWER,
597 	EFX_MON_STAT_0_9V,
598 	EFX_MON_STAT_I0_9V,
599 	EFX_MON_STAT_I1_2V,
600 	EFX_MON_STAT_0_9V_ADC,
601 	EFX_MON_STAT_INT_TEMP2,
602 	EFX_MON_STAT_VREG_TEMP,
603 	EFX_MON_STAT_VREG_0_9V_TEMP,
604 	EFX_MON_STAT_VREG_1_2V_TEMP,
605 	EFX_MON_STAT_INT_VPTAT,
606 	EFX_MON_STAT_INT_ADC_TEMP,
607 	EFX_MON_STAT_EXT_VPTAT,
608 	EFX_MON_STAT_EXT_ADC_TEMP,
609 	EFX_MON_STAT_AMBIENT_TEMP,
610 	EFX_MON_STAT_AIRFLOW,
611 	EFX_MON_STAT_VDD08D_VSS08D_CSR,
612 	EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
613 	EFX_MON_STAT_HOTPOINT_TEMP,
614 	EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
615 	EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
616 	EFX_MON_STAT_MUM_VCC,
617 	EFX_MON_STAT_0V9_A,
618 	EFX_MON_STAT_I0V9_A,
619 	EFX_MON_STAT_0V9_A_TEMP,
620 	EFX_MON_STAT_0V9_B,
621 	EFX_MON_STAT_I0V9_B,
622 	EFX_MON_STAT_0V9_B_TEMP,
623 	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
624 	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
625 	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
626 	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
627 	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
628 	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
629 	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
630 	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
631 	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
632 	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
633 	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
634 	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
635 	EFX_MON_STAT_SODIMM_VOUT,
636 	EFX_MON_STAT_SODIMM_0_TEMP,
637 	EFX_MON_STAT_SODIMM_1_TEMP,
638 	EFX_MON_STAT_PHY0_VCC,
639 	EFX_MON_STAT_PHY1_VCC,
640 	EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
641 	EFX_MON_STAT_BOARD_FRONT_TEMP,
642 	EFX_MON_STAT_BOARD_BACK_TEMP,
643 	EFX_MON_NSTATS
644 } efx_mon_stat_t;
645 
646 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
647 
648 typedef enum efx_mon_stat_state_e {
649 	EFX_MON_STAT_STATE_OK = 0,
650 	EFX_MON_STAT_STATE_WARNING = 1,
651 	EFX_MON_STAT_STATE_FATAL = 2,
652 	EFX_MON_STAT_STATE_BROKEN = 3,
653 	EFX_MON_STAT_STATE_NO_READING = 4,
654 } efx_mon_stat_state_t;
655 
656 typedef struct efx_mon_stat_value_s {
657 	uint16_t	emsv_value;
658 	uint16_t	emsv_state;
659 } efx_mon_stat_value_t;
660 
661 #if EFSYS_OPT_NAMES
662 
663 extern					const char *
664 efx_mon_stat_name(
665 	__in				efx_nic_t *enp,
666 	__in				efx_mon_stat_t id);
667 
668 #endif	/* EFSYS_OPT_NAMES */
669 
670 extern	__checkReturn			efx_rc_t
671 efx_mon_stats_update(
672 	__in				efx_nic_t *enp,
673 	__in				efsys_mem_t *esmp,
674 	__inout_ecount(EFX_MON_NSTATS)	efx_mon_stat_value_t *values);
675 
676 #endif	/* EFSYS_OPT_MON_STATS */
677 
678 extern		void
679 efx_mon_fini(
680 	__in	efx_nic_t *enp);
681 
682 /* PHY */
683 
684 extern	__checkReturn	efx_rc_t
685 efx_phy_verify(
686 	__in		efx_nic_t *enp);
687 
688 #if EFSYS_OPT_PHY_LED_CONTROL
689 
690 typedef enum efx_phy_led_mode_e {
691 	EFX_PHY_LED_DEFAULT = 0,
692 	EFX_PHY_LED_OFF,
693 	EFX_PHY_LED_ON,
694 	EFX_PHY_LED_FLASH,
695 	EFX_PHY_LED_NMODES
696 } efx_phy_led_mode_t;
697 
698 extern	__checkReturn	efx_rc_t
699 efx_phy_led_set(
700 	__in	efx_nic_t *enp,
701 	__in	efx_phy_led_mode_t mode);
702 
703 #endif	/* EFSYS_OPT_PHY_LED_CONTROL */
704 
705 extern	__checkReturn	efx_rc_t
706 efx_port_init(
707 	__in		efx_nic_t *enp);
708 
709 #if EFSYS_OPT_LOOPBACK
710 
711 typedef enum efx_loopback_type_e {
712 	EFX_LOOPBACK_OFF = 0,
713 	EFX_LOOPBACK_DATA = 1,
714 	EFX_LOOPBACK_GMAC = 2,
715 	EFX_LOOPBACK_XGMII = 3,
716 	EFX_LOOPBACK_XGXS = 4,
717 	EFX_LOOPBACK_XAUI = 5,
718 	EFX_LOOPBACK_GMII = 6,
719 	EFX_LOOPBACK_SGMII = 7,
720 	EFX_LOOPBACK_XGBR = 8,
721 	EFX_LOOPBACK_XFI = 9,
722 	EFX_LOOPBACK_XAUI_FAR = 10,
723 	EFX_LOOPBACK_GMII_FAR = 11,
724 	EFX_LOOPBACK_SGMII_FAR = 12,
725 	EFX_LOOPBACK_XFI_FAR = 13,
726 	EFX_LOOPBACK_GPHY = 14,
727 	EFX_LOOPBACK_PHY_XS = 15,
728 	EFX_LOOPBACK_PCS = 16,
729 	EFX_LOOPBACK_PMA_PMD = 17,
730 	EFX_LOOPBACK_XPORT = 18,
731 	EFX_LOOPBACK_XGMII_WS = 19,
732 	EFX_LOOPBACK_XAUI_WS = 20,
733 	EFX_LOOPBACK_XAUI_WS_FAR = 21,
734 	EFX_LOOPBACK_XAUI_WS_NEAR = 22,
735 	EFX_LOOPBACK_GMII_WS = 23,
736 	EFX_LOOPBACK_XFI_WS = 24,
737 	EFX_LOOPBACK_XFI_WS_FAR = 25,
738 	EFX_LOOPBACK_PHYXS_WS = 26,
739 	EFX_LOOPBACK_PMA_INT = 27,
740 	EFX_LOOPBACK_SD_NEAR = 28,
741 	EFX_LOOPBACK_SD_FAR = 29,
742 	EFX_LOOPBACK_PMA_INT_WS = 30,
743 	EFX_LOOPBACK_SD_FEP2_WS = 31,
744 	EFX_LOOPBACK_SD_FEP1_5_WS = 32,
745 	EFX_LOOPBACK_SD_FEP_WS = 33,
746 	EFX_LOOPBACK_SD_FES_WS = 34,
747 	EFX_LOOPBACK_NTYPES
748 } efx_loopback_type_t;
749 
750 typedef enum efx_loopback_kind_e {
751 	EFX_LOOPBACK_KIND_OFF = 0,
752 	EFX_LOOPBACK_KIND_ALL,
753 	EFX_LOOPBACK_KIND_MAC,
754 	EFX_LOOPBACK_KIND_PHY,
755 	EFX_LOOPBACK_NKINDS
756 } efx_loopback_kind_t;
757 
758 extern			void
759 efx_loopback_mask(
760 	__in	efx_loopback_kind_t loopback_kind,
761 	__out	efx_qword_t *maskp);
762 
763 extern	__checkReturn	efx_rc_t
764 efx_port_loopback_set(
765 	__in	efx_nic_t *enp,
766 	__in	efx_link_mode_t link_mode,
767 	__in	efx_loopback_type_t type);
768 
769 #if EFSYS_OPT_NAMES
770 
771 extern	__checkReturn	const char *
772 efx_loopback_type_name(
773 	__in		efx_nic_t *enp,
774 	__in		efx_loopback_type_t type);
775 
776 #endif	/* EFSYS_OPT_NAMES */
777 
778 #endif	/* EFSYS_OPT_LOOPBACK */
779 
780 extern	__checkReturn	efx_rc_t
781 efx_port_poll(
782 	__in		efx_nic_t *enp,
783 	__out_opt	efx_link_mode_t	*link_modep);
784 
785 extern 		void
786 efx_port_fini(
787 	__in	efx_nic_t *enp);
788 
789 typedef enum efx_phy_cap_type_e {
790 	EFX_PHY_CAP_INVALID = 0,
791 	EFX_PHY_CAP_10HDX,
792 	EFX_PHY_CAP_10FDX,
793 	EFX_PHY_CAP_100HDX,
794 	EFX_PHY_CAP_100FDX,
795 	EFX_PHY_CAP_1000HDX,
796 	EFX_PHY_CAP_1000FDX,
797 	EFX_PHY_CAP_10000FDX,
798 	EFX_PHY_CAP_PAUSE,
799 	EFX_PHY_CAP_ASYM,
800 	EFX_PHY_CAP_AN,
801 	EFX_PHY_CAP_40000FDX,
802 	EFX_PHY_CAP_NTYPES
803 } efx_phy_cap_type_t;
804 
805 
806 #define	EFX_PHY_CAP_CURRENT	0x00000000
807 #define	EFX_PHY_CAP_DEFAULT	0x00000001
808 #define	EFX_PHY_CAP_PERM	0x00000002
809 
810 extern		void
811 efx_phy_adv_cap_get(
812 	__in		efx_nic_t *enp,
813 	__in            uint32_t flag,
814 	__out		uint32_t *maskp);
815 
816 extern	__checkReturn	efx_rc_t
817 efx_phy_adv_cap_set(
818 	__in		efx_nic_t *enp,
819 	__in		uint32_t mask);
820 
821 extern			void
822 efx_phy_lp_cap_get(
823 	__in		efx_nic_t *enp,
824 	__out		uint32_t *maskp);
825 
826 extern	__checkReturn	efx_rc_t
827 efx_phy_oui_get(
828 	__in		efx_nic_t *enp,
829 	__out		uint32_t *ouip);
830 
831 typedef enum efx_phy_media_type_e {
832 	EFX_PHY_MEDIA_INVALID = 0,
833 	EFX_PHY_MEDIA_XAUI,
834 	EFX_PHY_MEDIA_CX4,
835 	EFX_PHY_MEDIA_KX4,
836 	EFX_PHY_MEDIA_XFP,
837 	EFX_PHY_MEDIA_SFP_PLUS,
838 	EFX_PHY_MEDIA_BASE_T,
839 	EFX_PHY_MEDIA_QSFP_PLUS,
840 	EFX_PHY_MEDIA_NTYPES
841 } efx_phy_media_type_t;
842 
843 /* Get the type of medium currently used.  If the board has ports for
844  * modules, a module is present, and we recognise the media type of
845  * the module, then this will be the media type of the module.
846  * Otherwise it will be the media type of the port.
847  */
848 extern			void
849 efx_phy_media_type_get(
850 	__in		efx_nic_t *enp,
851 	__out		efx_phy_media_type_t *typep);
852 
853 extern					efx_rc_t
854 efx_phy_module_get_info(
855 	__in				efx_nic_t *enp,
856 	__in				uint8_t dev_addr,
857 	__in				uint8_t offset,
858 	__in				uint8_t len,
859 	__out_bcount(len)		uint8_t *data);
860 
861 #if EFSYS_OPT_PHY_STATS
862 
863 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
864 typedef enum efx_phy_stat_e {
865 	EFX_PHY_STAT_OUI,
866 	EFX_PHY_STAT_PMA_PMD_LINK_UP,
867 	EFX_PHY_STAT_PMA_PMD_RX_FAULT,
868 	EFX_PHY_STAT_PMA_PMD_TX_FAULT,
869 	EFX_PHY_STAT_PMA_PMD_REV_A,
870 	EFX_PHY_STAT_PMA_PMD_REV_B,
871 	EFX_PHY_STAT_PMA_PMD_REV_C,
872 	EFX_PHY_STAT_PMA_PMD_REV_D,
873 	EFX_PHY_STAT_PCS_LINK_UP,
874 	EFX_PHY_STAT_PCS_RX_FAULT,
875 	EFX_PHY_STAT_PCS_TX_FAULT,
876 	EFX_PHY_STAT_PCS_BER,
877 	EFX_PHY_STAT_PCS_BLOCK_ERRORS,
878 	EFX_PHY_STAT_PHY_XS_LINK_UP,
879 	EFX_PHY_STAT_PHY_XS_RX_FAULT,
880 	EFX_PHY_STAT_PHY_XS_TX_FAULT,
881 	EFX_PHY_STAT_PHY_XS_ALIGN,
882 	EFX_PHY_STAT_PHY_XS_SYNC_A,
883 	EFX_PHY_STAT_PHY_XS_SYNC_B,
884 	EFX_PHY_STAT_PHY_XS_SYNC_C,
885 	EFX_PHY_STAT_PHY_XS_SYNC_D,
886 	EFX_PHY_STAT_AN_LINK_UP,
887 	EFX_PHY_STAT_AN_MASTER,
888 	EFX_PHY_STAT_AN_LOCAL_RX_OK,
889 	EFX_PHY_STAT_AN_REMOTE_RX_OK,
890 	EFX_PHY_STAT_CL22EXT_LINK_UP,
891 	EFX_PHY_STAT_SNR_A,
892 	EFX_PHY_STAT_SNR_B,
893 	EFX_PHY_STAT_SNR_C,
894 	EFX_PHY_STAT_SNR_D,
895 	EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
896 	EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
897 	EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
898 	EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
899 	EFX_PHY_STAT_AN_COMPLETE,
900 	EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
901 	EFX_PHY_STAT_PMA_PMD_REV_MINOR,
902 	EFX_PHY_STAT_PMA_PMD_REV_MICRO,
903 	EFX_PHY_STAT_PCS_FW_VERSION_0,
904 	EFX_PHY_STAT_PCS_FW_VERSION_1,
905 	EFX_PHY_STAT_PCS_FW_VERSION_2,
906 	EFX_PHY_STAT_PCS_FW_VERSION_3,
907 	EFX_PHY_STAT_PCS_FW_BUILD_YY,
908 	EFX_PHY_STAT_PCS_FW_BUILD_MM,
909 	EFX_PHY_STAT_PCS_FW_BUILD_DD,
910 	EFX_PHY_STAT_PCS_OP_MODE,
911 	EFX_PHY_NSTATS
912 } efx_phy_stat_t;
913 
914 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
915 
916 #if EFSYS_OPT_NAMES
917 
918 extern					const char *
919 efx_phy_stat_name(
920 	__in				efx_nic_t *enp,
921 	__in				efx_phy_stat_t stat);
922 
923 #endif	/* EFSYS_OPT_NAMES */
924 
925 #define	EFX_PHY_STATS_SIZE 0x100
926 
927 extern	__checkReturn			efx_rc_t
928 efx_phy_stats_update(
929 	__in				efx_nic_t *enp,
930 	__in				efsys_mem_t *esmp,
931 	__inout_ecount(EFX_PHY_NSTATS)	uint32_t *stat);
932 
933 #endif	/* EFSYS_OPT_PHY_STATS */
934 
935 
936 #if EFSYS_OPT_BIST
937 
938 typedef enum efx_bist_type_e {
939 	EFX_BIST_TYPE_UNKNOWN,
940 	EFX_BIST_TYPE_PHY_NORMAL,
941 	EFX_BIST_TYPE_PHY_CABLE_SHORT,
942 	EFX_BIST_TYPE_PHY_CABLE_LONG,
943 	EFX_BIST_TYPE_MC_MEM,	/* Test the MC DMEM and IMEM */
944 	EFX_BIST_TYPE_SAT_MEM,	/* Test the DMEM and IMEM of satellite cpus*/
945 	EFX_BIST_TYPE_REG,	/* Test the register memories */
946 	EFX_BIST_TYPE_NTYPES,
947 } efx_bist_type_t;
948 
949 typedef enum efx_bist_result_e {
950 	EFX_BIST_RESULT_UNKNOWN,
951 	EFX_BIST_RESULT_RUNNING,
952 	EFX_BIST_RESULT_PASSED,
953 	EFX_BIST_RESULT_FAILED,
954 } efx_bist_result_t;
955 
956 typedef enum efx_phy_cable_status_e {
957 	EFX_PHY_CABLE_STATUS_OK,
958 	EFX_PHY_CABLE_STATUS_INVALID,
959 	EFX_PHY_CABLE_STATUS_OPEN,
960 	EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
961 	EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
962 	EFX_PHY_CABLE_STATUS_BUSY,
963 } efx_phy_cable_status_t;
964 
965 typedef enum efx_bist_value_e {
966 	EFX_BIST_PHY_CABLE_LENGTH_A,
967 	EFX_BIST_PHY_CABLE_LENGTH_B,
968 	EFX_BIST_PHY_CABLE_LENGTH_C,
969 	EFX_BIST_PHY_CABLE_LENGTH_D,
970 	EFX_BIST_PHY_CABLE_STATUS_A,
971 	EFX_BIST_PHY_CABLE_STATUS_B,
972 	EFX_BIST_PHY_CABLE_STATUS_C,
973 	EFX_BIST_PHY_CABLE_STATUS_D,
974 	EFX_BIST_FAULT_CODE,
975 	/* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
976 	 * response. */
977 	EFX_BIST_MEM_TEST,
978 	EFX_BIST_MEM_ADDR,
979 	EFX_BIST_MEM_BUS,
980 	EFX_BIST_MEM_EXPECT,
981 	EFX_BIST_MEM_ACTUAL,
982 	EFX_BIST_MEM_ECC,
983 	EFX_BIST_MEM_ECC_PARITY,
984 	EFX_BIST_MEM_ECC_FATAL,
985 	EFX_BIST_NVALUES,
986 } efx_bist_value_t;
987 
988 extern	__checkReturn		efx_rc_t
989 efx_bist_enable_offline(
990 	__in			efx_nic_t *enp);
991 
992 extern	__checkReturn		efx_rc_t
993 efx_bist_start(
994 	__in			efx_nic_t *enp,
995 	__in			efx_bist_type_t type);
996 
997 extern	__checkReturn		efx_rc_t
998 efx_bist_poll(
999 	__in			efx_nic_t *enp,
1000 	__in			efx_bist_type_t type,
1001 	__out			efx_bist_result_t *resultp,
1002 	__out_opt		uint32_t *value_maskp,
1003 	__out_ecount_opt(count)	unsigned long *valuesp,
1004 	__in			size_t count);
1005 
1006 extern				void
1007 efx_bist_stop(
1008 	__in			efx_nic_t *enp,
1009 	__in			efx_bist_type_t type);
1010 
1011 #endif	/* EFSYS_OPT_BIST */
1012 
1013 #define	EFX_FEATURE_IPV6		0x00000001
1014 #define	EFX_FEATURE_LFSR_HASH_INSERT	0x00000002
1015 #define	EFX_FEATURE_LINK_EVENTS		0x00000004
1016 #define	EFX_FEATURE_PERIODIC_MAC_STATS	0x00000008
1017 #define	EFX_FEATURE_WOL			0x00000010
1018 #define	EFX_FEATURE_MCDI		0x00000020
1019 #define	EFX_FEATURE_LOOKAHEAD_SPLIT	0x00000040
1020 #define	EFX_FEATURE_MAC_HEADER_FILTERS	0x00000080
1021 #define	EFX_FEATURE_TURBO		0x00000100
1022 #define	EFX_FEATURE_MCDI_DMA		0x00000200
1023 #define	EFX_FEATURE_TX_SRC_FILTERS	0x00000400
1024 #define	EFX_FEATURE_PIO_BUFFERS		0x00000800
1025 #define	EFX_FEATURE_FW_ASSISTED_TSO	0x00001000
1026 #define	EFX_FEATURE_FW_ASSISTED_TSO_V2	0x00002000
1027 
1028 typedef struct efx_nic_cfg_s {
1029 	uint32_t		enc_board_type;
1030 	uint32_t		enc_phy_type;
1031 #if EFSYS_OPT_NAMES
1032 	char			enc_phy_name[21];
1033 #endif
1034 	char			enc_phy_revision[21];
1035 	efx_mon_type_t		enc_mon_type;
1036 #if EFSYS_OPT_MON_STATS
1037 	uint32_t		enc_mon_stat_dma_buf_size;
1038 	uint32_t		enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1039 #endif
1040 	unsigned int		enc_features;
1041 	uint8_t			enc_mac_addr[6];
1042 	uint8_t			enc_port;	/* PHY port number */
1043 	uint32_t		enc_func_flags;
1044 	uint32_t		enc_intr_vec_base;
1045 	uint32_t		enc_intr_limit;
1046 	uint32_t		enc_evq_limit;
1047 	uint32_t		enc_txq_limit;
1048 	uint32_t		enc_rxq_limit;
1049 	uint32_t		enc_buftbl_limit;
1050 	uint32_t		enc_piobuf_limit;
1051 	uint32_t		enc_piobuf_size;
1052 	uint32_t		enc_piobuf_min_alloc_size;
1053 	uint32_t		enc_evq_timer_quantum_ns;
1054 	uint32_t		enc_evq_timer_max_us;
1055 	uint32_t		enc_clk_mult;
1056 	uint32_t		enc_rx_prefix_size;
1057 	uint32_t		enc_rx_buf_align_start;
1058 	uint32_t		enc_rx_buf_align_end;
1059 #if EFSYS_OPT_LOOPBACK
1060 	efx_qword_t		enc_loopback_types[EFX_LINK_NMODES];
1061 #endif	/* EFSYS_OPT_LOOPBACK */
1062 #if EFSYS_OPT_PHY_FLAGS
1063 	uint32_t		enc_phy_flags_mask;
1064 #endif	/* EFSYS_OPT_PHY_FLAGS */
1065 #if EFSYS_OPT_PHY_LED_CONTROL
1066 	uint32_t		enc_led_mask;
1067 #endif	/* EFSYS_OPT_PHY_LED_CONTROL */
1068 #if EFSYS_OPT_PHY_STATS
1069 	uint64_t		enc_phy_stat_mask;
1070 #endif	/* EFSYS_OPT_PHY_STATS */
1071 #if EFSYS_OPT_SIENA
1072 	uint8_t			enc_mcdi_mdio_channel;
1073 #if EFSYS_OPT_PHY_STATS
1074 	uint32_t		enc_mcdi_phy_stat_mask;
1075 #endif	/* EFSYS_OPT_PHY_STATS */
1076 #endif /* EFSYS_OPT_SIENA */
1077 #if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
1078 #if EFSYS_OPT_MON_STATS
1079 	uint32_t		*enc_mcdi_sensor_maskp;
1080 	uint32_t		enc_mcdi_sensor_mask_size;
1081 #endif	/* EFSYS_OPT_MON_STATS */
1082 #endif	/* (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
1083 #if EFSYS_OPT_BIST
1084 	uint32_t		enc_bist_mask;
1085 #endif	/* EFSYS_OPT_BIST */
1086 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1087 	uint32_t		enc_pf;
1088 	uint32_t		enc_vf;
1089 	uint32_t		enc_privilege_mask;
1090 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1091 	boolean_t		enc_bug26807_workaround;
1092 	boolean_t		enc_bug35388_workaround;
1093 	boolean_t		enc_bug41750_workaround;
1094 	boolean_t		enc_rx_batching_enabled;
1095 	/* Maximum number of descriptors completed in an rx event. */
1096 	uint32_t		enc_rx_batch_max;
1097         /* Number of rx descriptors the hardware requires for a push. */
1098         uint32_t		enc_rx_push_align;
1099 	/*
1100 	 * Maximum number of bytes into the packet the TCP header can start for
1101 	 * the hardware to apply TSO packet edits.
1102 	 */
1103 	uint32_t                enc_tx_tso_tcp_header_offset_limit;
1104 	boolean_t               enc_fw_assisted_tso_enabled;
1105 	boolean_t               enc_fw_assisted_tso_v2_enabled;
1106 	boolean_t               enc_hw_tx_insert_vlan_enabled;
1107 	/* Datapath firmware vadapter/vport/vswitch support */
1108 	boolean_t		enc_datapath_cap_evb;
1109 	boolean_t               enc_rx_disable_scatter_supported;
1110 	boolean_t               enc_allow_set_mac_with_installed_filters;
1111 	boolean_t		enc_enhanced_set_mac_supported;
1112 	/* External port identifier */
1113 	uint8_t			enc_external_port;
1114 	uint32_t		enc_mcdi_max_payload_length;
1115 	/* VPD may be per-PF or global */
1116 	boolean_t		enc_vpd_is_global;
1117 } efx_nic_cfg_t;
1118 
1119 #define	EFX_PCI_FUNCTION_IS_PF(_encp)	((_encp)->enc_vf == 0xffff)
1120 #define	EFX_PCI_FUNCTION_IS_VF(_encp)	((_encp)->enc_vf != 0xffff)
1121 
1122 #define	EFX_PCI_FUNCTION(_encp)	\
1123 	(EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1124 
1125 #define	EFX_PCI_VF_PARENT(_encp)	((_encp)->enc_pf)
1126 
1127 extern			const efx_nic_cfg_t *
1128 efx_nic_cfg_get(
1129 	__in		efx_nic_t *enp);
1130 
1131 /* Driver resource limits (minimum required/maximum usable). */
1132 typedef struct efx_drv_limits_s
1133 {
1134 	uint32_t	edl_min_evq_count;
1135 	uint32_t	edl_max_evq_count;
1136 
1137 	uint32_t	edl_min_rxq_count;
1138 	uint32_t	edl_max_rxq_count;
1139 
1140 	uint32_t	edl_min_txq_count;
1141 	uint32_t	edl_max_txq_count;
1142 
1143 	/* PIO blocks (sub-allocated from piobuf) */
1144 	uint32_t	edl_min_pio_alloc_size;
1145 	uint32_t	edl_max_pio_alloc_count;
1146 } efx_drv_limits_t;
1147 
1148 extern	__checkReturn	efx_rc_t
1149 efx_nic_set_drv_limits(
1150 	__inout		efx_nic_t *enp,
1151 	__in		efx_drv_limits_t *edlp);
1152 
1153 typedef enum efx_nic_region_e {
1154 	EFX_REGION_VI,			/* Memory BAR UC mapping */
1155 	EFX_REGION_PIO_WRITE_VI,	/* Memory BAR WC mapping */
1156 } efx_nic_region_t;
1157 
1158 extern	__checkReturn	efx_rc_t
1159 efx_nic_get_bar_region(
1160 	__in		efx_nic_t *enp,
1161 	__in		efx_nic_region_t region,
1162 	__out		uint32_t *offsetp,
1163 	__out		size_t *sizep);
1164 
1165 extern	__checkReturn	efx_rc_t
1166 efx_nic_get_vi_pool(
1167 	__in		efx_nic_t *enp,
1168 	__out		uint32_t *evq_countp,
1169 	__out		uint32_t *rxq_countp,
1170 	__out		uint32_t *txq_countp);
1171 
1172 
1173 #if EFSYS_OPT_VPD
1174 
1175 typedef enum efx_vpd_tag_e {
1176 	EFX_VPD_ID = 0x02,
1177 	EFX_VPD_END = 0x0f,
1178 	EFX_VPD_RO = 0x10,
1179 	EFX_VPD_RW = 0x11,
1180 } efx_vpd_tag_t;
1181 
1182 typedef uint16_t efx_vpd_keyword_t;
1183 
1184 typedef struct efx_vpd_value_s {
1185 	efx_vpd_tag_t		evv_tag;
1186 	efx_vpd_keyword_t	evv_keyword;
1187 	uint8_t			evv_length;
1188 	uint8_t			evv_value[0x100];
1189 } efx_vpd_value_t;
1190 
1191 
1192 #define	EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1193 
1194 extern	__checkReturn		efx_rc_t
1195 efx_vpd_init(
1196 	__in			efx_nic_t *enp);
1197 
1198 extern	__checkReturn		efx_rc_t
1199 efx_vpd_size(
1200 	__in			efx_nic_t *enp,
1201 	__out			size_t *sizep);
1202 
1203 extern	__checkReturn		efx_rc_t
1204 efx_vpd_read(
1205 	__in			efx_nic_t *enp,
1206 	__out_bcount(size)	caddr_t data,
1207 	__in			size_t size);
1208 
1209 extern	__checkReturn		efx_rc_t
1210 efx_vpd_verify(
1211 	__in			efx_nic_t *enp,
1212 	__in_bcount(size)	caddr_t data,
1213 	__in			size_t size);
1214 
1215 extern  __checkReturn		efx_rc_t
1216 efx_vpd_reinit(
1217 	__in			efx_nic_t *enp,
1218 	__in_bcount(size)	caddr_t data,
1219 	__in			size_t size);
1220 
1221 extern	__checkReturn		efx_rc_t
1222 efx_vpd_get(
1223 	__in			efx_nic_t *enp,
1224 	__in_bcount(size)	caddr_t data,
1225 	__in			size_t size,
1226 	__inout			efx_vpd_value_t *evvp);
1227 
1228 extern	__checkReturn		efx_rc_t
1229 efx_vpd_set(
1230 	__in			efx_nic_t *enp,
1231 	__inout_bcount(size)	caddr_t data,
1232 	__in			size_t size,
1233 	__in			efx_vpd_value_t *evvp);
1234 
1235 extern	__checkReturn		efx_rc_t
1236 efx_vpd_next(
1237 	__in			efx_nic_t *enp,
1238 	__inout_bcount(size)	caddr_t data,
1239 	__in			size_t size,
1240 	__out			efx_vpd_value_t *evvp,
1241 	__inout			unsigned int *contp);
1242 
1243 extern __checkReturn		efx_rc_t
1244 efx_vpd_write(
1245 	__in			efx_nic_t *enp,
1246 	__in_bcount(size)	caddr_t data,
1247 	__in			size_t size);
1248 
1249 extern				void
1250 efx_vpd_fini(
1251 	__in			efx_nic_t *enp);
1252 
1253 #endif	/* EFSYS_OPT_VPD */
1254 
1255 /* NVRAM */
1256 
1257 #if EFSYS_OPT_NVRAM
1258 
1259 typedef enum efx_nvram_type_e {
1260 	EFX_NVRAM_INVALID = 0,
1261 	EFX_NVRAM_BOOTROM,
1262 	EFX_NVRAM_BOOTROM_CFG,
1263 	EFX_NVRAM_MC_FIRMWARE,
1264 	EFX_NVRAM_MC_GOLDEN,
1265 	EFX_NVRAM_PHY,
1266 	EFX_NVRAM_NULLPHY,
1267 	EFX_NVRAM_FPGA,
1268 	EFX_NVRAM_FCFW,
1269 	EFX_NVRAM_CPLD,
1270 	EFX_NVRAM_FPGA_BACKUP,
1271 	EFX_NVRAM_DYNAMIC_CFG,
1272 	EFX_NVRAM_LICENSE,
1273 	EFX_NVRAM_NTYPES,
1274 } efx_nvram_type_t;
1275 
1276 extern	__checkReturn		efx_rc_t
1277 efx_nvram_init(
1278 	__in			efx_nic_t *enp);
1279 
1280 #if EFSYS_OPT_DIAG
1281 
1282 extern	__checkReturn		efx_rc_t
1283 efx_nvram_test(
1284 	__in			efx_nic_t *enp);
1285 
1286 #endif	/* EFSYS_OPT_DIAG */
1287 
1288 extern	__checkReturn		efx_rc_t
1289 efx_nvram_size(
1290 	__in			efx_nic_t *enp,
1291 	__in			efx_nvram_type_t type,
1292 	__out			size_t *sizep);
1293 
1294 extern	__checkReturn		efx_rc_t
1295 efx_nvram_rw_start(
1296 	__in			efx_nic_t *enp,
1297 	__in			efx_nvram_type_t type,
1298 	__out_opt		size_t *pref_chunkp);
1299 
1300 extern				void
1301 efx_nvram_rw_finish(
1302 	__in			efx_nic_t *enp,
1303 	__in			efx_nvram_type_t type);
1304 
1305 extern	__checkReturn		efx_rc_t
1306 efx_nvram_get_version(
1307 	__in			efx_nic_t *enp,
1308 	__in			efx_nvram_type_t type,
1309 	__out			uint32_t *subtypep,
1310 	__out_ecount(4)		uint16_t version[4]);
1311 
1312 extern	__checkReturn		efx_rc_t
1313 efx_nvram_read_chunk(
1314 	__in			efx_nic_t *enp,
1315 	__in			efx_nvram_type_t type,
1316 	__in			unsigned int offset,
1317 	__out_bcount(size)	caddr_t data,
1318 	__in			size_t size);
1319 
1320 extern	__checkReturn		efx_rc_t
1321 efx_nvram_set_version(
1322 	__in			efx_nic_t *enp,
1323 	__in			efx_nvram_type_t type,
1324 	__in_ecount(4)		uint16_t version[4]);
1325 
1326 extern	__checkReturn		efx_rc_t
1327 efx_nvram_validate(
1328 	__in			efx_nic_t *enp,
1329 	__in			efx_nvram_type_t type,
1330 	__in_bcount(partn_size)	caddr_t partn_data,
1331 	__in			size_t partn_size);
1332 
1333 extern	 __checkReturn		efx_rc_t
1334 efx_nvram_erase(
1335 	__in			efx_nic_t *enp,
1336 	__in			efx_nvram_type_t type);
1337 
1338 extern	__checkReturn		efx_rc_t
1339 efx_nvram_write_chunk(
1340 	__in			efx_nic_t *enp,
1341 	__in			efx_nvram_type_t type,
1342 	__in			unsigned int offset,
1343 	__in_bcount(size)	caddr_t data,
1344 	__in			size_t size);
1345 
1346 extern				void
1347 efx_nvram_fini(
1348 	__in			efx_nic_t *enp);
1349 
1350 #endif	/* EFSYS_OPT_NVRAM */
1351 
1352 #if EFSYS_OPT_BOOTCFG
1353 
1354 extern				efx_rc_t
1355 efx_bootcfg_read(
1356 	__in			efx_nic_t *enp,
1357 	__out_bcount(size)	caddr_t data,
1358 	__in			size_t size);
1359 
1360 extern				efx_rc_t
1361 efx_bootcfg_write(
1362 	__in			efx_nic_t *enp,
1363 	__in_bcount(size)	caddr_t data,
1364 	__in			size_t size);
1365 
1366 #endif	/* EFSYS_OPT_BOOTCFG */
1367 
1368 #if EFSYS_OPT_WOL
1369 
1370 typedef enum efx_wol_type_e {
1371 	EFX_WOL_TYPE_INVALID,
1372 	EFX_WOL_TYPE_MAGIC,
1373 	EFX_WOL_TYPE_BITMAP,
1374 	EFX_WOL_TYPE_LINK,
1375 	EFX_WOL_NTYPES,
1376 } efx_wol_type_t;
1377 
1378 typedef enum efx_lightsout_offload_type_e {
1379 	EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID,
1380 	EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP,
1381 	EFX_LIGHTSOUT_OFFLOAD_TYPE_NS,
1382 } efx_lightsout_offload_type_t;
1383 
1384 #define	EFX_WOL_BITMAP_MASK_SIZE    (48)
1385 #define	EFX_WOL_BITMAP_VALUE_SIZE   (128)
1386 
1387 typedef union efx_wol_param_u {
1388 	struct {
1389 		uint8_t mac_addr[6];
1390 	} ewp_magic;
1391 	struct {
1392 		uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE];   /* 1 bit per byte */
1393 		uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */
1394 		uint8_t value_len;
1395 	} ewp_bitmap;
1396 } efx_wol_param_t;
1397 
1398 typedef union efx_lightsout_offload_param_u {
1399 	struct {
1400 		uint8_t mac_addr[6];
1401 		uint32_t ip;
1402 	} elop_arp;
1403 	struct {
1404 		uint8_t mac_addr[6];
1405 		uint32_t solicited_node[4];
1406 		uint32_t ip[4];
1407 	} elop_ns;
1408 } efx_lightsout_offload_param_t;
1409 
1410 extern	__checkReturn	efx_rc_t
1411 efx_wol_init(
1412 	__in		efx_nic_t *enp);
1413 
1414 extern	__checkReturn	efx_rc_t
1415 efx_wol_filter_clear(
1416 	__in		efx_nic_t *enp);
1417 
1418 extern	__checkReturn	efx_rc_t
1419 efx_wol_filter_add(
1420 	__in		efx_nic_t *enp,
1421 	__in		efx_wol_type_t type,
1422 	__in		efx_wol_param_t *paramp,
1423 	__out		uint32_t *filter_idp);
1424 
1425 extern	__checkReturn	efx_rc_t
1426 efx_wol_filter_remove(
1427 	__in		efx_nic_t *enp,
1428 	__in		uint32_t filter_id);
1429 
1430 extern	__checkReturn	efx_rc_t
1431 efx_lightsout_offload_add(
1432 	__in		efx_nic_t *enp,
1433 	__in		efx_lightsout_offload_type_t type,
1434 	__in		efx_lightsout_offload_param_t *paramp,
1435 	__out		uint32_t *filter_idp);
1436 
1437 extern	__checkReturn	efx_rc_t
1438 efx_lightsout_offload_remove(
1439 	__in		efx_nic_t *enp,
1440 	__in		efx_lightsout_offload_type_t type,
1441 	__in		uint32_t filter_id);
1442 
1443 extern			void
1444 efx_wol_fini(
1445 	__in		efx_nic_t *enp);
1446 
1447 #endif	/* EFSYS_OPT_WOL */
1448 
1449 #if EFSYS_OPT_DIAG
1450 
1451 typedef enum efx_pattern_type_t {
1452 	EFX_PATTERN_BYTE_INCREMENT = 0,
1453 	EFX_PATTERN_ALL_THE_SAME,
1454 	EFX_PATTERN_BIT_ALTERNATE,
1455 	EFX_PATTERN_BYTE_ALTERNATE,
1456 	EFX_PATTERN_BYTE_CHANGING,
1457 	EFX_PATTERN_BIT_SWEEP,
1458 	EFX_PATTERN_NTYPES
1459 } efx_pattern_type_t;
1460 
1461 typedef 		void
1462 (*efx_sram_pattern_fn_t)(
1463 	__in		size_t row,
1464 	__in		boolean_t negate,
1465 	__out		efx_qword_t *eqp);
1466 
1467 extern	__checkReturn	efx_rc_t
1468 efx_sram_test(
1469 	__in		efx_nic_t *enp,
1470 	__in		efx_pattern_type_t type);
1471 
1472 #endif	/* EFSYS_OPT_DIAG */
1473 
1474 extern	__checkReturn	efx_rc_t
1475 efx_sram_buf_tbl_set(
1476 	__in		efx_nic_t *enp,
1477 	__in		uint32_t id,
1478 	__in		efsys_mem_t *esmp,
1479 	__in		size_t n);
1480 
1481 extern		void
1482 efx_sram_buf_tbl_clear(
1483 	__in	efx_nic_t *enp,
1484 	__in	uint32_t id,
1485 	__in	size_t n);
1486 
1487 #define	EFX_BUF_TBL_SIZE	0x20000
1488 
1489 #define	EFX_BUF_SIZE		4096
1490 
1491 /* EV */
1492 
1493 typedef struct efx_evq_s	efx_evq_t;
1494 
1495 #if EFSYS_OPT_QSTATS
1496 
1497 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1498 typedef enum efx_ev_qstat_e {
1499 	EV_ALL,
1500 	EV_RX,
1501 	EV_RX_OK,
1502 	EV_RX_FRM_TRUNC,
1503 	EV_RX_TOBE_DISC,
1504 	EV_RX_PAUSE_FRM_ERR,
1505 	EV_RX_BUF_OWNER_ID_ERR,
1506 	EV_RX_IPV4_HDR_CHKSUM_ERR,
1507 	EV_RX_TCP_UDP_CHKSUM_ERR,
1508 	EV_RX_ETH_CRC_ERR,
1509 	EV_RX_IP_FRAG_ERR,
1510 	EV_RX_MCAST_PKT,
1511 	EV_RX_MCAST_HASH_MATCH,
1512 	EV_RX_TCP_IPV4,
1513 	EV_RX_TCP_IPV6,
1514 	EV_RX_UDP_IPV4,
1515 	EV_RX_UDP_IPV6,
1516 	EV_RX_OTHER_IPV4,
1517 	EV_RX_OTHER_IPV6,
1518 	EV_RX_NON_IP,
1519 	EV_RX_BATCH,
1520 	EV_TX,
1521 	EV_TX_WQ_FF_FULL,
1522 	EV_TX_PKT_ERR,
1523 	EV_TX_PKT_TOO_BIG,
1524 	EV_TX_UNEXPECTED,
1525 	EV_GLOBAL,
1526 	EV_GLOBAL_MNT,
1527 	EV_DRIVER,
1528 	EV_DRIVER_SRM_UPD_DONE,
1529 	EV_DRIVER_TX_DESCQ_FLS_DONE,
1530 	EV_DRIVER_RX_DESCQ_FLS_DONE,
1531 	EV_DRIVER_RX_DESCQ_FLS_FAILED,
1532 	EV_DRIVER_RX_DSC_ERROR,
1533 	EV_DRIVER_TX_DSC_ERROR,
1534 	EV_DRV_GEN,
1535 	EV_MCDI_RESPONSE,
1536 	EV_NQSTATS
1537 } efx_ev_qstat_t;
1538 
1539 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1540 
1541 #endif	/* EFSYS_OPT_QSTATS */
1542 
1543 extern	__checkReturn	efx_rc_t
1544 efx_ev_init(
1545 	__in		efx_nic_t *enp);
1546 
1547 extern		void
1548 efx_ev_fini(
1549 	__in		efx_nic_t *enp);
1550 
1551 #define	EFX_EVQ_MAXNEVS		32768
1552 #define	EFX_EVQ_MINNEVS		512
1553 
1554 #define	EFX_EVQ_SIZE(_nevs)	((_nevs) * sizeof (efx_qword_t))
1555 #define	EFX_EVQ_NBUFS(_nevs)	(EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1556 
1557 extern	__checkReturn	efx_rc_t
1558 efx_ev_qcreate(
1559 	__in		efx_nic_t *enp,
1560 	__in		unsigned int index,
1561 	__in		efsys_mem_t *esmp,
1562 	__in		size_t n,
1563 	__in		uint32_t id,
1564 	__deref_out	efx_evq_t **eepp);
1565 
1566 extern		void
1567 efx_ev_qpost(
1568 	__in		efx_evq_t *eep,
1569 	__in		uint16_t data);
1570 
1571 typedef __checkReturn	boolean_t
1572 (*efx_initialized_ev_t)(
1573 	__in_opt	void *arg);
1574 
1575 #define	EFX_PKT_UNICAST		0x0004
1576 #define	EFX_PKT_START		0x0008
1577 
1578 #define	EFX_PKT_VLAN_TAGGED	0x0010
1579 #define	EFX_CKSUM_TCPUDP	0x0020
1580 #define	EFX_CKSUM_IPV4		0x0040
1581 #define	EFX_PKT_CONT		0x0080
1582 
1583 #define	EFX_CHECK_VLAN		0x0100
1584 #define	EFX_PKT_TCP		0x0200
1585 #define	EFX_PKT_UDP		0x0400
1586 #define	EFX_PKT_IPV4		0x0800
1587 
1588 #define	EFX_PKT_IPV6		0x1000
1589 #define	EFX_PKT_PREFIX_LEN	0x2000
1590 #define	EFX_ADDR_MISMATCH	0x4000
1591 #define	EFX_DISCARD		0x8000
1592 
1593 #define	EFX_EV_RX_NLABELS	32
1594 #define	EFX_EV_TX_NLABELS	32
1595 
1596 typedef	__checkReturn	boolean_t
1597 (*efx_rx_ev_t)(
1598 	__in_opt	void *arg,
1599 	__in		uint32_t label,
1600 	__in		uint32_t id,
1601 	__in		uint32_t size,
1602 	__in		uint16_t flags);
1603 
1604 typedef	__checkReturn	boolean_t
1605 (*efx_tx_ev_t)(
1606 	__in_opt	void *arg,
1607 	__in		uint32_t label,
1608 	__in		uint32_t id);
1609 
1610 #define	EFX_EXCEPTION_RX_RECOVERY	0x00000001
1611 #define	EFX_EXCEPTION_RX_DSC_ERROR	0x00000002
1612 #define	EFX_EXCEPTION_TX_DSC_ERROR	0x00000003
1613 #define	EFX_EXCEPTION_UNKNOWN_SENSOREVT	0x00000004
1614 #define	EFX_EXCEPTION_FWALERT_SRAM	0x00000005
1615 #define	EFX_EXCEPTION_UNKNOWN_FWALERT	0x00000006
1616 #define	EFX_EXCEPTION_RX_ERROR		0x00000007
1617 #define	EFX_EXCEPTION_TX_ERROR		0x00000008
1618 #define	EFX_EXCEPTION_EV_ERROR		0x00000009
1619 
1620 typedef	__checkReturn	boolean_t
1621 (*efx_exception_ev_t)(
1622 	__in_opt	void *arg,
1623 	__in		uint32_t label,
1624 	__in		uint32_t data);
1625 
1626 typedef	__checkReturn	boolean_t
1627 (*efx_rxq_flush_done_ev_t)(
1628 	__in_opt	void *arg,
1629 	__in		uint32_t rxq_index);
1630 
1631 typedef	__checkReturn	boolean_t
1632 (*efx_rxq_flush_failed_ev_t)(
1633 	__in_opt	void *arg,
1634 	__in		uint32_t rxq_index);
1635 
1636 typedef	__checkReturn	boolean_t
1637 (*efx_txq_flush_done_ev_t)(
1638 	__in_opt	void *arg,
1639 	__in		uint32_t txq_index);
1640 
1641 typedef	__checkReturn	boolean_t
1642 (*efx_software_ev_t)(
1643 	__in_opt	void *arg,
1644 	__in		uint16_t magic);
1645 
1646 typedef	__checkReturn	boolean_t
1647 (*efx_sram_ev_t)(
1648 	__in_opt	void *arg,
1649 	__in		uint32_t code);
1650 
1651 #define	EFX_SRAM_CLEAR		0
1652 #define	EFX_SRAM_UPDATE		1
1653 #define	EFX_SRAM_ILLEGAL_CLEAR	2
1654 
1655 typedef	__checkReturn	boolean_t
1656 (*efx_wake_up_ev_t)(
1657 	__in_opt	void *arg,
1658 	__in		uint32_t label);
1659 
1660 typedef	__checkReturn	boolean_t
1661 (*efx_timer_ev_t)(
1662 	__in_opt	void *arg,
1663 	__in		uint32_t label);
1664 
1665 typedef __checkReturn	boolean_t
1666 (*efx_link_change_ev_t)(
1667 	__in_opt	void *arg,
1668 	__in		efx_link_mode_t	link_mode);
1669 
1670 #if EFSYS_OPT_MON_STATS
1671 
1672 typedef __checkReturn	boolean_t
1673 (*efx_monitor_ev_t)(
1674 	__in_opt	void *arg,
1675 	__in		efx_mon_stat_t id,
1676 	__in		efx_mon_stat_value_t value);
1677 
1678 #endif	/* EFSYS_OPT_MON_STATS */
1679 
1680 #if EFSYS_OPT_MAC_STATS
1681 
1682 typedef __checkReturn	boolean_t
1683 (*efx_mac_stats_ev_t)(
1684 	__in_opt	void *arg,
1685 	__in		uint32_t generation
1686 	);
1687 
1688 #endif	/* EFSYS_OPT_MAC_STATS */
1689 
1690 typedef struct efx_ev_callbacks_s {
1691 	efx_initialized_ev_t		eec_initialized;
1692 	efx_rx_ev_t			eec_rx;
1693 	efx_tx_ev_t			eec_tx;
1694 	efx_exception_ev_t		eec_exception;
1695 	efx_rxq_flush_done_ev_t		eec_rxq_flush_done;
1696 	efx_rxq_flush_failed_ev_t	eec_rxq_flush_failed;
1697 	efx_txq_flush_done_ev_t		eec_txq_flush_done;
1698 	efx_software_ev_t		eec_software;
1699 	efx_sram_ev_t			eec_sram;
1700 	efx_wake_up_ev_t		eec_wake_up;
1701 	efx_timer_ev_t			eec_timer;
1702 	efx_link_change_ev_t		eec_link_change;
1703 #if EFSYS_OPT_MON_STATS
1704 	efx_monitor_ev_t		eec_monitor;
1705 #endif	/* EFSYS_OPT_MON_STATS */
1706 #if EFSYS_OPT_MAC_STATS
1707 	efx_mac_stats_ev_t		eec_mac_stats;
1708 #endif	/* EFSYS_OPT_MAC_STATS */
1709 } efx_ev_callbacks_t;
1710 
1711 extern	__checkReturn	boolean_t
1712 efx_ev_qpending(
1713 	__in		efx_evq_t *eep,
1714 	__in		unsigned int count);
1715 
1716 #if EFSYS_OPT_EV_PREFETCH
1717 
1718 extern			void
1719 efx_ev_qprefetch(
1720 	__in		efx_evq_t *eep,
1721 	__in		unsigned int count);
1722 
1723 #endif	/* EFSYS_OPT_EV_PREFETCH */
1724 
1725 extern			void
1726 efx_ev_qpoll(
1727 	__in		efx_evq_t *eep,
1728 	__inout		unsigned int *countp,
1729 	__in		const efx_ev_callbacks_t *eecp,
1730 	__in_opt	void *arg);
1731 
1732 extern	__checkReturn	efx_rc_t
1733 efx_ev_qmoderate(
1734 	__in		efx_evq_t *eep,
1735 	__in		unsigned int us);
1736 
1737 extern	__checkReturn	efx_rc_t
1738 efx_ev_qprime(
1739 	__in		efx_evq_t *eep,
1740 	__in		unsigned int count);
1741 
1742 #if EFSYS_OPT_QSTATS
1743 
1744 #if EFSYS_OPT_NAMES
1745 
1746 extern		const char *
1747 efx_ev_qstat_name(
1748 	__in	efx_nic_t *enp,
1749 	__in	unsigned int id);
1750 
1751 #endif	/* EFSYS_OPT_NAMES */
1752 
1753 extern					void
1754 efx_ev_qstats_update(
1755 	__in				efx_evq_t *eep,
1756 	__inout_ecount(EV_NQSTATS)	efsys_stat_t *stat);
1757 
1758 #endif	/* EFSYS_OPT_QSTATS */
1759 
1760 extern		void
1761 efx_ev_qdestroy(
1762 	__in	efx_evq_t *eep);
1763 
1764 /* RX */
1765 
1766 extern	__checkReturn	efx_rc_t
1767 efx_rx_init(
1768 	__inout		efx_nic_t *enp);
1769 
1770 extern		void
1771 efx_rx_fini(
1772 	__in		efx_nic_t *enp);
1773 
1774 #if EFSYS_OPT_RX_SCATTER
1775 	__checkReturn	efx_rc_t
1776 efx_rx_scatter_enable(
1777 	__in		efx_nic_t *enp,
1778 	__in		unsigned int buf_size);
1779 #endif	/* EFSYS_OPT_RX_SCATTER */
1780 
1781 #if EFSYS_OPT_RX_SCALE
1782 
1783 typedef enum efx_rx_hash_alg_e {
1784 	EFX_RX_HASHALG_LFSR = 0,
1785 	EFX_RX_HASHALG_TOEPLITZ
1786 } efx_rx_hash_alg_t;
1787 
1788 typedef enum efx_rx_hash_type_e {
1789 	EFX_RX_HASH_IPV4 = 0,
1790 	EFX_RX_HASH_TCPIPV4,
1791 	EFX_RX_HASH_IPV6,
1792 	EFX_RX_HASH_TCPIPV6,
1793 } efx_rx_hash_type_t;
1794 
1795 typedef enum efx_rx_hash_support_e {
1796 	EFX_RX_HASH_UNAVAILABLE = 0,	/* Hardware hash not inserted */
1797 	EFX_RX_HASH_AVAILABLE		/* Insert hash with/without RSS */
1798 } efx_rx_hash_support_t;
1799 
1800 #define	EFX_RSS_TBL_SIZE	128	/* Rows in RX indirection table */
1801 #define	EFX_MAXRSS	    	64	/* RX indirection entry range */
1802 #define	EFX_MAXRSS_LEGACY   	16 	/* See bug16611 and bug17213 */
1803 
1804 typedef enum efx_rx_scale_support_e {
1805 	EFX_RX_SCALE_UNAVAILABLE = 0,	/* Not supported */
1806 	EFX_RX_SCALE_EXCLUSIVE,		/* Writable key/indirection table */
1807 	EFX_RX_SCALE_SHARED		/* Read-only key/indirection table */
1808 } efx_rx_scale_support_t;
1809 
1810 extern	__checkReturn	efx_rc_t
1811 efx_rx_hash_support_get(
1812 	__in		efx_nic_t *enp,
1813 	__out		efx_rx_hash_support_t *supportp);
1814 
1815 
1816 extern	__checkReturn	efx_rc_t
1817 efx_rx_scale_support_get(
1818 	__in		efx_nic_t *enp,
1819 	__out		efx_rx_scale_support_t *supportp);
1820 
1821 extern	__checkReturn	efx_rc_t
1822 efx_rx_scale_mode_set(
1823 	__in	efx_nic_t *enp,
1824 	__in	efx_rx_hash_alg_t alg,
1825 	__in	efx_rx_hash_type_t type,
1826 	__in	boolean_t insert);
1827 
1828 extern	__checkReturn	efx_rc_t
1829 efx_rx_scale_tbl_set(
1830 	__in		efx_nic_t *enp,
1831 	__in_ecount(n)	unsigned int *table,
1832 	__in		size_t n);
1833 
1834 extern	__checkReturn	efx_rc_t
1835 efx_rx_scale_key_set(
1836 	__in		efx_nic_t *enp,
1837 	__in_ecount(n)	uint8_t *key,
1838 	__in		size_t n);
1839 
1840 extern	__checkReturn	uint32_t
1841 efx_psuedo_hdr_hash_get(
1842 	__in		efx_nic_t *enp,
1843 	__in		efx_rx_hash_alg_t func,
1844 	__in		uint8_t *buffer);
1845 
1846 #endif	/* EFSYS_OPT_RX_SCALE */
1847 
1848 extern	__checkReturn	efx_rc_t
1849 efx_psuedo_hdr_pkt_length_get(
1850 	__in		efx_nic_t *enp,
1851 	__in		uint8_t *buffer,
1852 	__out		uint16_t *pkt_lengthp);
1853 
1854 #define	EFX_RXQ_MAXNDESCS		4096
1855 #define	EFX_RXQ_MINNDESCS		512
1856 
1857 #define	EFX_RXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
1858 #define	EFX_RXQ_NBUFS(_ndescs)		(EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1859 #define	EFX_RXQ_LIMIT(_ndescs)		((_ndescs) - 16)
1860 #define	EFX_RXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
1861 
1862 typedef enum efx_rxq_type_e {
1863 	EFX_RXQ_TYPE_DEFAULT,
1864 	EFX_RXQ_TYPE_SCATTER,
1865 	EFX_RXQ_NTYPES
1866 } efx_rxq_type_t;
1867 
1868 extern	__checkReturn	efx_rc_t
1869 efx_rx_qcreate(
1870 	__in		efx_nic_t *enp,
1871 	__in		unsigned int index,
1872 	__in		unsigned int label,
1873 	__in		efx_rxq_type_t type,
1874 	__in		efsys_mem_t *esmp,
1875 	__in		size_t n,
1876 	__in		uint32_t id,
1877 	__in		efx_evq_t *eep,
1878 	__deref_out	efx_rxq_t **erpp);
1879 
1880 typedef struct efx_buffer_s {
1881 	efsys_dma_addr_t	eb_addr;
1882 	size_t			eb_size;
1883 	boolean_t		eb_eop;
1884 } efx_buffer_t;
1885 
1886 typedef struct efx_desc_s {
1887 	efx_qword_t ed_eq;
1888 } efx_desc_t;
1889 
1890 extern			void
1891 efx_rx_qpost(
1892 	__in		efx_rxq_t *erp,
1893 	__in_ecount(n)	efsys_dma_addr_t *addrp,
1894 	__in		size_t size,
1895 	__in		unsigned int n,
1896 	__in		unsigned int completed,
1897 	__in		unsigned int added);
1898 
1899 extern		void
1900 efx_rx_qpush(
1901 	__in	efx_rxq_t *erp,
1902 	__in	unsigned int added,
1903 	__inout	unsigned int *pushedp);
1904 
1905 extern	__checkReturn	efx_rc_t
1906 efx_rx_qflush(
1907 	__in	efx_rxq_t *erp);
1908 
1909 extern		void
1910 efx_rx_qenable(
1911 	__in	efx_rxq_t *erp);
1912 
1913 extern		void
1914 efx_rx_qdestroy(
1915 	__in	efx_rxq_t *erp);
1916 
1917 /* TX */
1918 
1919 typedef struct efx_txq_s	efx_txq_t;
1920 
1921 #if EFSYS_OPT_QSTATS
1922 
1923 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1924 typedef enum efx_tx_qstat_e {
1925 	TX_POST,
1926 	TX_POST_PIO,
1927 	TX_NQSTATS
1928 } efx_tx_qstat_t;
1929 
1930 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1931 
1932 #endif	/* EFSYS_OPT_QSTATS */
1933 
1934 extern	__checkReturn	efx_rc_t
1935 efx_tx_init(
1936 	__in		efx_nic_t *enp);
1937 
1938 extern		void
1939 efx_tx_fini(
1940 	__in	efx_nic_t *enp);
1941 
1942 #define	EFX_BUG35388_WORKAROUND(_encp)					\
1943 	(((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0))
1944 
1945 #define	EFX_TXQ_MAXNDESCS(_encp)					\
1946 	((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096)
1947 
1948 #define	EFX_TXQ_MINNDESCS		512
1949 
1950 #define	EFX_TXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
1951 #define	EFX_TXQ_NBUFS(_ndescs)		(EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1952 #define	EFX_TXQ_LIMIT(_ndescs)		((_ndescs) - 16)
1953 #define	EFX_TXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
1954 
1955 #define	EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
1956 
1957 #define	EFX_TXQ_CKSUM_IPV4	0x0001
1958 #define	EFX_TXQ_CKSUM_TCPUDP	0x0002
1959 #define	EFX_TXQ_FATSOV2		0x0004
1960 
1961 extern	__checkReturn	efx_rc_t
1962 efx_tx_qcreate(
1963 	__in		efx_nic_t *enp,
1964 	__in		unsigned int index,
1965 	__in		unsigned int label,
1966 	__in		efsys_mem_t *esmp,
1967 	__in		size_t n,
1968 	__in		uint32_t id,
1969 	__in		uint16_t flags,
1970 	__in		efx_evq_t *eep,
1971 	__deref_out	efx_txq_t **etpp,
1972 	__out		unsigned int *addedp);
1973 
1974 extern	__checkReturn	efx_rc_t
1975 efx_tx_qpost(
1976 	__in		efx_txq_t *etp,
1977 	__in_ecount(n)	efx_buffer_t *eb,
1978 	__in		unsigned int n,
1979 	__in		unsigned int completed,
1980 	__inout		unsigned int *addedp);
1981 
1982 extern	__checkReturn	efx_rc_t
1983 efx_tx_qpace(
1984 	__in		efx_txq_t *etp,
1985 	__in		unsigned int ns);
1986 
1987 extern			void
1988 efx_tx_qpush(
1989 	__in		efx_txq_t *etp,
1990 	__in		unsigned int added,
1991 	__in		unsigned int pushed);
1992 
1993 extern	__checkReturn	efx_rc_t
1994 efx_tx_qflush(
1995 	__in		efx_txq_t *etp);
1996 
1997 extern			void
1998 efx_tx_qenable(
1999 	__in		efx_txq_t *etp);
2000 
2001 extern	__checkReturn	efx_rc_t
2002 efx_tx_qpio_enable(
2003 	__in		efx_txq_t *etp);
2004 
2005 extern			void
2006 efx_tx_qpio_disable(
2007 	__in		efx_txq_t *etp);
2008 
2009 extern	__checkReturn	efx_rc_t
2010 efx_tx_qpio_write(
2011 	__in			efx_txq_t *etp,
2012 	__in_ecount(buf_length)	uint8_t *buffer,
2013 	__in			size_t buf_length,
2014 	__in                    size_t pio_buf_offset);
2015 
2016 extern	__checkReturn	efx_rc_t
2017 efx_tx_qpio_post(
2018 	__in			efx_txq_t *etp,
2019 	__in			size_t pkt_length,
2020 	__in			unsigned int completed,
2021 	__inout			unsigned int *addedp);
2022 
2023 extern	__checkReturn	efx_rc_t
2024 efx_tx_qdesc_post(
2025 	__in		efx_txq_t *etp,
2026 	__in_ecount(n)	efx_desc_t *ed,
2027 	__in		unsigned int n,
2028 	__in		unsigned int completed,
2029 	__inout		unsigned int *addedp);
2030 
2031 extern	void
2032 efx_tx_qdesc_dma_create(
2033 	__in	efx_txq_t *etp,
2034 	__in	efsys_dma_addr_t addr,
2035 	__in	size_t size,
2036 	__in	boolean_t eop,
2037 	__out	efx_desc_t *edp);
2038 
2039 extern	void
2040 efx_tx_qdesc_tso_create(
2041 	__in	efx_txq_t *etp,
2042 	__in	uint16_t ipv4_id,
2043 	__in	uint32_t tcp_seq,
2044 	__in	uint8_t  tcp_flags,
2045 	__out	efx_desc_t *edp);
2046 
2047 /* Number of FATSOv2 option descriptors */
2048 #define	EFX_TX_FATSOV2_OPT_NDESCS		2
2049 
2050 /* Maximum number of DMA segments per TSO packet (not superframe) */
2051 #define	EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX	24
2052 
2053 extern	void
2054 efx_tx_qdesc_tso2_create(
2055 	__in			efx_txq_t *etp,
2056 	__in			uint16_t ipv4_id,
2057 	__in			uint32_t tcp_seq,
2058 	__in			uint16_t tcp_mss,
2059 	__out_ecount(count)	efx_desc_t *edp,
2060 	__in			int count);
2061 
2062 extern	void
2063 efx_tx_qdesc_vlantci_create(
2064 	__in	efx_txq_t *etp,
2065 	__in	uint16_t tci,
2066 	__out	efx_desc_t *edp);
2067 
2068 #if EFSYS_OPT_QSTATS
2069 
2070 #if EFSYS_OPT_NAMES
2071 
2072 extern		const char *
2073 efx_tx_qstat_name(
2074 	__in	efx_nic_t *etp,
2075 	__in	unsigned int id);
2076 
2077 #endif	/* EFSYS_OPT_NAMES */
2078 
2079 extern					void
2080 efx_tx_qstats_update(
2081 	__in				efx_txq_t *etp,
2082 	__inout_ecount(TX_NQSTATS)	efsys_stat_t *stat);
2083 
2084 #endif	/* EFSYS_OPT_QSTATS */
2085 
2086 extern		void
2087 efx_tx_qdestroy(
2088 	__in	efx_txq_t *etp);
2089 
2090 
2091 /* FILTER */
2092 
2093 #if EFSYS_OPT_FILTER
2094 
2095 #define	EFX_ETHER_TYPE_IPV4 0x0800
2096 #define	EFX_ETHER_TYPE_IPV6 0x86DD
2097 
2098 #define	EFX_IPPROTO_TCP 6
2099 #define	EFX_IPPROTO_UDP 17
2100 
2101 typedef enum efx_filter_flag_e {
2102 	EFX_FILTER_FLAG_RX_RSS = 0x01,		/* use RSS to spread across
2103 						 * multiple queues */
2104 	EFX_FILTER_FLAG_RX_SCATTER = 0x02,	/* enable RX scatter */
2105 	EFX_FILTER_FLAG_RX_OVER_AUTO = 0x04,	/* Override an automatic filter
2106 						 * (priority EFX_FILTER_PRI_AUTO).
2107 						 * May only be set by the filter
2108 						 * implementation for each type.
2109 						 * A removal request will
2110 						 * restore the automatic filter
2111 						 * in its place. */
2112 	EFX_FILTER_FLAG_RX = 0x08,		/* Filter is for RX */
2113 	EFX_FILTER_FLAG_TX = 0x10,		/* Filter is for TX */
2114 } efx_filter_flag_t;
2115 
2116 typedef enum efx_filter_match_flags_e {
2117 	EFX_FILTER_MATCH_REM_HOST = 0x0001,	/* Match by remote IP host
2118 						 * address */
2119 	EFX_FILTER_MATCH_LOC_HOST = 0x0002,	/* Match by local IP host
2120 						 * address */
2121 	EFX_FILTER_MATCH_REM_MAC = 0x0004,	/* Match by remote MAC address */
2122 	EFX_FILTER_MATCH_REM_PORT = 0x0008,	/* Match by remote TCP/UDP port */
2123 	EFX_FILTER_MATCH_LOC_MAC = 0x0010,	/* Match by remote TCP/UDP port */
2124 	EFX_FILTER_MATCH_LOC_PORT = 0x0020,	/* Match by local TCP/UDP port */
2125 	EFX_FILTER_MATCH_ETHER_TYPE = 0x0040,	/* Match by Ether-type */
2126 	EFX_FILTER_MATCH_INNER_VID = 0x0080,	/* Match by inner VLAN ID */
2127 	EFX_FILTER_MATCH_OUTER_VID = 0x0100,	/* Match by outer VLAN ID */
2128 	EFX_FILTER_MATCH_IP_PROTO = 0x0200,	/* Match by IP transport
2129 						 * protocol */
2130 	EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400,	/* Match by local MAC address
2131 						 * I/G bit. Used for RX default
2132 						 * unicast and multicast/
2133 						 * broadcast filters. */
2134 } efx_filter_match_flags_t;
2135 
2136 typedef enum efx_filter_priority_s {
2137 	EFX_FILTER_PRI_HINT = 0,	/* Performance hint */
2138 	EFX_FILTER_PRI_AUTO,		/* Automatic filter based on device
2139 					 * address list or hardware
2140 					 * requirements. This may only be used
2141 					 * by the filter implementation for
2142 					 * each NIC type. */
2143 	EFX_FILTER_PRI_MANUAL,		/* Manually configured filter */
2144 	EFX_FILTER_PRI_REQUIRED,	/* Required for correct behaviour of the
2145 					 * client (e.g. SR-IOV, HyperV VMQ etc.)
2146 					 */
2147 } efx_filter_priority_t;
2148 
2149 /*
2150  * FIXME: All these fields are assumed to be in little-endian byte order.
2151  * It may be better for some to be big-endian. See bug42804.
2152  */
2153 
2154 typedef struct efx_filter_spec_s {
2155 	uint32_t	efs_match_flags:12;
2156 	uint32_t	efs_priority:2;
2157 	uint32_t	efs_flags:6;
2158 	uint32_t	efs_dmaq_id:12;
2159 	uint32_t	efs_rss_context;
2160 	uint16_t	efs_outer_vid;
2161 	uint16_t	efs_inner_vid;
2162 	uint8_t		efs_loc_mac[EFX_MAC_ADDR_LEN];
2163 	uint8_t		efs_rem_mac[EFX_MAC_ADDR_LEN];
2164 	uint16_t	efs_ether_type;
2165 	uint8_t		efs_ip_proto;
2166 	uint16_t	efs_loc_port;
2167 	uint16_t	efs_rem_port;
2168 	efx_oword_t	efs_rem_host;
2169 	efx_oword_t	efs_loc_host;
2170 } efx_filter_spec_t;
2171 
2172 
2173 /* Default values for use in filter specifications */
2174 #define	EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT	0xffffffff
2175 #define	EFX_FILTER_SPEC_RX_DMAQ_ID_DROP		0xfff
2176 #define	EFX_FILTER_SPEC_VID_UNSPEC		0xffff
2177 
2178 extern	__checkReturn	efx_rc_t
2179 efx_filter_init(
2180 	__in		efx_nic_t *enp);
2181 
2182 extern			void
2183 efx_filter_fini(
2184 	__in		efx_nic_t *enp);
2185 
2186 extern	__checkReturn	efx_rc_t
2187 efx_filter_insert(
2188 	__in		efx_nic_t *enp,
2189 	__inout		efx_filter_spec_t *spec);
2190 
2191 extern	__checkReturn	efx_rc_t
2192 efx_filter_remove(
2193 	__in		efx_nic_t *enp,
2194 	__inout		efx_filter_spec_t *spec);
2195 
2196 extern	__checkReturn	efx_rc_t
2197 efx_filter_restore(
2198 	__in		efx_nic_t *enp);
2199 
2200 extern	__checkReturn	efx_rc_t
2201 efx_filter_supported_filters(
2202 	__in		efx_nic_t *enp,
2203 	__out		uint32_t *list,
2204 	__out		size_t *length);
2205 
2206 extern			void
2207 efx_filter_spec_init_rx(
2208 	__out		efx_filter_spec_t *spec,
2209 	__in		efx_filter_priority_t priority,
2210 	__in		efx_filter_flag_t flags,
2211 	__in		efx_rxq_t *erp);
2212 
2213 extern			void
2214 efx_filter_spec_init_tx(
2215 	__out		efx_filter_spec_t *spec,
2216 	__in		efx_txq_t *etp);
2217 
2218 extern	__checkReturn	efx_rc_t
2219 efx_filter_spec_set_ipv4_local(
2220 	__inout		efx_filter_spec_t *spec,
2221 	__in		uint8_t proto,
2222 	__in		uint32_t host,
2223 	__in		uint16_t port);
2224 
2225 extern	__checkReturn	efx_rc_t
2226 efx_filter_spec_set_ipv4_full(
2227 	__inout		efx_filter_spec_t *spec,
2228 	__in		uint8_t proto,
2229 	__in		uint32_t lhost,
2230 	__in		uint16_t lport,
2231 	__in		uint32_t rhost,
2232 	__in		uint16_t rport);
2233 
2234 extern	__checkReturn	efx_rc_t
2235 efx_filter_spec_set_eth_local(
2236 	__inout		efx_filter_spec_t *spec,
2237 	__in		uint16_t vid,
2238 	__in		const uint8_t *addr);
2239 
2240 extern	__checkReturn	efx_rc_t
2241 efx_filter_spec_set_uc_def(
2242 	__inout		efx_filter_spec_t *spec);
2243 
2244 extern	__checkReturn	efx_rc_t
2245 efx_filter_spec_set_mc_def(
2246 	__inout		efx_filter_spec_t *spec);
2247 
2248 #endif	/* EFSYS_OPT_FILTER */
2249 
2250 /* HASH */
2251 
2252 extern	__checkReturn		uint32_t
2253 efx_hash_dwords(
2254 	__in_ecount(count)	uint32_t const *input,
2255 	__in			size_t count,
2256 	__in			uint32_t init);
2257 
2258 extern	__checkReturn		uint32_t
2259 efx_hash_bytes(
2260 	__in_ecount(length)	uint8_t const *input,
2261 	__in			size_t length,
2262 	__in			uint32_t init);
2263 
2264 #if EFSYS_OPT_LICENSING
2265 
2266 /* LICENSING */
2267 
2268 typedef struct efx_key_stats_s {
2269 	uint32_t	eks_valid;
2270 	uint32_t	eks_invalid;
2271 	uint32_t	eks_blacklisted;
2272 	uint32_t	eks_unverifiable;
2273 	uint32_t	eks_wrong_node;
2274 	uint32_t	eks_licensed_apps_lo;
2275 	uint32_t	eks_licensed_apps_hi;
2276 	uint32_t	eks_licensed_features_lo;
2277 	uint32_t	eks_licensed_features_hi;
2278 } efx_key_stats_t;
2279 
2280 extern	__checkReturn		efx_rc_t
2281 efx_lic_init(
2282 	__in			efx_nic_t *enp);
2283 
2284 extern				void
2285 efx_lic_fini(
2286 	__in			efx_nic_t *enp);
2287 
2288 extern	__checkReturn	efx_rc_t
2289 efx_lic_update_licenses(
2290 	__in		efx_nic_t *enp);
2291 
2292 extern	__checkReturn	efx_rc_t
2293 efx_lic_get_key_stats(
2294 	__in		efx_nic_t *enp,
2295 	__out		efx_key_stats_t *ksp);
2296 
2297 extern	__checkReturn	efx_rc_t
2298 efx_lic_app_state(
2299 	__in		efx_nic_t *enp,
2300 	__in		uint64_t app_id,
2301 	__out		boolean_t *licensedp);
2302 
2303 extern	__checkReturn	efx_rc_t
2304 efx_lic_get_id(
2305 	__in		efx_nic_t *enp,
2306 	__in		size_t buffer_size,
2307 	__out		uint32_t *typep,
2308 	__out		size_t *lengthp,
2309 	__out_opt	uint8_t *bufferp);
2310 
2311 
2312 extern	__checkReturn		efx_rc_t
2313 efx_lic_find_start(
2314 	__in			efx_nic_t *enp,
2315 	__in_bcount(buffer_size)
2316 				caddr_t bufferp,
2317 	__in			size_t buffer_size,
2318 	__out			uint32_t *startp
2319 	);
2320 
2321 extern	__checkReturn		efx_rc_t
2322 efx_lic_find_end(
2323 	__in			efx_nic_t *enp,
2324 	__in_bcount(buffer_size)
2325 				caddr_t bufferp,
2326 	__in			size_t buffer_size,
2327 	__in			uint32_t offset,
2328 	__out			uint32_t *endp
2329 	);
2330 
2331 extern	__checkReturn	__success(return != B_FALSE)	boolean_t
2332 efx_lic_find_key(
2333 	__in			efx_nic_t *enp,
2334 	__in_bcount(buffer_size)
2335 				caddr_t bufferp,
2336 	__in			size_t buffer_size,
2337 	__in			uint32_t offset,
2338 	__out			uint32_t *startp,
2339 	__out			uint32_t *lengthp
2340 	);
2341 
2342 extern	__checkReturn	__success(return != B_FALSE)	boolean_t
2343 efx_lic_validate_key(
2344 	__in			efx_nic_t *enp,
2345 	__in_bcount(length)	caddr_t keyp,
2346 	__in			uint32_t length
2347 	);
2348 
2349 extern	__checkReturn		efx_rc_t
2350 efx_lic_read_key(
2351 	__in			efx_nic_t *enp,
2352 	__in_bcount(buffer_size)
2353 				caddr_t bufferp,
2354 	__in			size_t buffer_size,
2355 	__in			uint32_t offset,
2356 	__in			uint32_t length,
2357 	__out_bcount_part(key_max_size, *lengthp)
2358 				caddr_t keyp,
2359 	__in			size_t key_max_size,
2360 	__out			uint32_t *lengthp
2361 	);
2362 
2363 extern	__checkReturn		efx_rc_t
2364 efx_lic_write_key(
2365 	__in			efx_nic_t *enp,
2366 	__in_bcount(buffer_size)
2367 				caddr_t bufferp,
2368 	__in			size_t buffer_size,
2369 	__in			uint32_t offset,
2370 	__in_bcount(length)	caddr_t keyp,
2371 	__in			uint32_t length,
2372 	__out			uint32_t *lengthp
2373 	);
2374 
2375 	__checkReturn		efx_rc_t
2376 efx_lic_delete_key(
2377 	__in			efx_nic_t *enp,
2378 	__in_bcount(buffer_size)
2379 				caddr_t bufferp,
2380 	__in			size_t buffer_size,
2381 	__in			uint32_t offset,
2382 	__in			uint32_t length,
2383 	__in			uint32_t end,
2384 	__out			uint32_t *deltap
2385 	);
2386 
2387 extern	__checkReturn		efx_rc_t
2388 efx_lic_create_partition(
2389 	__in			efx_nic_t *enp,
2390 	__in_bcount(buffer_size)
2391 				caddr_t bufferp,
2392 	__in			size_t buffer_size
2393 	);
2394 
2395 extern	__checkReturn		efx_rc_t
2396 efx_lic_finish_partition(
2397 	__in			efx_nic_t *enp,
2398 	__in_bcount(buffer_size)
2399 				caddr_t bufferp,
2400 	__in			size_t buffer_size
2401 	);
2402 
2403 #endif	/* EFSYS_OPT_LICENSING */
2404 
2405 
2406 
2407 #ifdef	__cplusplus
2408 }
2409 #endif
2410 
2411 #endif	/* _SYS_EFX_H */
2412