1 /*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "opt_ah.h"
18
19 #include "ah.h"
20 #include "ah_internal.h"
21 #include "ah_devid.h"
22
23 #include "ar9300/ar9300desc.h"
24 #include "ar9300/ar9300.h"
25 #include "ar9300/ar9300reg.h"
26 #include "ar9300/ar9300phy.h"
27 #include "ar9300/ar9300paprd.h"
28
29 #include "ar9300/ar9300_stub.h"
30 #include "ar9300/ar9300_stub_funcs.h"
31
32
33 /* Add static register initialization vectors */
34 #include "ar9300/ar9300_osprey22.ini"
35 #include "ar9300/ar9330_11.ini"
36 #include "ar9300/ar9330_12.ini"
37 #include "ar9300/ar9340.ini"
38 #include "ar9300/ar9485.ini"
39 #include "ar9300/ar9485_1_1.ini"
40 #include "ar9300/ar9300_jupiter10.ini"
41 /* TODO: convert the 2.0 code to use the new initvals from ath9k */
42 #include "ar9300/ar9300_jupiter20.ini"
43 #include "ar9300/ar9462_2p0_initvals.h"
44 #include "ar9300/ar9462_2p1_initvals.h"
45 #include "ar9300/ar9580.ini"
46 #include "ar9300/ar955x.ini"
47 #include "ar9300/ar953x.ini"
48 #include "ar9300/ar9300_aphrodite10.ini"
49
50
51 /* Include various freebsd specific HAL methods */
52 #include "ar9300/ar9300_freebsd.h"
53
54 /* XXX duplicate in ar9300_radio.c ? */
55 static HAL_BOOL ar9300_get_chip_power_limits(struct ath_hal *ah,
56 struct ieee80211_channel *chan);
57
58 static inline HAL_STATUS ar9300_init_mac_addr(struct ath_hal *ah);
59 static inline HAL_STATUS ar9300_hw_attach(struct ath_hal *ah);
60 static inline void ar9300_hw_detach(struct ath_hal *ah);
61 static int16_t ar9300_get_nf_adjust(struct ath_hal *ah,
62 const HAL_CHANNEL_INTERNAL *c);
63 #if 0
64 int ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp,
65 HAL_CAL_QUERY query);
66 #endif
67
68 #if ATH_TRAFFIC_FAST_RECOVER
69 unsigned long ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah);
70 #endif
71 static int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid);
72
73
74 static void
75 ar9300_disable_pcie_phy(struct ath_hal *ah);
76
77 static const HAL_PERCAL_DATA iq_cal_single_sample =
78 {IQ_MISMATCH_CAL,
79 MIN_CAL_SAMPLES,
80 PER_MAX_LOG_COUNT,
81 ar9300_iq_cal_collect,
82 ar9300_iq_calibration};
83
84 #if 0
85 static HAL_CALIBRATION_TIMER ar9300_cals[] =
86 { {IQ_MISMATCH_CAL, /* Cal type */
87 1200000, /* Cal interval */
88 0 /* Cal timestamp */
89 },
90 {TEMP_COMP_CAL,
91 5000,
92 0
93 },
94 };
95 #endif
96
97 #if ATH_PCIE_ERROR_MONITOR
98
ar9300_start_pcie_error_monitor(struct ath_hal * ah,int b_auto_stop)99 int ar9300_start_pcie_error_monitor(struct ath_hal *ah, int b_auto_stop)
100 {
101 u_int32_t val;
102
103 /* Clear the counters */
104 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR0, 0);
105 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR1, 0);
106
107 /* Read the previous value */
108 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL);
109
110 /* Set auto_stop */
111 if (b_auto_stop) {
112 val |=
113 RCVD_ERR_CTR_AUTO_STOP | BAD_TLP_ERR_CTR_AUTO_STOP |
114 BAD_DLLP_ERR_CTR_AUTO_STOP | RPLY_TO_ERR_CTR_AUTO_STOP |
115 RPLY_NUM_RO_ERR_CTR_AUTO_STOP;
116 } else {
117 val &= ~(
118 RCVD_ERR_CTR_AUTO_STOP | BAD_TLP_ERR_CTR_AUTO_STOP |
119 BAD_DLLP_ERR_CTR_AUTO_STOP | RPLY_TO_ERR_CTR_AUTO_STOP |
120 RPLY_NUM_RO_ERR_CTR_AUTO_STOP);
121 }
122 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val );
123
124 /*
125 * Start to run.
126 * This has to be done separately from the above auto_stop flag setting,
127 * to avoid a HW race condition.
128 */
129 val |=
130 RCVD_ERR_CTR_RUN | BAD_TLP_ERR_CTR_RUN | BAD_DLLP_ERR_CTR_RUN |
131 RPLY_TO_ERR_CTR_RUN | RPLY_NUM_RO_ERR_CTR_RUN;
132 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val);
133
134 return 0;
135 }
136
ar9300_read_pcie_error_monitor(struct ath_hal * ah,void * p_read_counters)137 int ar9300_read_pcie_error_monitor(struct ath_hal *ah, void* p_read_counters)
138 {
139 u_int32_t val;
140 ar_pcie_error_moniter_counters *p_counters =
141 (ar_pcie_error_moniter_counters*) p_read_counters;
142
143 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR0);
144
145 p_counters->uc_receiver_errors = MS(val, RCVD_ERR_MASK);
146 p_counters->uc_bad_tlp_errors = MS(val, BAD_TLP_ERR_MASK);
147 p_counters->uc_bad_dllp_errors = MS(val, BAD_DLLP_ERR_MASK);
148
149 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR1);
150
151 p_counters->uc_replay_timeout_errors = MS(val, RPLY_TO_ERR_MASK);
152 p_counters->uc_replay_number_rollover_errors= MS(val, RPLY_NUM_RO_ERR_MASK);
153
154 return 0;
155 }
156
ar9300_stop_pcie_error_monitor(struct ath_hal * ah)157 int ar9300_stop_pcie_error_monitor(struct ath_hal *ah)
158 {
159 u_int32_t val;
160
161 /* Read the previous value */
162 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL);
163
164 val &= ~(
165 RCVD_ERR_CTR_RUN |
166 BAD_TLP_ERR_CTR_RUN |
167 BAD_DLLP_ERR_CTR_RUN |
168 RPLY_TO_ERR_CTR_RUN |
169 RPLY_NUM_RO_ERR_CTR_RUN);
170
171 /* Start to stop */
172 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val );
173
174 return 0;
175 }
176
177 #endif /* ATH_PCIE_ERROR_MONITOR */
178
179 #if 0
180 /* WIN32 does not support C99 */
181 static const struct ath_hal_private ar9300hal = {
182 {
183 ar9300_get_rate_table, /* ah_get_rate_table */
184 ar9300_detach, /* ah_detach */
185
186 /* Reset Functions */
187 ar9300_reset, /* ah_reset */
188 ar9300_phy_disable, /* ah_phy_disable */
189 ar9300_disable, /* ah_disable */
190 ar9300_config_pci_power_save, /* ah_config_pci_power_save */
191 ar9300_set_pcu_config, /* ah_set_pcu_config */
192 ar9300_calibration, /* ah_per_calibration */
193 ar9300_reset_cal_valid, /* ah_reset_cal_valid */
194 ar9300_set_tx_power_limit, /* ah_set_tx_power_limit */
195
196 #if ATH_ANT_DIV_COMB
197 ar9300_ant_ctrl_set_lna_div_use_bt_ant, /* ah_ant_ctrl_set_lna_div_use_bt_ant */
198 #endif /* ATH_ANT_DIV_COMB */
199 #ifdef ATH_SUPPORT_DFS
200 ar9300_radar_wait, /* ah_radar_wait */
201
202 /* New DFS functions */
203 ar9300_check_dfs, /* ah_ar_check_dfs */
204 ar9300_dfs_found, /* ah_ar_dfs_found */
205 ar9300_enable_dfs, /* ah_ar_enable_dfs */
206 ar9300_get_dfs_thresh, /* ah_ar_get_dfs_thresh */
207 ar9300_get_dfs_radars, /* ah_ar_get_dfs_radars */
208 ar9300_adjust_difs, /* ah_adjust_difs */
209 ar9300_dfs_config_fft, /* ah_dfs_config_fft */
210 ar9300_dfs_cac_war, /* ah_dfs_cac_war */
211 ar9300_cac_tx_quiet, /* ah_cac_tx_quiet */
212 #endif
213 ar9300_get_extension_channel, /* ah_get_extension_channel */
214 ar9300_is_fast_clock_enabled, /* ah_is_fast_clock_enabled */
215
216 /* Transmit functions */
217 ar9300_update_tx_trig_level, /* ah_update_tx_trig_level */
218 ar9300_get_tx_trig_level, /* ah_get_tx_trig_level */
219 ar9300_setup_tx_queue, /* ah_setup_tx_queue */
220 ar9300_set_tx_queue_props, /* ah_set_tx_queue_props */
221 ar9300_get_tx_queue_props, /* ah_get_tx_queue_props */
222 ar9300_release_tx_queue, /* ah_release_tx_queue */
223 ar9300_reset_tx_queue, /* ah_reset_tx_queue */
224 ar9300_get_tx_dp, /* ah_get_tx_dp */
225 ar9300_set_tx_dp, /* ah_set_tx_dp */
226 ar9300_num_tx_pending, /* ah_num_tx_pending */
227 ar9300_start_tx_dma, /* ah_start_tx_dma */
228 ar9300_stop_tx_dma, /* ah_stop_tx_dma */
229 ar9300_stop_tx_dma_indv_que, /* ah_stop_tx_dma_indv_que */
230 ar9300_abort_tx_dma, /* ah_abort_tx_dma */
231 ar9300_fill_tx_desc, /* ah_fill_tx_desc */
232 ar9300_set_desc_link, /* ah_set_desc_link */
233 ar9300_get_desc_link_ptr, /* ah_get_desc_link_ptr */
234 ar9300_clear_tx_desc_status, /* ah_clear_tx_desc_status */
235 #ifdef ATH_SWRETRY
236 ar9300_clear_dest_mask, /* ah_clear_dest_mask */
237 #endif
238 ar9300_proc_tx_desc, /* ah_proc_tx_desc */
239 ar9300_get_raw_tx_desc, /* ah_get_raw_tx_desc */
240 ar9300_get_tx_rate_code, /* ah_get_tx_rate_code */
241 AH_NULL, /* ah_get_tx_intr_queue */
242 ar9300_tx_req_intr_desc, /* ah_req_tx_intr_desc */
243 ar9300_calc_tx_airtime, /* ah_calc_tx_airtime */
244 ar9300_setup_tx_status_ring, /* ah_setup_tx_status_ring */
245
246 /* RX Functions */
247 ar9300_get_rx_dp, /* ah_get_rx_dp */
248 ar9300_set_rx_dp, /* ah_set_rx_dp */
249 ar9300_enable_receive, /* ah_enable_receive */
250 ar9300_stop_dma_receive, /* ah_stop_dma_receive */
251 ar9300_start_pcu_receive, /* ah_start_pcu_receive */
252 ar9300_stop_pcu_receive, /* ah_stop_pcu_receive */
253 ar9300_set_multicast_filter, /* ah_set_multicast_filter */
254 ar9300_get_rx_filter, /* ah_get_rx_filter */
255 ar9300_set_rx_filter, /* ah_set_rx_filter */
256 ar9300_set_rx_sel_evm, /* ah_set_rx_sel_evm */
257 ar9300_set_rx_abort, /* ah_set_rx_abort */
258 AH_NULL, /* ah_setup_rx_desc */
259 ar9300_proc_rx_desc, /* ah_proc_rx_desc */
260 ar9300_get_rx_key_idx, /* ah_get_rx_key_idx */
261 ar9300_proc_rx_desc_fast, /* ah_proc_rx_desc_fast */
262 ar9300_ani_ar_poll, /* ah_rx_monitor */
263 ar9300_process_mib_intr, /* ah_proc_mib_event */
264
265 /* Misc Functions */
266 ar9300_get_capability, /* ah_get_capability */
267 ar9300_set_capability, /* ah_set_capability */
268 ar9300_get_diag_state, /* ah_get_diag_state */
269 ar9300_get_mac_address, /* ah_get_mac_address */
270 ar9300_set_mac_address, /* ah_set_mac_address */
271 ar9300_get_bss_id_mask, /* ah_get_bss_id_mask */
272 ar9300_set_bss_id_mask, /* ah_set_bss_id_mask */
273 ar9300_set_regulatory_domain, /* ah_set_regulatory_domain */
274 ar9300_set_led_state, /* ah_set_led_state */
275 ar9300_set_power_led_state, /* ah_setpowerledstate */
276 ar9300_set_network_led_state, /* ah_setnetworkledstate */
277 ar9300_write_associd, /* ah_write_associd */
278 ar9300_force_tsf_sync, /* ah_force_tsf_sync */
279 ar9300_gpio_cfg_input, /* ah_gpio_cfg_input */
280 ar9300_gpio_cfg_output, /* ah_gpio_cfg_output */
281 ar9300_gpio_cfg_output_led_off, /* ah_gpio_cfg_output_led_off */
282 ar9300_gpio_get, /* ah_gpio_get */
283 ar9300_gpio_set, /* ah_gpio_set */
284 ar9300_gpio_get_intr, /* ah_gpio_get_intr */
285 ar9300_gpio_set_intr, /* ah_gpio_set_intr */
286 ar9300_gpio_get_polarity, /* ah_gpio_get_polarity */
287 ar9300_gpio_set_polarity, /* ah_gpio_set_polarity */
288 ar9300_gpio_get_mask, /* ah_gpio_get_mask */
289 ar9300_gpio_set_mask, /* ah_gpio_set_mask */
290 ar9300_get_tsf32, /* ah_get_tsf32 */
291 ar9300_get_tsf64, /* ah_get_tsf64 */
292 ar9300_get_tsf2_32, /* ah_get_tsf2_32 */
293 ar9300_reset_tsf, /* ah_reset_tsf */
294 ar9300_detect_card_present, /* ah_detect_card_present */
295 ar9300_update_mib_mac_stats, /* ah_update_mib_mac_stats */
296 ar9300_get_mib_mac_stats, /* ah_get_mib_mac_stats */
297 ar9300_get_rfgain, /* ah_get_rf_gain */
298 ar9300_get_def_antenna, /* ah_get_def_antenna */
299 ar9300_set_def_antenna, /* ah_set_def_antenna */
300 ar9300_set_slot_time, /* ah_set_slot_time */
301 ar9300_set_ack_timeout, /* ah_set_ack_timeout */
302 ar9300_get_ack_timeout, /* ah_get_ack_timeout */
303 ar9300_set_coverage_class, /* ah_set_coverage_class */
304 ar9300_set_quiet, /* ah_set_quiet */
305 ar9300_set_antenna_switch, /* ah_set_antenna_switch */
306 ar9300_get_desc_info, /* ah_get_desc_info */
307 ar9300_select_ant_config, /* ah_select_ant_config */
308 ar9300_ant_ctrl_common_get, /* ah_ant_ctrl_common_get */
309 ar9300_ant_swcom_sel, /* ah_ant_swcom_sel */
310 ar9300_enable_tpc, /* ah_enable_tpc */
311 AH_NULL, /* ah_olpc_temp_compensation */
312 #if ATH_SUPPORT_CRDC
313 ar9300_chain_rssi_diff_compensation,/*ah_chain_rssi_diff_compensation*/
314 #endif
315 ar9300_disable_phy_restart, /* ah_disable_phy_restart */
316 ar9300_enable_keysearch_always,
317 ar9300_interference_is_present, /* ah_interference_is_present */
318 ar9300_disp_tpc_tables, /* ah_disp_tpc_tables */
319 ar9300_get_tpc_tables, /* ah_get_tpc_tables */
320 /* Key Cache Functions */
321 ar9300_get_key_cache_size, /* ah_get_key_cache_size */
322 ar9300_reset_key_cache_entry, /* ah_reset_key_cache_entry */
323 ar9300_is_key_cache_entry_valid, /* ah_is_key_cache_entry_valid */
324 ar9300_set_key_cache_entry, /* ah_set_key_cache_entry */
325 ar9300_set_key_cache_entry_mac, /* ah_set_key_cache_entry_mac */
326 ar9300_print_keycache, /* ah_print_key_cache */
327 #if ATH_SUPPORT_KEYPLUMB_WAR
328 ar9300_check_key_cache_entry, /* ah_check_key_cache_entry */
329 #endif
330 /* Power Management Functions */
331 ar9300_set_power_mode, /* ah_set_power_mode */
332 ar9300_set_sm_power_mode, /* ah_set_sm_ps_mode */
333 #if ATH_WOW
334 ar9300_wow_apply_pattern, /* ah_wow_apply_pattern */
335 ar9300_wow_enable, /* ah_wow_enable */
336 ar9300_wow_wake_up, /* ah_wow_wake_up */
337 #if ATH_WOW_OFFLOAD
338 ar9300_wowoffload_prep, /* ah_wow_offload_prep */
339 ar9300_wowoffload_post, /* ah_wow_offload_post */
340 ar9300_wowoffload_download_rekey_data, /* ah_wow_offload_download_rekey_data */
341 ar9300_wowoffload_retrieve_data, /* ah_wow_offload_retrieve_data */
342 ar9300_wowoffload_download_acer_magic, /* ah_wow_offload_download_acer_magic */
343 ar9300_wowoffload_download_acer_swka, /* ah_wow_offload_download_acer_swka */
344 ar9300_wowoffload_download_arp_info, /* ah_wow_offload_download_arp_info */
345 ar9300_wowoffload_download_ns_info, /* ah_wow_offload_download_ns_info */
346 #endif /* ATH_WOW_OFFLOAD */
347 #endif
348
349 /* Get Channel Noise */
350 ath_hal_get_chan_noise, /* ah_get_chan_noise */
351 ar9300_chain_noise_floor, /* ah_get_chain_noise_floor */
352 ar9300_get_nf_from_reg, /* ah_get_nf_from_reg */
353 ar9300_get_rx_nf_offset, /* ah_get_rx_nf_offset */
354
355 /* Beacon Functions */
356 ar9300_beacon_init, /* ah_beacon_init */
357 ar9300_set_sta_beacon_timers, /* ah_set_station_beacon_timers */
358
359 /* Interrupt Functions */
360 ar9300_is_interrupt_pending, /* ah_is_interrupt_pending */
361 ar9300_get_pending_interrupts, /* ah_get_pending_interrupts */
362 ar9300_get_interrupts, /* ah_get_interrupts */
363 ar9300_set_interrupts, /* ah_set_interrupts */
364 ar9300_set_intr_mitigation_timer, /* ah_set_intr_mitigation_timer */
365 ar9300_get_intr_mitigation_timer, /* ah_get_intr_mitigation_timer */
366 ar9300ForceVCS,
367 ar9300SetDfs3StreamFix,
368 ar9300Get3StreamSignature,
369
370 /* 11n specific functions (NOT applicable to ar9300) */
371 ar9300_set_11n_tx_desc, /* ah_set_11n_tx_desc */
372 /* Update rxchain */
373 ar9300_set_rx_chainmask, /*ah_set_rx_chainmask*/
374 /*Updating locationing register */
375 ar9300_update_loc_ctl_reg, /*ah_update_loc_ctl_reg*/
376 /* Start PAPRD functions */
377 ar9300_set_paprd_tx_desc, /* ah_set_paprd_tx_desc */
378 ar9300_paprd_init_table, /* ah_paprd_init_table */
379 ar9300_paprd_setup_gain_table, /* ah_paprd_setup_gain_table */
380 ar9300_paprd_create_curve, /* ah_paprd_create_curve */
381 ar9300_paprd_is_done, /* ah_paprd_is_done */
382 ar9300_enable_paprd, /* ah_PAPRDEnable */
383 ar9300_populate_paprd_single_table,/* ah_paprd_populate_table */
384 ar9300_is_tx_done, /* ah_is_tx_done */
385 ar9300_paprd_dec_tx_pwr, /* ah_paprd_dec_tx_pwr*/
386 ar9300_paprd_thermal_send, /* ah_paprd_thermal_send */
387 /* End PAPRD functions */
388 ar9300_set_11n_rate_scenario, /* ah_set_11n_rate_scenario */
389 ar9300_set_11n_aggr_first, /* ah_set_11n_aggr_first */
390 ar9300_set_11n_aggr_middle, /* ah_set_11n_aggr_middle */
391 ar9300_set_11n_aggr_last, /* ah_set_11n_aggr_last */
392 ar9300_clr_11n_aggr, /* ah_clr_11n_aggr */
393 ar9300_set_11n_rifs_burst_middle, /* ah_set_11n_rifs_burst_middle */
394 ar9300_set_11n_rifs_burst_last, /* ah_set_11n_rifs_burst_last */
395 ar9300_clr_11n_rifs_burst, /* ah_clr_11n_rifs_burst */
396 ar9300_set_11n_aggr_rifs_burst, /* ah_set_11n_aggr_rifs_burst */
397 ar9300_set_11n_rx_rifs, /* ah_set_11n_rx_rifs */
398 ar9300_set_smart_antenna, /* ah_setSmartAntenna */
399 ar9300_detect_bb_hang, /* ah_detect_bb_hang */
400 ar9300_detect_mac_hang, /* ah_detect_mac_hang */
401 ar9300_set_immunity, /* ah_immunity */
402 ar9300_get_hw_hangs, /* ah_get_hang_types */
403 ar9300_set_11n_burst_duration, /* ah_set_11n_burst_duration */
404 ar9300_set_11n_virtual_more_frag, /* ah_set_11n_virtual_more_frag */
405 ar9300_get_11n_ext_busy, /* ah_get_11n_ext_busy */
406 ar9300_set_11n_mac2040, /* ah_set_11n_mac2040 */
407 ar9300_get_11n_rx_clear, /* ah_get_11n_rx_clear */
408 ar9300_set_11n_rx_clear, /* ah_set_11n_rx_clear */
409 ar9300_get_mib_cycle_counts_pct, /* ah_get_mib_cycle_counts_pct */
410 ar9300_dma_reg_dump, /* ah_dma_reg_dump */
411
412 /* force_ppm specific functions */
413 ar9300_ppm_get_rssi_dump, /* ah_ppm_get_rssi_dump */
414 ar9300_ppm_arm_trigger, /* ah_ppm_arm_trigger */
415 ar9300_ppm_get_trigger, /* ah_ppm_get_trigger */
416 ar9300_ppm_force, /* ah_ppm_force */
417 ar9300_ppm_un_force, /* ah_ppm_un_force */
418 ar9300_ppm_get_force_state, /* ah_ppm_get_force_state */
419
420 ar9300_get_spur_info, /* ah_get_spur_info */
421 ar9300_set_spur_info, /* ah_get_spur_info */
422
423 ar9300_get_min_cca_pwr, /* ah_ar_get_noise_floor_val */
424
425 ar9300_green_ap_ps_on_off, /* ah_set_rx_green_ap_ps_on_off */
426 ar9300_is_single_ant_power_save_possible, /* ah_is_single_ant_power_save_possible */
427
428 /* radio measurement specific functions */
429 ar9300_get_mib_cycle_counts, /* ah_get_mib_cycle_counts */
430 ar9300_get_vow_stats, /* ah_get_vow_stats */
431 ar9300_clear_mib_counters, /* ah_clear_mib_counters */
432 #if ATH_GEN_RANDOMNESS
433 ar9300_get_rssi_chain0, /* ah_get_rssi_chain0 */
434 #endif
435 #ifdef ATH_BT_COEX
436 /* Bluetooth Coexistence functions */
437 ar9300_set_bt_coex_info, /* ah_set_bt_coex_info */
438 ar9300_bt_coex_config, /* ah_bt_coex_config */
439 ar9300_bt_coex_set_qcu_thresh, /* ah_bt_coex_set_qcu_thresh */
440 ar9300_bt_coex_set_weights, /* ah_bt_coex_set_weights */
441 ar9300_bt_coex_setup_bmiss_thresh, /* ah_bt_coex_set_bmiss_thresh */
442 ar9300_bt_coex_set_parameter, /* ah_bt_coex_set_parameter */
443 ar9300_bt_coex_disable, /* ah_bt_coex_disable */
444 ar9300_bt_coex_enable, /* ah_bt_coex_enable */
445 ar9300_get_bt_active_gpio, /* ah_bt_coex_info*/
446 ar9300_get_wlan_active_gpio, /* ah__coex_wlan_info*/
447 #endif
448 /* Generic Timer functions */
449 ar9300_alloc_generic_timer, /* ah_gentimer_alloc */
450 ar9300_free_generic_timer, /* ah_gentimer_free */
451 ar9300_start_generic_timer, /* ah_gentimer_start */
452 ar9300_stop_generic_timer, /* ah_gentimer_stop */
453 ar9300_get_gen_timer_interrupts, /* ah_gentimer_get_intr */
454
455 ar9300_set_dcs_mode, /* ah_set_dcs_mode */
456 ar9300_get_dcs_mode, /* ah_get_dcs_mode */
457
458 #if ATH_ANT_DIV_COMB
459 ar9300_ant_div_comb_get_config, /* ah_get_ant_dvi_comb_conf */
460 ar9300_ant_div_comb_set_config, /* ah_set_ant_dvi_comb_conf */
461 #endif
462
463 ar9300_get_bb_panic_info, /* ah_get_bb_panic_info */
464 ar9300_handle_radar_bb_panic, /* ah_handle_radar_bb_panic */
465 ar9300_set_hal_reset_reason, /* ah_set_hal_reset_reason */
466
467 #if ATH_PCIE_ERROR_MONITOR
468 ar9300_start_pcie_error_monitor, /* ah_start_pcie_error_monitor */
469 ar9300_read_pcie_error_monitor, /* ah_read_pcie_error_monitor*/
470 ar9300_stop_pcie_error_monitor, /* ah_stop_pcie_error_monitor*/
471 #endif /* ATH_PCIE_ERROR_MONITOR */
472
473 #if ATH_SUPPORT_SPECTRAL
474 /* Spectral scan */
475 ar9300_configure_spectral_scan, /* ah_ar_configure_spectral */
476 ar9300_get_spectral_params, /* ah_ar_get_spectral_config */
477 ar9300_start_spectral_scan, /* ah_ar_start_spectral_scan */
478 ar9300_stop_spectral_scan, /* ah_ar_stop_spectral_scan */
479 ar9300_is_spectral_enabled, /* ah_ar_is_spectral_enabled */
480 ar9300_is_spectral_active, /* ah_ar_is_spectral_active */
481 ar9300_get_ctl_chan_nf, /* ah_ar_get_ctl_nf */
482 ar9300_get_ext_chan_nf, /* ah_ar_get_ext_nf */
483 #endif /* ATH_SUPPORT_SPECTRAL */
484
485
486 ar9300_promisc_mode, /* ah_promisc_mode */
487 ar9300_read_pktlog_reg, /* ah_read_pktlog_reg */
488 ar9300_write_pktlog_reg, /* ah_write_pktlog_reg */
489 ar9300_set_proxy_sta, /* ah_set_proxy_sta */
490 ar9300_get_cal_intervals, /* ah_get_cal_intervals */
491 #if ATH_TRAFFIC_FAST_RECOVER
492 ar9300_get_pll3_sqsum_dvc, /* ah_get_pll3_sqsum_dvc */
493 #endif
494 #ifdef ATH_SUPPORT_HTC
495 AH_NULL,
496 #endif
497
498 #ifdef ATH_TX99_DIAG
499 /* Tx99 functions */
500 #ifdef ATH_SUPPORT_HTC
501 AH_NULL,
502 AH_NULL,
503 AH_NULL,
504 AH_NULL,
505 AH_NULL,
506 AH_NULL,
507 AH_NULL,
508 #else
509 AH_NULL,
510 AH_NULL,
511 ar9300_tx99_channel_pwr_update, /* ah_tx99channelpwrupdate */
512 ar9300_tx99_start, /* ah_tx99start */
513 ar9300_tx99_stop, /* ah_tx99stop */
514 ar9300_tx99_chainmsk_setup, /* ah_tx99_chainmsk_setup */
515 ar9300_tx99_set_single_carrier, /* ah_tx99_set_single_carrier */
516 #endif
517 #endif
518 ar9300_chk_rssi_update_tx_pwr,
519 ar9300_is_skip_paprd_by_greentx, /* ah_is_skip_paprd_by_greentx */
520 ar9300_hwgreentx_set_pal_spare, /* ah_hwgreentx_set_pal_spare */
521 #if ATH_SUPPORT_MCI
522 /* MCI Coexistence Functions */
523 ar9300_mci_setup, /* ah_mci_setup */
524 ar9300_mci_send_message, /* ah_mci_send_message */
525 ar9300_mci_get_interrupt, /* ah_mci_get_interrupt */
526 ar9300_mci_state, /* ah_mci_state */
527 ar9300_mci_detach, /* ah_mci_detach */
528 #endif
529 ar9300_reset_hw_beacon_proc_crc, /* ah_reset_hw_beacon_proc_crc */
530 ar9300_get_hw_beacon_rssi, /* ah_get_hw_beacon_rssi */
531 ar9300_set_hw_beacon_rssi_threshold,/*ah_set_hw_beacon_rssi_threshold*/
532 ar9300_reset_hw_beacon_rssi, /* ah_reset_hw_beacon_rssi */
533 ar9300_mat_enable, /* ah_mat_enable */
534 ar9300_dump_keycache, /* ah_dump_keycache */
535 ar9300_is_ani_noise_spur, /* ah_is_ani_noise_spur */
536 ar9300_set_hw_beacon_proc, /* ah_set_hw_beacon_proc */
537 ar9300_set_ctl_pwr, /* ah_set_ctl_pwr */
538 ar9300_set_txchainmaskopt, /* ah_set_txchainmaskopt */
539 },
540
541 ar9300_get_channel_edges, /* ah_get_channel_edges */
542 ar9300_get_wireless_modes, /* ah_get_wireless_modes */
543 ar9300_eeprom_read_word, /* ah_eeprom_read */
544 AH_NULL,
545 ar9300_eeprom_dump_support, /* ah_eeprom_dump */
546 ar9300_get_chip_power_limits, /* ah_get_chip_power_limits */
547
548 ar9300_get_nf_adjust, /* ah_get_nf_adjust */
549 /* rest is zero'd by compiler */
550 };
551 #endif
552
553 /*
554 * Read MAC version/revision information from Chip registers and initialize
555 * local data structures.
556 */
557 void
ar9300_read_revisions(struct ath_hal * ah)558 ar9300_read_revisions(struct ath_hal *ah)
559 {
560 u_int32_t val;
561
562 /* XXX verify if this is the correct way to read revision on Osprey */
563 /* new SREV format for Sowl and later */
564 val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV));
565
566 if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9340) {
567 /* XXX: AR_SREV register in Wasp reads 0 */
568 AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_WASP;
569 } else if(AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_QCA955X) {
570 /* XXX: AR_SREV register in Scorpion reads 0 */
571 AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_SCORPION;
572 } else if(AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_QCA953X) {
573 /* XXX: AR_SREV register in HoneyBEE reads 0 */
574 AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_HONEYBEE;
575 } else {
576 /*
577 * Include 6-bit Chip Type (masked to 0)
578 * to differentiate from pre-Sowl versions
579 */
580 AH_PRIVATE(ah)->ah_macVersion =
581 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
582 }
583
584
585
586
587
588 #ifdef AH_SUPPORT_HORNET
589 /*
590 * EV74984, due to Hornet 1.1 didn't update WMAC revision,
591 * so that have to read SoC's revision ID instead
592 */
593 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_HORNET) {
594 #define AR_SOC_RST_REVISION_ID 0xB8060090
595 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg))
596 if ((REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_HORNET_11_MASK)
597 == AR_SREV_REVISION_HORNET_11)
598 {
599 AH_PRIVATE(ah)->ah_macRev = AR_SREV_REVISION_HORNET_11;
600 } else {
601 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2);
602 }
603 #undef REG_READ
604 #undef AR_SOC_RST_REVISION_ID
605 } else
606 #endif
607 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_WASP)
608 {
609 #define AR_SOC_RST_REVISION_ID 0xB8060090
610 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg))
611
612 AH_PRIVATE(ah)->ah_macRev =
613 REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_WASP_MASK;
614 #undef REG_READ
615 #undef AR_SOC_RST_REVISION_ID
616 }
617 else
618 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2);
619
620 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
621 AH_PRIVATE(ah)->ah_ispcie = AH_TRUE;
622 }
623 else {
624 AH_PRIVATE(ah)->ah_ispcie =
625 (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
626 }
627
628 }
629
630 /*
631 * Attach for an AR9300 part.
632 */
633 struct ath_hal *
ar9300_attach(u_int16_t devid,HAL_SOFTC sc,HAL_BUS_TAG st,HAL_BUS_HANDLE sh,uint16_t * eepromdata,HAL_OPS_CONFIG * ah_config,HAL_STATUS * status)634 ar9300_attach(u_int16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st,
635 HAL_BUS_HANDLE sh, uint16_t *eepromdata, HAL_OPS_CONFIG *ah_config,
636 HAL_STATUS *status)
637 {
638 struct ath_hal_9300 *ahp;
639 struct ath_hal *ah;
640 struct ath_hal_private *ahpriv;
641 HAL_STATUS ecode;
642
643 HAL_NO_INTERSPERSED_READS;
644
645 /* NB: memory is returned zero'd */
646 ahp = ar9300_new_state(devid, sc, st, sh, eepromdata, ah_config, status);
647 if (ahp == AH_NULL) {
648 return AH_NULL;
649 }
650 ah = &ahp->ah_priv.h;
651 ar9300_init_offsets(ah, devid);
652 ahpriv = AH_PRIVATE(ah);
653 // AH_PRIVATE(ah)->ah_bustype = bustype;
654
655 /* FreeBSD: to make OTP work for now, provide this.. */
656 AH9300(ah)->ah_cal_mem = ath_hal_malloc(HOST_CALDATA_SIZE);
657 if (AH9300(ah)->ah_cal_mem == NULL) {
658 ath_hal_printf(ah, "%s: caldata malloc failed!\n", __func__);
659 ecode = HAL_EIO;
660 goto bad;
661 }
662
663 /*
664 * If eepromdata is not NULL, copy it it into ah_cal_mem.
665 */
666 if (eepromdata != NULL)
667 OS_MEMCPY(AH9300(ah)->ah_cal_mem, eepromdata, HOST_CALDATA_SIZE);
668
669 /* XXX FreeBSD: enable RX mitigation */
670 ah->ah_config.ath_hal_intr_mitigation_rx = 1;
671
672 /* interrupt mitigation */
673 #ifdef AR5416_INT_MITIGATION
674 if (ah->ah_config.ath_hal_intr_mitigation_rx != 0) {
675 ahp->ah_intr_mitigation_rx = AH_TRUE;
676 }
677 #else
678 /* Enable Rx mitigation (default) */
679 ahp->ah_intr_mitigation_rx = AH_TRUE;
680 ah->ah_config.ath_hal_intr_mitigation_rx = 1;
681
682 #endif
683 #ifdef HOST_OFFLOAD
684 /* Reset default Rx mitigation values for Hornet */
685 if (AR_SREV_HORNET(ah)) {
686 ahp->ah_intr_mitigation_rx = AH_FALSE;
687 #ifdef AR5416_INT_MITIGATION
688 ah->ah_config.ath_hal_intr_mitigation_rx = 0;
689 #endif
690 }
691 #endif
692
693 if (ah->ah_config.ath_hal_intr_mitigation_tx != 0) {
694 ahp->ah_intr_mitigation_tx = AH_TRUE;
695 }
696
697 /*
698 * Read back AR_WA into a permanent copy and set bits 14 and 17.
699 * We need to do this to avoid RMW of this register.
700 * Do this before calling ar9300_set_reset_reg.
701 * If not, the AR_WA register which was inited via EEPROM
702 * will get wiped out.
703 */
704 ahp->ah_wa_reg_val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_WA));
705 /* Set Bits 14 and 17 in the AR_WA register. */
706 ahp->ah_wa_reg_val |=
707 AR_WA_D3_TO_L1_DISABLE | AR_WA_ASPM_TIMER_BASED_DISABLE;
708
709 if (!ar9300_set_reset_reg(ah, HAL_RESET_POWER_ON)) { /* reset chip */
710 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't reset chip\n", __func__);
711 ecode = HAL_EIO;
712 goto bad;
713 }
714
715 if (AR_SREV_JUPITER(ah)
716 #if ATH_WOW_OFFLOAD
717 && !HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_SET_4004_BIT14)
718 #endif
719 )
720 {
721 /* Jupiter doesn't need bit 14 to be set. */
722 ahp->ah_wa_reg_val &= ~AR_WA_D3_TO_L1_DISABLE;
723 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val);
724 }
725
726 #if ATH_SUPPORT_MCI
727 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
728 #if 1
729 ah->ah_btCoexSetWeights = ar9300_mci_bt_coex_set_weights;
730 ah->ah_btCoexDisable = ar9300_mci_bt_coex_disable;
731 ah->ah_btCoexEnable = ar9300_mci_bt_coex_enable;
732 #endif
733 ahp->ah_mci_ready = AH_FALSE;
734 ahp->ah_mci_bt_state = MCI_BT_SLEEP;
735 ahp->ah_mci_coex_major_version_wlan = MCI_GPM_COEX_MAJOR_VERSION_WLAN;
736 ahp->ah_mci_coex_minor_version_wlan = MCI_GPM_COEX_MINOR_VERSION_WLAN;
737 ahp->ah_mci_coex_major_version_bt = MCI_GPM_COEX_MAJOR_VERSION_DEFAULT;
738 ahp->ah_mci_coex_minor_version_bt = MCI_GPM_COEX_MINOR_VERSION_DEFAULT;
739 ahp->ah_mci_coex_bt_version_known = AH_FALSE;
740 ahp->ah_mci_coex_2g5g_update = AH_TRUE; /* track if 2g5g status sent */
741 /* will be updated before boot up sequence */
742 ahp->ah_mci_coex_is_2g = AH_TRUE;
743 ahp->ah_mci_coex_wlan_channels_update = AH_FALSE;
744 ahp->ah_mci_coex_wlan_channels[0] = 0x00000000;
745 ahp->ah_mci_coex_wlan_channels[1] = 0xffffffff;
746 ahp->ah_mci_coex_wlan_channels[2] = 0xffffffff;
747 ahp->ah_mci_coex_wlan_channels[3] = 0x7fffffff;
748 ahp->ah_mci_query_bt = AH_TRUE; /* In case WLAN start after BT */
749 ahp->ah_mci_unhalt_bt_gpm = AH_TRUE; /* Send UNHALT at beginning */
750 ahp->ah_mci_halted_bt_gpm = AH_FALSE; /* Allow first HALT */
751 ahp->ah_mci_need_flush_btinfo = AH_FALSE;
752 ahp->ah_mci_wlan_cal_seq = 0;
753 ahp->ah_mci_wlan_cal_done = 0;
754 }
755 #endif /* ATH_SUPPORT_MCI */
756
757 #if ATH_WOW_OFFLOAD
758 ahp->ah_mcast_filter_l32_set = 0;
759 ahp->ah_mcast_filter_u32_set = 0;
760 #endif
761
762 if (AR_SREV_HORNET(ah)) {
763 #ifdef AH_SUPPORT_HORNET
764 if (!AR_SREV_HORNET_11(ah)) {
765 /*
766 * Do not check bootstrap register, which cannot be trusted
767 * due to s26 switch issue on CUS164/AP121.
768 */
769 ahp->clk_25mhz = 1;
770 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n");
771 } else {
772 /* check bootstrap clock setting */
773 #define AR_SOC_SEL_25M_40M 0xB80600AC
774 #define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val);
775 #define REG_READ(_reg) (*((volatile u_int32_t *)(_reg)))
776 if (REG_READ(AR_SOC_SEL_25M_40M) & 0x1) {
777 ahp->clk_25mhz = 0;
778 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE,
779 "Bootstrap clock 40MHz\n");
780 } else {
781 ahp->clk_25mhz = 1;
782 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE,
783 "Bootstrap clock 25MHz\n");
784 }
785 #undef REG_READ
786 #undef REG_WRITE
787 #undef AR_SOC_SEL_25M_40M
788 }
789 #endif /* AH_SUPPORT_HORNET */
790 }
791
792 if (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
793 /* check bootstrap clock setting */
794 #define AR9340_SOC_SEL_25M_40M 0xB80600B0
795 #define AR9340_REF_CLK_40 (1 << 4) /* 0 - 25MHz 1 - 40 MHz */
796 #define REG_READ(_reg) (*((volatile u_int32_t *)(_reg)))
797 if (REG_READ(AR9340_SOC_SEL_25M_40M) & AR9340_REF_CLK_40) {
798 ahp->clk_25mhz = 0;
799 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 40MHz\n");
800 } else {
801 ahp->clk_25mhz = 1;
802 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n");
803 }
804 #undef REG_READ
805 #undef AR9340_SOC_SEL_25M_40M
806 #undef AR9340_REF_CLK_40
807 }
808
809 if (AR_SREV_HONEYBEE(ah)) {
810 ahp->clk_25mhz = 1;
811 }
812
813 ar9300_init_pll(ah, AH_NULL);
814
815 if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) {
816 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't wakeup chip\n", __func__);
817 ecode = HAL_EIO;
818 goto bad;
819 }
820
821 /* No serialization of Register Accesses needed. */
822 ah->ah_config.ah_serialise_reg_war = SER_REG_MODE_OFF;
823 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: ah_serialise_reg_war is %d\n",
824 __func__, ah->ah_config.ah_serialise_reg_war);
825
826 /*
827 * Add mac revision check when needed.
828 * - Osprey 1.0 and 2.0 no longer supported.
829 */
830 if (((ahpriv->ah_macVersion == AR_SREV_VERSION_OSPREY) &&
831 (ahpriv->ah_macRev <= AR_SREV_REVISION_OSPREY_20)) ||
832 (ahpriv->ah_macVersion != AR_SREV_VERSION_OSPREY &&
833 ahpriv->ah_macVersion != AR_SREV_VERSION_WASP &&
834 ahpriv->ah_macVersion != AR_SREV_VERSION_HORNET &&
835 ahpriv->ah_macVersion != AR_SREV_VERSION_POSEIDON &&
836 ahpriv->ah_macVersion != AR_SREV_VERSION_SCORPION &&
837 ahpriv->ah_macVersion != AR_SREV_VERSION_HONEYBEE &&
838 ahpriv->ah_macVersion != AR_SREV_VERSION_JUPITER &&
839 ahpriv->ah_macVersion != AR_SREV_VERSION_APHRODITE) ) {
840 HALDEBUG(ah, HAL_DEBUG_RESET,
841 "%s: Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
842 __func__,
843 ahpriv->ah_macVersion,
844 ahpriv->ah_macRev);
845 ecode = HAL_ENOTSUPP;
846 goto bad;
847 }
848
849 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
850
851 /* Setup supported calibrations */
852 ahp->ah_iq_cal_data.cal_data = &iq_cal_single_sample;
853 ahp->ah_supp_cals = IQ_MISMATCH_CAL;
854
855 /* Enable ANI */
856 ahp->ah_ani_function = HAL_ANI_ALL;
857
858 /* Enable RIFS */
859 ahp->ah_rifs_enabled = AH_TRUE;
860
861 /* by default, stop RX also in abort txdma, due to
862 "Unable to stop TxDMA" msg observed */
863 ahp->ah_abort_txdma_norx = AH_TRUE;
864
865 /* do not use optional tx chainmask by default */
866 ahp->ah_tx_chainmaskopt = 0;
867
868 ahp->ah_skip_rx_iq_cal = AH_FALSE;
869 ahp->ah_rx_cal_complete = AH_FALSE;
870 ahp->ah_rx_cal_chan = 0;
871 ahp->ah_rx_cal_chan_flag = 0;
872
873 HALDEBUG(ah, HAL_DEBUG_RESET,
874 "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__,
875 ahpriv->ah_macVersion,
876 ahpriv->ah_macRev);
877
878 if (AR_SREV_HORNET_12(ah)) {
879 /* mac */
880 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0);
881 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
882 ar9331_hornet1_2_mac_core,
883 ARRAY_LENGTH(ar9331_hornet1_2_mac_core), 2);
884 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST],
885 ar9331_hornet1_2_mac_postamble,
886 ARRAY_LENGTH(ar9331_hornet1_2_mac_postamble), 5);
887
888 /* bb */
889 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0);
890 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE],
891 ar9331_hornet1_2_baseband_core,
892 ARRAY_LENGTH(ar9331_hornet1_2_baseband_core), 2);
893 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
894 ar9331_hornet1_2_baseband_postamble,
895 ARRAY_LENGTH(ar9331_hornet1_2_baseband_postamble), 5);
896
897 /* radio */
898 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0);
899 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE],
900 ar9331_hornet1_2_radio_core,
901 ARRAY_LENGTH(ar9331_hornet1_2_radio_core), 2);
902 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], NULL, 0, 0);
903
904 /* soc */
905 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
906 ar9331_hornet1_2_soc_preamble,
907 ARRAY_LENGTH(ar9331_hornet1_2_soc_preamble), 2);
908 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0);
909 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST],
910 ar9331_hornet1_2_soc_postamble,
911 ARRAY_LENGTH(ar9331_hornet1_2_soc_postamble), 2);
912
913 /* rx/tx gain */
914 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
915 ar9331_common_rx_gain_hornet1_2,
916 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_2), 2);
917 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
918 ar9331_modes_lowest_ob_db_tx_gain_hornet1_2,
919 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5);
920
921 ah->ah_config.ath_hal_pcie_power_save_enable = 0;
922
923 /* Japan 2484Mhz CCK settings */
924 INIT_INI_ARRAY(&ahp->ah_ini_japan2484,
925 ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484,
926 ARRAY_LENGTH(
927 ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484), 2);
928
929 #if 0 /* ATH_WOW */
930 /* SerDes values during WOW sleep */
931 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow,
932 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2);
933 #endif
934
935 /* additional clock settings */
936 if (AH9300(ah)->clk_25mhz) {
937 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional,
938 ar9331_hornet1_2_xtal_25M,
939 ARRAY_LENGTH(ar9331_hornet1_2_xtal_25M), 2);
940 } else {
941 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional,
942 ar9331_hornet1_2_xtal_40M,
943 ARRAY_LENGTH(ar9331_hornet1_2_xtal_40M), 2);
944 }
945
946 } else if (AR_SREV_HORNET_11(ah)) {
947 /* mac */
948 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0);
949 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
950 ar9331_hornet1_1_mac_core,
951 ARRAY_LENGTH(ar9331_hornet1_1_mac_core), 2);
952 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST],
953 ar9331_hornet1_1_mac_postamble,
954 ARRAY_LENGTH(ar9331_hornet1_1_mac_postamble), 5);
955
956 /* bb */
957 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0);
958 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE],
959 ar9331_hornet1_1_baseband_core,
960 ARRAY_LENGTH(ar9331_hornet1_1_baseband_core), 2);
961 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
962 ar9331_hornet1_1_baseband_postamble,
963 ARRAY_LENGTH(ar9331_hornet1_1_baseband_postamble), 5);
964
965 /* radio */
966 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0);
967 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE],
968 ar9331_hornet1_1_radio_core,
969 ARRAY_LENGTH(ar9331_hornet1_1_radio_core), 2);
970 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], NULL, 0, 0);
971
972 /* soc */
973 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
974 ar9331_hornet1_1_soc_preamble,
975 ARRAY_LENGTH(ar9331_hornet1_1_soc_preamble), 2);
976 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0);
977 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST],
978 ar9331_hornet1_1_soc_postamble,
979 ARRAY_LENGTH(ar9331_hornet1_1_soc_postamble), 2);
980
981 /* rx/tx gain */
982 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
983 ar9331_common_rx_gain_hornet1_1,
984 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_1), 2);
985 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
986 ar9331_modes_lowest_ob_db_tx_gain_hornet1_1,
987 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5);
988
989 ah->ah_config.ath_hal_pcie_power_save_enable = 0;
990
991 /* Japan 2484Mhz CCK settings */
992 INIT_INI_ARRAY(&ahp->ah_ini_japan2484,
993 ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484,
994 ARRAY_LENGTH(
995 ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484), 2);
996
997 #if 0 /* ATH_WOW */
998 /* SerDes values during WOW sleep */
999 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow,
1000 N(ar9300_pcie_phy_awow), 2);
1001 #endif
1002
1003 /* additional clock settings */
1004 if (AH9300(ah)->clk_25mhz) {
1005 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional,
1006 ar9331_hornet1_1_xtal_25M,
1007 ARRAY_LENGTH(ar9331_hornet1_1_xtal_25M), 2);
1008 } else {
1009 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional,
1010 ar9331_hornet1_1_xtal_40M,
1011 ARRAY_LENGTH(ar9331_hornet1_1_xtal_40M), 2);
1012 }
1013
1014 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
1015 /* mac */
1016 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0);
1017 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
1018 ar9485_poseidon1_1_mac_core,
1019 ARRAY_LENGTH( ar9485_poseidon1_1_mac_core), 2);
1020 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST],
1021 ar9485_poseidon1_1_mac_postamble,
1022 ARRAY_LENGTH(ar9485_poseidon1_1_mac_postamble), 5);
1023
1024 /* bb */
1025 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE],
1026 ar9485_poseidon1_1, ARRAY_LENGTH(ar9485_poseidon1_1), 2);
1027 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE],
1028 ar9485_poseidon1_1_baseband_core,
1029 ARRAY_LENGTH(ar9485_poseidon1_1_baseband_core), 2);
1030 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
1031 ar9485_poseidon1_1_baseband_postamble,
1032 ARRAY_LENGTH(ar9485_poseidon1_1_baseband_postamble), 5);
1033
1034 /* radio */
1035 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0);
1036 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE],
1037 ar9485_poseidon1_1_radio_core,
1038 ARRAY_LENGTH(ar9485_poseidon1_1_radio_core), 2);
1039 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST],
1040 ar9485_poseidon1_1_radio_postamble,
1041 ARRAY_LENGTH(ar9485_poseidon1_1_radio_postamble), 2);
1042
1043 /* soc */
1044 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
1045 ar9485_poseidon1_1_soc_preamble,
1046 ARRAY_LENGTH(ar9485_poseidon1_1_soc_preamble), 2);
1047
1048 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0);
1049 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], NULL, 0, 0);
1050
1051 /* rx/tx gain */
1052 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
1053 ar9485_common_wo_xlna_rx_gain_poseidon1_1,
1054 ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2);
1055 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
1056 ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1,
1057 ARRAY_LENGTH(ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1), 5);
1058
1059 /* Japan 2484Mhz CCK settings */
1060 INIT_INI_ARRAY(&ahp->ah_ini_japan2484,
1061 ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484,
1062 ARRAY_LENGTH(
1063 ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484), 2);
1064
1065 /* Load PCIE SERDES settings from INI */
1066 if (ah->ah_config.ath_hal_pcie_clock_req) {
1067 /* Pci-e Clock Request = 1 */
1068 if (ah->ah_config.ath_hal_pll_pwr_save
1069 & AR_PCIE_PLL_PWRSAVE_CONTROL)
1070 {
1071 /* Sleep Setting */
1072 if (ah->ah_config.ath_hal_pll_pwr_save &
1073 AR_PCIE_PLL_PWRSAVE_ON_D3)
1074 {
1075 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1076 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1,
1077 ARRAY_LENGTH(
1078 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1),
1079 2);
1080 } else {
1081 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1082 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1,
1083 ARRAY_LENGTH(
1084 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1),
1085 2);
1086 }
1087 /* Awake Setting */
1088 if (ah->ah_config.ath_hal_pll_pwr_save &
1089 AR_PCIE_PLL_PWRSAVE_ON_D0)
1090 {
1091 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1092 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1,
1093 ARRAY_LENGTH(
1094 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1),
1095 2);
1096 } else {
1097 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1098 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1,
1099 ARRAY_LENGTH(
1100 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1),
1101 2);
1102 }
1103
1104 } else {
1105 /*Use driver default setting*/
1106 /* Sleep Setting */
1107 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1108 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1,
1109 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1),
1110 2);
1111 /* Awake Setting */
1112 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1113 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1,
1114 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1),
1115 2);
1116 }
1117 } else {
1118 /* Pci-e Clock Request = 0 */
1119 if (ah->ah_config.ath_hal_pll_pwr_save
1120 & AR_PCIE_PLL_PWRSAVE_CONTROL)
1121 {
1122 /* Sleep Setting */
1123 if (ah->ah_config.ath_hal_pll_pwr_save &
1124 AR_PCIE_PLL_PWRSAVE_ON_D3)
1125 {
1126 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1127 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1,
1128 ARRAY_LENGTH(
1129 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1),
1130 2);
1131 } else {
1132 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1133 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1,
1134 ARRAY_LENGTH(
1135 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1),
1136 2);
1137 }
1138 /* Awake Setting */
1139 if (ah->ah_config.ath_hal_pll_pwr_save &
1140 AR_PCIE_PLL_PWRSAVE_ON_D0)
1141 {
1142 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1143 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1,
1144 ARRAY_LENGTH(
1145 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1),
1146 2);
1147 } else {
1148 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1149 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1,
1150 ARRAY_LENGTH(
1151 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1),
1152 2);
1153 }
1154
1155 } else {
1156 /*Use driver default setting*/
1157 /* Sleep Setting */
1158 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1159 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1,
1160 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1),
1161 2);
1162 /* Awake Setting */
1163 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1164 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1,
1165 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1),
1166 2);
1167 }
1168 }
1169 /* pcie ps setting will honor registry setting, default is 0 */
1170 //ah->ah_config.ath_hal_pciePowerSaveEnable = 0;
1171 } else if (AR_SREV_POSEIDON(ah)) {
1172 /* mac */
1173 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0);
1174 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
1175 ar9485_poseidon1_0_mac_core,
1176 ARRAY_LENGTH(ar9485_poseidon1_0_mac_core), 2);
1177 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST],
1178 ar9485_poseidon1_0_mac_postamble,
1179 ARRAY_LENGTH(ar9485_poseidon1_0_mac_postamble), 5);
1180
1181 /* bb */
1182 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE],
1183 ar9485_poseidon1_0,
1184 ARRAY_LENGTH(ar9485_poseidon1_0), 2);
1185 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE],
1186 ar9485_poseidon1_0_baseband_core,
1187 ARRAY_LENGTH(ar9485_poseidon1_0_baseband_core), 2);
1188 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
1189 ar9485_poseidon1_0_baseband_postamble,
1190 ARRAY_LENGTH(ar9485_poseidon1_0_baseband_postamble), 5);
1191
1192 /* radio */
1193 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0);
1194 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE],
1195 ar9485_poseidon1_0_radio_core,
1196 ARRAY_LENGTH(ar9485_poseidon1_0_radio_core), 2);
1197 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST],
1198 ar9485_poseidon1_0_radio_postamble,
1199 ARRAY_LENGTH(ar9485_poseidon1_0_radio_postamble), 2);
1200
1201 /* soc */
1202 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
1203 ar9485_poseidon1_0_soc_preamble,
1204 ARRAY_LENGTH(ar9485_poseidon1_0_soc_preamble), 2);
1205 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0);
1206 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], NULL, 0, 0);
1207
1208 /* rx/tx gain */
1209 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
1210 ar9485Common_wo_xlna_rx_gain_poseidon1_0,
1211 ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2);
1212 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
1213 ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0,
1214 ARRAY_LENGTH(ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0), 5);
1215
1216 /* Japan 2484Mhz CCK settings */
1217 INIT_INI_ARRAY(&ahp->ah_ini_japan2484,
1218 ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484,
1219 ARRAY_LENGTH(
1220 ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484), 2);
1221
1222 /* Load PCIE SERDES settings from INI */
1223 if (ah->ah_config.ath_hal_pcie_clock_req) {
1224 /* Pci-e Clock Request = 1 */
1225 if (ah->ah_config.ath_hal_pll_pwr_save
1226 & AR_PCIE_PLL_PWRSAVE_CONTROL)
1227 {
1228 /* Sleep Setting */
1229 if (ah->ah_config.ath_hal_pll_pwr_save &
1230 AR_PCIE_PLL_PWRSAVE_ON_D3)
1231 {
1232 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1233 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1,
1234 ARRAY_LENGTH(
1235 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1),
1236 2);
1237 } else {
1238 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1239 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1,
1240 ARRAY_LENGTH(
1241 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1),
1242 2);
1243 }
1244 /* Awake Setting */
1245 if (ah->ah_config.ath_hal_pll_pwr_save &
1246 AR_PCIE_PLL_PWRSAVE_ON_D0)
1247 {
1248 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1249 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1,
1250 ARRAY_LENGTH(
1251 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1),
1252 2);
1253 } else {
1254 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1255 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1,
1256 ARRAY_LENGTH(
1257 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1),
1258 2);
1259 }
1260
1261 } else {
1262 /*Use driver default setting*/
1263 /* Sleep Setting */
1264 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1265 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1,
1266 ARRAY_LENGTH(
1267 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1),
1268 2);
1269 /* Awake Setting */
1270 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1271 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1,
1272 ARRAY_LENGTH(
1273 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1),
1274 2);
1275 }
1276 } else {
1277 /* Pci-e Clock Request = 0 */
1278 if (ah->ah_config.ath_hal_pll_pwr_save
1279 & AR_PCIE_PLL_PWRSAVE_CONTROL)
1280 {
1281 /* Sleep Setting */
1282 if (ah->ah_config.ath_hal_pll_pwr_save &
1283 AR_PCIE_PLL_PWRSAVE_ON_D3)
1284 {
1285 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1286 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1,
1287 ARRAY_LENGTH(
1288 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1),
1289 2);
1290 } else {
1291 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1292 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1,
1293 ARRAY_LENGTH(
1294 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1),
1295 2);
1296 }
1297 /* Awake Setting */
1298 if (ah->ah_config.ath_hal_pll_pwr_save &
1299 AR_PCIE_PLL_PWRSAVE_ON_D0)
1300 {
1301 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1302 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1,
1303 ARRAY_LENGTH(
1304 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1),
1305 2);
1306 } else {
1307 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1308 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1,
1309 ARRAY_LENGTH(
1310 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1),
1311 2);
1312 }
1313
1314 } else {
1315 /*Use driver default setting*/
1316 /* Sleep Setting */
1317 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1318 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1,
1319 ARRAY_LENGTH(
1320 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1),
1321 2);
1322 /* Awake Setting */
1323 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1324 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1,
1325 ARRAY_LENGTH(
1326 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1),
1327 2);
1328 }
1329 }
1330 /* pcie ps setting will honor registry setting, default is 0 */
1331 /*ah->ah_config.ath_hal_pcie_power_save_enable = 0;*/
1332
1333 #if 0 /* ATH_WOW */
1334 /* SerDes values during WOW sleep */
1335 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow,
1336 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2);
1337 #endif
1338
1339 } else if (AR_SREV_WASP(ah)) {
1340 /* mac */
1341 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0);
1342 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
1343 ar9340_wasp_1p0_mac_core,
1344 ARRAY_LENGTH(ar9340_wasp_1p0_mac_core), 2);
1345 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST],
1346 ar9340_wasp_1p0_mac_postamble,
1347 ARRAY_LENGTH(ar9340_wasp_1p0_mac_postamble), 5);
1348
1349 /* bb */
1350 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0);
1351 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE],
1352 ar9340_wasp_1p0_baseband_core,
1353 ARRAY_LENGTH(ar9340_wasp_1p0_baseband_core), 2);
1354 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
1355 ar9340_wasp_1p0_baseband_postamble,
1356 ARRAY_LENGTH(ar9340_wasp_1p0_baseband_postamble), 5);
1357
1358 /* radio */
1359 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0);
1360 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE],
1361 ar9340_wasp_1p0_radio_core,
1362 ARRAY_LENGTH(ar9340_wasp_1p0_radio_core), 2);
1363 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST],
1364 ar9340_wasp_1p0_radio_postamble,
1365 ARRAY_LENGTH(ar9340_wasp_1p0_radio_postamble), 5);
1366
1367 /* soc */
1368 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
1369 ar9340_wasp_1p0_soc_preamble,
1370 ARRAY_LENGTH(ar9340_wasp_1p0_soc_preamble), 2);
1371 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0);
1372 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST],
1373 ar9340_wasp_1p0_soc_postamble,
1374 ARRAY_LENGTH(ar9340_wasp_1p0_soc_postamble), 5);
1375
1376 /* rx/tx gain */
1377 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
1378 ar9340Common_wo_xlna_rx_gain_table_wasp_1p0,
1379 ARRAY_LENGTH(ar9340Common_wo_xlna_rx_gain_table_wasp_1p0), 2);
1380 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
1381 ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0,
1382 ARRAY_LENGTH(ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0), 5);
1383
1384 ah->ah_config.ath_hal_pcie_power_save_enable = 0;
1385
1386 /* Fast clock modal settings */
1387 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional,
1388 ar9340Modes_fast_clock_wasp_1p0,
1389 ARRAY_LENGTH(ar9340Modes_fast_clock_wasp_1p0), 3);
1390
1391 /* XXX TODO: need to add this for freebsd; it's missing from the current .ini files */
1392 #if 0
1393 /* Japan 2484Mhz CCK settings */
1394 INIT_INI_ARRAY(&ahp->ah_ini_japan2484,
1395 ar9340_wasp_1p0_baseband_core_txfir_coeff_japan_2484,
1396 ARRAY_LENGTH(
1397 ar9340_wasp_1p0_baseband_core_txfir_coeff_japan_2484), 2);
1398 #endif
1399
1400 /* Additional setttings for 40Mhz */
1401 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40mhz,
1402 ar9340_wasp_1p0_radio_core_40M,
1403 ARRAY_LENGTH(ar9340_wasp_1p0_radio_core_40M), 2);
1404
1405 /* DFS */
1406 INIT_INI_ARRAY(&ahp->ah_ini_dfs,
1407 ar9340_wasp_1p0_baseband_postamble_dfs_channel,
1408 ARRAY_LENGTH(ar9340_wasp_1p0_baseband_postamble_dfs_channel), 3);
1409 } else if (AR_SREV_SCORPION(ah)) {
1410 /* mac */
1411 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0);
1412 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
1413 ar955x_scorpion_1p0_mac_core,
1414 ARRAY_LENGTH(ar955x_scorpion_1p0_mac_core), 2);
1415 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST],
1416 ar955x_scorpion_1p0_mac_postamble,
1417 ARRAY_LENGTH(ar955x_scorpion_1p0_mac_postamble), 5);
1418
1419 /* bb */
1420 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0);
1421 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE],
1422 ar955x_scorpion_1p0_baseband_core,
1423 ARRAY_LENGTH(ar955x_scorpion_1p0_baseband_core), 2);
1424 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
1425 ar955x_scorpion_1p0_baseband_postamble,
1426 ARRAY_LENGTH(ar955x_scorpion_1p0_baseband_postamble), 5);
1427
1428 /* radio */
1429 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0);
1430 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE],
1431 ar955x_scorpion_1p0_radio_core,
1432 ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core), 2);
1433 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST],
1434 ar955x_scorpion_1p0_radio_postamble,
1435 ARRAY_LENGTH(ar955x_scorpion_1p0_radio_postamble), 5);
1436
1437 /* soc */
1438 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
1439 ar955x_scorpion_1p0_soc_preamble,
1440 ARRAY_LENGTH(ar955x_scorpion_1p0_soc_preamble), 2);
1441 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0);
1442 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST],
1443 ar955x_scorpion_1p0_soc_postamble,
1444 ARRAY_LENGTH(ar955x_scorpion_1p0_soc_postamble), 5);
1445
1446 /* rx/tx gain */
1447 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
1448 ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0,
1449 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0), 2);
1450 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds,
1451 ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0,
1452 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5);
1453 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
1454 ar955xModes_no_xpa_tx_gain_table_scorpion_1p0,
1455 ARRAY_LENGTH(ar955xModes_no_xpa_tx_gain_table_scorpion_1p0), 5);
1456
1457 /*ath_hal_pciePowerSaveEnable should be 2 for OWL/Condor and 0 for merlin */
1458 ah->ah_config.ath_hal_pcie_power_save_enable = 0;
1459
1460 /* Fast clock modal settings */
1461 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional,
1462 ar955xModes_fast_clock_scorpion_1p0,
1463 ARRAY_LENGTH(ar955xModes_fast_clock_scorpion_1p0), 3);
1464
1465 /* Additional setttings for 40Mhz */
1466 //INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40M,
1467 // ar955x_scorpion_1p0_radio_core_40M,
1468 // ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core_40M), 2);
1469 } else if (AR_SREV_HONEYBEE(ah)) {
1470 /* mac */
1471 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0);
1472 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
1473 qca953x_honeybee_1p0_mac_core,
1474 ARRAY_LENGTH(qca953x_honeybee_1p0_mac_core), 2);
1475 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST],
1476 qca953x_honeybee_1p0_mac_postamble,
1477 ARRAY_LENGTH(qca953x_honeybee_1p0_mac_postamble), 5);
1478
1479 /* bb */
1480 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0);
1481 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE],
1482 qca953x_honeybee_1p0_baseband_core,
1483 ARRAY_LENGTH(qca953x_honeybee_1p0_baseband_core), 2);
1484 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
1485 qca953x_honeybee_1p0_baseband_postamble,
1486 ARRAY_LENGTH(qca953x_honeybee_1p0_baseband_postamble), 5);
1487
1488 /* radio */
1489 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0);
1490 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE],
1491 qca953x_honeybee_1p0_radio_core,
1492 ARRAY_LENGTH(qca953x_honeybee_1p0_radio_core), 2);
1493 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST],
1494 qca953x_honeybee_1p0_radio_postamble,
1495 ARRAY_LENGTH(qca953x_honeybee_1p0_radio_postamble), 5);
1496
1497 /* soc */
1498 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
1499 qca953x_honeybee_1p0_soc_preamble,
1500 ARRAY_LENGTH(qca953x_honeybee_1p0_soc_preamble), 2);
1501 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0);
1502 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST],
1503 qca953x_honeybee_1p0_soc_postamble,
1504 ARRAY_LENGTH(qca953x_honeybee_1p0_soc_postamble), 5);
1505
1506 /* rx/tx gain */
1507 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
1508 qca953xCommon_wo_xlna_rx_gain_table_honeybee_1p0,
1509 ARRAY_LENGTH(qca953xCommon_wo_xlna_rx_gain_table_honeybee_1p0), 2);
1510 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds,
1511 qca953xCommon_wo_xlna_rx_gain_bounds_honeybee_1p0,
1512 ARRAY_LENGTH(qca953xCommon_wo_xlna_rx_gain_bounds_honeybee_1p0), 5);
1513 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
1514 qca953xModes_no_xpa_tx_gain_table_honeybee_1p0,
1515 ARRAY_LENGTH(qca953xModes_no_xpa_tx_gain_table_honeybee_1p0), 2);
1516
1517 /*ath_hal_pciePowerSaveEnable should be 2 for OWL/Condor and 0 for merlin */
1518 ah->ah_config.ath_hal_pcie_power_save_enable = 0;
1519
1520 /* Fast clock modal settings */
1521 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional,
1522 qca953xModes_fast_clock_honeybee_1p0,
1523 ARRAY_LENGTH(qca953xModes_fast_clock_honeybee_1p0), 3);
1524
1525 /* Additional setttings for 40Mhz */
1526 //INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40M,
1527 // qca953x_honeybee_1p0_radio_core_40M,
1528 // ARRAY_LENGTH(qca953x_honeybee_1p0_radio_core_40M), 2);
1529
1530 } else if (AR_SREV_JUPITER_10(ah)) {
1531 /* Jupiter: new INI format (pre, core, post arrays per subsystem) */
1532
1533 /* mac */
1534 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0);
1535 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
1536 ar9300_jupiter_1p0_mac_core,
1537 ARRAY_LENGTH(ar9300_jupiter_1p0_mac_core), 2);
1538 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST],
1539 ar9300_jupiter_1p0_mac_postamble,
1540 ARRAY_LENGTH(ar9300_jupiter_1p0_mac_postamble), 5);
1541
1542 /* bb */
1543 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0);
1544 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE],
1545 ar9300_jupiter_1p0_baseband_core,
1546 ARRAY_LENGTH(ar9300_jupiter_1p0_baseband_core), 2);
1547 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
1548 ar9300_jupiter_1p0_baseband_postamble,
1549 ARRAY_LENGTH(ar9300_jupiter_1p0_baseband_postamble), 5);
1550
1551 /* radio */
1552 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0);
1553 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE],
1554 ar9300_jupiter_1p0_radio_core,
1555 ARRAY_LENGTH(ar9300_jupiter_1p0_radio_core), 2);
1556 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST],
1557 ar9300_jupiter_1p0_radio_postamble,
1558 ARRAY_LENGTH(ar9300_jupiter_1p0_radio_postamble), 5);
1559
1560 /* soc */
1561 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
1562 ar9300_jupiter_1p0_soc_preamble,
1563 ARRAY_LENGTH(ar9300_jupiter_1p0_soc_preamble), 2);
1564 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0);
1565 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST],
1566 ar9300_jupiter_1p0_soc_postamble,
1567 ARRAY_LENGTH(ar9300_jupiter_1p0_soc_postamble), 5);
1568
1569 /* rx/tx gain */
1570 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
1571 ar9300_common_rx_gain_table_jupiter_1p0,
1572 ARRAY_LENGTH(ar9300_common_rx_gain_table_jupiter_1p0), 2);
1573
1574 /* Load PCIE SERDES settings from INI */
1575 if (ah->ah_config.ath_hal_pcie_clock_req) {
1576 /* Pci-e Clock Request = 1 */
1577 /*
1578 * PLL ON + clkreq enable is not a valid combination,
1579 * thus to ignore ath_hal_pll_pwr_save, use PLL OFF.
1580 */
1581 {
1582 /*Use driver default setting*/
1583 /* Awake -> Sleep Setting */
1584 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1585 ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0,
1586 ARRAY_LENGTH(ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0),
1587 2);
1588 /* Sleep -> Awake Setting */
1589 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1590 ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0,
1591 ARRAY_LENGTH(ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0),
1592 2);
1593 }
1594 }
1595 else {
1596 /*
1597 * Since Jupiter 1.0 and 2.0 share the same device id and will be
1598 * installed with same INF, but Jupiter 1.0 has issue with PLL OFF.
1599 *
1600 * Force Jupiter 1.0 to use ON/ON setting.
1601 */
1602 ah->ah_config.ath_hal_pll_pwr_save = 0;
1603 /* Pci-e Clock Request = 0 */
1604 if (ah->ah_config.ath_hal_pll_pwr_save &
1605 AR_PCIE_PLL_PWRSAVE_CONTROL)
1606 {
1607 /* Awake -> Sleep Setting */
1608 if (ah->ah_config.ath_hal_pll_pwr_save &
1609 AR_PCIE_PLL_PWRSAVE_ON_D3)
1610 {
1611 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1612 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0,
1613 ARRAY_LENGTH(
1614 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0),
1615 2);
1616 }
1617 else {
1618 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1619 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0,
1620 ARRAY_LENGTH(
1621 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0),
1622 2);
1623 }
1624 /* Sleep -> Awake Setting */
1625 if (ah->ah_config.ath_hal_pll_pwr_save &
1626 AR_PCIE_PLL_PWRSAVE_ON_D0)
1627 {
1628 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1629 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0,
1630 ARRAY_LENGTH(
1631 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0),
1632 2);
1633 }
1634 else {
1635 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1636 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0,
1637 ARRAY_LENGTH(
1638 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0),
1639 2);
1640 }
1641
1642 }
1643 else {
1644 /*Use driver default setting*/
1645 /* Awake -> Sleep Setting */
1646 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1647 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0,
1648 ARRAY_LENGTH(
1649 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0),
1650 2);
1651 /* Sleep -> Awake Setting */
1652 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1653 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0,
1654 ARRAY_LENGTH(
1655 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0),
1656 2);
1657 }
1658 }
1659 /*
1660 * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and
1661 * 0 for merlin
1662 */
1663 ah->ah_config.ath_hal_pcie_power_save_enable = 0;
1664
1665 #if 0 // ATH_WOW
1666 /* SerDes values during WOW sleep */
1667 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW,
1668 ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2);
1669 #endif
1670
1671 /* Fast clock modal settings */
1672 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional,
1673 ar9300_modes_fast_clock_jupiter_1p0,
1674 ARRAY_LENGTH(ar9300_modes_fast_clock_jupiter_1p0), 3);
1675 INIT_INI_ARRAY(&ahp->ah_ini_japan2484,
1676 ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484,
1677 ARRAY_LENGTH(
1678 ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484), 2);
1679
1680 }
1681 else if (AR_SREV_JUPITER_20_OR_LATER(ah)) {
1682 /* Jupiter: new INI format (pre, core, post arrays per subsystem) */
1683
1684 /* FreeBSD: just override the registers for jupiter 2.1 */
1685 /* XXX TODO: refactor this stuff out; reinit all the 2.1 registers */
1686
1687 /* mac */
1688 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0);
1689
1690 if (AR_SREV_JUPITER_21(ah)) {
1691 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
1692 ar9462_2p1_mac_core,
1693 ARRAY_LENGTH(ar9462_2p1_mac_core), 2);
1694 } else {
1695 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
1696 ar9300_jupiter_2p0_mac_core,
1697 ARRAY_LENGTH(ar9300_jupiter_2p0_mac_core), 2);
1698 }
1699
1700 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST],
1701 ar9300_jupiter_2p0_mac_postamble,
1702 ARRAY_LENGTH(ar9300_jupiter_2p0_mac_postamble), 5);
1703
1704 /* bb */
1705 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0);
1706 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE],
1707 ar9300_jupiter_2p0_baseband_core,
1708 ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_core), 2);
1709
1710 if (AR_SREV_JUPITER_21(ah)) {
1711 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
1712 ar9462_2p1_baseband_postamble,
1713 ARRAY_LENGTH(ar9462_2p1_baseband_postamble), 5);
1714 } else {
1715 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
1716 ar9300_jupiter_2p0_baseband_postamble,
1717 ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_postamble), 5);
1718 }
1719
1720 /* radio */
1721 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0);
1722 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE],
1723 ar9300_jupiter_2p0_radio_core,
1724 ARRAY_LENGTH(ar9300_jupiter_2p0_radio_core), 2);
1725 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST],
1726 ar9300_jupiter_2p0_radio_postamble,
1727 ARRAY_LENGTH(ar9300_jupiter_2p0_radio_postamble), 5);
1728 INIT_INI_ARRAY(&ahp->ah_ini_radio_post_sys2ant,
1729 ar9300_jupiter_2p0_radio_postamble_sys2ant,
1730 ARRAY_LENGTH(ar9300_jupiter_2p0_radio_postamble_sys2ant), 5);
1731
1732 /* soc */
1733 if (AR_SREV_JUPITER_21(ah)) {
1734 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
1735 ar9462_2p1_soc_preamble,
1736 ARRAY_LENGTH(ar9462_2p1_soc_preamble), 2);
1737 } else {
1738 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
1739 ar9300_jupiter_2p0_soc_preamble,
1740 ARRAY_LENGTH(ar9300_jupiter_2p0_soc_preamble), 2);
1741 }
1742 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0);
1743 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST],
1744 ar9300_jupiter_2p0_soc_postamble,
1745 ARRAY_LENGTH(ar9300_jupiter_2p0_soc_postamble), 5);
1746
1747 /* rx/tx gain */
1748 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
1749 ar9300Common_rx_gain_table_jupiter_2p0,
1750 ARRAY_LENGTH(ar9300Common_rx_gain_table_jupiter_2p0), 2);
1751
1752 /* BTCOEX */
1753 INIT_INI_ARRAY(&ahp->ah_ini_BTCOEX_MAX_TXPWR,
1754 ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table,
1755 ARRAY_LENGTH(ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table), 2);
1756
1757 /* Load PCIE SERDES settings from INI */
1758 if (ah->ah_config.ath_hal_pcie_clock_req) {
1759 /* Pci-e Clock Request = 1 */
1760 /*
1761 * PLL ON + clkreq enable is not a valid combination,
1762 * thus to ignore ath_hal_pll_pwr_save, use PLL OFF.
1763 */
1764 {
1765 /*Use driver default setting*/
1766 /* Awake -> Sleep Setting */
1767 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1768 ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0,
1769 ARRAY_LENGTH(ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0),
1770 2);
1771 /* Sleep -> Awake Setting */
1772 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1773 ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0,
1774 ARRAY_LENGTH(ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0),
1775 2);
1776 }
1777 }
1778 else {
1779 /* Pci-e Clock Request = 0 */
1780 if (ah->ah_config.ath_hal_pll_pwr_save &
1781 AR_PCIE_PLL_PWRSAVE_CONTROL)
1782 {
1783 /* Awake -> Sleep Setting */
1784 if (ah->ah_config.ath_hal_pll_pwr_save &
1785 AR_PCIE_PLL_PWRSAVE_ON_D3)
1786 {
1787 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1788 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0,
1789 ARRAY_LENGTH(
1790 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0),
1791 2);
1792 }
1793 else {
1794 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1795 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0,
1796 ARRAY_LENGTH(
1797 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0),
1798 2);
1799 }
1800 /* Sleep -> Awake Setting */
1801 if (ah->ah_config.ath_hal_pll_pwr_save &
1802 AR_PCIE_PLL_PWRSAVE_ON_D0)
1803 {
1804 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1805 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0,
1806 ARRAY_LENGTH(
1807 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0),
1808 2);
1809 }
1810 else {
1811 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1812 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0,
1813 ARRAY_LENGTH(
1814 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0),
1815 2);
1816 }
1817
1818 }
1819 else {
1820 /*Use driver default setting*/
1821 /* Awake -> Sleep Setting */
1822 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1823 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0,
1824 ARRAY_LENGTH(
1825 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0),
1826 2);
1827 /* Sleep -> Awake Setting */
1828 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1829 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0,
1830 ARRAY_LENGTH(
1831 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0),
1832 2);
1833 }
1834 }
1835
1836 /*
1837 * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and
1838 * 0 for merlin
1839 */
1840 ah->ah_config.ath_hal_pcie_power_save_enable = 0;
1841
1842 #if 0 // ATH_WOW
1843 /* SerDes values during WOW sleep */
1844 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW,
1845 ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2);
1846 #endif
1847
1848 /* Fast clock modal settings */
1849 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional,
1850 ar9300Modes_fast_clock_jupiter_2p0,
1851 ARRAY_LENGTH(ar9300Modes_fast_clock_jupiter_2p0), 3);
1852 INIT_INI_ARRAY(&ahp->ah_ini_japan2484,
1853 ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484,
1854 ARRAY_LENGTH(
1855 ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484), 2);
1856
1857 } else if (AR_SREV_APHRODITE(ah)) {
1858 /* Aphrodite: new INI format (pre, core, post arrays per subsystem) */
1859
1860 /* mac */
1861 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0);
1862 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
1863 ar956X_aphrodite_1p0_mac_core,
1864 ARRAY_LENGTH(ar956X_aphrodite_1p0_mac_core), 2);
1865 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST],
1866 ar956X_aphrodite_1p0_mac_postamble,
1867 ARRAY_LENGTH(ar956X_aphrodite_1p0_mac_postamble), 5);
1868
1869 /* bb */
1870 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0);
1871 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE],
1872 ar956X_aphrodite_1p0_baseband_core,
1873 ARRAY_LENGTH(ar956X_aphrodite_1p0_baseband_core), 2);
1874 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
1875 ar956X_aphrodite_1p0_baseband_postamble,
1876 ARRAY_LENGTH(ar956X_aphrodite_1p0_baseband_postamble), 5);
1877
1878 //mark jupiter have but aphrodite don't have
1879 // /* radio */
1880 // INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0);
1881 // INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE],
1882 // ar9300_aphrodite_1p0_radio_core,
1883 // ARRAY_LENGTH(ar9300_aphrodite_1p0_radio_core), 2);
1884 // INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST],
1885 // ar9300_aphrodite_1p0_radio_postamble,
1886 // ARRAY_LENGTH(ar9300_aphrodite_1p0_radio_postamble), 5);
1887
1888 /* soc */
1889 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
1890 ar956X_aphrodite_1p0_soc_preamble,
1891 ARRAY_LENGTH(ar956X_aphrodite_1p0_soc_preamble), 2);
1892 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0);
1893 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST],
1894 ar956X_aphrodite_1p0_soc_postamble,
1895 ARRAY_LENGTH(ar956X_aphrodite_1p0_soc_postamble), 5);
1896
1897 /* rx/tx gain */
1898 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
1899 ar956XCommon_rx_gain_table_aphrodite_1p0,
1900 ARRAY_LENGTH(ar956XCommon_rx_gain_table_aphrodite_1p0), 2);
1901 //INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
1902 // ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0,
1903 // ARRAY_LENGTH(ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0),
1904 // 5);
1905
1906
1907 /*
1908 * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and
1909 * 0 for merlin
1910 */
1911 ah->ah_config.ath_hal_pcie_power_save_enable = 0;
1912
1913 #if 0 // ATH_WOW
1914 /* SerDes values during WOW sleep */
1915 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW,
1916 ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2);
1917 #endif
1918 /* Fast clock modal settings */
1919 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional,
1920 ar956XModes_fast_clock_aphrodite_1p0,
1921 ARRAY_LENGTH(ar956XModes_fast_clock_aphrodite_1p0), 3);
1922
1923 } else if (AR_SREV_AR9580(ah)) {
1924 /*
1925 * AR9580/Peacock -
1926 * new INI format (pre, core, post arrays per subsystem)
1927 */
1928
1929 /* mac */
1930 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0);
1931 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
1932 ar9300_ar9580_1p0_mac_core,
1933 ARRAY_LENGTH(ar9300_ar9580_1p0_mac_core), 2);
1934 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST],
1935 ar9300_ar9580_1p0_mac_postamble,
1936 ARRAY_LENGTH(ar9300_ar9580_1p0_mac_postamble), 5);
1937
1938 /* bb */
1939 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0);
1940 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE],
1941 ar9300_ar9580_1p0_baseband_core,
1942 ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_core), 2);
1943 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
1944 ar9300_ar9580_1p0_baseband_postamble,
1945 ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_postamble), 5);
1946
1947 /* radio */
1948 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0);
1949 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE],
1950 ar9300_ar9580_1p0_radio_core,
1951 ARRAY_LENGTH(ar9300_ar9580_1p0_radio_core), 2);
1952 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST],
1953 ar9300_ar9580_1p0_radio_postamble,
1954 ARRAY_LENGTH(ar9300_ar9580_1p0_radio_postamble), 5);
1955
1956 /* soc */
1957 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
1958 ar9300_ar9580_1p0_soc_preamble,
1959 ARRAY_LENGTH(ar9300_ar9580_1p0_soc_preamble), 2);
1960 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0);
1961 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST],
1962 ar9300_ar9580_1p0_soc_postamble,
1963 ARRAY_LENGTH(ar9300_ar9580_1p0_soc_postamble), 5);
1964
1965 /* rx/tx gain */
1966 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
1967 ar9300_common_rx_gain_table_ar9580_1p0,
1968 ARRAY_LENGTH(ar9300_common_rx_gain_table_ar9580_1p0), 2);
1969 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
1970 ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0,
1971 ARRAY_LENGTH(ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0), 5);
1972
1973 /* DFS */
1974 INIT_INI_ARRAY(&ahp->ah_ini_dfs,
1975 ar9300_ar9580_1p0_baseband_postamble_dfs_channel,
1976 ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_postamble_dfs_channel), 3);
1977
1978
1979 /* Load PCIE SERDES settings from INI */
1980
1981 /*D3 Setting */
1982 if (ah->ah_config.ath_hal_pcie_clock_req) {
1983 if (ah->ah_config.ath_hal_pll_pwr_save &
1984 AR_PCIE_PLL_PWRSAVE_CONTROL)
1985 { //registry control
1986 if (ah->ah_config.ath_hal_pll_pwr_save &
1987 AR_PCIE_PLL_PWRSAVE_ON_D3)
1988 { //bit1, in to D3
1989 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1990 ar9300PciePhy_clkreq_enable_L1_ar9580_1p0,
1991 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_ar9580_1p0),
1992 2);
1993 } else {
1994 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1995 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0,
1996 ARRAY_LENGTH(
1997 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0),
1998 2);
1999 }
2000 } else {//no registry control, default is pll on
2001 INIT_INI_ARRAY(
2002 &ahp->ah_ini_pcie_serdes,
2003 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0,
2004 ARRAY_LENGTH(
2005 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0),
2006 2);
2007 }
2008 } else {
2009 if (ah->ah_config.ath_hal_pll_pwr_save &
2010 AR_PCIE_PLL_PWRSAVE_CONTROL)
2011 { //registry control
2012 if (ah->ah_config.ath_hal_pll_pwr_save &
2013 AR_PCIE_PLL_PWRSAVE_ON_D3)
2014 { //bit1, in to D3
2015 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
2016 ar9300PciePhy_clkreq_disable_L1_ar9580_1p0,
2017 ARRAY_LENGTH(
2018 ar9300PciePhy_clkreq_disable_L1_ar9580_1p0),
2019 2);
2020 } else {
2021 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
2022 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0,
2023 ARRAY_LENGTH(
2024 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0),
2025 2);
2026 }
2027 } else {//no registry control, default is pll on
2028 INIT_INI_ARRAY(
2029 &ahp->ah_ini_pcie_serdes,
2030 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0,
2031 ARRAY_LENGTH(
2032 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0),
2033 2);
2034 }
2035 }
2036
2037 /*D0 Setting */
2038 if (ah->ah_config.ath_hal_pcie_clock_req) {
2039 if (ah->ah_config.ath_hal_pll_pwr_save &
2040 AR_PCIE_PLL_PWRSAVE_CONTROL)
2041 { //registry control
2042 if (ah->ah_config.ath_hal_pll_pwr_save &
2043 AR_PCIE_PLL_PWRSAVE_ON_D0)
2044 { //bit2, out of D3
2045 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
2046 ar9300PciePhy_clkreq_enable_L1_ar9580_1p0,
2047 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_ar9580_1p0),
2048 2);
2049
2050 } else {
2051 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
2052 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0,
2053 ARRAY_LENGTH(
2054 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0),
2055 2);
2056 }
2057 } else { //no registry control, default is pll on
2058 INIT_INI_ARRAY(
2059 &ahp->ah_ini_pcie_serdes_low_power,
2060 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0,
2061 ARRAY_LENGTH(
2062 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0),
2063 2);
2064 }
2065 } else {
2066 if (ah->ah_config.ath_hal_pll_pwr_save &
2067 AR_PCIE_PLL_PWRSAVE_CONTROL)
2068 {//registry control
2069 if (ah->ah_config.ath_hal_pll_pwr_save &
2070 AR_PCIE_PLL_PWRSAVE_ON_D0)
2071 {//bit2, out of D3
2072 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
2073 ar9300PciePhy_clkreq_disable_L1_ar9580_1p0,
2074 ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_ar9580_1p0),
2075 2);
2076 } else {
2077 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
2078 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0,
2079 ARRAY_LENGTH(
2080 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0),
2081 2);
2082 }
2083 } else { //no registry control, default is pll on
2084 INIT_INI_ARRAY(
2085 &ahp->ah_ini_pcie_serdes_low_power,
2086 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0,
2087 ARRAY_LENGTH(
2088 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0),
2089 2);
2090 }
2091 }
2092
2093 ah->ah_config.ath_hal_pcie_power_save_enable = 0;
2094
2095 #if 0 /* ATH_WOW */
2096 /* SerDes values during WOW sleep */
2097 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow,
2098 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2);
2099 #endif
2100
2101 /* Fast clock modal settings */
2102 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional,
2103 ar9300Modes_fast_clock_ar9580_1p0,
2104 ARRAY_LENGTH(ar9300Modes_fast_clock_ar9580_1p0), 3);
2105 INIT_INI_ARRAY(&ahp->ah_ini_japan2484,
2106 ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484,
2107 ARRAY_LENGTH(
2108 ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484), 2);
2109
2110 } else {
2111 /*
2112 * Osprey 2.2 - new INI format (pre, core, post arrays per subsystem)
2113 */
2114
2115 /* mac */
2116 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0);
2117 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
2118 ar9300_osprey_2p2_mac_core,
2119 ARRAY_LENGTH(ar9300_osprey_2p2_mac_core), 2);
2120 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST],
2121 ar9300_osprey_2p2_mac_postamble,
2122 ARRAY_LENGTH(ar9300_osprey_2p2_mac_postamble), 5);
2123
2124 /* bb */
2125 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0);
2126 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE],
2127 ar9300_osprey_2p2_baseband_core,
2128 ARRAY_LENGTH(ar9300_osprey_2p2_baseband_core), 2);
2129 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
2130 ar9300_osprey_2p2_baseband_postamble,
2131 ARRAY_LENGTH(ar9300_osprey_2p2_baseband_postamble), 5);
2132
2133 /* radio */
2134 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0);
2135 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE],
2136 ar9300_osprey_2p2_radio_core,
2137 ARRAY_LENGTH(ar9300_osprey_2p2_radio_core), 2);
2138 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST],
2139 ar9300_osprey_2p2_radio_postamble,
2140 ARRAY_LENGTH(ar9300_osprey_2p2_radio_postamble), 5);
2141
2142 /* soc */
2143 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
2144 ar9300_osprey_2p2_soc_preamble,
2145 ARRAY_LENGTH(ar9300_osprey_2p2_soc_preamble), 2);
2146 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0);
2147 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST],
2148 ar9300_osprey_2p2_soc_postamble,
2149 ARRAY_LENGTH(ar9300_osprey_2p2_soc_postamble), 5);
2150
2151 /* rx/tx gain */
2152 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
2153 ar9300_common_rx_gain_table_osprey_2p2,
2154 ARRAY_LENGTH(ar9300_common_rx_gain_table_osprey_2p2), 2);
2155 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
2156 ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2,
2157 ARRAY_LENGTH(ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2), 5);
2158
2159 /* DFS */
2160 INIT_INI_ARRAY(&ahp->ah_ini_dfs,
2161 ar9300_osprey_2p2_baseband_postamble_dfs_channel,
2162 ARRAY_LENGTH(ar9300_osprey_2p2_baseband_postamble_dfs_channel), 3);
2163
2164 /* Load PCIE SERDES settings from INI */
2165
2166 /*D3 Setting */
2167 if (ah->ah_config.ath_hal_pcie_clock_req) {
2168 if (ah->ah_config.ath_hal_pll_pwr_save &
2169 AR_PCIE_PLL_PWRSAVE_CONTROL)
2170 { //registry control
2171 if (ah->ah_config.ath_hal_pll_pwr_save &
2172 AR_PCIE_PLL_PWRSAVE_ON_D3)
2173 { //bit1, in to D3
2174 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
2175 ar9300PciePhy_clkreq_enable_L1_osprey_2p2,
2176 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_osprey_2p2),
2177 2);
2178 } else {
2179 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
2180 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2,
2181 ARRAY_LENGTH(
2182 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2),
2183 2);
2184 }
2185 } else {//no registry control, default is pll on
2186 #ifndef ATH_BUS_PM
2187 INIT_INI_ARRAY(
2188 &ahp->ah_ini_pcie_serdes,
2189 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2,
2190 ARRAY_LENGTH(
2191 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2),
2192 2);
2193 #else
2194 //no registry control, default is pll off
2195 INIT_INI_ARRAY(
2196 &ahp->ah_ini_pcie_serdes,
2197 ar9300PciePhy_clkreq_disable_L1_osprey_2p2,
2198 ARRAY_LENGTH(
2199 ar9300PciePhy_clkreq_disable_L1_osprey_2p2),
2200 2);
2201 #endif
2202
2203 }
2204 } else {
2205 if (ah->ah_config.ath_hal_pll_pwr_save &
2206 AR_PCIE_PLL_PWRSAVE_CONTROL)
2207 { //registry control
2208 if (ah->ah_config.ath_hal_pll_pwr_save &
2209 AR_PCIE_PLL_PWRSAVE_ON_D3)
2210 { //bit1, in to D3
2211 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
2212 ar9300PciePhy_clkreq_disable_L1_osprey_2p2,
2213 ARRAY_LENGTH(
2214 ar9300PciePhy_clkreq_disable_L1_osprey_2p2),
2215 2);
2216 } else {
2217 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
2218 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2,
2219 ARRAY_LENGTH(
2220 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2),
2221 2);
2222 }
2223 } else {
2224 #ifndef ATH_BUS_PM
2225 //no registry control, default is pll on
2226 INIT_INI_ARRAY(
2227 &ahp->ah_ini_pcie_serdes,
2228 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2,
2229 ARRAY_LENGTH(
2230 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2),
2231 2);
2232 #else
2233 //no registry control, default is pll off
2234 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300PciePhy_clkreq_disable_L1_osprey_2p2,
2235 ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2);
2236 #endif
2237 }
2238 }
2239
2240 /*D0 Setting */
2241 if (ah->ah_config.ath_hal_pcie_clock_req) {
2242 if (ah->ah_config.ath_hal_pll_pwr_save &
2243 AR_PCIE_PLL_PWRSAVE_CONTROL)
2244 { //registry control
2245 if (ah->ah_config.ath_hal_pll_pwr_save &
2246 AR_PCIE_PLL_PWRSAVE_ON_D0)
2247 { //bit2, out of D3
2248 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
2249 ar9300PciePhy_clkreq_enable_L1_osprey_2p2,
2250 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_osprey_2p2),
2251 2);
2252
2253 } else {
2254 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
2255 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2,
2256 ARRAY_LENGTH(
2257 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2),
2258 2);
2259 }
2260 } else { //no registry control, default is pll on
2261 INIT_INI_ARRAY(
2262 &ahp->ah_ini_pcie_serdes_low_power,
2263 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2,
2264 ARRAY_LENGTH(
2265 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2),
2266 2);
2267 }
2268 } else {
2269 if (ah->ah_config.ath_hal_pll_pwr_save &
2270 AR_PCIE_PLL_PWRSAVE_CONTROL)
2271 {//registry control
2272 if (ah->ah_config.ath_hal_pll_pwr_save &
2273 AR_PCIE_PLL_PWRSAVE_ON_D0)
2274 {//bit2, out of D3
2275 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
2276 ar9300PciePhy_clkreq_disable_L1_osprey_2p2,
2277 ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_osprey_2p2),
2278 2);
2279 } else {
2280 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
2281 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2,
2282 ARRAY_LENGTH(
2283 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2),
2284 2);
2285 }
2286 } else { //no registry control, default is pll on
2287 INIT_INI_ARRAY(
2288 &ahp->ah_ini_pcie_serdes_low_power,
2289 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2,
2290 ARRAY_LENGTH(
2291 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2),
2292 2);
2293 }
2294 }
2295
2296 ah->ah_config.ath_hal_pcie_power_save_enable = 0;
2297
2298 #ifdef ATH_BUS_PM
2299 /*Use HAL to config PCI powersave by writing into the SerDes Registers */
2300 ah->ah_config.ath_hal_pcie_ser_des_write = 1;
2301 #endif
2302
2303 #if 0 /* ATH_WOW */
2304 /* SerDes values during WOW sleep */
2305 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow,
2306 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2);
2307 #endif
2308
2309 /* Fast clock modal settings */
2310 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional,
2311 ar9300Modes_fast_clock_osprey_2p2,
2312 ARRAY_LENGTH(ar9300Modes_fast_clock_osprey_2p2), 3);
2313 INIT_INI_ARRAY(&ahp->ah_ini_japan2484,
2314 ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484,
2315 ARRAY_LENGTH(
2316 ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484), 2);
2317
2318 }
2319
2320 if(AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah))
2321 {
2322 #define AR_SOC_RST_OTP_INTF 0xB80600B4
2323 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg))
2324
2325 ahp->ah_enterprise_mode = REG_READ(AR_SOC_RST_OTP_INTF);
2326 if (AR_SREV_SCORPION(ah)) {
2327 ahp->ah_enterprise_mode = ahp->ah_enterprise_mode << 12;
2328 }
2329 ath_hal_printf (ah, "Enterprise mode: 0x%08x\n", ahp->ah_enterprise_mode);
2330 #undef REG_READ
2331 #undef AR_SOC_RST_OTP_INTF
2332 } else {
2333 ahp->ah_enterprise_mode = OS_REG_READ(ah, AR_ENT_OTP);
2334 }
2335
2336
2337 if (ahpriv->ah_ispcie) {
2338 ar9300_config_pci_power_save(ah, 0, 0);
2339 } else {
2340 ar9300_disable_pcie_phy(ah);
2341 }
2342 #if 0
2343 ath_hal_printf(ah, "%s: calling ar9300_hw_attach\n", __func__);
2344 #endif
2345 ecode = ar9300_hw_attach(ah);
2346 if (ecode != HAL_OK) {
2347 goto bad;
2348 }
2349
2350 /* set gain table pointers according to values read from the eeprom */
2351 ar9300_tx_gain_table_apply(ah);
2352 ar9300_rx_gain_table_apply(ah);
2353
2354 /*
2355 **
2356 ** Got everything we need now to setup the capabilities.
2357 */
2358
2359 if (!ar9300_fill_capability_info(ah)) {
2360 HALDEBUG(ah, HAL_DEBUG_RESET,
2361 "%s:failed ar9300_fill_capability_info\n", __func__);
2362 ecode = HAL_EEREAD;
2363 goto bad;
2364 }
2365 ecode = ar9300_init_mac_addr(ah);
2366 if (ecode != HAL_OK) {
2367 HALDEBUG(ah, HAL_DEBUG_RESET,
2368 "%s: failed initializing mac address\n", __func__);
2369 goto bad;
2370 }
2371
2372 /*
2373 * Initialize receive buffer size to MAC default
2374 */
2375 ahp->rx_buf_size = HAL_RXBUFSIZE_DEFAULT;
2376
2377 #if ATH_WOW
2378 #if 0
2379 /*
2380 * Needs to be removed once we stop using XB92 XXX
2381 * FIXME: Check with latest boards too - SriniK
2382 */
2383 ar9300_wow_set_gpio_reset_low(ah);
2384 #endif
2385
2386 /*
2387 * Clear the Wow Status.
2388 */
2389 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL),
2390 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL)) |
2391 AR_PMCTRL_WOW_PME_CLR);
2392 OS_REG_WRITE(ah, AR_WOW_PATTERN_REG,
2393 AR_WOW_CLEAR_EVENTS(OS_REG_READ(ah, AR_WOW_PATTERN_REG)));
2394 #endif
2395
2396 /*
2397 * Set the cur_trig_level to a value that works all modes - 11a/b/g or 11n
2398 * with aggregation enabled or disabled.
2399 */
2400 ahp->ah_tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
2401
2402 if (AR_SREV_HORNET(ah)) {
2403 ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_HORNET_2GHZ;
2404 ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ;
2405 ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ;
2406 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ;
2407 ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ;
2408 ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ;
2409 ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA;
2410 } else if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){
2411 ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_JUPITER_2GHZ;
2412 ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ;
2413 ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_2GHZ;
2414 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_JUPITER_5GHZ;
2415 ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ;
2416 ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_5GHZ;
2417 ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA;
2418 } else {
2419 ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_2GHZ;
2420 ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ;
2421 ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ;
2422 if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
2423 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_PEACOCK_5GHZ;
2424 } else {
2425 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ;
2426 }
2427 ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ;
2428 ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ;
2429 ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA;
2430 }
2431
2432
2433
2434
2435 /* init BB Panic Watchdog timeout */
2436 if (AR_SREV_HORNET(ah)) {
2437 ahp->ah_bb_panic_timeout_ms = HAL_BB_PANIC_WD_TMO_HORNET;
2438 } else {
2439 ahp->ah_bb_panic_timeout_ms = HAL_BB_PANIC_WD_TMO;
2440 }
2441
2442
2443 /*
2444 * Determine whether tx IQ calibration HW should be enabled,
2445 * and whether tx IQ calibration should be performed during
2446 * AGC calibration, or separately.
2447 */
2448 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
2449 /*
2450 * Register not initialized yet. This flag will be re-initialized
2451 * after INI loading following each reset.
2452 */
2453 ahp->tx_iq_cal_enable = 1;
2454 /* if tx IQ cal is enabled, do it together with AGC cal */
2455 ahp->tx_iq_cal_during_agc_cal = 1;
2456 } else if (AR_SREV_POSEIDON_OR_LATER(ah) && !AR_SREV_WASP(ah)) {
2457 ahp->tx_iq_cal_enable = 1;
2458 ahp->tx_iq_cal_during_agc_cal = 1;
2459 } else {
2460 /* osprey, hornet, wasp */
2461 ahp->tx_iq_cal_enable = 1;
2462 ahp->tx_iq_cal_during_agc_cal = 0;
2463 }
2464 return ah;
2465
2466 bad:
2467 if (ahp) {
2468 ar9300_detach((struct ath_hal *) ahp);
2469 }
2470 if (status) {
2471 *status = ecode;
2472 }
2473 return AH_NULL;
2474 }
2475
2476 void
ar9300_detach(struct ath_hal * ah)2477 ar9300_detach(struct ath_hal *ah)
2478 {
2479 HALASSERT(ah != AH_NULL);
2480 HALASSERT(ah->ah_magic == AR9300_MAGIC);
2481
2482 /* Make sure that chip is awake before writing to it */
2483 if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) {
2484 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
2485 "%s: failed to wake up chip\n",
2486 __func__);
2487 }
2488
2489 ar9300_hw_detach(ah);
2490 ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
2491
2492 // ath_hal_hdprintf_deregister(ah);
2493
2494 if (AH9300(ah)->ah_cal_mem)
2495 ath_hal_free(AH9300(ah)->ah_cal_mem);
2496 AH9300(ah)->ah_cal_mem = AH_NULL;
2497
2498 ath_hal_free(ah);
2499 }
2500
2501 struct ath_hal_9300 *
ar9300_new_state(u_int16_t devid,HAL_SOFTC sc,HAL_BUS_TAG st,HAL_BUS_HANDLE sh,uint16_t * eepromdata,HAL_OPS_CONFIG * ah_config,HAL_STATUS * status)2502 ar9300_new_state(u_int16_t devid, HAL_SOFTC sc,
2503 HAL_BUS_TAG st, HAL_BUS_HANDLE sh,
2504 uint16_t *eepromdata,
2505 HAL_OPS_CONFIG *ah_config,
2506 HAL_STATUS *status)
2507 {
2508 static const u_int8_t defbssidmask[IEEE80211_ADDR_LEN] =
2509 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
2510 struct ath_hal_9300 *ahp;
2511 struct ath_hal *ah;
2512
2513 /* NB: memory is returned zero'd */
2514 ahp = ath_hal_malloc(sizeof(struct ath_hal_9300));
2515 if (ahp == AH_NULL) {
2516 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE,
2517 "%s: cannot allocate memory for state block\n",
2518 __func__);
2519 *status = HAL_ENOMEM;
2520 return AH_NULL;
2521 }
2522
2523 ah = &ahp->ah_priv.h;
2524 /* set initial values */
2525
2526 /* stub everything first */
2527 ar9300_set_stub_functions(ah);
2528
2529 /* setup the FreeBSD HAL methods */
2530 ar9300_attach_freebsd_ops(ah);
2531
2532 /* These are private to this particular file, so .. */
2533 ah->ah_disablePCIE = ar9300_disable_pcie_phy;
2534 AH_PRIVATE(ah)->ah_getNfAdjust = ar9300_get_nf_adjust;
2535 AH_PRIVATE(ah)->ah_getChipPowerLimits = ar9300_get_chip_power_limits;
2536
2537 #if 0
2538 /* Attach Osprey structure as default hal structure */
2539 OS_MEMCPY(&ahp->ah_priv.priv, &ar9300hal, sizeof(ahp->ah_priv.priv));
2540 #endif
2541
2542 #if 0
2543 AH_PRIVATE(ah)->amem_handle = amem_handle;
2544 AH_PRIVATE(ah)->ah_osdev = osdev;
2545 #endif
2546 ah->ah_sc = sc;
2547 ah->ah_st = st;
2548 ah->ah_sh = sh;
2549 ah->ah_magic = AR9300_MAGIC;
2550 AH_PRIVATE(ah)->ah_devid = devid;
2551
2552 AH_PRIVATE(ah)->ah_flags = 0;
2553
2554 /*
2555 ** Initialize factory defaults in the private space
2556 */
2557 // ath_hal_factory_defaults(AH_PRIVATE(ah), hal_conf_parm);
2558 ar9300_config_defaults_freebsd(ah, ah_config);
2559
2560 /* XXX FreeBSD: cal is always in EEPROM */
2561 #if 0
2562 if (!hal_conf_parm->calInFlash) {
2563 AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM;
2564 }
2565 #endif
2566 AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM;
2567
2568 #if 0
2569 if (ar9300_eep_data_in_flash(ah)) {
2570 ahp->ah_priv.priv.ah_eeprom_read = ar9300_flash_read;
2571 ahp->ah_priv.priv.ah_eeprom_dump = AH_NULL;
2572 } else {
2573 ahp->ah_priv.priv.ah_eeprom_read = ar9300_eeprom_read_word;
2574 }
2575 #endif
2576
2577 /* XXX FreeBSD - for now, just supports EEPROM reading */
2578 ahp->ah_priv.ah_eepromRead = ar9300_eeprom_read_word;
2579
2580 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER;
2581 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */
2582
2583 ahp->ah_atim_window = 0; /* [0..1000] */
2584
2585 ahp->ah_diversity_control =
2586 ah->ah_config.ath_hal_diversity_control;
2587 ahp->ah_antenna_switch_swap =
2588 ah->ah_config.ath_hal_antenna_switch_swap;
2589
2590 /*
2591 * Enable MIC handling.
2592 */
2593 ahp->ah_sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
2594 ahp->ah_enable32k_hz_clock = DONT_USE_32KHZ;/* XXX */
2595 ahp->ah_slot_time = (u_int) -1;
2596 ahp->ah_ack_timeout = (u_int) -1;
2597 OS_MEMCPY(&ahp->ah_bssid_mask, defbssidmask, IEEE80211_ADDR_LEN);
2598
2599 /*
2600 * 11g-specific stuff
2601 */
2602 ahp->ah_g_beacon_rate = 0; /* adhoc beacon fixed rate */
2603
2604 /* SM power mode: Attach time, disable any setting */
2605 ahp->ah_sm_power_mode = HAL_SMPS_DEFAULT;
2606
2607 return ahp;
2608 }
2609
2610 HAL_BOOL
ar9300_chip_test(struct ath_hal * ah)2611 ar9300_chip_test(struct ath_hal *ah)
2612 {
2613 /*u_int32_t reg_addr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };*/
2614 u_int32_t reg_addr[2] = { AR_STA_ID0 };
2615 u_int32_t reg_hold[2];
2616 u_int32_t pattern_data[4] =
2617 { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 };
2618 int i, j;
2619
2620 /* Test PHY & MAC registers */
2621 for (i = 0; i < 1; i++) {
2622 u_int32_t addr = reg_addr[i];
2623 u_int32_t wr_data, rd_data;
2624
2625 reg_hold[i] = OS_REG_READ(ah, addr);
2626 for (j = 0; j < 0x100; j++) {
2627 wr_data = (j << 16) | j;
2628 OS_REG_WRITE(ah, addr, wr_data);
2629 rd_data = OS_REG_READ(ah, addr);
2630 if (rd_data != wr_data) {
2631 HALDEBUG(ah, HAL_DEBUG_REGIO,
2632 "%s: address test failed addr: "
2633 "0x%08x - wr:0x%08x != rd:0x%08x\n",
2634 __func__, addr, wr_data, rd_data);
2635 return AH_FALSE;
2636 }
2637 }
2638 for (j = 0; j < 4; j++) {
2639 wr_data = pattern_data[j];
2640 OS_REG_WRITE(ah, addr, wr_data);
2641 rd_data = OS_REG_READ(ah, addr);
2642 if (wr_data != rd_data) {
2643 HALDEBUG(ah, HAL_DEBUG_REGIO,
2644 "%s: address test failed addr: "
2645 "0x%08x - wr:0x%08x != rd:0x%08x\n",
2646 __func__, addr, wr_data, rd_data);
2647 return AH_FALSE;
2648 }
2649 }
2650 OS_REG_WRITE(ah, reg_addr[i], reg_hold[i]);
2651 }
2652 OS_DELAY(100);
2653 return AH_TRUE;
2654 }
2655
2656 /*
2657 * Store the channel edges for the requested operational mode
2658 */
2659 HAL_BOOL
ar9300_get_channel_edges(struct ath_hal * ah,u_int16_t flags,u_int16_t * low,u_int16_t * high)2660 ar9300_get_channel_edges(struct ath_hal *ah,
2661 u_int16_t flags, u_int16_t *low, u_int16_t *high)
2662 {
2663 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2664 HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps;
2665
2666 if (flags & IEEE80211_CHAN_5GHZ) {
2667 *low = p_cap->halLow5GhzChan;
2668 *high = p_cap->halHigh5GhzChan;
2669 return AH_TRUE;
2670 }
2671 if ((flags & IEEE80211_CHAN_2GHZ)) {
2672 *low = p_cap->halLow2GhzChan;
2673 *high = p_cap->halHigh2GhzChan;
2674
2675 return AH_TRUE;
2676 }
2677 return AH_FALSE;
2678 }
2679
2680 HAL_BOOL
ar9300_regulatory_domain_override(struct ath_hal * ah,u_int16_t regdmn)2681 ar9300_regulatory_domain_override(struct ath_hal *ah, u_int16_t regdmn)
2682 {
2683 AH_PRIVATE(ah)->ah_currentRD = regdmn;
2684 return AH_TRUE;
2685 }
2686
2687 /*
2688 * Fill all software cached or static hardware state information.
2689 * Return failure if capabilities are to come from EEPROM and
2690 * cannot be read.
2691 */
2692 HAL_BOOL
ar9300_fill_capability_info(struct ath_hal * ah)2693 ar9300_fill_capability_info(struct ath_hal *ah)
2694 {
2695 #define AR_KEYTABLE_SIZE 128
2696 struct ath_hal_9300 *ahp = AH9300(ah);
2697 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2698 HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps;
2699 u_int16_t cap_field = 0, eeval;
2700
2701 ahpriv->ah_devType = (u_int16_t)ar9300_eeprom_get(ahp, EEP_DEV_TYPE);
2702 eeval = ar9300_eeprom_get(ahp, EEP_REG_0);
2703
2704 /* XXX record serial number */
2705 AH_PRIVATE(ah)->ah_currentRD = eeval;
2706
2707 /* Always enable fast clock; leave it up to EEPROM and channel */
2708 p_cap->halSupportsFastClock5GHz = AH_TRUE;
2709
2710 p_cap->halIntrMitigation = AH_TRUE;
2711 eeval = ar9300_eeprom_get(ahp, EEP_REG_1);
2712 AH_PRIVATE(ah)->ah_currentRDext = eeval | AR9300_RDEXT_DEFAULT;
2713
2714 /* Read the capability EEPROM location */
2715 cap_field = ar9300_eeprom_get(ahp, EEP_OP_CAP);
2716
2717 /* Construct wireless mode from EEPROM */
2718 p_cap->halWirelessModes = 0;
2719 eeval = ar9300_eeprom_get(ahp, EEP_OP_MODE);
2720
2721 /*
2722 * XXX FreeBSD specific: for now, set ath_hal_ht_enable to 1,
2723 * or we won't have 11n support.
2724 */
2725 ah->ah_config.ath_hal_ht_enable = 1;
2726
2727 if (eeval & AR9300_OPFLAGS_11A) {
2728 p_cap->halWirelessModes |= HAL_MODE_11A |
2729 ((!ah->ah_config.ath_hal_ht_enable ||
2730 (eeval & AR9300_OPFLAGS_N_5G_HT20)) ? 0 :
2731 (HAL_MODE_11NA_HT20 | ((eeval & AR9300_OPFLAGS_N_5G_HT40) ? 0 :
2732 (HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS))));
2733 }
2734 if (eeval & AR9300_OPFLAGS_11G) {
2735 p_cap->halWirelessModes |= HAL_MODE_11B | HAL_MODE_11G |
2736 ((!ah->ah_config.ath_hal_ht_enable ||
2737 (eeval & AR9300_OPFLAGS_N_2G_HT20)) ? 0 :
2738 (HAL_MODE_11NG_HT20 | ((eeval & AR9300_OPFLAGS_N_2G_HT40) ? 0 :
2739 (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS))));
2740 }
2741
2742 /* Get chainamsks from eeprom */
2743 p_cap->halTxChainMask = ar9300_eeprom_get(ahp, EEP_TX_MASK);
2744 p_cap->halRxChainMask = ar9300_eeprom_get(ahp, EEP_RX_MASK);
2745
2746
2747
2748 #define owl_get_ntxchains(_txchainmask) \
2749 (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
2750
2751 /* FreeBSD: Update number of TX/RX streams */
2752 p_cap->halTxStreams = owl_get_ntxchains(p_cap->halTxChainMask);
2753 p_cap->halRxStreams = owl_get_ntxchains(p_cap->halRxChainMask);
2754
2755
2756 /*
2757 * This being a newer chip supports TKIP non-splitmic mode.
2758 *
2759 */
2760 ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2761 p_cap->halTkipMicTxRxKeySupport = AH_TRUE;
2762
2763 p_cap->halLow2GhzChan = 2312;
2764 p_cap->halHigh2GhzChan = 2732;
2765
2766 p_cap->halLow5GhzChan = 4920;
2767 p_cap->halHigh5GhzChan = 6100;
2768
2769 p_cap->halCipherCkipSupport = AH_FALSE;
2770 p_cap->halCipherTkipSupport = AH_TRUE;
2771 p_cap->halCipherAesCcmSupport = AH_TRUE;
2772
2773 p_cap->halMicCkipSupport = AH_FALSE;
2774 p_cap->halMicTkipSupport = AH_TRUE;
2775 p_cap->halMicAesCcmSupport = AH_TRUE;
2776
2777 p_cap->halChanSpreadSupport = AH_TRUE;
2778 p_cap->halSleepAfterBeaconBroken = AH_TRUE;
2779
2780 p_cap->halBurstSupport = AH_TRUE;
2781 p_cap->halChapTuningSupport = AH_TRUE;
2782 p_cap->halTurboPrimeSupport = AH_TRUE;
2783 p_cap->halFastFramesSupport = AH_TRUE;
2784
2785 p_cap->halTurboGSupport = p_cap->halWirelessModes & HAL_MODE_108G;
2786
2787 // p_cap->hal_xr_support = AH_FALSE;
2788
2789 p_cap->halHTSupport =
2790 ah->ah_config.ath_hal_ht_enable ? AH_TRUE : AH_FALSE;
2791
2792 p_cap->halGTTSupport = AH_TRUE;
2793 p_cap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */
2794 p_cap->halNumMRRetries = 4; /* Hardware supports 4 MRR */
2795 p_cap->halHTSGI20Support = AH_TRUE;
2796 p_cap->halVEOLSupport = AH_TRUE;
2797 p_cap->halBssIdMaskSupport = AH_TRUE;
2798 /* Bug 26802, fixed in later revs? */
2799 p_cap->halMcastKeySrchSupport = AH_TRUE;
2800 p_cap->halTsfAddSupport = AH_TRUE;
2801
2802 if (cap_field & AR_EEPROM_EEPCAP_MAXQCU) {
2803 p_cap->halTotalQueues = MS(cap_field, AR_EEPROM_EEPCAP_MAXQCU);
2804 } else {
2805 p_cap->halTotalQueues = HAL_NUM_TX_QUEUES;
2806 }
2807
2808 if (cap_field & AR_EEPROM_EEPCAP_KC_ENTRIES) {
2809 p_cap->halKeyCacheSize =
2810 1 << MS(cap_field, AR_EEPROM_EEPCAP_KC_ENTRIES);
2811 } else {
2812 p_cap->halKeyCacheSize = AR_KEYTABLE_SIZE;
2813 }
2814 p_cap->halFastCCSupport = AH_TRUE;
2815 // p_cap->hal_num_mr_retries = 4;
2816 // ahp->hal_tx_trig_level_max = MAX_TX_FIFO_THRESHOLD;
2817
2818 p_cap->halNumGpioPins = AR9382_MAX_GPIO_PIN_NUM;
2819
2820 #if 0
2821 /* XXX Verify support in Osprey */
2822 if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
2823 p_cap->halWowSupport = AH_TRUE;
2824 p_cap->hal_wow_match_pattern_exact = AH_TRUE;
2825 if (AR_SREV_MERLIN(ah)) {
2826 p_cap->hal_wow_pattern_match_dword = AH_TRUE;
2827 }
2828 } else {
2829 p_cap->halWowSupport = AH_FALSE;
2830 p_cap->hal_wow_match_pattern_exact = AH_FALSE;
2831 }
2832 #endif
2833 p_cap->halWowSupport = AH_TRUE;
2834 p_cap->halWowMatchPatternExact = AH_TRUE;
2835 if (AR_SREV_POSEIDON(ah)) {
2836 p_cap->halWowMatchPatternExact = AH_TRUE;
2837 }
2838
2839 p_cap->halCSTSupport = AH_TRUE;
2840
2841 p_cap->halRifsRxSupport = AH_TRUE;
2842 p_cap->halRifsTxSupport = AH_TRUE;
2843
2844 #define IEEE80211_AMPDU_LIMIT_MAX (65536)
2845 p_cap->halRtsAggrLimit = IEEE80211_AMPDU_LIMIT_MAX;
2846 #undef IEEE80211_AMPDU_LIMIT_MAX
2847
2848 p_cap->halMfpSupport = ah->ah_config.ath_hal_mfp_support;
2849
2850 p_cap->halForcePpmSupport = AH_TRUE;
2851 p_cap->halHwBeaconProcSupport = AH_TRUE;
2852
2853 /* ar9300 - has the HW UAPSD trigger support,
2854 * but it has the following limitations
2855 * The power state change from the following
2856 * frames are not put in High priority queue.
2857 * i) Mgmt frames
2858 * ii) NoN QoS frames
2859 * iii) QoS frames form the access categories for which
2860 * UAPSD is not enabled.
2861 * so we can not enable this feature currently.
2862 * could be enabled, if these limitations are fixed
2863 * in later versions of ar9300 chips
2864 */
2865 p_cap->halHasUapsdSupport = AH_FALSE;
2866
2867 /* Number of buffers that can be help in a single TxD */
2868 p_cap->halNumTxMaps = 4;
2869
2870 p_cap->halTxDescLen = sizeof(struct ar9300_txc);
2871 p_cap->halTxStatusLen = sizeof(struct ar9300_txs);
2872 p_cap->halRxStatusLen = sizeof(struct ar9300_rxs);
2873
2874 p_cap->halRxHpFifoDepth = HAL_HP_RXFIFO_DEPTH;
2875 p_cap->halRxLpFifoDepth = HAL_LP_RXFIFO_DEPTH;
2876
2877 /* Enable extension channel DFS support */
2878 p_cap->halUseCombinedRadarRssi = AH_TRUE;
2879 p_cap->halExtChanDfsSupport = AH_TRUE;
2880 #if ATH_SUPPORT_SPECTRAL
2881 p_cap->halSpectralScanSupport = AH_TRUE;
2882 #endif
2883 ahpriv->ah_rfsilent = ar9300_eeprom_get(ahp, EEP_RF_SILENT);
2884 if (ahpriv->ah_rfsilent & EEP_RFSILENT_ENABLED) {
2885 ahp->ah_gpio_select = MS(ahpriv->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
2886 ahp->ah_polarity = MS(ahpriv->ah_rfsilent, EEP_RFSILENT_POLARITY);
2887
2888 ath_hal_enable_rfkill(ah, AH_TRUE);
2889 p_cap->halRfSilentSupport = AH_TRUE;
2890 }
2891
2892 /* XXX */
2893 p_cap->halWpsPushButtonSupport = AH_FALSE;
2894
2895 #ifdef ATH_BT_COEX
2896 p_cap->halBtCoexSupport = AH_TRUE;
2897 p_cap->halBtCoexApsmWar = AH_FALSE;
2898 #endif
2899
2900 p_cap->halGenTimerSupport = AH_TRUE;
2901 ahp->ah_avail_gen_timers = ~((1 << AR_FIRST_NDP_TIMER) - 1);
2902 ahp->ah_avail_gen_timers &= (1 << AR_NUM_GEN_TIMERS) - 1;
2903 /*
2904 * According to Kyungwan, generic timer 0 and 8 are special
2905 * timers. Remove timer 8 from the available gen timer list.
2906 * Jupiter testing shows timer won't trigger with timer 8.
2907 */
2908 ahp->ah_avail_gen_timers &= ~(1 << AR_GEN_TIMER_RESERVED);
2909
2910 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
2911 #if ATH_SUPPORT_MCI
2912 if (ah->ah_config.ath_hal_mci_config & ATH_MCI_CONFIG_DISABLE_MCI)
2913 {
2914 p_cap->halMciSupport = AH_FALSE;
2915 }
2916 else
2917 #endif
2918 {
2919 p_cap->halMciSupport = (ahp->ah_enterprise_mode &
2920 AR_ENT_OTP_49GHZ_DISABLE) ? AH_FALSE: AH_TRUE;
2921 }
2922 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE,
2923 "%s: (MCI) MCI support = %d\n",
2924 __func__, p_cap->halMciSupport);
2925 }
2926 else {
2927 p_cap->halMciSupport = AH_FALSE;
2928 }
2929
2930 /* XXX TODO: jupiter 2.1? */
2931 if (AR_SREV_JUPITER_20(ah)) {
2932 p_cap->halRadioRetentionSupport = AH_TRUE;
2933 } else {
2934 p_cap->halRadioRetentionSupport = AH_FALSE;
2935 }
2936
2937 p_cap->halAutoSleepSupport = AH_TRUE;
2938
2939 p_cap->halMbssidAggrSupport = AH_TRUE;
2940 // p_cap->hal_proxy_sta_support = AH_TRUE;
2941
2942 /* XXX Mark it true after it is verfied as fixed */
2943 p_cap->hal4kbSplitTransSupport = AH_FALSE;
2944
2945 /* Read regulatory domain flag */
2946 if (AH_PRIVATE(ah)->ah_currentRDext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2947 /*
2948 * If REG_EXT_JAPAN_MIDBAND is set, turn on U1 EVEN, U2, and MIDBAND.
2949 */
2950 p_cap->halRegCap =
2951 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2952 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2953 AR_EEPROM_EEREGCAP_EN_KK_U2 |
2954 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2955 } else {
2956 p_cap->halRegCap =
2957 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2958 }
2959
2960 /* For AR9300 and above, midband channels are always supported */
2961 p_cap->halRegCap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2962
2963 p_cap->halNumAntCfg5GHz =
2964 ar9300_eeprom_get_num_ant_config(ahp, HAL_FREQ_BAND_5GHZ);
2965 p_cap->halNumAntCfg2GHz =
2966 ar9300_eeprom_get_num_ant_config(ahp, HAL_FREQ_BAND_2GHZ);
2967
2968 /* STBC supported */
2969 p_cap->halRxStbcSupport = 1; /* number of streams for STBC recieve. */
2970 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) {
2971 p_cap->halTxStbcSupport = 0;
2972 } else {
2973 p_cap->halTxStbcSupport = 1;
2974 }
2975
2976 p_cap->halEnhancedDmaSupport = AH_TRUE;
2977 p_cap->halEnhancedDfsSupport = AH_TRUE;
2978
2979 /*
2980 * EV61133 (missing interrupts due to AR_ISR_RAC).
2981 * Fixed in Osprey 2.0.
2982 */
2983 p_cap->halIsrRacSupport = AH_TRUE;
2984
2985 /* XXX FreeBSD won't support TKIP and WEP aggregation */
2986 #if 0
2987 p_cap->hal_wep_tkip_aggr_support = AH_TRUE;
2988 p_cap->hal_wep_tkip_aggr_num_tx_delim = 10; /* TBD */
2989 p_cap->hal_wep_tkip_aggr_num_rx_delim = 10; /* TBD */
2990 p_cap->hal_wep_tkip_max_ht_rate = 15; /* TBD */
2991 #endif
2992
2993 /*
2994 * XXX FreeBSD won't need these; but eventually add them
2995 * and add the WARs - AGGR extra delim WAR is useful to know
2996 * about.
2997 */
2998 #if 0
2999 p_cap->hal_cfend_fix_support = AH_FALSE;
3000 p_cap->hal_aggr_extra_delim_war = AH_FALSE;
3001 #endif
3002 p_cap->halTxTstampPrecision = 32;
3003 p_cap->halRxTstampPrecision = 32;
3004 p_cap->halRxTxAbortSupport = AH_TRUE;
3005 p_cap->hal_ani_poll_interval = AR9300_ANI_POLLINTERVAL;
3006 p_cap->hal_channel_switch_time_usec = AR9300_CHANNEL_SWITCH_TIME_USEC;
3007
3008 /* Transmit Beamforming supported, fill capabilities */
3009 p_cap->halPaprdEnabled = ar9300_eeprom_get(ahp, EEP_PAPRD_ENABLED);
3010 p_cap->halChanHalfRate =
3011 !(ahp->ah_enterprise_mode & AR_ENT_OTP_10MHZ_DISABLE);
3012 p_cap->halChanQuarterRate =
3013 !(ahp->ah_enterprise_mode & AR_ENT_OTP_5MHZ_DISABLE);
3014
3015 if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){
3016 /* There is no AR_ENT_OTP_49GHZ_DISABLE feature in Jupiter, now the bit is used to disable BT. */
3017 p_cap->hal49GhzSupport = 1;
3018 } else {
3019 p_cap->hal49GhzSupport = !(ahp->ah_enterprise_mode & AR_ENT_OTP_49GHZ_DISABLE);
3020 }
3021
3022 if (AR_SREV_POSEIDON(ah) || AR_SREV_HORNET(ah) || AR_SREV_APHRODITE(ah)) {
3023 /* LDPC supported */
3024 /* Poseidon doesn't support LDPC, or it will cause receiver CRC Error */
3025 p_cap->halLDPCSupport = AH_FALSE;
3026 /* PCI_E LCR offset */
3027 if (AR_SREV_POSEIDON(ah)) {
3028 p_cap->hal_pcie_lcr_offset = 0x80; /*for Poseidon*/
3029 }
3030 /*WAR method for APSM L0s with Poseidon 1.0*/
3031 if (AR_SREV_POSEIDON_10(ah)) {
3032 p_cap->hal_pcie_lcr_extsync_en = AH_TRUE;
3033 }
3034 } else {
3035 p_cap->halLDPCSupport = AH_TRUE;
3036 }
3037
3038 /* XXX is this a flag, or a chainmask number? */
3039 p_cap->halApmEnable = !! ar9300_eeprom_get(ahp, EEP_CHAIN_MASK_REDUCE);
3040 #if ATH_ANT_DIV_COMB
3041 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) {
3042 if (ahp->ah_diversity_control == HAL_ANT_VARIABLE) {
3043 u_int8_t ant_div_control1 =
3044 ar9300_eeprom_get(ahp, EEP_ANTDIV_control);
3045 /* if enable_lnadiv is 0x1 and enable_fast_div is 0x1,
3046 * we enable the diversity-combining algorithm.
3047 */
3048 if ((ant_div_control1 >> 0x6) == 0x3) {
3049 p_cap->halAntDivCombSupport = AH_TRUE;
3050 }
3051 p_cap->halAntDivCombSupportOrg = p_cap->halAntDivCombSupport;
3052 }
3053 }
3054 #endif /* ATH_ANT_DIV_COMB */
3055
3056 /*
3057 * FreeBSD: enable LNA mixing if the chip is Hornet or Poseidon.
3058 */
3059 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3060 p_cap->halRxUsingLnaMixing = AH_TRUE;
3061 }
3062
3063 /*
3064 * AR5416 and later NICs support MYBEACON filtering.
3065 */
3066 p_cap->halRxDoMyBeacon = AH_TRUE;
3067
3068 #if ATH_WOW_OFFLOAD
3069 if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) {
3070 p_cap->hal_wow_gtk_offload_support = AH_TRUE;
3071 p_cap->hal_wow_arp_offload_support = AH_TRUE;
3072 p_cap->hal_wow_ns_offload_support = AH_TRUE;
3073 p_cap->hal_wow_4way_hs_wakeup_support = AH_TRUE;
3074 p_cap->hal_wow_acer_magic_support = AH_TRUE;
3075 p_cap->hal_wow_acer_swka_support = AH_TRUE;
3076 } else {
3077 p_cap->hal_wow_gtk_offload_support = AH_FALSE;
3078 p_cap->hal_wow_arp_offload_support = AH_FALSE;
3079 p_cap->hal_wow_ns_offload_support = AH_FALSE;
3080 p_cap->hal_wow_4way_hs_wakeup_support = AH_FALSE;
3081 p_cap->hal_wow_acer_magic_support = AH_FALSE;
3082 p_cap->hal_wow_acer_swka_support = AH_FALSE;
3083 }
3084 #endif /* ATH_WOW_OFFLOAD */
3085
3086
3087 return AH_TRUE;
3088 #undef AR_KEYTABLE_SIZE
3089 }
3090
3091 #if 0
3092 static HAL_BOOL
3093 ar9300_get_chip_power_limits(struct ath_hal *ah, HAL_CHANNEL *chans,
3094 u_int32_t nchans)
3095 {
3096 struct ath_hal_9300 *ahp = AH9300(ah);
3097
3098 return ahp->ah_rf_hal.get_chip_power_lim(ah, chans, nchans);
3099 }
3100 #endif
3101 /* XXX FreeBSD */
3102
3103 static HAL_BOOL
ar9300_get_chip_power_limits(struct ath_hal * ah,struct ieee80211_channel * chan)3104 ar9300_get_chip_power_limits(struct ath_hal *ah,
3105 struct ieee80211_channel *chan)
3106 {
3107
3108 chan->ic_maxpower = AR9300_MAX_RATE_POWER;
3109 chan->ic_minpower = 0;
3110
3111 return AH_TRUE;
3112 }
3113
3114 /*
3115 * Disable PLL when in L0s as well as receiver clock when in L1.
3116 * This power saving option must be enabled through the Serdes.
3117 *
3118 * Programming the Serdes must go through the same 288 bit serial shift
3119 * register as the other analog registers. Hence the 9 writes.
3120 *
3121 * XXX Clean up the magic numbers.
3122 */
3123 void
ar9300_config_pci_power_save(struct ath_hal * ah,int restore,int power_off)3124 ar9300_config_pci_power_save(struct ath_hal *ah, int restore, int power_off)
3125 {
3126 struct ath_hal_9300 *ahp = AH9300(ah);
3127 int i;
3128
3129 if (AH_PRIVATE(ah)->ah_ispcie != AH_TRUE) {
3130 return;
3131 }
3132
3133 /*
3134 * Increase L1 Entry Latency. Some WB222 boards don't have
3135 * this change in eeprom/OTP.
3136 */
3137 if (AR_SREV_JUPITER(ah)) {
3138 u_int32_t val = ah->ah_config.ath_hal_war70c;
3139 if ((val & 0xff000000) == 0x17000000) {
3140 val &= 0x00ffffff;
3141 val |= 0x27000000;
3142 OS_REG_WRITE(ah, 0x570c, val);
3143 }
3144 }
3145
3146 /* Do not touch SERDES registers */
3147 if (ah->ah_config.ath_hal_pcie_power_save_enable == 2) {
3148 return;
3149 }
3150
3151 /* Nothing to do on restore for 11N */
3152 if (!restore) {
3153 /* set bit 19 to allow forcing of pcie core into L1 state */
3154 OS_REG_SET_BIT(ah,
3155 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), AR_PCIE_PM_CTRL_ENA);
3156
3157 /*
3158 * Set PCIE workaround config only if requested, else use the reset
3159 * value of this register.
3160 */
3161 if (ah->ah_config.ath_hal_pcie_waen) {
3162 OS_REG_WRITE(ah,
3163 AR_HOSTIF_REG(ah, AR_WA),
3164 ah->ah_config.ath_hal_pcie_waen);
3165 } else {
3166 /* Set Bits 17 and 14 in the AR_WA register. */
3167 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val);
3168 }
3169 }
3170
3171 /* Configure PCIE after Ini init. SERDES values now come from ini file */
3172 if (ah->ah_config.ath_hal_pcie_ser_des_write) {
3173 if (power_off) {
3174 for (i = 0; i < ahp->ah_ini_pcie_serdes.ia_rows; i++) {
3175 OS_REG_WRITE(ah,
3176 INI_RA(&ahp->ah_ini_pcie_serdes, i, 0),
3177 INI_RA(&ahp->ah_ini_pcie_serdes, i, 1));
3178 }
3179 } else {
3180 for (i = 0; i < ahp->ah_ini_pcie_serdes_low_power.ia_rows; i++) {
3181 OS_REG_WRITE(ah,
3182 INI_RA(&ahp->ah_ini_pcie_serdes_low_power, i, 0),
3183 INI_RA(&ahp->ah_ini_pcie_serdes_low_power, i, 1));
3184 }
3185 }
3186 }
3187
3188 }
3189
3190 /*
3191 * Recipe from charles to turn off PCIe PHY in PCI mode for power savings
3192 */
3193 void
ar9300_disable_pcie_phy(struct ath_hal * ah)3194 ar9300_disable_pcie_phy(struct ath_hal *ah)
3195 {
3196 /* Osprey does not support PCI mode */
3197 }
3198
3199 static inline HAL_STATUS
ar9300_init_mac_addr(struct ath_hal * ah)3200 ar9300_init_mac_addr(struct ath_hal *ah)
3201 {
3202 u_int32_t sum;
3203 int i;
3204 u_int16_t eeval;
3205 struct ath_hal_9300 *ahp = AH9300(ah);
3206 u_int32_t EEP_MAC [] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
3207
3208 sum = 0;
3209 for (i = 0; i < 3; i++) {
3210 eeval = ar9300_eeprom_get(ahp, EEP_MAC[i]);
3211 sum += eeval;
3212 ahp->ah_macaddr[2*i] = eeval >> 8;
3213 ahp->ah_macaddr[2*i + 1] = eeval & 0xff;
3214 }
3215 if (sum == 0 || sum == 0xffff*3) {
3216 HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: mac address read failed: %s\n",
3217 __func__, ath_hal_ether_sprintf(ahp->ah_macaddr));
3218 return HAL_EEBADMAC;
3219 }
3220
3221 return HAL_OK;
3222 }
3223
3224 /*
3225 * Code for the "real" chip i.e. non-emulation. Review and revisit
3226 * when actual hardware is at hand.
3227 */
3228 static inline HAL_STATUS
ar9300_hw_attach(struct ath_hal * ah)3229 ar9300_hw_attach(struct ath_hal *ah)
3230 {
3231 HAL_STATUS ecode;
3232
3233 if (!ar9300_chip_test(ah)) {
3234 HALDEBUG(ah, HAL_DEBUG_REGIO,
3235 "%s: hardware self-test failed\n", __func__);
3236 return HAL_ESELFTEST;
3237 }
3238
3239 #if 0
3240 ath_hal_printf(ah, "%s: calling ar9300_eeprom_attach\n", __func__);
3241 #endif
3242 ecode = ar9300_eeprom_attach(ah);
3243 ath_hal_printf(ah, "%s: ar9300_eeprom_attach returned %d\n", __func__, ecode);
3244 if (ecode != HAL_OK) {
3245 return ecode;
3246 }
3247 if (!ar9300_rf_attach(ah, &ecode)) {
3248 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: RF setup failed, status %u\n",
3249 __func__, ecode);
3250 }
3251
3252 if (ecode != HAL_OK) {
3253 return ecode;
3254 }
3255 ar9300_ani_attach(ah);
3256
3257 return HAL_OK;
3258 }
3259
3260 static inline void
ar9300_hw_detach(struct ath_hal * ah)3261 ar9300_hw_detach(struct ath_hal *ah)
3262 {
3263 /* XXX EEPROM allocated state */
3264 ar9300_ani_detach(ah);
3265 }
3266
3267 static int16_t
ar9300_get_nf_adjust(struct ath_hal * ah,const HAL_CHANNEL_INTERNAL * c)3268 ar9300_get_nf_adjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
3269 {
3270 return 0;
3271 }
3272
3273 void
ar9300_set_immunity(struct ath_hal * ah,HAL_BOOL enable)3274 ar9300_set_immunity(struct ath_hal *ah, HAL_BOOL enable)
3275 {
3276 struct ath_hal_9300 *ahp = AH9300(ah);
3277 u_int32_t m1_thresh_low = enable ? 127 : ahp->ah_immunity_vals[0],
3278 m2_thresh_low = enable ? 127 : ahp->ah_immunity_vals[1],
3279 m1_thresh = enable ? 127 : ahp->ah_immunity_vals[2],
3280 m2_thresh = enable ? 127 : ahp->ah_immunity_vals[3],
3281 m2_count_thr = enable ? 31 : ahp->ah_immunity_vals[4],
3282 m2_count_thr_low = enable ? 63 : ahp->ah_immunity_vals[5];
3283
3284 if (ahp->ah_immunity_on == enable) {
3285 return;
3286 }
3287
3288 ahp->ah_immunity_on = enable;
3289
3290 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
3291 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1_thresh_low);
3292 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
3293 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2_thresh_low);
3294 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
3295 AR_PHY_SFCORR_M1_THRESH, m1_thresh);
3296 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
3297 AR_PHY_SFCORR_M2_THRESH, m2_thresh);
3298 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
3299 AR_PHY_SFCORR_M2COUNT_THR, m2_count_thr);
3300 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
3301 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2_count_thr_low);
3302
3303 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
3304 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1_thresh_low);
3305 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
3306 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2_thresh_low);
3307 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
3308 AR_PHY_SFCORR_EXT_M1_THRESH, m1_thresh);
3309 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
3310 AR_PHY_SFCORR_EXT_M2_THRESH, m2_thresh);
3311
3312 if (!enable) {
3313 OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
3314 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
3315 } else {
3316 OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
3317 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
3318 }
3319 }
3320
3321 /* XXX FreeBSD: I'm not sure how to implement this.. */
3322 #if 0
3323 int
3324 ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp,
3325 HAL_CAL_QUERY query)
3326 {
3327 #define AR9300_IS_CHAIN_RX_IQCAL_INVALID(_ah, _reg) \
3328 ((OS_REG_READ((_ah), _reg) & 0x3fff) == 0)
3329 #define AR9300_IS_RX_IQCAL_DISABLED(_ah) \
3330 (!(OS_REG_READ((_ah), AR_PHY_RX_IQCAL_CORR_B0) & \
3331 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE))
3332 /* Avoid comilation warnings. Variables are not used when EMULATION. */
3333 struct ath_hal_9300 *ahp = AH9300(ah);
3334 u_int8_t rxchainmask = ahp->ah_rx_chainmask, i;
3335 int rx_iqcal_invalid = 0, num_chains = 0;
3336 static const u_int32_t offset_array[3] = {
3337 AR_PHY_RX_IQCAL_CORR_B0,
3338 AR_PHY_RX_IQCAL_CORR_B1,
3339 AR_PHY_RX_IQCAL_CORR_B2};
3340
3341 *timerp = ar9300_cals;
3342
3343 switch (query) {
3344 case HAL_QUERY_CALS:
3345 return AR9300_NUM_CAL_TYPES;
3346 case HAL_QUERY_RERUN_CALS:
3347 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
3348 if (rxchainmask & (1 << i)) {
3349 num_chains++;
3350 }
3351 }
3352 for (i = 0; i < num_chains; i++) {
3353 if (AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) {
3354 HALASSERT(num_chains == 0x1);
3355 }
3356 if (AR9300_IS_CHAIN_RX_IQCAL_INVALID(ah, offset_array[i])) {
3357 rx_iqcal_invalid = 1;
3358 }
3359 }
3360 if (AR9300_IS_RX_IQCAL_DISABLED(ah)) {
3361 rx_iqcal_invalid = 1;
3362 }
3363
3364 return rx_iqcal_invalid;
3365 default:
3366 HALASSERT(0);
3367 }
3368 return 0;
3369 }
3370 #endif
3371
3372 #if ATH_TRAFFIC_FAST_RECOVER
3373 #define PLL3 0x16188
3374 #define PLL3_DO_MEAS_MASK 0x40000000
3375 #define PLL4 0x1618c
3376 #define PLL4_MEAS_DONE 0x8
3377 #define SQSUM_DVC_MASK 0x007ffff8
3378 unsigned long
ar9300_get_pll3_sqsum_dvc(struct ath_hal * ah)3379 ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah)
3380 {
3381 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
3382 OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) & ~(PLL3_DO_MEAS_MASK)));
3383 OS_DELAY(100);
3384 OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) | PLL3_DO_MEAS_MASK));
3385
3386 while ( (OS_REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
3387 OS_DELAY(100);
3388 }
3389
3390 return (( OS_REG_READ(ah, PLL3) & SQSUM_DVC_MASK ) >> 3);
3391 } else {
3392 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
3393 "%s: unable to get pll3_sqsum_dvc\n",
3394 __func__);
3395 return 0;
3396 }
3397 }
3398 #endif
3399
3400
3401 #define RX_GAIN_TABLE_LENGTH 128
3402 // this will be called if rfGainCAP is enabled and rfGainCAP setting is changed,
3403 // or rxGainTable setting is changed
ar9300_rf_gain_cap_apply(struct ath_hal * ah,int is_2GHz)3404 HAL_BOOL ar9300_rf_gain_cap_apply(struct ath_hal *ah, int is_2GHz)
3405 {
3406 int i, done = 0, i_rx_gain = 32;
3407 u_int32_t rf_gain_cap;
3408 u_int32_t rx_gain_value, a_Byte, rx_gain_value_caped;
3409 static u_int32_t rx_gain_table[RX_GAIN_TABLE_LENGTH * 2][2];
3410 ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom;
3411 struct ath_hal_9300 *ahp = AH9300(ah);
3412
3413 if ( !((eep->base_eep_header.misc_configuration & 0x80) >> 7) )
3414 return AH_FALSE;
3415
3416 if (is_2GHz)
3417 {
3418 rf_gain_cap = (u_int32_t) eep->modal_header_2g.rf_gain_cap;
3419 }
3420 else
3421 {
3422 rf_gain_cap = (u_int32_t) eep->modal_header_5g.rf_gain_cap;
3423 }
3424
3425 if (rf_gain_cap == 0)
3426 return AH_FALSE;
3427
3428 for (i = 0; i< RX_GAIN_TABLE_LENGTH * 2; i++)
3429 {
3430 if (AR_SREV_AR9580(ah))
3431 {
3432 // BB_rx_ocgain2
3433 i_rx_gain = 128 + 32;
3434 switch (ar9300_rx_gain_index_get(ah))
3435 {
3436 case 0:
3437 rx_gain_table[i][0] =
3438 ar9300_common_rx_gain_table_ar9580_1p0[i][0];
3439 rx_gain_table[i][1] =
3440 ar9300_common_rx_gain_table_ar9580_1p0[i][1];
3441 break;
3442 case 1:
3443 rx_gain_table[i][0] =
3444 ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[i][0];
3445 rx_gain_table[i][1] =
3446 ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[i][1];
3447 break;
3448 }
3449 }
3450 else if (AR_SREV_OSPREY_22(ah))
3451 {
3452 i_rx_gain = 128 + 32;
3453 switch (ar9300_rx_gain_index_get(ah))
3454 {
3455 case 0:
3456 rx_gain_table[i][0] = ar9300_common_rx_gain_table_osprey_2p2[i][0];
3457 rx_gain_table[i][1] = ar9300_common_rx_gain_table_osprey_2p2[i][1];
3458 break;
3459 case 1:
3460 rx_gain_table[i][0] =
3461 ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[i][0];
3462 rx_gain_table[i][1] =
3463 ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[i][1];
3464 break;
3465 }
3466 }
3467 else
3468 {
3469 return AH_FALSE;
3470 }
3471 }
3472
3473 while (1)
3474 {
3475 rx_gain_value = rx_gain_table[i_rx_gain][1];
3476 rx_gain_value_caped = rx_gain_value;
3477 a_Byte = rx_gain_value & (0x000000FF);
3478 if (a_Byte>rf_gain_cap)
3479 {
3480 rx_gain_value_caped = (rx_gain_value_caped &
3481 (0xFFFFFF00)) + rf_gain_cap;
3482 }
3483 a_Byte = rx_gain_value & (0x0000FF00);
3484 if ( a_Byte > ( rf_gain_cap << 8 ) )
3485 {
3486 rx_gain_value_caped = (rx_gain_value_caped &
3487 (0xFFFF00FF)) + (rf_gain_cap<<8);
3488 }
3489 a_Byte = rx_gain_value & (0x00FF0000);
3490 if ( a_Byte > ( rf_gain_cap << 16 ) )
3491 {
3492 rx_gain_value_caped = (rx_gain_value_caped &
3493 (0xFF00FFFF)) + (rf_gain_cap<<16);
3494 }
3495 a_Byte = rx_gain_value & (0xFF000000);
3496 if ( a_Byte > ( rf_gain_cap << 24 ) )
3497 {
3498 rx_gain_value_caped = (rx_gain_value_caped &
3499 (0x00FFFFFF)) + (rf_gain_cap<<24);
3500 }
3501 else
3502 {
3503 done = 1;
3504 }
3505 HALDEBUG(ah, HAL_DEBUG_RESET,
3506 "%s: rx_gain_address: %x, rx_gain_value: %x rx_gain_value_caped: %x\n",
3507 __func__, rx_gain_table[i_rx_gain][0], rx_gain_value, rx_gain_value_caped);
3508 if (rx_gain_value_caped != rx_gain_value)
3509 {
3510 rx_gain_table[i_rx_gain][1] = rx_gain_value_caped;
3511 }
3512 if (done == 1)
3513 break;
3514 i_rx_gain ++;
3515 }
3516 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, rx_gain_table, ARRAY_LENGTH(rx_gain_table), 2);
3517 return AH_TRUE;
3518 }
3519
3520
ar9300_rx_gain_table_apply(struct ath_hal * ah)3521 void ar9300_rx_gain_table_apply(struct ath_hal *ah)
3522 {
3523 struct ath_hal_9300 *ahp = AH9300(ah);
3524 //struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
3525 u_int32_t xlan_gpio_cfg;
3526 u_int8_t i;
3527
3528 if (AR_SREV_OSPREY(ah) || AR_SREV_AR9580(ah))
3529 {
3530 // this will be called if rxGainTable setting is changed
3531 if (ar9300_rf_gain_cap_apply(ah, 1))
3532 return;
3533 }
3534
3535 switch (ar9300_rx_gain_index_get(ah))
3536 {
3537 case 2:
3538 if (AR_SREV_JUPITER_10(ah)) {
3539 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3540 ar9300_common_mixed_rx_gain_table_jupiter_1p0,
3541 ARRAY_LENGTH(ar9300_common_mixed_rx_gain_table_jupiter_1p0), 2);
3542 break;
3543 }
3544 else if (AR_SREV_JUPITER_20(ah)) {
3545 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3546 ar9300Common_mixed_rx_gain_table_jupiter_2p0,
3547 ARRAY_LENGTH(ar9300Common_mixed_rx_gain_table_jupiter_2p0), 2);
3548 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bb_core,
3549 ar9462_2p0_baseband_core_mix_rxgain,
3550 ARRAY_LENGTH(ar9462_2p0_baseband_core_mix_rxgain), 2);
3551 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bb_postamble,
3552 ar9462_2p0_baseband_postamble_mix_rxgain,
3553 ARRAY_LENGTH(ar9462_2p0_baseband_postamble_mix_rxgain), 2);
3554 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_xlna,
3555 ar9462_2p0_baseband_postamble_5g_xlna,
3556 ARRAY_LENGTH(ar9462_2p0_baseband_postamble_5g_xlna), 2);
3557 break;
3558 }
3559 else if (AR_SREV_JUPITER_21(ah)) {
3560 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3561 ar9462_2p1_common_mixed_rx_gain,
3562 ARRAY_LENGTH(ar9462_2p1_common_mixed_rx_gain), 2);
3563 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bb_core,
3564 ar9462_2p1_baseband_core_mix_rxgain,
3565 ARRAY_LENGTH(ar9462_2p1_baseband_core_mix_rxgain), 2);
3566 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bb_postamble,
3567 ar9462_2p1_baseband_postamble_mix_rxgain,
3568 ARRAY_LENGTH(ar9462_2p1_baseband_postamble_mix_rxgain), 2);
3569 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_xlna,
3570 ar9462_2p1_baseband_postamble_5g_xlna,
3571 ARRAY_LENGTH(ar9462_2p1_baseband_postamble_5g_xlna), 2);
3572
3573 break;
3574 }
3575 case 3:
3576 if (AR_SREV_JUPITER_21(ah)) {
3577 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3578 ar9462_2p1_common_5g_xlna_only_rxgain,
3579 ARRAY_LENGTH(ar9462_2p1_common_5g_xlna_only_rxgain), 2);
3580 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_xlna,
3581 ar9462_2p1_baseband_postamble_5g_xlna,
3582 ARRAY_LENGTH(ar9462_2p1_baseband_postamble_5g_xlna), 2);
3583 } else if (AR_SREV_JUPITER_20(ah)) {
3584 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3585 ar9462_2p0_common_5g_xlna_only_rxgain,
3586 ARRAY_LENGTH(ar9462_2p0_common_5g_xlna_only_rxgain), 2);
3587 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_xlna,
3588 ar9462_2p0_baseband_postamble_5g_xlna,
3589 ARRAY_LENGTH(ar9462_2p0_baseband_postamble_5g_xlna), 2);
3590 }
3591 break;
3592 case 0:
3593 default:
3594 if (AR_SREV_HORNET_12(ah)) {
3595 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3596 ar9331_common_rx_gain_hornet1_2,
3597 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_2), 2);
3598 } else if (AR_SREV_HORNET_11(ah)) {
3599 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3600 ar9331_common_rx_gain_hornet1_1,
3601 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_1), 2);
3602 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3603 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3604 ar9485_common_wo_xlna_rx_gain_poseidon1_1,
3605 ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2);
3606 /* XXX FreeBSD: this needs to be revisited!! */
3607 xlan_gpio_cfg = ah->ah_config.ath_hal_ext_lna_ctl_gpio;
3608 if (xlan_gpio_cfg) {
3609 for (i = 0; i < 32; i++) {
3610 if (xlan_gpio_cfg & (1 << i)) {
3611 /*
3612 * XXX FreeBSD: definitely make sure this
3613 * results in the correct value being written
3614 * to the hardware, or weird crap is very likely
3615 * to occur!
3616 */
3617 ath_hal_gpioCfgOutput(ah, i,
3618 HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED);
3619 }
3620 }
3621 }
3622
3623 } else if (AR_SREV_POSEIDON(ah)) {
3624 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3625 ar9485Common_wo_xlna_rx_gain_poseidon1_0,
3626 ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2);
3627 } else if (AR_SREV_JUPITER_10(ah)) {
3628 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3629 ar9300_common_rx_gain_table_jupiter_1p0,
3630 ARRAY_LENGTH(ar9300_common_rx_gain_table_jupiter_1p0), 2);
3631 } else if (AR_SREV_JUPITER_20(ah)) {
3632 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3633 ar9300Common_rx_gain_table_jupiter_2p0,
3634 ARRAY_LENGTH(ar9300Common_rx_gain_table_jupiter_2p0), 2);
3635 } else if (AR_SREV_JUPITER_21(ah)) {
3636 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3637 ar9462_2p1_common_rx_gain,
3638 ARRAY_LENGTH(ar9462_2p1_common_rx_gain), 2);
3639 } else if (AR_SREV_AR9580(ah)) {
3640 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3641 ar9300_common_rx_gain_table_ar9580_1p0,
3642 ARRAY_LENGTH(ar9300_common_rx_gain_table_ar9580_1p0), 2);
3643 } else if (AR_SREV_WASP(ah)) {
3644 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3645 ar9340Common_rx_gain_table_wasp_1p0,
3646 ARRAY_LENGTH(ar9340Common_rx_gain_table_wasp_1p0), 2);
3647 } else if (AR_SREV_SCORPION(ah)) {
3648 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3649 ar955xCommon_rx_gain_table_scorpion_1p0,
3650 ARRAY_LENGTH(ar955xCommon_rx_gain_table_scorpion_1p0), 2);
3651 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds,
3652 ar955xCommon_rx_gain_bounds_scorpion_1p0,
3653 ARRAY_LENGTH(ar955xCommon_rx_gain_bounds_scorpion_1p0), 5);
3654 } else if (AR_SREV_HONEYBEE(ah)) {
3655 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3656 qca953xCommon_rx_gain_table_honeybee_1p0,
3657 ARRAY_LENGTH(qca953xCommon_rx_gain_table_honeybee_1p0), 2);
3658 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds,
3659 qca953xCommon_rx_gain_bounds_honeybee_1p0,
3660 ARRAY_LENGTH(qca953xCommon_rx_gain_bounds_honeybee_1p0), 5);
3661 } else {
3662 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3663 ar9300_common_rx_gain_table_osprey_2p2,
3664 ARRAY_LENGTH(ar9300_common_rx_gain_table_osprey_2p2), 2);
3665 }
3666 break;
3667 case 1:
3668 if (AR_SREV_HORNET_12(ah)) {
3669 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3670 ar9331_common_wo_xlna_rx_gain_hornet1_2,
3671 ARRAY_LENGTH(ar9331_common_wo_xlna_rx_gain_hornet1_2), 2);
3672 } else if (AR_SREV_HORNET_11(ah)) {
3673 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3674 ar9331_common_wo_xlna_rx_gain_hornet1_1,
3675 ARRAY_LENGTH(ar9331_common_wo_xlna_rx_gain_hornet1_1), 2);
3676 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3677 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3678 ar9485_common_wo_xlna_rx_gain_poseidon1_1,
3679 ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2);
3680 } else if (AR_SREV_POSEIDON(ah)) {
3681 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3682 ar9485Common_wo_xlna_rx_gain_poseidon1_0,
3683 ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2);
3684 } else if (AR_SREV_JUPITER_10(ah)) {
3685 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3686 ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0,
3687 ARRAY_LENGTH(ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0),
3688 2);
3689 } else if (AR_SREV_JUPITER_20(ah)) {
3690 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3691 ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0,
3692 ARRAY_LENGTH(ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0),
3693 2);
3694 } else if (AR_SREV_JUPITER_21(ah)) {
3695 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3696 ar9462_2p1_common_wo_xlna_rx_gain,
3697 ARRAY_LENGTH(ar9462_2p1_common_wo_xlna_rx_gain),
3698 2);
3699 } else if (AR_SREV_APHRODITE(ah)) {
3700 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3701 ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0,
3702 ARRAY_LENGTH(ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0),
3703 2);
3704 } else if (AR_SREV_AR9580(ah)) {
3705 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3706 ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0,
3707 ARRAY_LENGTH(ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0), 2);
3708 } else if (AR_SREV_WASP(ah)) {
3709 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3710 ar9340Common_wo_xlna_rx_gain_table_wasp_1p0,
3711 ARRAY_LENGTH(ar9340Common_wo_xlna_rx_gain_table_wasp_1p0), 2);
3712 } else if (AR_SREV_SCORPION(ah)) {
3713 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3714 ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0,
3715 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0), 2);
3716 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds,
3717 ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0,
3718 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5);
3719 } else if (AR_SREV_HONEYBEE(ah)) {
3720 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3721 qca953xCommon_wo_xlna_rx_gain_table_honeybee_1p0,
3722 ARRAY_LENGTH(qca953xCommon_wo_xlna_rx_gain_table_honeybee_1p0), 2);
3723 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds,
3724 qca953xCommon_wo_xlna_rx_gain_bounds_honeybee_1p0,
3725 ARRAY_LENGTH(qca953xCommon_wo_xlna_rx_gain_bounds_honeybee_1p0), 5);
3726 } else {
3727 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3728 ar9300Common_wo_xlna_rx_gain_table_osprey_2p2,
3729 ARRAY_LENGTH(ar9300Common_wo_xlna_rx_gain_table_osprey_2p2), 2);
3730 }
3731 break;
3732 }
3733 }
3734
ar9300_tx_gain_table_apply(struct ath_hal * ah)3735 void ar9300_tx_gain_table_apply(struct ath_hal *ah)
3736 {
3737 struct ath_hal_9300 *ahp = AH9300(ah);
3738
3739 switch (ar9300_tx_gain_index_get(ah))
3740 {
3741 case 0:
3742 default:
3743 if (AR_SREV_HORNET_12(ah)) {
3744 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3745 ar9331_modes_lowest_ob_db_tx_gain_hornet1_2,
3746 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5);
3747 } else if (AR_SREV_HORNET_11(ah)) {
3748 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3749 ar9331_modes_lowest_ob_db_tx_gain_hornet1_1,
3750 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5);
3751 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3752 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3753 ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1,
3754 ARRAY_LENGTH(ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1), 5);
3755 } else if (AR_SREV_POSEIDON(ah)) {
3756 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3757 ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0,
3758 ARRAY_LENGTH(ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0), 5);
3759 } else if (AR_SREV_AR9580(ah)) {
3760 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3761 ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0,
3762 ARRAY_LENGTH(ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0),
3763 5);
3764 } else if (AR_SREV_WASP(ah)) {
3765 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3766 ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0,
3767 ARRAY_LENGTH(ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0),
3768 5);
3769 } else if (AR_SREV_SCORPION(ah)) {
3770 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3771 ar955xModes_xpa_tx_gain_table_scorpion_1p0,
3772 ARRAY_LENGTH(ar955xModes_xpa_tx_gain_table_scorpion_1p0),
3773 9);
3774 } else if (AR_SREV_JUPITER_10(ah)) {
3775 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3776 ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0,
3777 ARRAY_LENGTH(ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0),
3778 5);
3779 } else if (AR_SREV_JUPITER_20(ah)) {
3780 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3781 ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0,
3782 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0),
3783 5);
3784 } else if (AR_SREV_JUPITER_21(ah)) {
3785 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3786 ar9462_2p1_modes_low_ob_db_tx_gain,
3787 ARRAY_LENGTH(ar9462_2p1_modes_low_ob_db_tx_gain),
3788 5);
3789 } else if (AR_SREV_HONEYBEE(ah)) {
3790 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3791 qca953xModes_xpa_tx_gain_table_honeybee_1p0,
3792 ARRAY_LENGTH(qca953xModes_xpa_tx_gain_table_honeybee_1p0),
3793 2);
3794 } else if (AR_SREV_APHRODITE(ah)) {
3795 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3796 ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0,
3797 ARRAY_LENGTH(ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0),
3798 5);
3799 } else {
3800 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3801 ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2,
3802 ARRAY_LENGTH(ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2),
3803 5);
3804 }
3805 break;
3806 case 1:
3807 if (AR_SREV_HORNET_12(ah)) {
3808 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3809 ar9331_modes_high_ob_db_tx_gain_hornet1_2,
3810 ARRAY_LENGTH(ar9331_modes_high_ob_db_tx_gain_hornet1_2), 5);
3811 } else if (AR_SREV_HORNET_11(ah)) {
3812 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3813 ar9331_modes_high_ob_db_tx_gain_hornet1_1,
3814 ARRAY_LENGTH(ar9331_modes_high_ob_db_tx_gain_hornet1_1), 5);
3815 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3816 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3817 ar9485_modes_high_ob_db_tx_gain_poseidon1_1,
3818 ARRAY_LENGTH(ar9485_modes_high_ob_db_tx_gain_poseidon1_1), 5);
3819 } else if (AR_SREV_POSEIDON(ah)) {
3820 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3821 ar9485Modes_high_ob_db_tx_gain_poseidon1_0,
3822 ARRAY_LENGTH(ar9485Modes_high_ob_db_tx_gain_poseidon1_0), 5);
3823 } else if (AR_SREV_AR9580(ah)) {
3824 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3825 ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0,
3826 ARRAY_LENGTH(ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0),
3827 5);
3828 } else if (AR_SREV_WASP(ah)) {
3829 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3830 ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0,
3831 ARRAY_LENGTH(ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0), 5);
3832 } else if (AR_SREV_SCORPION(ah)) {
3833 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3834 ar955xModes_no_xpa_tx_gain_table_scorpion_1p0,
3835 ARRAY_LENGTH(ar955xModes_no_xpa_tx_gain_table_scorpion_1p0), 9);
3836 } else if (AR_SREV_JUPITER_10(ah)) {
3837 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3838 ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0,
3839 ARRAY_LENGTH(
3840 ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0), 5);
3841 } else if (AR_SREV_JUPITER_20(ah)) {
3842 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3843 ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0,
3844 ARRAY_LENGTH(
3845 ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0), 5);
3846 } else if (AR_SREV_JUPITER_21(ah)) {
3847 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3848 ar9462_2p1_modes_high_ob_db_tx_gain,
3849 ARRAY_LENGTH(
3850 ar9462_2p1_modes_high_ob_db_tx_gain), 5);
3851 } else if (AR_SREV_APHRODITE(ah)) {
3852 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3853 ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0,
3854 ARRAY_LENGTH(
3855 ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0), 5);
3856 } else if (AR_SREV_HONEYBEE(ah)) {
3857 if (AR_SREV_HONEYBEE_11(ah)) {
3858 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3859 qca953xModes_no_xpa_tx_gain_table_honeybee_1p1,
3860 ARRAY_LENGTH(qca953xModes_no_xpa_tx_gain_table_honeybee_1p1), 2);
3861 } else {
3862 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3863 qca953xModes_no_xpa_tx_gain_table_honeybee_1p0,
3864 ARRAY_LENGTH(qca953xModes_no_xpa_tx_gain_table_honeybee_1p0), 2);
3865 }
3866 } else {
3867 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3868 ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2,
3869 ARRAY_LENGTH(ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2),
3870 5);
3871 }
3872 break;
3873 case 2:
3874 if (AR_SREV_HORNET_12(ah)) {
3875 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3876 ar9331_modes_low_ob_db_tx_gain_hornet1_2,
3877 ARRAY_LENGTH(ar9331_modes_low_ob_db_tx_gain_hornet1_2), 5);
3878 } else if (AR_SREV_HORNET_11(ah)) {
3879 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3880 ar9331_modes_low_ob_db_tx_gain_hornet1_1,
3881 ARRAY_LENGTH(ar9331_modes_low_ob_db_tx_gain_hornet1_1), 5);
3882 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3883 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3884 ar9485_modes_low_ob_db_tx_gain_poseidon1_1,
3885 ARRAY_LENGTH(ar9485_modes_low_ob_db_tx_gain_poseidon1_1), 5);
3886 } else if (AR_SREV_POSEIDON(ah)) {
3887 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3888 ar9485Modes_low_ob_db_tx_gain_poseidon1_0,
3889 ARRAY_LENGTH(ar9485Modes_low_ob_db_tx_gain_poseidon1_0), 5);
3890 } else if (AR_SREV_AR9580(ah)) {
3891 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3892 ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0,
3893 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0),
3894 5);
3895 } else if (AR_SREV_WASP(ah)) {
3896 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3897 ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0,
3898 ARRAY_LENGTH(ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0), 5);
3899 } else if (AR_SREV_APHRODITE(ah)) {
3900 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3901 ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0,
3902 ARRAY_LENGTH(ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0), 5);
3903 } else {
3904 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3905 ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2,
3906 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2),
3907 5);
3908 }
3909 break;
3910 case 3:
3911 if (AR_SREV_HORNET_12(ah)) {
3912 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3913 ar9331_modes_high_power_tx_gain_hornet1_2,
3914 ARRAY_LENGTH(ar9331_modes_high_power_tx_gain_hornet1_2), 5);
3915 } else if (AR_SREV_HORNET_11(ah)) {
3916 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3917 ar9331_modes_high_power_tx_gain_hornet1_1,
3918 ARRAY_LENGTH(ar9331_modes_high_power_tx_gain_hornet1_1), 5);
3919 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3920 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3921 ar9485_modes_high_power_tx_gain_poseidon1_1,
3922 ARRAY_LENGTH(ar9485_modes_high_power_tx_gain_poseidon1_1), 5);
3923 } else if (AR_SREV_POSEIDON(ah)) {
3924 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3925 ar9485Modes_high_power_tx_gain_poseidon1_0,
3926 ARRAY_LENGTH(ar9485Modes_high_power_tx_gain_poseidon1_0), 5);
3927 } else if (AR_SREV_AR9580(ah)) {
3928 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3929 ar9300Modes_high_power_tx_gain_table_ar9580_1p0,
3930 ARRAY_LENGTH(ar9300Modes_high_power_tx_gain_table_ar9580_1p0),
3931 5);
3932 } else if (AR_SREV_WASP(ah)) {
3933 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3934 ar9340Modes_high_power_tx_gain_table_wasp_1p0,
3935 ARRAY_LENGTH(ar9340Modes_high_power_tx_gain_table_wasp_1p0),
3936 5);
3937 } else if (AR_SREV_APHRODITE(ah)) {
3938 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3939 ar956XModes_high_power_tx_gain_table_aphrodite_1p0,
3940 ARRAY_LENGTH(ar956XModes_high_power_tx_gain_table_aphrodite_1p0), 5);
3941 } else {
3942 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3943 ar9300Modes_high_power_tx_gain_table_osprey_2p2,
3944 ARRAY_LENGTH(ar9300Modes_high_power_tx_gain_table_osprey_2p2),
3945 5);
3946 }
3947 break;
3948 case 4:
3949 if (AR_SREV_WASP(ah)) {
3950 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3951 ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0,
3952 ARRAY_LENGTH(ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0),
3953 5);
3954 } else if (AR_SREV_AR9580(ah)) {
3955 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3956 ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0,
3957 ARRAY_LENGTH(ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0),
3958 5);
3959 } else {
3960 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3961 ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2,
3962 ARRAY_LENGTH(ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2),
3963 5);
3964 }
3965 break;
3966 case 5:
3967 /* HW Green TX */
3968 if (AR_SREV_POSEIDON(ah)) {
3969 if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3970 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3971 ar9485_modes_green_ob_db_tx_gain_poseidon1_1,
3972 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_1) /
3973 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_1[0]), 5);
3974 } else {
3975 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3976 ar9485_modes_green_ob_db_tx_gain_poseidon1_0,
3977 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_0) /
3978 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_0[0]), 5);
3979 }
3980 ahp->ah_hw_green_tx_enable = 1;
3981 }
3982 else if (AR_SREV_WASP(ah)) {
3983 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3984 ar9340_modes_ub124_tx_gain_table_wasp_1p0,
3985 sizeof(ar9340_modes_ub124_tx_gain_table_wasp_1p0) /
3986 sizeof(ar9340_modes_ub124_tx_gain_table_wasp_1p0[0]), 5);
3987 }
3988 else if (AR_SREV_AR9580(ah)) {
3989 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3990 ar9300_modes_type5_tx_gain_table_ar9580_1p0,
3991 ARRAY_LENGTH( ar9300_modes_type5_tx_gain_table_ar9580_1p0),
3992 5);
3993 }
3994 else if (AR_SREV_OSPREY_22(ah)) {
3995 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3996 ar9300_modes_number_5_tx_gain_table_osprey_2p2,
3997 ARRAY_LENGTH( ar9300_modes_number_5_tx_gain_table_osprey_2p2),
3998 5);
3999 }
4000 break;
4001 case 6:
4002 if (AR_SREV_WASP(ah)) {
4003 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
4004 ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0,
4005 sizeof(ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0) /
4006 sizeof(ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0[0]), 5);
4007 }
4008 /* HW Green TX */
4009 else if (AR_SREV_POSEIDON(ah)) {
4010 if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
4011 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
4012 ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1,
4013 sizeof(ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1) /
4014 sizeof(ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1[0]),
4015 5);
4016 }
4017 ahp->ah_hw_green_tx_enable = 1;
4018 }
4019 else if (AR_SREV_AR9580(ah)) {
4020 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
4021 ar9300_modes_type6_tx_gain_table_ar9580_1p0,
4022 ARRAY_LENGTH( ar9300_modes_type6_tx_gain_table_ar9580_1p0),
4023 5);
4024 }
4025 break;
4026 case 7:
4027 if (AR_SREV_WASP(ah)) {
4028 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
4029 ar9340Modes_cus227_tx_gain_table_wasp_1p0,
4030 sizeof(ar9340Modes_cus227_tx_gain_table_wasp_1p0) /
4031 sizeof(ar9340Modes_cus227_tx_gain_table_wasp_1p0[0]), 5);
4032 }
4033 break;
4034 }
4035 }
4036
4037 #if ATH_ANT_DIV_COMB
4038 void
ar9300_ant_div_comb_get_config(struct ath_hal * ah,HAL_ANT_COMB_CONFIG * div_comb_conf)4039 ar9300_ant_div_comb_get_config(struct ath_hal *ah,
4040 HAL_ANT_COMB_CONFIG *div_comb_conf)
4041 {
4042 u_int32_t reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
4043 div_comb_conf->main_lna_conf =
4044 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__READ(reg_val);
4045 div_comb_conf->alt_lna_conf =
4046 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__READ(reg_val);
4047 div_comb_conf->fast_div_bias =
4048 MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__READ(reg_val);
4049 if (AR_SREV_HORNET_11(ah)) {
4050 div_comb_conf->antdiv_configgroup = HAL_ANTDIV_CONFIG_GROUP_1;
4051 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
4052 div_comb_conf->antdiv_configgroup = HAL_ANTDIV_CONFIG_GROUP_2;
4053 } else {
4054 div_comb_conf->antdiv_configgroup = DEFAULT_ANTDIV_CONFIG_GROUP;
4055 }
4056
4057 /*
4058 * XXX TODO: allow the HAL to override the rssithres and fast_div_bias
4059 * values (eg CUS198.)
4060 */
4061 }
4062
4063 void
ar9300_ant_div_comb_set_config(struct ath_hal * ah,HAL_ANT_COMB_CONFIG * div_comb_conf)4064 ar9300_ant_div_comb_set_config(struct ath_hal *ah,
4065 HAL_ANT_COMB_CONFIG *div_comb_conf)
4066 {
4067 u_int32_t reg_val;
4068 struct ath_hal_9300 *ahp = AH9300(ah);
4069
4070 /* DO NOTHING when set to fixed antenna for manufacturing purpose */
4071 if (AR_SREV_POSEIDON(ah) && ( ahp->ah_diversity_control == HAL_ANT_FIXED_A
4072 || ahp->ah_diversity_control == HAL_ANT_FIXED_B)) {
4073 return;
4074 }
4075 reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
4076 reg_val &= ~(MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MASK |
4077 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MASK |
4078 MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__MASK |
4079 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MASK |
4080 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MASK );
4081 reg_val |=
4082 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__WRITE(
4083 div_comb_conf->main_gaintb);
4084 reg_val |=
4085 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__WRITE(
4086 div_comb_conf->alt_gaintb);
4087 reg_val |=
4088 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__WRITE(
4089 div_comb_conf->main_lna_conf);
4090 reg_val |=
4091 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__WRITE(
4092 div_comb_conf->alt_lna_conf);
4093 reg_val |=
4094 MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__WRITE(
4095 div_comb_conf->fast_div_bias);
4096 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, reg_val);
4097
4098 }
4099 #endif /* ATH_ANT_DIV_COMB */
4100
4101 static void
ar9300_init_hostif_offsets(struct ath_hal * ah)4102 ar9300_init_hostif_offsets(struct ath_hal *ah)
4103 {
4104 AR_HOSTIF_REG(ah, AR_RC) =
4105 AR9300_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL);
4106 AR_HOSTIF_REG(ah, AR_WA) =
4107 AR9300_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND);
4108 AR_HOSTIF_REG(ah, AR_PM_STATE) =
4109 AR9300_HOSTIF_OFFSET(HOST_INTF_PM_STATE);
4110 AR_HOSTIF_REG(ah, AR_H_INFOL) =
4111 AR9300_HOSTIF_OFFSET(HOST_INTF_CXPL_DEBUG_INFOL);
4112 AR_HOSTIF_REG(ah, AR_H_INFOH) =
4113 AR9300_HOSTIF_OFFSET(HOST_INTF_CXPL_DEBUG_INFOH);
4114 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) =
4115 AR9300_HOSTIF_OFFSET(HOST_INTF_PM_CTRL);
4116 AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) =
4117 AR9300_HOSTIF_OFFSET(HOST_INTF_TIMEOUT);
4118 AR_HOSTIF_REG(ah, AR_EEPROM) =
4119 AR9300_HOSTIF_OFFSET(HOST_INTF_EEPROM_CTRL);
4120 AR_HOSTIF_REG(ah, AR_SREV) =
4121 AR9300_HOSTIF_OFFSET(HOST_INTF_SREV);
4122 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) =
4123 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE);
4124 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) =
4125 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE);
4126 AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) =
4127 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE);
4128 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) =
4129 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK);
4130 AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) =
4131 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK);
4132 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) =
4133 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE);
4134 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) =
4135 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE);
4136 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) =
4137 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE);
4138 AR_HOSTIF_REG(ah, AR_PCIE_SERDES) =
4139 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_RW);
4140 AR_HOSTIF_REG(ah, AR_PCIE_SERDES2) =
4141 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_LOAD);
4142 AR_HOSTIF_REG(ah, AR_GPIO_OUT) =
4143 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT);
4144 AR_HOSTIF_REG(ah, AR_GPIO_IN) =
4145 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_IN);
4146 AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) =
4147 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OE);
4148 AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) =
4149 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1);
4150 AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) =
4151 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR);
4152 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) =
4153 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE);
4154 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) =
4155 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1);
4156 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) =
4157 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2);
4158 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) =
4159 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1);
4160 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) =
4161 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2);
4162 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) =
4163 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3);
4164 AR_HOSTIF_REG(ah, AR_INPUT_STATE) =
4165 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE);
4166 AR_HOSTIF_REG(ah, AR_SPARE) =
4167 AR9300_HOSTIF_OFFSET(HOST_INTF_SPARE);
4168 AR_HOSTIF_REG(ah, AR_PCIE_CORE_RESET_EN) =
4169 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_CORE_RST_EN);
4170 AR_HOSTIF_REG(ah, AR_CLKRUN) =
4171 AR9300_HOSTIF_OFFSET(HOST_INTF_CLKRUN);
4172 AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) =
4173 AR9300_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS);
4174 AR_HOSTIF_REG(ah, AR_OBS) =
4175 AR9300_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL);
4176 AR_HOSTIF_REG(ah, AR_RFSILENT) =
4177 AR9300_HOSTIF_OFFSET(HOST_INTF_RFSILENT);
4178 AR_HOSTIF_REG(ah, AR_GPIO_PDPU) =
4179 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_PDPU);
4180 AR_HOSTIF_REG(ah, AR_GPIO_DS) =
4181 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_DS);
4182 AR_HOSTIF_REG(ah, AR_MISC) =
4183 AR9300_HOSTIF_OFFSET(HOST_INTF_MISC);
4184 AR_HOSTIF_REG(ah, AR_PCIE_MSI) =
4185 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI);
4186 #if 0 /* Offsets are not defined in reg_map structure */
4187 AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_ACTIVE) =
4188 AR9300_HOSTIF_OFFSET(HOST_INTF_TSF_SNAPSHOT_BT_ACTIVE);
4189 AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_PRIORITY) =
4190 AR9300_HOSTIF_OFFSET(HOST_INTF_TSF_SNAPSHOT_BT_PRIORITY);
4191 AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_CNTL) =
4192 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TSF_SNAPSHOT_BT_CNTL);
4193 #endif
4194 AR_HOSTIF_REG(ah, AR_PCIE_PHY_LATENCY_NFTS_ADJ) =
4195 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ);
4196 AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) =
4197 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL);
4198 AR_HOSTIF_REG(ah, AR_TXAPSYNC) =
4199 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC);
4200 AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) =
4201 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR);
4202 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) =
4203 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE);
4204 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) =
4205 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE);
4206 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) =
4207 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK);
4208 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) =
4209 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK);
4210 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) =
4211 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE);
4212 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) =
4213 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE);
4214 }
4215
4216 static void
ar9340_init_hostif_offsets(struct ath_hal * ah)4217 ar9340_init_hostif_offsets(struct ath_hal *ah)
4218 {
4219 AR_HOSTIF_REG(ah, AR_RC) =
4220 AR9340_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL);
4221 AR_HOSTIF_REG(ah, AR_WA) =
4222 AR9340_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND);
4223 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) =
4224 AR9340_HOSTIF_OFFSET(HOST_INTF_PM_CTRL);
4225 AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) =
4226 AR9340_HOSTIF_OFFSET(HOST_INTF_TIMEOUT);
4227 AR_HOSTIF_REG(ah, AR_SREV) =
4228 AR9340_HOSTIF_OFFSET(HOST_INTF_SREV);
4229 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) =
4230 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE);
4231 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) =
4232 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE);
4233 AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) =
4234 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE);
4235 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) =
4236 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK);
4237 AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) =
4238 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK);
4239 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) =
4240 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE);
4241 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) =
4242 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE);
4243 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) =
4244 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE);
4245 AR_HOSTIF_REG(ah, AR_GPIO_OUT) =
4246 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT);
4247 AR_HOSTIF_REG(ah, AR_GPIO_IN) =
4248 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_IN);
4249 AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) =
4250 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE);
4251 AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) =
4252 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1);
4253 AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) =
4254 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR);
4255 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) =
4256 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE);
4257 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) =
4258 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1);
4259 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) =
4260 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2);
4261 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) =
4262 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1);
4263 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) =
4264 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2);
4265 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) =
4266 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3);
4267 AR_HOSTIF_REG(ah, AR_INPUT_STATE) =
4268 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE);
4269 AR_HOSTIF_REG(ah, AR_CLKRUN) =
4270 AR9340_HOSTIF_OFFSET(HOST_INTF_CLKRUN);
4271 AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) =
4272 AR9340_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS);
4273 AR_HOSTIF_REG(ah, AR_OBS) =
4274 AR9340_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL);
4275 AR_HOSTIF_REG(ah, AR_RFSILENT) =
4276 AR9340_HOSTIF_OFFSET(HOST_INTF_RFSILENT);
4277 AR_HOSTIF_REG(ah, AR_MISC) =
4278 AR9340_HOSTIF_OFFSET(HOST_INTF_MISC);
4279 AR_HOSTIF_REG(ah, AR_PCIE_MSI) =
4280 AR9340_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI);
4281 AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) =
4282 AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL);
4283 AR_HOSTIF_REG(ah, AR_TXAPSYNC) =
4284 AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC);
4285 AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) =
4286 AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR);
4287 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) =
4288 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE);
4289 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) =
4290 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE);
4291 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) =
4292 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK);
4293 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) =
4294 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK);
4295 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) =
4296 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE);
4297 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) =
4298 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE);
4299 }
4300
4301 /*
4302 * Host interface register offsets are different for Osprey and Wasp
4303 * and hence store the offsets in hal structure
4304 */
ar9300_init_offsets(struct ath_hal * ah,u_int16_t devid)4305 static int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid)
4306 {
4307 if (devid == AR9300_DEVID_AR9340) {
4308 ar9340_init_hostif_offsets(ah);
4309 } else {
4310 ar9300_init_hostif_offsets(ah);
4311 }
4312 return 0;
4313 }
4314
4315
4316 static const char*
ar9300_probe(uint16_t vendorid,uint16_t devid)4317 ar9300_probe(uint16_t vendorid, uint16_t devid)
4318 {
4319 if (vendorid != ATHEROS_VENDOR_ID)
4320 return AH_NULL;
4321
4322 switch (devid) {
4323 case AR9300_DEVID_AR9380_PCIE: /* PCIE (Osprey) */
4324 return "Atheros AR938x";
4325 case AR9300_DEVID_AR9340: /* Wasp */
4326 return "Atheros AR934x";
4327 case AR9300_DEVID_AR9485_PCIE: /* Poseidon */
4328 return "Atheros AR9485";
4329 case AR9300_DEVID_AR9580_PCIE: /* Peacock */
4330 return "Atheros AR9580";
4331 case AR9300_DEVID_AR946X_PCIE: /* AR9462, AR9463, AR9482 */
4332 return "Atheros AR946x/AR948x";
4333 case AR9300_DEVID_AR9330: /* Hornet */
4334 return "Atheros AR933x";
4335 case AR9300_DEVID_QCA955X: /* Scorpion */
4336 return "Qualcomm Atheros QCA955x";
4337 case AR9300_DEVID_QCA9565: /* Aphrodite */
4338 return "Qualcomm Atheros AR9565";
4339 case AR9300_DEVID_QCA953X: /* Honeybee */
4340 return "Qualcomm Atheros QCA953x";
4341 case AR9300_DEVID_AR1111_PCIE:
4342 return "Atheros AR1111";
4343 default:
4344 return AH_NULL;
4345 }
4346
4347 return AH_NULL;
4348 }
4349
4350 AH_CHIP(AR9300, ar9300_probe, ar9300_attach);
4351
4352