1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org> 5 * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* 32 * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved. 33 * 34 * Permission to use, copy, modify, and/or distribute this software for 35 * any purpose with or without fee is hereby granted, provided that the 36 * above copyright notice and this permission notice appear in all copies. 37 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 38 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 39 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 40 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 41 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 42 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT 43 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 44 45 */ 46 47 #ifndef __QCOM_ESS_EDMA_REG_H__ 48 #define __QCOM_ESS_EDMA_REG_H__ 49 50 /* 51 * Alignment of descriptor ring memory allocation. 52 */ 53 #define EDMA_DESC_RING_ALIGN PAGE_SIZE 54 55 /* Not sure if this is really valid or not */ 56 #define EDMA_DESC_MAX_BUFFER_SIZE 4096 57 58 /* The hardware can accept both of these, so we don't need bounce buffers! */ 59 #define ESS_EDMA_TX_BUFFER_ALIGN 1 60 #define ESS_EDMA_RX_BUFFER_ALIGN 1 61 62 /* register definition */ 63 #define EDMA_REG_MAS_CTRL 0x0 64 #define EDMA_REG_TIMEOUT_CTRL 0x004 65 #define EDMA_REG_DBG0 0x008 66 #define EDMA_REG_DBG1 0x00C 67 #define EDMA_REG_SW_CTRL0 0x100 68 #define EDMA_REG_SW_CTRL1 0x104 69 70 /* Interrupt Status Register */ 71 #define EDMA_REG_RX_ISR 0x200 72 #define EDMA_REG_TX_ISR 0x208 73 #define EDMA_REG_MISC_ISR 0x210 74 #define EDMA_REG_WOL_ISR 0x218 75 76 #define EDMA_MISC_ISR_RX_URG_Q(x) (1U << (x)x) 77 78 #define EDMA_MISC_ISR_AXIR_TIMEOUT 0x00000100 79 #define EDMA_MISC_ISR_AXIR_ERR 0x00000200 80 #define EDMA_MISC_ISR_TXF_DEAD 0x00000400 81 #define EDMA_MISC_ISR_AXIW_ERR 0x00000800 82 #define EDMA_MISC_ISR_AXIW_TIMEOUT 0x00001000 83 84 #define EDMA_WOL_ISR 0x00000001 85 86 /* Interrupt Mask Register */ 87 #define EDMA_REG_MISC_IMR 0x214 88 #define EDMA_REG_WOL_IMR 0x218 89 90 #define EDMA_RX_IMR_NORMAL_MASK 0x1 91 #define EDMA_TX_IMR_NORMAL_MASK 0x1 92 #define EDMA_MISC_IMR_NORMAL_MASK 0x80001FFF 93 #define EDMA_WOL_IMR_NORMAL_MASK 0x1 94 95 /* Edma receive consumer index */ 96 #define EDMA_REG_RX_SW_CONS_IDX_Q(x) (0x220 + ((x) << 2)) /* x is the queue id */ 97 /* Edma transmit consumer index */ 98 #define EDMA_REG_TX_SW_CONS_IDX_Q(x) (0x240 + ((x) << 2)) /* x is the queue id */ 99 100 /* IRQ Moderator Initial Timer Register */ 101 #define EDMA_REG_IRQ_MODRT_TIMER_INIT 0x280 102 #define EDMA_IRQ_MODRT_TIMER_MASK 0xFFFF 103 #define EDMA_IRQ_MODRT_RX_TIMER_SHIFT 0 104 #define EDMA_IRQ_MODRT_TX_TIMER_SHIFT 16 105 106 /* Interrupt Control Register */ 107 #define EDMA_REG_INTR_CTRL 0x284 108 #define EDMA_INTR_CLR_TYP_SHIFT 0 109 #define EDMA_INTR_SW_IDX_W_TYP_SHIFT 1 110 #define EDMA_INTR_CLEAR_TYPE_W1 0 111 #define EDMA_INTR_CLEAR_TYPE_R 1 112 113 /* RX Interrupt Mask Register */ 114 #define EDMA_REG_RX_INT_MASK_Q(x) (0x300 + ((x) << 2)) /* x = queue id */ 115 116 /* TX Interrupt mask register */ 117 #define EDMA_REG_TX_INT_MASK_Q(x) (0x340 + ((x) << 2)) /* x = queue id */ 118 119 /* Load Ptr Register 120 * Software sets this bit after the initialization of the head and tail 121 */ 122 #define EDMA_REG_TX_SRAM_PART 0x400 123 #define EDMA_LOAD_PTR_SHIFT 16 124 125 /* TXQ Control Register */ 126 #define EDMA_REG_TXQ_CTRL 0x404 127 #define EDMA_TXQ_CTRL_IP_OPTION_EN 0x10 128 #define EDMA_TXQ_CTRL_TXQ_EN 0x20 129 #define EDMA_TXQ_CTRL_ENH_MODE 0x40 130 #define EDMA_TXQ_CTRL_LS_8023_EN 0x80 131 #define EDMA_TXQ_CTRL_TPD_BURST_EN 0x100 132 #define EDMA_TXQ_CTRL_LSO_BREAK_EN 0x200 133 #define EDMA_TXQ_NUM_TPD_BURST_MASK 0xF 134 #define EDMA_TXQ_TXF_BURST_NUM_MASK 0xFFFF 135 #define EDMA_TXQ_NUM_TPD_BURST_SHIFT 0 136 #define EDMA_TXQ_TXF_BURST_NUM_SHIFT 16 137 138 #define EDMA_REG_TXF_WATER_MARK 0x408 /* In 8-bytes */ 139 #define EDMA_TXF_WATER_MARK_MASK 0x0FFF 140 #define EDMA_TXF_LOW_WATER_MARK_SHIFT 0 141 #define EDMA_TXF_HIGH_WATER_MARK_SHIFT 16 142 #define EDMA_TXQ_CTRL_BURST_MODE_EN 0x80000000 143 144 /* WRR Control Register */ 145 #define EDMA_REG_WRR_CTRL_Q0_Q3 0x40c 146 #define EDMA_REG_WRR_CTRL_Q4_Q7 0x410 147 #define EDMA_REG_WRR_CTRL_Q8_Q11 0x414 148 #define EDMA_REG_WRR_CTRL_Q12_Q15 0x418 149 150 /* Weight round robin(WRR), it takes queue as input, and computes 151 * starting bits where we need to write the weight for a particular 152 * queue 153 */ 154 #define EDMA_WRR_SHIFT(x) (((x) * 5) % 20) 155 156 /* Tx Descriptor Control Register */ 157 #define EDMA_REG_TPD_RING_SIZE 0x41C 158 #define EDMA_TPD_RING_SIZE_SHIFT 0 159 #define EDMA_TPD_RING_SIZE_MASK 0xFFFF 160 161 /* Transmit descriptor base address */ 162 #define EDMA_REG_TPD_BASE_ADDR_Q(x) (0x420 + ((x) << 2)) /* x = queue id */ 163 164 /* TPD Index Register */ 165 #define EDMA_REG_TPD_IDX_Q(x) (0x460 + ((x) << 2)) /* x = queue id */ 166 167 #define EDMA_TPD_PROD_IDX_BITS 0x0000FFFF 168 #define EDMA_TPD_CONS_IDX_BITS 0xFFFF0000 169 #define EDMA_TPD_PROD_IDX_MASK 0xFFFF 170 #define EDMA_TPD_CONS_IDX_MASK 0xFFFF 171 #define EDMA_TPD_PROD_IDX_SHIFT 0 172 #define EDMA_TPD_CONS_IDX_SHIFT 16 173 174 /* TX Virtual Queue Mapping Control Register */ 175 #define EDMA_REG_VQ_CTRL0 0x4A0 176 #define EDMA_REG_VQ_CTRL1 0x4A4 177 178 /* Virtual QID shift, it takes queue as input, and computes 179 * Virtual QID position in virtual qid control register 180 */ 181 #define EDMA_VQ_ID_SHIFT(i) (((i) * 3) % 24) 182 183 /* Virtual Queue Default Value */ 184 #define EDMA_VQ_REG_VALUE 0x240240 185 186 /* Tx side Port Interface Control Register */ 187 #define EDMA_REG_PORT_CTRL 0x4A8 188 #define EDMA_PAD_EN_SHIFT 15 189 190 /* Tx side VLAN Configuration Register */ 191 #define EDMA_REG_VLAN_CFG 0x4AC 192 193 #define EDMA_TX_CVLAN 16 194 #define EDMA_TX_INS_CVLAN 17 195 #define EDMA_TX_CVLAN_TAG_SHIFT 0 196 197 #define EDMA_TX_SVLAN 14 198 #define EDMA_TX_INS_SVLAN 15 199 #define EDMA_TX_SVLAN_TAG_SHIFT 16 200 201 /* Tx Queue Packet Statistic Register */ 202 #define EDMA_REG_TX_STAT_PKT_Q(x) (0x700 + ((x) << 3)) /* x = queue id */ 203 204 #define EDMA_TX_STAT_PKT_MASK 0xFFFFFF 205 206 /* Tx Queue Byte Statistic Register */ 207 #define EDMA_REG_TX_STAT_BYTE_Q(x) (0x704 + ((x) << 3)) /* x = queue id */ 208 209 /* Load Balance Based Ring Offset Register */ 210 #define EDMA_REG_LB_RING 0x800 211 #define EDMA_LB_RING_ENTRY_MASK 0xff 212 #define EDMA_LB_RING_ID_MASK 0x7 213 #define EDMA_LB_RING_PROFILE_ID_MASK 0x3 214 #define EDMA_LB_RING_ENTRY_BIT_OFFSET 8 215 #define EDMA_LB_RING_ID_OFFSET 0 216 #define EDMA_LB_RING_PROFILE_ID_OFFSET 3 217 #define EDMA_LB_REG_VALUE 0x6040200 218 219 /* Load Balance Priority Mapping Register */ 220 #define EDMA_REG_LB_PRI_START 0x804 221 #define EDMA_REG_LB_PRI_END 0x810 222 #define EDMA_LB_PRI_REG_INC 4 223 #define EDMA_LB_PRI_ENTRY_BIT_OFFSET 4 224 #define EDMA_LB_PRI_ENTRY_MASK 0xf 225 226 /* RSS Priority Mapping Register */ 227 #define EDMA_REG_RSS_PRI 0x820 228 #define EDMA_RSS_PRI_ENTRY_MASK 0xf 229 #define EDMA_RSS_RING_ID_MASK 0x7 230 #define EDMA_RSS_PRI_ENTRY_BIT_OFFSET 4 231 232 /* RSS Indirection Register */ 233 #define EDMA_REG_RSS_IDT(x) (0x840 + ((x) << 2)) /* x = No. of indirection table */ 234 #define EDMA_NUM_IDT 16 235 #define EDMA_RSS_IDT_VALUE 0x64206420 236 237 /* Default RSS Ring Register */ 238 #define EDMA_REG_DEF_RSS 0x890 239 #define EDMA_DEF_RSS_MASK 0x7 240 241 /* RSS Hash Function Type Register */ 242 #define EDMA_REG_RSS_TYPE 0x894 243 #define EDMA_RSS_TYPE_NONE 0x01 244 #define EDMA_RSS_TYPE_IPV4TCP 0x02 245 #define EDMA_RSS_TYPE_IPV6_TCP 0x04 246 #define EDMA_RSS_TYPE_IPV4_UDP 0x08 247 #define EDMA_RSS_TYPE_IPV6UDP 0x10 248 #define EDMA_RSS_TYPE_IPV4 0x20 249 #define EDMA_RSS_TYPE_IPV6 0x40 250 #define EDMA_RSS_HASH_MODE_MASK 0x7f 251 252 #define EDMA_REG_RSS_HASH_VALUE 0x8C0 253 254 #define EDMA_REG_RSS_TYPE_RESULT 0x8C4 255 256 257 /* rrd5 */ 258 #define EDMA_HASH_TYPE_SHIFT 12 259 #define EDMA_HASH_TYPE_MASK 0xf 260 #define EDMA_RRD_RSS_TYPE_NONE 0 261 #define EDMA_RRD_RSS_TYPE_IPV4TCP 1 262 #define EDMA_RRD_RSS_TYPE_IPV6_TCP 2 263 #define EDMA_RRD_RSS_TYPE_IPV4_UDP 3 264 #define EDMA_RRD_RSS_TYPE_IPV6UDP 4 265 #define EDMA_RRD_RSS_TYPE_IPV4 5 266 #define EDMA_RRD_RSS_TYPE_IPV6 6 267 268 #define EDMA_RFS_FLOW_ENTRIES 1024 269 #define EDMA_RFS_FLOW_ENTRIES_MASK (EDMA_RFS_FLOW_ENTRIES - 1) 270 #define EDMA_RFS_EXPIRE_COUNT_PER_CALL 128 271 272 /* RFD Base Address Register */ 273 #define EDMA_REG_RFD_BASE_ADDR_Q(x) (0x950 + ((x) << 2)) /* x = queue id */ 274 275 /* RFD Index Register */ 276 #define EDMA_REG_RFD_IDX_Q(x) (0x9B0 + ((x) << 2)) 277 278 #define EDMA_RFD_PROD_IDX_BITS 0x00000FFF 279 #define EDMA_RFD_CONS_IDX_BITS 0x0FFF0000 280 #define EDMA_RFD_PROD_IDX_MASK 0xFFF 281 #define EDMA_RFD_CONS_IDX_MASK 0xFFF 282 #define EDMA_RFD_PROD_IDX_SHIFT 0 283 #define EDMA_RFD_CONS_IDX_SHIFT 16 284 285 /* Rx Descriptor Control Register */ 286 #define EDMA_REG_RX_DESC0 0xA10 287 #define EDMA_RFD_RING_SIZE_MASK 0xFFF 288 #define EDMA_RX_BUF_SIZE_MASK 0xFFFF 289 #define EDMA_RFD_RING_SIZE_SHIFT 0 290 #define EDMA_RX_BUF_SIZE_SHIFT 16 291 292 #define EDMA_REG_RX_DESC1 0xA14 293 #define EDMA_RXQ_RFD_BURST_NUM_MASK 0x3F 294 #define EDMA_RXQ_RFD_PF_THRESH_MASK 0x1F 295 #define EDMA_RXQ_RFD_LOW_THRESH_MASK 0xFFF 296 #define EDMA_RXQ_RFD_BURST_NUM_SHIFT 0 297 #define EDMA_RXQ_RFD_PF_THRESH_SHIFT 8 298 #define EDMA_RXQ_RFD_LOW_THRESH_SHIFT 16 299 300 /* RXQ Control Register */ 301 #define EDMA_REG_RXQ_CTRL 0xA18 302 #define EDMA_FIFO_THRESH_TYPE_SHIF 0 303 #define EDMA_FIFO_THRESH_128_BYTE 0x0 304 #define EDMA_FIFO_THRESH_64_BYTE 0x1 305 #define EDMA_RXQ_CTRL_RMV_VLAN 0x00000002 306 #define EDMA_RXQ_CTRL_EN 0x0000FF00 307 308 /* AXI Burst Size Config */ 309 #define EDMA_REG_AXIW_CTRL_MAXWRSIZE 0xA1C 310 #define EDMA_AXIW_MAXWRSIZE_VALUE 0x0 311 312 /* Rx Statistics Register */ 313 #define EDMA_REG_RX_STAT_BYTE_Q(x) (0xA30 + ((x) << 2)) /* x = queue id */ 314 #define EDMA_REG_RX_STAT_PKT_Q(x) (0xA50 + ((x) << 2)) /* x = queue id */ 315 316 /* WoL Pattern Length Register */ 317 #define EDMA_REG_WOL_PATTERN_LEN0 0xC00 318 #define EDMA_WOL_PT_LEN_MASK 0xFF 319 #define EDMA_WOL_PT0_LEN_SHIFT 0 320 #define EDMA_WOL_PT1_LEN_SHIFT 8 321 #define EDMA_WOL_PT2_LEN_SHIFT 16 322 #define EDMA_WOL_PT3_LEN_SHIFT 24 323 324 #define EDMA_REG_WOL_PATTERN_LEN1 0xC04 325 #define EDMA_WOL_PT4_LEN_SHIFT 0 326 #define EDMA_WOL_PT5_LEN_SHIFT 8 327 #define EDMA_WOL_PT6_LEN_SHIFT 16 328 329 /* WoL Control Register */ 330 #define EDMA_REG_WOL_CTRL 0xC08 331 #define EDMA_WOL_WK_EN 0x00000001 332 #define EDMA_WOL_MG_EN 0x00000002 333 #define EDMA_WOL_PT0_EN 0x00000004 334 #define EDMA_WOL_PT1_EN 0x00000008 335 #define EDMA_WOL_PT2_EN 0x00000010 336 #define EDMA_WOL_PT3_EN 0x00000020 337 #define EDMA_WOL_PT4_EN 0x00000040 338 #define EDMA_WOL_PT5_EN 0x00000080 339 #define EDMA_WOL_PT6_EN 0x00000100 340 341 /* MAC Control Register */ 342 #define EDMA_REG_MAC_CTRL0 0xC20 343 #define EDMA_REG_MAC_CTRL1 0xC24 344 345 /* WoL Pattern Register */ 346 #define EDMA_REG_WOL_PATTERN_START 0x5000 347 #define EDMA_PATTERN_PART_REG_OFFSET 0x40 348 349 /* TX descriptor fields */ 350 #define EDMA_TPD_HDR_SHIFT 0 351 #define EDMA_TPD_PPPOE_EN 0x00000100 352 #define EDMA_TPD_IP_CSUM_EN 0x00000200 353 #define EDMA_TPD_TCP_CSUM_EN 0x0000400 354 #define EDMA_TPD_UDP_CSUM_EN 0x00000800 355 #define EDMA_TPD_CUSTOM_CSUM_EN 0x00000C00 356 #define EDMA_TPD_LSO_EN 0x00001000 357 #define EDMA_TPD_LSO_V2_EN 0x00002000 358 #define EDMA_TPD_IPV4_EN 0x00010000 359 #define EDMA_TPD_MSS_MASK 0x1FFF 360 #define EDMA_TPD_MSS_SHIFT 18 361 #define EDMA_TPD_CUSTOM_CSUM_SHIFT 18 362 #define EDMA_TPD_EOP 0x80000000 363 364 /* word3 */ 365 #define EDMA_TPD_PORT_BITMAP_SHIFT 18 366 #define EDMA_TPD_FROM_CPU_SHIFT 25 367 #define EDMA_FROM_CPU_MASK 0x80 368 369 /* TX descriptor - little endian */ 370 struct qcom_ess_edma_tx_desc { 371 uint16_t len; /* full packet including CRC */ 372 uint16_t svlan_tag; /* vlan tag */ 373 uint32_t word1; /* byte 4-7 */ 374 uint32_t addr; /* address of buffer */ 375 uint32_t word3; /* byte 12 */ 376 } __packed; 377 378 /* RRD descriptor fields */ 379 #define EDMA_RRD_NUM_RFD_MASK 0x000F 380 #define EDMA_RRD_SVLAN 0x8000 381 #define EDMA_RRD_FLOW_COOKIE_MASK 0x07FF 382 383 #define EDMA_RRD_PKT_SIZE_MASK 0x3FFF 384 #define EDMA_RRD_CSUM_FAIL_MASK 0xC000 385 #define EDMA_RRD_CVLAN 0x0001 386 #define EDMA_RRD_DESC_VALID 0x8000 387 388 #define EDMA_RRD_PRIORITY_SHIFT 4 389 #define EDMA_RRD_PRIORITY_MASK 0x7 390 #define EDMA_RRD_PORT_TYPE_SHIFT 7 391 #define EDMA_RRD_PORT_TYPE_MASK 0x1F 392 393 #define EDMA_PORT_ID_SHIFT 12 394 #define EDMA_PORT_ID_MASK 0x7 395 396 /* RX RRD descriptor - 16 bytes */ 397 struct qcom_edma_rx_return_desc { 398 uint16_t rrd0; 399 uint16_t rrd1; 400 uint16_t rrd2; 401 uint16_t rrd3; 402 uint16_t rrd4; 403 uint16_t rrd5; 404 uint16_t rrd6; 405 uint16_t rrd7; 406 } __packed; 407 408 409 /* RX RFD descriptor - little endian */ 410 struct qcom_ess_edma_rx_free_desc { 411 uint32_t addr; /* buffer addr */ 412 } __packed; 413 414 #define ESS_RGMII_CTRL 0x0004 415 416 /* Configurations */ 417 #define EDMA_INTR_CLEAR_TYPE 0 418 #define EDMA_INTR_SW_IDX_W_TYPE 0 419 #define EDMA_FIFO_THRESH_TYPE 0 420 #define EDMA_RSS_TYPE 0 421 #define EDMA_RX_IMT 0x0020 422 #define EDMA_TX_IMT 0x0050 423 #define EDMA_TPD_BURST 5 424 #define EDMA_TXF_BURST 0x100 425 #define EDMA_RFD_BURST 8 426 #define EDMA_RFD_THR 16 427 #define EDMA_RFD_LTHR 0 428 429 #endif /* __QCOM_ESS_EDMA_REG_H__ */ 430