1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef __FCOE_COMMON__ 30 #define __FCOE_COMMON__ 31 /*********************/ 32 /* FCOE FW CONSTANTS */ 33 /*********************/ 34 35 #define FC_ABTS_REPLY_MAX_PAYLOAD_LEN 12 36 37 /* 38 * The fcoe storm task context protection-information of Ystorm 39 */ 40 struct protection_info_ctx 41 { 42 __le16 flags; 43 #define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK 0x3 /* 0=none, 1=DIF, 2=DIX */ 44 #define PROTECTION_INFO_CTX_HOST_INTERFACE_SHIFT 0 45 #define PROTECTION_INFO_CTX_DIF_TO_PEER_MASK 0x1 /* 0=no, 1=yes */ 46 #define PROTECTION_INFO_CTX_DIF_TO_PEER_SHIFT 2 47 #define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_MASK 0x1 /* 0=no, 1=yes */ 48 #define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_SHIFT 3 49 #define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_MASK 0xF /* Protection log interval (9=512 10=1024 11=2048 12=4096 13=8192) */ 50 #define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_SHIFT 4 51 #define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1 /* 0=no, 1=yes */ 52 #define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_SHIFT 8 53 #define PROTECTION_INFO_CTX_RESERVED0_MASK 0x7F 54 #define PROTECTION_INFO_CTX_RESERVED0_SHIFT 9 55 u8 dix_block_size /* Source protection data size */; 56 u8 dst_size /* Destination protection data size */; 57 }; 58 59 /* 60 * The fcoe storm task context protection-information of Ystorm 61 */ 62 union protection_info_union_ctx 63 { 64 struct protection_info_ctx info; 65 __le32 value /* If and only if this field is not 0 then protection is set */; 66 }; 67 68 /* 69 * FCP CMD payload 70 */ 71 struct fcoe_fcp_cmd_payload 72 { 73 __le32 opaque[8] /* The FCP_CMD payload */; 74 }; 75 76 /* 77 * FCP RSP payload 78 */ 79 struct fcoe_fcp_rsp_payload 80 { 81 __le32 opaque[6] /* The FCP_RSP payload */; 82 }; 83 84 /* 85 * FCP RSP payload 86 */ 87 struct fcp_rsp_payload_padded 88 { 89 struct fcoe_fcp_rsp_payload rsp_payload /* The FCP_RSP payload */; 90 __le32 reserved[2]; 91 }; 92 93 /* 94 * FCP RSP payload 95 */ 96 struct fcoe_fcp_xfer_payload 97 { 98 __le32 opaque[3] /* The FCP_XFER payload */; 99 }; 100 101 /* 102 * FCP RSP payload 103 */ 104 struct fcp_xfer_payload_padded 105 { 106 struct fcoe_fcp_xfer_payload xfer_payload /* The FCP_XFER payload */; 107 __le32 reserved[5]; 108 }; 109 110 /* 111 * Task params 112 */ 113 struct fcoe_tx_data_params 114 { 115 __le32 data_offset /* Data offset */; 116 __le32 offset_in_io /* For sequence cleanup */; 117 u8 flags; 118 #define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_MASK 0x1 /* Should we send offset in IO */ 119 #define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_SHIFT 0 120 #define FCOE_TX_DATA_PARAMS_DROP_DATA_MASK 0x1 /* Should the PBF drop this data */ 121 #define FCOE_TX_DATA_PARAMS_DROP_DATA_SHIFT 1 122 #define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_MASK 0x1 /* Indication if the task after seqqence recovery flow */ 123 #define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_SHIFT 2 124 #define FCOE_TX_DATA_PARAMS_RESERVED0_MASK 0x1F 125 #define FCOE_TX_DATA_PARAMS_RESERVED0_SHIFT 3 126 u8 dif_residual /* Residual from protection interval */; 127 __le16 seq_cnt /* Sequence counter */; 128 __le16 single_sge_saved_offset /* Saved SGE length for single SGE case */; 129 __le16 next_dif_offset /* Tracking next DIF offset in FC payload */; 130 __le16 seq_id /* Sequence ID (Set [saved] upon seq_cnt==0 (start of sequence) and used throughout sequence) */; 131 __le16 reserved3; 132 }; 133 134 /* 135 * Middle path parameters: FC header fields provided by the driver 136 */ 137 struct fcoe_tx_mid_path_params 138 { 139 __le32 parameter; 140 u8 r_ctl; 141 u8 type; 142 u8 cs_ctl; 143 u8 df_ctl; 144 __le16 rx_id; 145 __le16 ox_id; 146 }; 147 148 /* 149 * Task params 150 */ 151 struct fcoe_tx_params 152 { 153 struct fcoe_tx_data_params data /* Data offset */; 154 struct fcoe_tx_mid_path_params mid_path; 155 }; 156 157 /* 158 * Union of FCP CMD payload \ TX params \ ABTS \ Cleanup 159 */ 160 union fcoe_tx_info_union_ctx 161 { 162 struct fcoe_fcp_cmd_payload fcp_cmd_payload /* FCP CMD payload */; 163 struct fcp_rsp_payload_padded fcp_rsp_payload /* FCP RSP payload */; 164 struct fcp_xfer_payload_padded fcp_xfer_payload /* FCP XFER payload */; 165 struct fcoe_tx_params tx_params /* Task TX params */; 166 }; 167 168 /* 169 * Data sgl 170 */ 171 struct fcoe_slow_sgl_ctx 172 { 173 struct regpair base_sgl_addr /* Address of first SGE in SGL */; 174 __le16 curr_sge_off /* Offset in current BD (in bytes) */; 175 __le16 remainder_num_sges /* Number of BDs */; 176 __le16 curr_sgl_index /* Index of current SGE */; 177 __le16 reserved; 178 }; 179 180 /* 181 * Union of DIX SGL \ cached DIX sges 182 */ 183 union fcoe_dix_desc_ctx 184 { 185 struct fcoe_slow_sgl_ctx dix_sgl /* DIX slow-SGL data base */; 186 struct scsi_sge cached_dix_sge /* Cached DIX sge */; 187 }; 188 189 /* 190 * The fcoe storm task context of Ystorm 191 */ 192 struct ystorm_fcoe_task_st_ctx 193 { 194 u8 task_type /* Task type. use enum fcoe_task_type (use enum fcoe_task_type) */; 195 u8 sgl_mode; 196 #define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1 /* use enum scsi_sgl_mode (use enum scsi_sgl_mode) */ 197 #define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 0 198 #define YSTORM_FCOE_TASK_ST_CTX_RSRV_MASK 0x7F 199 #define YSTORM_FCOE_TASK_ST_CTX_RSRV_SHIFT 1 200 u8 cached_dix_sge /* Dix sge is cached on task context */; 201 u8 expect_first_xfer /* Will let Ystorm know when it should initialize fcp_cmd_payload_params_union.params */; 202 __le32 num_pbf_zero_write /* The amount of bytes that PBF should dummy write - Relevant for protection only. */; 203 union protection_info_union_ctx protection_info_union /* Protection information */; 204 __le32 data_2_trns_rem /* Entire SGL-buffer remainder */; 205 struct scsi_sgl_params sgl_params; 206 u8 reserved1[12]; 207 union fcoe_tx_info_union_ctx tx_info_union /* Union of FCP CMD payload / TX params / ABTS / Cleanup */; 208 union fcoe_dix_desc_ctx dix_desc /* Union of DIX SGL / cached DIX sges */; 209 struct scsi_cached_sges data_desc /* Data cached SGEs */; 210 __le16 ox_id /* OX-ID. Used in Target mode only */; 211 __le16 rx_id /* RX-ID. Used in Target mode only */; 212 __le32 task_rety_identifier /* Parameter field of the FCP CMDs FC header */; 213 u8 reserved2[8]; 214 }; 215 216 struct e4_ystorm_fcoe_task_ag_ctx 217 { 218 u8 byte0 /* cdu_validation */; 219 u8 byte1 /* state */; 220 __le16 word0 /* icid */; 221 u8 flags0; 222 #define E4_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF /* connection_type */ 223 #define E4_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0 224 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 225 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4 226 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 227 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 228 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 229 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6 230 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 231 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7 232 u8 flags1; 233 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 234 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0 235 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 236 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2 237 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */ 238 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 239 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 240 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6 241 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 242 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7 243 u8 flags2; 244 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 245 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0 246 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 247 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1 248 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 249 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2 250 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 251 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3 252 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 253 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4 254 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 255 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5 256 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 257 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6 258 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 259 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7 260 u8 byte2 /* byte2 */; 261 __le32 reg0 /* reg0 */; 262 u8 byte3 /* byte3 */; 263 u8 byte4 /* byte4 */; 264 __le16 rx_id /* word1 */; 265 __le16 word2 /* word2 */; 266 __le16 word3 /* word3 */; 267 __le16 word4 /* word4 */; 268 __le16 word5 /* word5 */; 269 __le32 reg1 /* reg1 */; 270 __le32 reg2 /* reg2 */; 271 }; 272 273 struct e4_tstorm_fcoe_task_ag_ctx 274 { 275 u8 reserved /* cdu_validation */; 276 u8 byte1 /* state */; 277 __le16 icid /* icid */; 278 u8 flags0; 279 #define E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 280 #define E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 281 #define E4_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 282 #define E4_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 283 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 284 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 285 #define E4_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1 /* bit2 */ 286 #define E4_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6 287 #define E4_TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1 /* bit3 */ 288 #define E4_TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7 289 u8 flags1; 290 #define E4_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1 /* bit4 */ 291 #define E4_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0 292 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 293 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1 294 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3 /* timer0cf */ 295 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2 296 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3 /* timer1cf */ 297 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4 298 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 299 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6 300 u8 flags2; 301 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 302 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0 303 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 /* cf4 */ 304 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2 305 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3 /* cf5 */ 306 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4 307 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3 /* cf6 */ 308 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6 309 u8 flags3; 310 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3 /* cf7 */ 311 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0 312 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1 /* cf0en */ 313 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2 314 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1 /* cf1en */ 315 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3 316 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 317 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4 318 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */ 319 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5 320 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1 /* cf4en */ 321 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6 322 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1 /* cf5en */ 323 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7 324 u8 flags4; 325 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1 /* cf6en */ 326 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0 327 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1 /* cf7en */ 328 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1 329 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 330 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2 331 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 332 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3 333 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 334 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4 335 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 336 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5 337 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 338 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6 339 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 340 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7 341 u8 cleanup_state /* byte2 */; 342 __le16 last_sent_tid /* word1 */; 343 __le32 rec_rr_tov_exp_timeout /* reg0 */; 344 u8 byte3 /* byte3 */; 345 u8 byte4 /* byte4 */; 346 __le16 word2 /* word2 */; 347 __le16 word3 /* word3 */; 348 __le16 word4 /* word4 */; 349 __le32 data_offset_end_of_seq /* reg1 */; 350 __le32 data_offset_next /* reg2 */; 351 }; 352 353 /* 354 * Cached data sges 355 */ 356 struct fcoe_exp_ro 357 { 358 __le32 data_offset /* data-offset */; 359 __le32 reserved /* High data-offset */; 360 }; 361 362 /* 363 * Union of Cleanup address \ expected relative offsets 364 */ 365 union fcoe_cleanup_addr_exp_ro_union 366 { 367 struct regpair abts_rsp_fc_payload_hi /* Abts flow: first 64 bits of fcPayload, out of 96 */; 368 struct fcoe_exp_ro exp_ro /* Expected relative offsets */; 369 }; 370 371 /* 372 * fields coppied from ABTSrsp pckt 373 */ 374 struct fcoe_abts_pkt 375 { 376 __le32 abts_rsp_fc_payload_lo /* Abts flow: last 32 bits of fcPayload, out of 96 */; 377 __le16 abts_rsp_rx_id /* Abts flow: rxId parameter of the abts packet */; 378 u8 abts_rsp_rctl /* Abts flow: rctl parameter of the abts packet */; 379 u8 reserved2; 380 }; 381 382 /* 383 * FW read- write (modifyable) part The fcoe task storm context of Tstorm 384 */ 385 struct fcoe_tstorm_fcoe_task_st_ctx_read_write 386 { 387 union fcoe_cleanup_addr_exp_ro_union cleanup_addr_exp_ro_union /* Union of Cleanup address / expected relative offsets */; 388 __le16 flags; 389 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_MASK 0x1 /* Rx SGL type. use enum scsi_sgl_mode (use enum scsi_sgl_mode) */ 390 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_SHIFT 0 391 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_MASK 0x1 /* Expected first frame flag */ 392 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_SHIFT 1 393 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_MASK 0x1 /* Sequence active */ 394 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_SHIFT 2 395 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_MASK 0x1 /* Sequence timeout for an active Sequence */ 396 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_SHIFT 3 397 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_MASK 0x1 /* Set by Data-in flow. Indicate that this exchange contains a single FCP DATA packet */ 398 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_SHIFT 4 399 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_MASK 0x1 /* The status of the current out of order received Sequence */ 400 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_SHIFT 5 401 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_MASK 0x3 /* number of additional CQE that will be produced for this task completion */ 402 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_SHIFT 6 403 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_MASK 0xFF 404 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_SHIFT 8 405 __le16 seq_cnt /* Sequence counter */; 406 u8 seq_id /* Sequence id */; 407 u8 ooo_rx_seq_id /* The last out of order received SEQ_ID */; 408 __le16 rx_id /* RX_ID of the exchange - should match each packet expect for the first */; 409 struct fcoe_abts_pkt abts_data /* The last out of order received SEQ_CNT */; 410 __le32 e_d_tov_exp_timeout_val /* E_D_TOV timer val (in msec) */; 411 __le16 ooo_rx_seq_cnt /* The last out of order received SEQ_CNT */; 412 __le16 reserved1; 413 }; 414 415 /* 416 * FW read only part The fcoe task storm context of Tstorm 417 */ 418 struct fcoe_tstorm_fcoe_task_st_ctx_read_only 419 { 420 u8 task_type /* Task type. use enum fcoe_task_type (use enum fcoe_task_type) */; 421 u8 dev_type /* Device type (disk or tape). use enum fcoe_device_type (use enum fcoe_device_type) */; 422 u8 conf_supported /* Confirmation supported indication */; 423 u8 glbl_q_num /* Global RQ/CQ num to be used for sense data placement/completion */; 424 __le32 cid /* CID which that tasks associated to */; 425 __le32 fcp_cmd_trns_size /* IO size as reflected in FCP CMD */; 426 __le32 rsrv; 427 }; 428 429 /* 430 * The fcoe task storm context of Tstorm 431 */ 432 struct tstorm_fcoe_task_st_ctx 433 { 434 struct fcoe_tstorm_fcoe_task_st_ctx_read_write read_write /* FW read- write (modifyable) part The fcoe task storm context of Tstorm */; 435 struct fcoe_tstorm_fcoe_task_st_ctx_read_only read_only /* FW read only part The fcoe task storm context of Tstorm */; 436 }; 437 438 struct e4_mstorm_fcoe_task_ag_ctx 439 { 440 u8 byte0 /* cdu_validation */; 441 u8 byte1 /* state */; 442 __le16 icid /* icid */; 443 u8 flags0; 444 #define E4_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 445 #define E4_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 446 #define E4_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 447 #define E4_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 448 #define E4_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1 /* exist_in_qm1 */ 449 #define E4_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5 450 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 451 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6 452 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 453 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7 454 u8 flags1; 455 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 /* cf0 */ 456 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0 457 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 458 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2 459 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */ 460 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4 461 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1 /* cf0en */ 462 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6 463 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 464 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7 465 u8 flags2; 466 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 467 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0 468 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 469 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1 470 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 471 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2 472 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 473 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3 474 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 475 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4 476 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 477 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5 478 #define E4_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1 /* rule5en */ 479 #define E4_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6 480 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 481 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7 482 u8 cleanup_state /* byte2 */; 483 __le32 received_bytes /* reg0 */; 484 u8 byte3 /* byte3 */; 485 u8 glbl_q_num /* byte4 */; 486 __le16 word1 /* word1 */; 487 __le16 tid_to_xfer /* word2 */; 488 __le16 word3 /* word3 */; 489 __le16 word4 /* word4 */; 490 __le16 word5 /* word5 */; 491 __le32 expected_bytes /* reg1 */; 492 __le32 reg2 /* reg2 */; 493 }; 494 495 /* 496 * The fcoe task storm context of Mstorm 497 */ 498 struct mstorm_fcoe_task_st_ctx 499 { 500 struct regpair rsp_buf_addr /* Buffer to place the sense/response data attached to FCP_RSP frame */; 501 __le32 rsrv[2]; 502 struct scsi_sgl_params sgl_params; 503 __le32 data_2_trns_rem /* Entire SGL buffer size remainder */; 504 __le32 data_buffer_offset /* Buffer offset */; 505 __le16 parent_id /* Used for multiple continuation in Target mode */; 506 __le16 flags; 507 #define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_MASK 0xF /* Protection log interval (9=512 10=1024 11=2048 12=4096 13=8192) */ 508 #define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_SHIFT 0 509 #define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_MASK 0x3 /* 0=none, 1=DIF, 2=DIX */ 510 #define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_SHIFT 4 511 #define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_MASK 0x1 /* 0=no, 1=yes */ 512 #define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_SHIFT 6 513 #define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_MASK 0x1 /* 0 = 24 Bytes FC Header not included in Middle-Path placement, 1 = 24 Bytes FC Header included in MP placement */ 514 #define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_SHIFT 7 515 #define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_MASK 0x3 /* DIX block size: can be 0:2B, 1:4B, 2:8B */ 516 #define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_SHIFT 8 517 #define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1 /* 0=no, 1=yes */ 518 #define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_SHIFT 10 519 #define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_MASK 0x1 /* Indication to a single cached DIX SGE instead of SGL */ 520 #define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_SHIFT 11 521 #define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_MASK 0x1 522 #define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_SHIFT 12 523 #define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1 /* use_enum scsi_sgl_mode (use enum scsi_sgl_mode) */ 524 #define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 13 525 #define MSTORM_FCOE_TASK_ST_CTX_RESERVED_MASK 0x3 526 #define MSTORM_FCOE_TASK_ST_CTX_RESERVED_SHIFT 14 527 struct scsi_cached_sges data_desc /* Union of Data SGL / cached sge */; 528 }; 529 530 struct e4_ustorm_fcoe_task_ag_ctx 531 { 532 u8 reserved /* cdu_validation */; 533 u8 byte1 /* state */; 534 __le16 icid /* icid */; 535 u8 flags0; 536 #define E4_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 537 #define E4_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 538 #define E4_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 539 #define E4_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 540 #define E4_USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 541 #define E4_USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 542 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 543 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6 544 u8 flags1; 545 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 546 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0 547 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 548 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2 549 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 550 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4 551 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 /* cf4 */ 552 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 553 u8 flags2; 554 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 555 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0 556 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 557 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1 558 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 559 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2 560 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 561 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3 562 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 /* cf4en */ 563 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 564 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 565 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5 566 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 567 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6 568 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 569 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7 570 u8 flags3; 571 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 572 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0 573 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 574 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1 575 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 576 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2 577 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 578 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3 579 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF /* nibble1 */ 580 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 581 __le32 dif_err_intervals /* reg0 */; 582 __le32 dif_error_1st_interval /* reg1 */; 583 __le32 global_cq_num /* reg2 */; 584 __le32 reg3 /* reg3 */; 585 __le32 reg4 /* reg4 */; 586 __le32 reg5 /* reg5 */; 587 }; 588 589 /* 590 * fcoe task context 591 */ 592 struct e4_fcoe_task_context 593 { 594 struct ystorm_fcoe_task_st_ctx ystorm_st_context /* ystorm storm context */; 595 struct regpair ystorm_st_padding[2] /* padding */; 596 struct tdif_task_context tdif_context /* tdif context */; 597 struct e4_ystorm_fcoe_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */; 598 struct e4_tstorm_fcoe_task_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 599 struct timers_context timer_context /* timer context */; 600 struct tstorm_fcoe_task_st_ctx tstorm_st_context /* tstorm storm context */; 601 struct regpair tstorm_st_padding[2] /* padding */; 602 struct e4_mstorm_fcoe_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */; 603 struct mstorm_fcoe_task_st_ctx mstorm_st_context /* mstorm storm context */; 604 struct e4_ustorm_fcoe_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 605 struct rdif_task_context rdif_context /* rdif context */; 606 }; 607 608 struct e5_ystorm_fcoe_task_ag_ctx 609 { 610 u8 byte0 /* cdu_validation */; 611 u8 byte1 /* state_and_core_id */; 612 __le16 word0 /* icid */; 613 u8 flags0; 614 #define E5_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF /* connection_type */ 615 #define E5_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0 616 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 617 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4 618 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 619 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 620 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 621 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6 622 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 623 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7 624 u8 flags1; 625 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 626 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0 627 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 628 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2 629 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */ 630 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 631 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 632 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6 633 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 634 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7 635 u8 flags2; 636 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 637 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0 638 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 639 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1 640 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 641 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2 642 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 643 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3 644 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 645 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4 646 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 647 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5 648 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 649 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6 650 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 651 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7 652 u8 flags3; 653 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit5 */ 654 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_SHIFT 0 655 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_MASK 0x3 /* cf3 */ 656 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_SHIFT 1 657 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf4 */ 658 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_SHIFT 3 659 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* cf3en */ 660 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_SHIFT 5 661 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf4en */ 662 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_SHIFT 6 663 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule7en */ 664 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_SHIFT 7 665 __le32 reg0 /* reg0 */; 666 u8 byte2 /* byte2 */; 667 u8 byte3 /* byte3 */; 668 u8 byte4 /* byte4 */; 669 u8 e4_reserved7 /* byte5 */; 670 __le16 rx_id /* word1 */; 671 __le16 word2 /* word2 */; 672 __le16 word3 /* word3 */; 673 __le16 word4 /* word4 */; 674 __le16 word5 /* word5 */; 675 __le16 e4_reserved8 /* word6 */; 676 __le32 reg1 /* reg1 */; 677 }; 678 679 struct e5_tstorm_fcoe_task_ag_ctx 680 { 681 u8 reserved /* cdu_validation */; 682 u8 byte1 /* state_and_core_id */; 683 __le16 icid /* icid */; 684 u8 flags0; 685 #define E5_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 686 #define E5_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 687 #define E5_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 688 #define E5_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 689 #define E5_TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 690 #define E5_TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 691 #define E5_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1 /* bit2 */ 692 #define E5_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6 693 #define E5_TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1 /* bit3 */ 694 #define E5_TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7 695 u8 flags1; 696 #define E5_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1 /* bit4 */ 697 #define E5_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0 698 #define E5_TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 699 #define E5_TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1 700 #define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3 /* timer0cf */ 701 #define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2 702 #define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3 /* timer1cf */ 703 #define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4 704 #define E5_TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 705 #define E5_TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6 706 u8 flags2; 707 #define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 708 #define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0 709 #define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 /* cf4 */ 710 #define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2 711 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3 /* cf5 */ 712 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4 713 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3 /* cf6 */ 714 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6 715 u8 flags3; 716 #define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3 /* cf7 */ 717 #define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0 718 #define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1 /* cf0en */ 719 #define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2 720 #define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1 /* cf1en */ 721 #define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3 722 #define E5_TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 723 #define E5_TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4 724 #define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */ 725 #define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5 726 #define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1 /* cf4en */ 727 #define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6 728 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1 /* cf5en */ 729 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7 730 u8 flags4; 731 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1 /* cf6en */ 732 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0 733 #define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1 /* cf7en */ 734 #define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1 735 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 736 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2 737 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 738 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3 739 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 740 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4 741 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 742 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5 743 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 744 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6 745 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 746 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7 747 u8 cleanup_state /* byte2 */; 748 __le16 last_sent_tid /* word1 */; 749 __le32 rec_rr_tov_exp_timeout /* reg0 */; 750 u8 byte3 /* regpair0 */; 751 u8 byte4 /* byte4 */; 752 __le16 word2 /* word2 */; 753 __le16 word3 /* word3 */; 754 __le16 word4 /* word4 */; 755 __le32 data_offset_end_of_seq /* regpair1 */; 756 __le32 data_offset_next /* reg2 */; 757 }; 758 759 struct e5_mstorm_fcoe_task_ag_ctx 760 { 761 u8 byte0 /* cdu_validation */; 762 u8 byte1 /* state_and_core_id */; 763 __le16 icid /* icid */; 764 u8 flags0; 765 #define E5_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 766 #define E5_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 767 #define E5_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 768 #define E5_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 769 #define E5_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1 /* exist_in_qm1 */ 770 #define E5_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5 771 #define E5_MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 772 #define E5_MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6 773 #define E5_MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 774 #define E5_MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7 775 u8 flags1; 776 #define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 /* cf0 */ 777 #define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0 778 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 779 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2 780 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */ 781 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4 782 #define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1 /* cf0en */ 783 #define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6 784 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 785 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7 786 u8 flags2; 787 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 788 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0 789 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 790 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1 791 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 792 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2 793 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 794 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3 795 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 796 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4 797 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 798 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5 799 #define E5_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1 /* rule5en */ 800 #define E5_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6 801 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 802 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7 803 u8 flags3; 804 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit4 */ 805 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_SHIFT 0 806 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_MASK 0x3 /* cf3 */ 807 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_SHIFT 1 808 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf4 */ 809 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_SHIFT 3 810 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* cf3en */ 811 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_SHIFT 5 812 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf4en */ 813 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_SHIFT 6 814 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule7en */ 815 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_SHIFT 7 816 __le32 received_bytes /* reg0 */; 817 u8 cleanup_state /* byte2 */; 818 u8 byte3 /* byte3 */; 819 u8 glbl_q_num /* byte4 */; 820 u8 e4_reserved7 /* byte5 */; 821 __le16 word1 /* regpair0 */; 822 __le16 tid_to_xfer /* word2 */; 823 __le16 word3 /* word3 */; 824 __le16 word4 /* word4 */; 825 __le16 word5 /* regpair1 */; 826 __le16 e4_reserved8 /* word6 */; 827 __le32 expected_bytes /* reg1 */; 828 }; 829 830 struct e5_ustorm_fcoe_task_ag_ctx 831 { 832 u8 reserved /* cdu_validation */; 833 u8 byte1 /* state_and_core_id */; 834 __le16 icid /* icid */; 835 u8 flags0; 836 #define E5_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 837 #define E5_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 838 #define E5_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 839 #define E5_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 840 #define E5_USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 841 #define E5_USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 842 #define E5_USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 843 #define E5_USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6 844 u8 flags1; 845 #define E5_USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 846 #define E5_USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0 847 #define E5_USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 848 #define E5_USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2 849 #define E5_USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 850 #define E5_USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4 851 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 /* dif_error_cf */ 852 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 853 u8 flags2; 854 #define E5_USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 855 #define E5_USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0 856 #define E5_USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 857 #define E5_USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1 858 #define E5_USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 859 #define E5_USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2 860 #define E5_USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 861 #define E5_USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3 862 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 /* cf4en */ 863 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 864 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 865 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5 866 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 867 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6 868 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 869 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7 870 u8 flags3; 871 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 872 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0 873 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 874 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1 875 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 876 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2 877 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 878 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3 879 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 880 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_SHIFT 4 881 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 882 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_SHIFT 5 883 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit4 */ 884 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_SHIFT 6 885 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* rule7en */ 886 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_SHIFT 7 887 u8 flags4; 888 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_MASK 0x3 /* cf5 */ 889 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_SHIFT 0 890 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf5en */ 891 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_SHIFT 2 892 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule8en */ 893 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED7_SHIFT 3 894 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF /* dif_error_type */ 895 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 896 u8 byte2 /* byte2 */; 897 u8 byte3 /* byte3 */; 898 u8 e4_reserved8 /* byte4 */; 899 __le32 dif_err_intervals /* dif_err_intervals */; 900 __le32 dif_error_1st_interval /* dif_error_1st_interval */; 901 __le32 global_cq_num /* reg2 */; 902 __le32 reg3 /* reg3 */; 903 __le32 reg4 /* reg4 */; 904 }; 905 906 /* 907 * fcoe task context 908 */ 909 struct e5_fcoe_task_context 910 { 911 struct ystorm_fcoe_task_st_ctx ystorm_st_context /* ystorm storm context */; 912 struct regpair ystorm_st_padding[2] /* padding */; 913 struct tdif_task_context tdif_context /* tdif context */; 914 struct e5_ystorm_fcoe_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */; 915 struct e5_tstorm_fcoe_task_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 916 struct timers_context timer_context /* timer context */; 917 struct tstorm_fcoe_task_st_ctx tstorm_st_context /* tstorm storm context */; 918 struct regpair tstorm_st_padding[2] /* padding */; 919 struct e5_mstorm_fcoe_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */; 920 struct mstorm_fcoe_task_st_ctx mstorm_st_context /* mstorm storm context */; 921 struct e5_ustorm_fcoe_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 922 struct rdif_task_context rdif_context /* rdif context */; 923 }; 924 925 /* 926 * FCoE additional WQE (Sq/ XferQ) information 927 */ 928 union fcoe_additional_info_union 929 { 930 __le32 previous_tid /* Previous tid. Used for Send XFER WQEs in Multiple continuation mode - Target only. */; 931 __le32 parent_tid /* Parent tid. Used for write tasks in a continuation mode - Target only */; 932 __le32 burst_length /* The desired burst length. */; 933 __le32 seq_rec_updated_offset /* The updated offset in SGL - Used in sequence recovery */; 934 }; 935 936 /* 937 * FCoE Ramrod Command IDs 938 */ 939 enum fcoe_completion_status 940 { 941 FCOE_COMPLETION_STATUS_SUCCESS /* FCoE ramrod completed successfully */, 942 FCOE_COMPLETION_STATUS_FCOE_VER_ERR /* Wrong FCoE version */, 943 FCOE_COMPLETION_STATUS_SRC_MAC_ADD_ARR_ERR /* src_mac_arr for the current physical port is full- allocation failed */, 944 MAX_FCOE_COMPLETION_STATUS 945 }; 946 947 /* 948 * FC address (SID/DID) network presentation 949 */ 950 struct fc_addr_nw 951 { 952 u8 addr_lo /* First byte of the SID/DID address that comes/goes from/to the NW (for example if SID is 11:22:33 - this is 0x11) */; 953 u8 addr_mid; 954 u8 addr_hi; 955 }; 956 957 /* 958 * FCoE connection offload 959 */ 960 struct fcoe_conn_offload_ramrod_data 961 { 962 struct regpair sq_pbl_addr /* SQ Pbl base address */; 963 struct regpair sq_curr_page_addr /* SQ current page address */; 964 struct regpair sq_next_page_addr /* SQ next page address */; 965 struct regpair xferq_pbl_addr /* XFERQ Pbl base address */; 966 struct regpair xferq_curr_page_addr /* XFERQ current page address */; 967 struct regpair xferq_next_page_addr /* XFERQ next page address */; 968 struct regpair respq_pbl_addr /* RESPQ Pbl base address */; 969 struct regpair respq_curr_page_addr /* RESPQ current page address */; 970 struct regpair respq_next_page_addr /* RESPQ next page address */; 971 __le16 dst_mac_addr_lo /* First word of the MAC address that comes/goes from/to the NW (for example if MAC is 11:22:33:44:55:66 - this is 0x2211) */; 972 __le16 dst_mac_addr_mid; 973 __le16 dst_mac_addr_hi; 974 __le16 src_mac_addr_lo /* Source MAC address in NW order - First word of the MAC address that comes/goes from/to the NW (for example if MAC is 11:22:33:44:55:66 - this is 0x2211) */; 975 __le16 src_mac_addr_mid; 976 __le16 src_mac_addr_hi; 977 __le16 tx_max_fc_pay_len /* The maximum acceptable FC payload size (Buffer-to-buffer Receive Data_Field size) supported by target, received during both FLOGI and PLOGI, minimum value should be taken */; 978 __le16 e_d_tov_timer_val /* E_D_TOV timeout value in resolution of 1 msec */; 979 __le16 rx_max_fc_pay_len /* Maximum acceptable FC payload size supported by us */; 980 __le16 vlan_tag; 981 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_MASK 0xFFF /* Vlan id */ 982 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_SHIFT 0 983 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_MASK 0x1 /* Canonical format indicator */ 984 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_SHIFT 12 985 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_MASK 0x7 /* Vlan priority */ 986 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_SHIFT 13 987 __le16 physical_q0 /* Physical QM queue to be linked to logical queue 0 (fastPath queue) */; 988 __le16 rec_rr_tov_timer_val /* REC_TOV timeout value in resolution of 1 msec */; 989 struct fc_addr_nw s_id /* Source ID in NW order, received during FLOGI */; 990 u8 max_conc_seqs_c3 /* Maximum concurrent Sequences for Class 3 supported by target, received during PLOGI */; 991 struct fc_addr_nw d_id /* Destination ID in NW order, received after inquiry of the fabric network */; 992 u8 flags; 993 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_MASK 0x1 /* Continuously increasing SEQ_CNT indication, received during PLOGI */ 994 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_SHIFT 0 995 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_MASK 0x1 /* Confirmation request supported */ 996 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_SHIFT 1 997 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_MASK 0x1 /* REC allowed */ 998 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_SHIFT 2 999 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_MASK 0x1 /* Does inner vlan exist */ 1000 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_SHIFT 3 1001 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_SINGLE_VLAN_MASK 0x1 /* Does a single vlan (inner/outer) should be used. - UFP mode */ 1002 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_SINGLE_VLAN_SHIFT 4 1003 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_MASK 0x3 /* indication for conn mode: 0=Initiator, 1=Target, 2=Both Initiator and Traget */ 1004 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_SHIFT 5 1005 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_MASK 0x1 1006 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT 7 1007 __le16 conn_id /* Drivers connection ID. Should be sent in EQs to speed-up drivers access to connection data. */; 1008 u8 def_q_idx /* Default queue number to be used for unsolicited traffic */; 1009 u8 reserved[5]; 1010 }; 1011 1012 /* 1013 * FCoE terminate connection request 1014 */ 1015 struct fcoe_conn_terminate_ramrod_data 1016 { 1017 struct regpair terminate_params_addr /* Terminate params ptr */; 1018 }; 1019 1020 /* 1021 * FCoE device type 1022 */ 1023 enum fcoe_device_type 1024 { 1025 FCOE_TASK_DEV_TYPE_DISK, 1026 FCOE_TASK_DEV_TYPE_TAPE, 1027 MAX_FCOE_DEVICE_TYPE 1028 }; 1029 1030 /* 1031 * Data sgl 1032 */ 1033 struct fcoe_fast_sgl_ctx 1034 { 1035 struct regpair sgl_start_addr /* Current sge address */; 1036 __le32 sgl_byte_offset /* Byte offset from the beginning of the first page in the SGL. In case SGL starts in the middle of page then driver should init this value with the start offset */; 1037 __le16 task_reuse_cnt /* The reuse count for that task. Wrap ion 4K value. */; 1038 __le16 init_offset_in_first_sge /* offset from the beginning of the first page in the SGL, never changed by FW */; 1039 }; 1040 1041 /* 1042 * FCoE firmware function init 1043 */ 1044 struct fcoe_init_func_ramrod_data 1045 { 1046 struct scsi_init_func_params func_params /* Common SCSI init params passed by driver to FW in function init ramrod */; 1047 struct scsi_init_func_queues q_params /* SCSI RQ/CQ/CMDQ firmware function init parameters */; 1048 __le16 mtu /* Max transmission unit */; 1049 __le16 sq_num_pages_in_pbl /* Number of pages at Send Queue */; 1050 __le32 reserved[3]; 1051 }; 1052 1053 /* 1054 * FCoE: Mode of the connection: Target or Initiator or both 1055 */ 1056 enum fcoe_mode_type 1057 { 1058 FCOE_INITIATOR_MODE=0x0, 1059 FCOE_TARGET_MODE=0x1, 1060 FCOE_BOTH_OR_NOT_CHOSEN=0x3, 1061 MAX_FCOE_MODE_TYPE 1062 }; 1063 1064 /* 1065 * Per PF FCoE receive path statistics - tStorm RAM structure 1066 */ 1067 struct fcoe_rx_stat 1068 { 1069 struct regpair fcoe_rx_byte_cnt /* Number of FCoE bytes that were received */; 1070 struct regpair fcoe_rx_data_pkt_cnt /* Number of FCoE FCP DATA packets that were received */; 1071 struct regpair fcoe_rx_xfer_pkt_cnt /* Number of FCoE FCP XFER RDY packets that were received */; 1072 struct regpair fcoe_rx_other_pkt_cnt /* Number of FCoE packets which are not DATA/XFER_RDY that were received */; 1073 __le32 fcoe_silent_drop_pkt_cmdq_full_cnt /* Number of packets that were silently dropped since CMDQ was full */; 1074 __le32 fcoe_silent_drop_pkt_rq_full_cnt /* Number of packets that were silently dropped since RQ (BDQ) was full */; 1075 __le32 fcoe_silent_drop_pkt_crc_error_cnt /* Number of packets that were silently dropped due to FC CRC error */; 1076 __le32 fcoe_silent_drop_pkt_task_invalid_cnt /* Number of packets that were silently dropped since task was not valid */; 1077 __le32 fcoe_silent_drop_total_pkt_cnt /* Number of FCoE packets that were silently dropped */; 1078 __le32 rsrv; 1079 }; 1080 1081 /* 1082 * FCoE SQE request type 1083 */ 1084 enum fcoe_sqe_request_type 1085 { 1086 SEND_FCOE_CMD, 1087 SEND_FCOE_MIDPATH, 1088 SEND_FCOE_ABTS_REQUEST, 1089 FCOE_EXCHANGE_CLEANUP, 1090 FCOE_SEQUENCE_RECOVERY, 1091 SEND_FCOE_XFER_RDY, 1092 SEND_FCOE_RSP, 1093 SEND_FCOE_RSP_WITH_SENSE_DATA, 1094 SEND_FCOE_TARGET_DATA, 1095 SEND_FCOE_INITIATOR_DATA, 1096 SEND_FCOE_XFER_CONTINUATION_RDY /* Xfer Continuation (==1) ready to be sent. Previous XFERs data received successfully. */, 1097 SEND_FCOE_TARGET_ABTS_RSP, 1098 MAX_FCOE_SQE_REQUEST_TYPE 1099 }; 1100 1101 /* 1102 * FCoe statistics request 1103 */ 1104 struct fcoe_stat_ramrod_data 1105 { 1106 struct regpair stat_params_addr /* Statistics host address */; 1107 }; 1108 1109 /* 1110 * FCoE task type 1111 */ 1112 enum fcoe_task_type 1113 { 1114 FCOE_TASK_TYPE_WRITE_INITIATOR, 1115 FCOE_TASK_TYPE_READ_INITIATOR, 1116 FCOE_TASK_TYPE_MIDPATH, 1117 FCOE_TASK_TYPE_UNSOLICITED, 1118 FCOE_TASK_TYPE_ABTS, 1119 FCOE_TASK_TYPE_EXCHANGE_CLEANUP, 1120 FCOE_TASK_TYPE_SEQUENCE_CLEANUP, 1121 FCOE_TASK_TYPE_WRITE_TARGET, 1122 FCOE_TASK_TYPE_READ_TARGET, 1123 FCOE_TASK_TYPE_RSP, 1124 FCOE_TASK_TYPE_RSP_SENSE_DATA, 1125 FCOE_TASK_TYPE_ABTS_TARGET, 1126 FCOE_TASK_TYPE_ENUM_SIZE, 1127 MAX_FCOE_TASK_TYPE 1128 }; 1129 1130 /* 1131 * Per PF FCoE transmit path statistics - pStorm RAM structure 1132 */ 1133 struct fcoe_tx_stat 1134 { 1135 struct regpair fcoe_tx_byte_cnt /* Transmitted FCoE bytes count */; 1136 struct regpair fcoe_tx_data_pkt_cnt /* Transmitted FCoE FCP DATA packets count */; 1137 struct regpair fcoe_tx_xfer_pkt_cnt /* Transmitted FCoE XFER_RDY packets count */; 1138 struct regpair fcoe_tx_other_pkt_cnt /* Transmitted FCoE packets which are not DATA/XFER_RDY count */; 1139 }; 1140 1141 /* 1142 * FCoE SQ/XferQ element 1143 */ 1144 struct fcoe_wqe 1145 { 1146 __le16 task_id /* Initiator - The task identifier (OX_ID). Target - Continuation tid or RX_ID in non-continuation mode */; 1147 __le16 flags; 1148 #define FCOE_WQE_REQ_TYPE_MASK 0xF /* Type of the wqe request. use enum fcoe_sqe_request_type (use enum fcoe_sqe_request_type) */ 1149 #define FCOE_WQE_REQ_TYPE_SHIFT 0 1150 #define FCOE_WQE_SGL_MODE_MASK 0x1 /* The driver will give a hint about sizes of SGEs for better credits evaluation at Xstorm. use enum scsi_sgl_mode (use enum scsi_sgl_mode) */ 1151 #define FCOE_WQE_SGL_MODE_SHIFT 4 1152 #define FCOE_WQE_CONTINUATION_MASK 0x1 /* Indication if this wqe is a continuation to an existing task (Target only) */ 1153 #define FCOE_WQE_CONTINUATION_SHIFT 5 1154 #define FCOE_WQE_SEND_AUTO_RSP_MASK 0x1 /* Indication to FW to send FCP_RSP after all data was sent - Target only */ 1155 #define FCOE_WQE_SEND_AUTO_RSP_SHIFT 6 1156 #define FCOE_WQE_RESERVED_MASK 0x1 1157 #define FCOE_WQE_RESERVED_SHIFT 7 1158 #define FCOE_WQE_NUM_SGES_MASK 0xF /* Number of SGEs. 8 = at least 8 sges */ 1159 #define FCOE_WQE_NUM_SGES_SHIFT 8 1160 #define FCOE_WQE_RESERVED1_MASK 0xF 1161 #define FCOE_WQE_RESERVED1_SHIFT 12 1162 union fcoe_additional_info_union additional_info_union /* Additional wqe information (if needed) */; 1163 }; 1164 1165 /* 1166 * FCoE XFRQ element 1167 */ 1168 struct xfrqe_prot_flags 1169 { 1170 u8 flags; 1171 #define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK 0xF /* Protection log interval (9=512 10=1024 11=2048 12=4096 13=8192) */ 1172 #define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0 1173 #define XFRQE_PROT_FLAGS_DIF_TO_PEER_MASK 0x1 /* If DIF protection is configured against target (0=no, 1=yes) */ 1174 #define XFRQE_PROT_FLAGS_DIF_TO_PEER_SHIFT 4 1175 #define XFRQE_PROT_FLAGS_HOST_INTERFACE_MASK 0x3 /* If DIF/DIX protection is configured against the host (0=none, 1=DIF, 2=DIX) */ 1176 #define XFRQE_PROT_FLAGS_HOST_INTERFACE_SHIFT 5 1177 #define XFRQE_PROT_FLAGS_RESERVED_MASK 0x1 /* Must set to 0 */ 1178 #define XFRQE_PROT_FLAGS_RESERVED_SHIFT 7 1179 }; 1180 1181 /* 1182 * FCoE doorbell data 1183 */ 1184 struct fcoe_db_data 1185 { 1186 u8 params; 1187 #define FCOE_DB_DATA_DEST_MASK 0x3 /* destination of doorbell (use enum db_dest) */ 1188 #define FCOE_DB_DATA_DEST_SHIFT 0 1189 #define FCOE_DB_DATA_AGG_CMD_MASK 0x3 /* aggregative command to CM (use enum db_agg_cmd_sel) */ 1190 #define FCOE_DB_DATA_AGG_CMD_SHIFT 2 1191 #define FCOE_DB_DATA_BYPASS_EN_MASK 0x1 /* enable QM bypass */ 1192 #define FCOE_DB_DATA_BYPASS_EN_SHIFT 4 1193 #define FCOE_DB_DATA_RESERVED_MASK 0x1 1194 #define FCOE_DB_DATA_RESERVED_SHIFT 5 1195 #define FCOE_DB_DATA_AGG_VAL_SEL_MASK 0x3 /* aggregative value selection */ 1196 #define FCOE_DB_DATA_AGG_VAL_SEL_SHIFT 6 1197 u8 agg_flags /* bit for every DQ counter flags in CM context that DQ can increment */; 1198 __le16 sq_prod; 1199 }; 1200 1201 #endif /* __FCOE_COMMON__ */ 1202