1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
3
4 Copyright (c) 2001-2020, Intel Corporation
5 All rights reserved.
6
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
12
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
16
17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
20
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32
33 ******************************************************************************/
34
35 /*
36 * 82575EB Gigabit Network Connection
37 * 82575EB Gigabit Backplane Connection
38 * 82575GB Gigabit Network Connection
39 * 82576 Gigabit Network Connection
40 * 82576 Quad Port Gigabit Mezzanine Adapter
41 * 82580 Gigabit Network Connection
42 * I350 Gigabit Network Connection
43 */
44
45 #include "e1000_api.h"
46 #include "e1000_i210.h"
47
48 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
49 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
50 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
51 static void e1000_release_nvm_82575(struct e1000_hw *hw);
52 static s32 e1000_check_for_link_82575(struct e1000_hw *hw);
53 static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw);
54 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
55 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
56 u16 *duplex);
57 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
58 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
59 u16 *data);
60 static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
61 static s32 e1000_init_hw_82575(struct e1000_hw *hw);
62 static s32 e1000_reset_hw_82580(struct e1000_hw *hw);
63 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
64 u32 offset, u16 *data);
65 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
66 u32 offset, u16 data);
67 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
68 bool active);
69 static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
70 bool active);
71 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
72 bool active);
73 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
74 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
75 static s32 e1000_get_media_type_82575(struct e1000_hw *hw);
76 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
77 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
78 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
79 u32 offset, u16 data);
80 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
81 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
82 u16 *speed, u16 *duplex);
83 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
84 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
85 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
86 static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
87 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
88 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
89 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
90 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
91 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
92 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
93 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
94 u16 offset);
95 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
96 u16 offset);
97 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
98 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
99 static void e1000_clear_vfta_i350(struct e1000_hw *hw);
100
101 static void e1000_i2c_start(struct e1000_hw *hw);
102 static void e1000_i2c_stop(struct e1000_hw *hw);
103 static void e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
104 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
105 static s32 e1000_get_i2c_ack(struct e1000_hw *hw);
106 static void e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
107 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
108 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
109 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
110 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
111 static bool e1000_get_i2c_data(u32 *i2cctl);
112
113 static const u16 e1000_82580_rxpbs_table[] = {
114 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
115 #define E1000_82580_RXPBS_TABLE_SIZE \
116 (sizeof(e1000_82580_rxpbs_table) / \
117 sizeof(e1000_82580_rxpbs_table[0]))
118
119
120 /**
121 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
122 * @hw: pointer to the HW structure
123 *
124 * Called to determine if the I2C pins are being used for I2C or as an
125 * external MDIO interface since the two options are mutually exclusive.
126 **/
e1000_sgmii_uses_mdio_82575(struct e1000_hw * hw)127 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
128 {
129 u32 reg = 0;
130 bool ext_mdio = false;
131
132 DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
133
134 switch (hw->mac.type) {
135 case e1000_82575:
136 case e1000_82576:
137 reg = E1000_READ_REG(hw, E1000_MDIC);
138 ext_mdio = !!(reg & E1000_MDIC_DEST);
139 break;
140 case e1000_82580:
141 case e1000_i350:
142 case e1000_i354:
143 case e1000_i210:
144 case e1000_i211:
145 reg = E1000_READ_REG(hw, E1000_MDICNFG);
146 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
147 break;
148 default:
149 break;
150 }
151 return ext_mdio;
152 }
153
154 /**
155 * e1000_init_phy_params_82575 - Initialize PHY function ptrs
156 * @hw: pointer to the HW structure
157 **/
e1000_init_phy_params_82575(struct e1000_hw * hw)158 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
159 {
160 struct e1000_phy_info *phy = &hw->phy;
161 s32 ret_val = E1000_SUCCESS;
162 u32 ctrl_ext;
163
164 DEBUGFUNC("e1000_init_phy_params_82575");
165
166 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
167 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
168
169 if (hw->phy.media_type != e1000_media_type_copper) {
170 phy->type = e1000_phy_none;
171 goto out;
172 }
173
174 phy->ops.power_up = e1000_power_up_phy_copper;
175 phy->ops.power_down = e1000_power_down_phy_copper_base;
176
177 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
178 phy->reset_delay_us = 100;
179
180 phy->ops.acquire = e1000_acquire_phy_base;
181 phy->ops.check_reset_block = e1000_check_reset_block_generic;
182 phy->ops.commit = e1000_phy_sw_reset_generic;
183 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
184 phy->ops.release = e1000_release_phy_base;
185
186 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
187
188 if (e1000_sgmii_active_82575(hw)) {
189 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
190 ctrl_ext |= E1000_CTRL_I2C_ENA;
191 } else {
192 phy->ops.reset = e1000_phy_hw_reset_generic;
193 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
194 }
195
196 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
197 e1000_reset_mdicnfg_82580(hw);
198
199 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
200 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
201 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
202 } else {
203 switch (hw->mac.type) {
204 case e1000_82580:
205 case e1000_i350:
206 case e1000_i354:
207 phy->ops.read_reg = e1000_read_phy_reg_82580;
208 phy->ops.write_reg = e1000_write_phy_reg_82580;
209 break;
210 case e1000_i210:
211 case e1000_i211:
212 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
213 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
214 break;
215 default:
216 phy->ops.read_reg = e1000_read_phy_reg_igp;
217 phy->ops.write_reg = e1000_write_phy_reg_igp;
218 }
219 }
220
221 /* Set phy->phy_addr and phy->id. */
222 ret_val = e1000_get_phy_id_82575(hw);
223
224 /* Verify phy id and set remaining function pointers */
225 switch (phy->id) {
226 case M88E1543_E_PHY_ID:
227 case M88E1512_E_PHY_ID:
228 case I347AT4_E_PHY_ID:
229 case M88E1112_E_PHY_ID:
230 case M88E1340M_E_PHY_ID:
231 phy->type = e1000_phy_m88;
232 phy->ops.check_polarity = e1000_check_polarity_m88;
233 phy->ops.get_info = e1000_get_phy_info_m88;
234 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
235 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
236 break;
237 case M88E1111_I_PHY_ID:
238 phy->type = e1000_phy_m88;
239 phy->ops.check_polarity = e1000_check_polarity_m88;
240 phy->ops.get_info = e1000_get_phy_info_m88;
241 phy->ops.get_cable_length = e1000_get_cable_length_m88;
242 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
243 break;
244 case IGP03E1000_E_PHY_ID:
245 case IGP04E1000_E_PHY_ID:
246 phy->type = e1000_phy_igp_3;
247 phy->ops.check_polarity = e1000_check_polarity_igp;
248 phy->ops.get_info = e1000_get_phy_info_igp;
249 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
250 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
251 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
252 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
253 break;
254 case I82580_I_PHY_ID:
255 case I350_I_PHY_ID:
256 phy->type = e1000_phy_82580;
257 phy->ops.check_polarity = e1000_check_polarity_82577;
258 phy->ops.get_info = e1000_get_phy_info_82577;
259 phy->ops.get_cable_length = e1000_get_cable_length_82577;
260 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
261 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
262 phy->ops.force_speed_duplex =
263 e1000_phy_force_speed_duplex_82577;
264 break;
265 case I210_I_PHY_ID:
266 phy->type = e1000_phy_i210;
267 phy->ops.check_polarity = e1000_check_polarity_m88;
268 phy->ops.get_info = e1000_get_phy_info_m88;
269 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
270 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
271 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
272 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
273 break;
274 default:
275 ret_val = -E1000_ERR_PHY;
276 goto out;
277 }
278
279 /* Check if this PHY is configured for media swap. */
280 switch (phy->id) {
281 case M88E1112_E_PHY_ID:
282 {
283 u16 data;
284
285 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 2);
286 if (ret_val)
287 goto out;
288 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_MAC_CTRL_1,
289 &data);
290 if (ret_val)
291 goto out;
292
293 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
294 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
295 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
296 data == E1000_M88E1112_AUTO_COPPER_BASEX)
297 hw->mac.ops.check_for_link =
298 e1000_check_for_link_media_swap;
299 break;
300 }
301 case M88E1512_E_PHY_ID:
302 {
303 ret_val = e1000_initialize_M88E1512_phy(hw);
304 break;
305 }
306 case M88E1543_E_PHY_ID:
307 {
308 ret_val = e1000_initialize_M88E1543_phy(hw);
309 break;
310 }
311 default:
312 goto out;
313 }
314
315 out:
316 return ret_val;
317 }
318
319 /**
320 * e1000_init_mac_params_82575 - Init MAC func ptrs.
321 * @hw: pointer to the HW structure
322 **/
e1000_init_mac_params_82575(struct e1000_hw * hw)323 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
324 {
325 struct e1000_mac_info *mac = &hw->mac;
326 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
327
328 DEBUGFUNC("e1000_init_mac_params_82575");
329
330 /* Initialize function pointer */
331 e1000_init_mac_ops_generic(hw);
332
333 /* Derives media type */
334 e1000_get_media_type_82575(hw);
335 /* Set MTA register count */
336 mac->mta_reg_count = 128;
337 /* Set UTA register count */
338 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
339 /* Set RAR entry count */
340 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
341 if (mac->type == e1000_82576)
342 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
343 if (mac->type == e1000_82580)
344 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
345 if (mac->type == e1000_i350 || mac->type == e1000_i354)
346 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
347
348 /* Enable EEE default settings for EEE supported devices */
349 if (mac->type >= e1000_i350)
350 dev_spec->eee_disable = false;
351
352 /* Allow a single clear of the SW semaphore on I210 and newer */
353 if (mac->type >= e1000_i210)
354 dev_spec->clear_semaphore_once = true;
355
356 /* Set if part includes ASF firmware */
357 mac->asf_firmware_present = true;
358 /* FWSM register */
359 mac->has_fwsm = true;
360 /* ARC supported; valid only if manageability features are enabled. */
361 mac->arc_subsystem_valid =
362 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
363
364 /* Function pointers */
365
366 /* bus type/speed/width */
367 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
368 /* reset */
369 if (mac->type >= e1000_82580)
370 mac->ops.reset_hw = e1000_reset_hw_82580;
371 else
372 mac->ops.reset_hw = e1000_reset_hw_82575;
373 /* HW initialization */
374 if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
375 mac->ops.init_hw = e1000_init_hw_i210;
376 else
377 mac->ops.init_hw = e1000_init_hw_82575;
378 /* link setup */
379 mac->ops.setup_link = e1000_setup_link_generic;
380 /* physical interface link setup */
381 mac->ops.setup_physical_interface =
382 (hw->phy.media_type == e1000_media_type_copper)
383 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
384 /* physical interface shutdown */
385 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
386 /* physical interface power up */
387 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
388 /* check for link */
389 mac->ops.check_for_link = e1000_check_for_link_82575;
390 /* read mac address */
391 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
392 /* configure collision distance */
393 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
394 /* multicast address update */
395 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
396 if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
397 /* writing VFTA */
398 mac->ops.write_vfta = e1000_write_vfta_i350;
399 /* clearing VFTA */
400 mac->ops.clear_vfta = e1000_clear_vfta_i350;
401 } else {
402 /* writing VFTA */
403 mac->ops.write_vfta = e1000_write_vfta_generic;
404 /* clearing VFTA */
405 mac->ops.clear_vfta = e1000_clear_vfta_generic;
406 }
407 if (hw->mac.type >= e1000_82580)
408 mac->ops.validate_mdi_setting =
409 e1000_validate_mdi_setting_crossover_generic;
410 /* ID LED init */
411 mac->ops.id_led_init = e1000_id_led_init_generic;
412 /* blink LED */
413 mac->ops.blink_led = e1000_blink_led_generic;
414 /* setup LED */
415 mac->ops.setup_led = e1000_setup_led_generic;
416 /* cleanup LED */
417 mac->ops.cleanup_led = e1000_cleanup_led_generic;
418 /* turn on/off LED */
419 mac->ops.led_on = e1000_led_on_generic;
420 mac->ops.led_off = e1000_led_off_generic;
421 /* clear hardware counters */
422 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
423 /* link info */
424 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
425 /* acquire SW_FW sync */
426 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync;
427 /* release SW_FW sync */
428 mac->ops.release_swfw_sync = e1000_release_swfw_sync;
429
430 /* set lan id for port to determine which phy lock to use */
431 hw->mac.ops.set_lan_id(hw);
432
433 return E1000_SUCCESS;
434 }
435
436 /**
437 * e1000_init_nvm_params_82575 - Initialize NVM function ptrs
438 * @hw: pointer to the HW structure
439 **/
e1000_init_nvm_params_82575(struct e1000_hw * hw)440 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
441 {
442 struct e1000_nvm_info *nvm = &hw->nvm;
443 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
444 u16 size;
445
446 DEBUGFUNC("e1000_init_nvm_params_82575");
447
448 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
449 E1000_EECD_SIZE_EX_SHIFT);
450 /* Added to a constant, "size" becomes the left-shift value
451 * for setting word_size.
452 */
453 size += NVM_WORD_SIZE_BASE_SHIFT;
454
455 /* Just in case size is out of range, cap it to the largest
456 * EEPROM size supported
457 */
458 if (size > 15)
459 size = 15;
460
461 nvm->word_size = 1 << size;
462 if (hw->mac.type < e1000_i210) {
463 nvm->opcode_bits = 8;
464 nvm->delay_usec = 1;
465
466 switch (nvm->override) {
467 case e1000_nvm_override_spi_large:
468 nvm->page_size = 32;
469 nvm->address_bits = 16;
470 break;
471 case e1000_nvm_override_spi_small:
472 nvm->page_size = 8;
473 nvm->address_bits = 8;
474 break;
475 default:
476 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
477 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
478 16 : 8;
479 break;
480 }
481 if (nvm->word_size == (1 << 15))
482 nvm->page_size = 128;
483
484 nvm->type = e1000_nvm_eeprom_spi;
485 } else {
486 nvm->type = e1000_nvm_flash_hw;
487 }
488
489 /* Function Pointers */
490 nvm->ops.acquire = e1000_acquire_nvm_82575;
491 nvm->ops.release = e1000_release_nvm_82575;
492 if (nvm->word_size < (1 << 15))
493 nvm->ops.read = e1000_read_nvm_eerd;
494 else
495 nvm->ops.read = e1000_read_nvm_spi;
496
497 nvm->ops.write = e1000_write_nvm_spi;
498 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
499 nvm->ops.update = e1000_update_nvm_checksum_generic;
500 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
501
502 /* override generic family function pointers for specific descendants */
503 switch (hw->mac.type) {
504 case e1000_82580:
505 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
506 nvm->ops.update = e1000_update_nvm_checksum_82580;
507 break;
508 case e1000_i350:
509 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
510 nvm->ops.update = e1000_update_nvm_checksum_i350;
511 break;
512 default:
513 break;
514 }
515
516 return E1000_SUCCESS;
517 }
518
519 /**
520 * e1000_init_function_pointers_82575 - Init func ptrs.
521 * @hw: pointer to the HW structure
522 *
523 * Called to initialize all function pointers and parameters.
524 **/
e1000_init_function_pointers_82575(struct e1000_hw * hw)525 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
526 {
527 DEBUGFUNC("e1000_init_function_pointers_82575");
528
529 hw->mac.ops.init_params = e1000_init_mac_params_82575;
530 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
531 hw->phy.ops.init_params = e1000_init_phy_params_82575;
532 hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
533 }
534
535 /**
536 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
537 * @hw: pointer to the HW structure
538 * @offset: register offset to be read
539 * @data: pointer to the read data
540 *
541 * Reads the PHY register at offset using the serial gigabit media independent
542 * interface and stores the retrieved information in data.
543 **/
e1000_read_phy_reg_sgmii_82575(struct e1000_hw * hw,u32 offset,u16 * data)544 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
545 u16 *data)
546 {
547 s32 ret_val = -E1000_ERR_PARAM;
548
549 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
550
551 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
552 DEBUGOUT1("PHY Address %u is out of range\n", offset);
553 goto out;
554 }
555
556 ret_val = hw->phy.ops.acquire(hw);
557 if (ret_val)
558 goto out;
559
560 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
561
562 hw->phy.ops.release(hw);
563
564 out:
565 return ret_val;
566 }
567
568 /**
569 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
570 * @hw: pointer to the HW structure
571 * @offset: register offset to write to
572 * @data: data to write at register offset
573 *
574 * Writes the data to PHY register at the offset using the serial gigabit
575 * media independent interface.
576 **/
e1000_write_phy_reg_sgmii_82575(struct e1000_hw * hw,u32 offset,u16 data)577 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
578 u16 data)
579 {
580 s32 ret_val = -E1000_ERR_PARAM;
581
582 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
583
584 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
585 DEBUGOUT1("PHY Address %d is out of range\n", offset);
586 goto out;
587 }
588
589 ret_val = hw->phy.ops.acquire(hw);
590 if (ret_val)
591 goto out;
592
593 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
594
595 hw->phy.ops.release(hw);
596
597 out:
598 return ret_val;
599 }
600
601 /**
602 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
603 * @hw: pointer to the HW structure
604 *
605 * Retrieves the PHY address and ID for both PHY's which do and do not use
606 * sgmi interface.
607 **/
e1000_get_phy_id_82575(struct e1000_hw * hw)608 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
609 {
610 struct e1000_phy_info *phy = &hw->phy;
611 s32 ret_val = E1000_SUCCESS;
612 u16 phy_id;
613 u32 ctrl_ext;
614 u32 mdic;
615
616 DEBUGFUNC("e1000_get_phy_id_82575");
617
618 /* some i354 devices need an extra read for phy id */
619 if (hw->mac.type == e1000_i354)
620 e1000_get_phy_id(hw);
621
622 /*
623 * For SGMII PHYs, we try the list of possible addresses until
624 * we find one that works. For non-SGMII PHYs
625 * (e.g. integrated copper PHYs), an address of 1 should
626 * work. The result of this function should mean phy->phy_addr
627 * and phy->id are set correctly.
628 */
629 if (!e1000_sgmii_active_82575(hw)) {
630 phy->addr = 1;
631 ret_val = e1000_get_phy_id(hw);
632 goto out;
633 }
634
635 if (e1000_sgmii_uses_mdio_82575(hw)) {
636 switch (hw->mac.type) {
637 case e1000_82575:
638 case e1000_82576:
639 mdic = E1000_READ_REG(hw, E1000_MDIC);
640 mdic &= E1000_MDIC_PHY_MASK;
641 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
642 break;
643 case e1000_82580:
644 case e1000_i350:
645 case e1000_i354:
646 case e1000_i210:
647 case e1000_i211:
648 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
649 mdic &= E1000_MDICNFG_PHY_MASK;
650 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
651 break;
652 default:
653 ret_val = -E1000_ERR_PHY;
654 goto out;
655 break;
656 }
657 ret_val = e1000_get_phy_id(hw);
658 goto out;
659 }
660
661 /* Power on sgmii phy if it is disabled */
662 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
663 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
664 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
665 E1000_WRITE_FLUSH(hw);
666 msec_delay(300);
667
668 /*
669 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
670 * Therefore, we need to test 1-7
671 */
672 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
673 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
674 if (ret_val == E1000_SUCCESS) {
675 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
676 phy_id, phy->addr);
677 /*
678 * At the time of this writing, The M88 part is
679 * the only supported SGMII PHY product.
680 */
681 if (phy_id == M88_VENDOR)
682 break;
683 } else {
684 DEBUGOUT1("PHY address %u was unreadable\n",
685 phy->addr);
686 }
687 }
688
689 /* A valid PHY type couldn't be found. */
690 if (phy->addr == 8) {
691 phy->addr = 0;
692 ret_val = -E1000_ERR_PHY;
693 } else {
694 ret_val = e1000_get_phy_id(hw);
695 }
696
697 /* restore previous sfp cage power state */
698 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
699
700 out:
701 return ret_val;
702 }
703
704 /**
705 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
706 * @hw: pointer to the HW structure
707 *
708 * Resets the PHY using the serial gigabit media independent interface.
709 **/
e1000_phy_hw_reset_sgmii_82575(struct e1000_hw * hw)710 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
711 {
712 s32 ret_val = E1000_SUCCESS;
713 struct e1000_phy_info *phy = &hw->phy;
714
715 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
716
717 /*
718 * This isn't a true "hard" reset, but is the only reset
719 * available to us at this time.
720 */
721
722 DEBUGOUT("Soft resetting SGMII attached PHY...\n");
723
724 if (!(hw->phy.ops.write_reg))
725 goto out;
726
727 /*
728 * SFP documentation requires the following to configure the SPF module
729 * to work on SGMII. No further documentation is given.
730 */
731 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
732 if (ret_val)
733 goto out;
734
735 ret_val = hw->phy.ops.commit(hw);
736 if (ret_val)
737 goto out;
738
739 if (phy->id == M88E1512_E_PHY_ID)
740 ret_val = e1000_initialize_M88E1512_phy(hw);
741 out:
742 return ret_val;
743 }
744
745 /**
746 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
747 * @hw: pointer to the HW structure
748 * @active: true to enable LPLU, false to disable
749 *
750 * Sets the LPLU D0 state according to the active flag. When
751 * activating LPLU this function also disables smart speed
752 * and vice versa. LPLU will not be activated unless the
753 * device autonegotiation advertisement meets standards of
754 * either 10 or 10/100 or 10/100/1000 at all duplexes.
755 * This is a function pointer entry point only called by
756 * PHY setup routines.
757 **/
e1000_set_d0_lplu_state_82575(struct e1000_hw * hw,bool active)758 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
759 {
760 struct e1000_phy_info *phy = &hw->phy;
761 s32 ret_val = E1000_SUCCESS;
762 u16 data;
763
764 DEBUGFUNC("e1000_set_d0_lplu_state_82575");
765
766 if (!(hw->phy.ops.read_reg))
767 goto out;
768
769 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
770 if (ret_val)
771 goto out;
772
773 if (active) {
774 data |= IGP02E1000_PM_D0_LPLU;
775 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
776 data);
777 if (ret_val)
778 goto out;
779
780 /* When LPLU is enabled, we should disable SmartSpeed */
781 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
782 &data);
783 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
784 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
785 data);
786 if (ret_val)
787 goto out;
788 } else {
789 data &= ~IGP02E1000_PM_D0_LPLU;
790 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
791 data);
792 /*
793 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
794 * during Dx states where the power conservation is most
795 * important. During driver activity we should enable
796 * SmartSpeed, so performance is maintained.
797 */
798 if (phy->smart_speed == e1000_smart_speed_on) {
799 ret_val = phy->ops.read_reg(hw,
800 IGP01E1000_PHY_PORT_CONFIG,
801 &data);
802 if (ret_val)
803 goto out;
804
805 data |= IGP01E1000_PSCFR_SMART_SPEED;
806 ret_val = phy->ops.write_reg(hw,
807 IGP01E1000_PHY_PORT_CONFIG,
808 data);
809 if (ret_val)
810 goto out;
811 } else if (phy->smart_speed == e1000_smart_speed_off) {
812 ret_val = phy->ops.read_reg(hw,
813 IGP01E1000_PHY_PORT_CONFIG,
814 &data);
815 if (ret_val)
816 goto out;
817
818 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
819 ret_val = phy->ops.write_reg(hw,
820 IGP01E1000_PHY_PORT_CONFIG,
821 data);
822 if (ret_val)
823 goto out;
824 }
825 }
826
827 out:
828 return ret_val;
829 }
830
831 /**
832 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
833 * @hw: pointer to the HW structure
834 * @active: true to enable LPLU, false to disable
835 *
836 * Sets the LPLU D0 state according to the active flag. When
837 * activating LPLU this function also disables smart speed
838 * and vice versa. LPLU will not be activated unless the
839 * device autonegotiation advertisement meets standards of
840 * either 10 or 10/100 or 10/100/1000 at all duplexes.
841 * This is a function pointer entry point only called by
842 * PHY setup routines.
843 **/
e1000_set_d0_lplu_state_82580(struct e1000_hw * hw,bool active)844 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
845 {
846 struct e1000_phy_info *phy = &hw->phy;
847 u32 data;
848
849 DEBUGFUNC("e1000_set_d0_lplu_state_82580");
850
851 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
852
853 if (active) {
854 data |= E1000_82580_PM_D0_LPLU;
855
856 /* When LPLU is enabled, we should disable SmartSpeed */
857 data &= ~E1000_82580_PM_SPD;
858 } else {
859 data &= ~E1000_82580_PM_D0_LPLU;
860
861 /*
862 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
863 * during Dx states where the power conservation is most
864 * important. During driver activity we should enable
865 * SmartSpeed, so performance is maintained.
866 */
867 if (phy->smart_speed == e1000_smart_speed_on)
868 data |= E1000_82580_PM_SPD;
869 else if (phy->smart_speed == e1000_smart_speed_off)
870 data &= ~E1000_82580_PM_SPD;
871 }
872
873 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
874 return E1000_SUCCESS;
875 }
876
877 /**
878 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
879 * @hw: pointer to the HW structure
880 * @active: boolean used to enable/disable lplu
881 *
882 * Success returns 0, Failure returns 1
883 *
884 * The low power link up (lplu) state is set to the power management level D3
885 * and SmartSpeed is disabled when active is true, else clear lplu for D3
886 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
887 * is used during Dx states where the power conservation is most important.
888 * During driver activity, SmartSpeed should be enabled so performance is
889 * maintained.
890 **/
e1000_set_d3_lplu_state_82580(struct e1000_hw * hw,bool active)891 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
892 {
893 struct e1000_phy_info *phy = &hw->phy;
894 u32 data;
895
896 DEBUGFUNC("e1000_set_d3_lplu_state_82580");
897
898 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
899
900 if (!active) {
901 data &= ~E1000_82580_PM_D3_LPLU;
902 /*
903 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
904 * during Dx states where the power conservation is most
905 * important. During driver activity we should enable
906 * SmartSpeed, so performance is maintained.
907 */
908 if (phy->smart_speed == e1000_smart_speed_on)
909 data |= E1000_82580_PM_SPD;
910 else if (phy->smart_speed == e1000_smart_speed_off)
911 data &= ~E1000_82580_PM_SPD;
912 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
913 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
914 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
915 data |= E1000_82580_PM_D3_LPLU;
916 /* When LPLU is enabled, we should disable SmartSpeed */
917 data &= ~E1000_82580_PM_SPD;
918 }
919
920 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
921 return E1000_SUCCESS;
922 }
923
924 /**
925 * e1000_acquire_nvm_82575 - Request for access to EEPROM
926 * @hw: pointer to the HW structure
927 *
928 * Acquire the necessary semaphores for exclusive access to the EEPROM.
929 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
930 * Return successful if access grant bit set, else clear the request for
931 * EEPROM access and return -E1000_ERR_NVM (-1).
932 **/
e1000_acquire_nvm_82575(struct e1000_hw * hw)933 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
934 {
935 s32 ret_val = E1000_SUCCESS;
936
937 DEBUGFUNC("e1000_acquire_nvm_82575");
938
939 ret_val = e1000_acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
940 if (ret_val)
941 goto out;
942
943 /*
944 * Check if there is some access
945 * error this access may hook on
946 */
947 if (hw->mac.type == e1000_i350) {
948 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
949 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
950 E1000_EECD_TIMEOUT)) {
951 /* Clear all access error flags */
952 E1000_WRITE_REG(hw, E1000_EECD, eecd |
953 E1000_EECD_ERROR_CLR);
954 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
955 }
956 }
957
958 if (hw->mac.type == e1000_82580) {
959 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
960 if (eecd & E1000_EECD_BLOCKED) {
961 /* Clear access error flag */
962 E1000_WRITE_REG(hw, E1000_EECD, eecd |
963 E1000_EECD_BLOCKED);
964 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
965 }
966 }
967
968 ret_val = e1000_acquire_nvm_generic(hw);
969 if (ret_val)
970 e1000_release_swfw_sync(hw, E1000_SWFW_EEP_SM);
971
972 out:
973 return ret_val;
974 }
975
976 /**
977 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
978 * @hw: pointer to the HW structure
979 *
980 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
981 * then release the semaphores acquired.
982 **/
e1000_release_nvm_82575(struct e1000_hw * hw)983 static void e1000_release_nvm_82575(struct e1000_hw *hw)
984 {
985 DEBUGFUNC("e1000_release_nvm_82575");
986
987 e1000_release_nvm_generic(hw);
988
989 e1000_release_swfw_sync(hw, E1000_SWFW_EEP_SM);
990 }
991
992 /**
993 * e1000_get_cfg_done_82575 - Read config done bit
994 * @hw: pointer to the HW structure
995 *
996 * Read the management control register for the config done bit for
997 * completion status. NOTE: silicon which is EEPROM-less will fail trying
998 * to read the config done bit, so an error is *ONLY* logged and returns
999 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
1000 * would not be able to be reset or change link.
1001 **/
e1000_get_cfg_done_82575(struct e1000_hw * hw)1002 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1003 {
1004 s32 timeout = PHY_CFG_TIMEOUT;
1005 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1006
1007 DEBUGFUNC("e1000_get_cfg_done_82575");
1008
1009 if (hw->bus.func == E1000_FUNC_1)
1010 mask = E1000_NVM_CFG_DONE_PORT_1;
1011 else if (hw->bus.func == E1000_FUNC_2)
1012 mask = E1000_NVM_CFG_DONE_PORT_2;
1013 else if (hw->bus.func == E1000_FUNC_3)
1014 mask = E1000_NVM_CFG_DONE_PORT_3;
1015 while (timeout) {
1016 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1017 break;
1018 msec_delay(1);
1019 timeout--;
1020 }
1021 if (!timeout)
1022 DEBUGOUT("MNG configuration cycle has not completed.\n");
1023
1024 /* If EEPROM is not marked present, init the PHY manually */
1025 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1026 (hw->phy.type == e1000_phy_igp_3))
1027 e1000_phy_init_script_igp3(hw);
1028
1029 return E1000_SUCCESS;
1030 }
1031
1032 /**
1033 * e1000_get_link_up_info_82575 - Get link speed/duplex info
1034 * @hw: pointer to the HW structure
1035 * @speed: stores the current speed
1036 * @duplex: stores the current duplex
1037 *
1038 * This is a wrapper function, if using the serial gigabit media independent
1039 * interface, use PCS to retrieve the link speed and duplex information.
1040 * Otherwise, use the generic function to get the link speed and duplex info.
1041 **/
e1000_get_link_up_info_82575(struct e1000_hw * hw,u16 * speed,u16 * duplex)1042 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1043 u16 *duplex)
1044 {
1045 s32 ret_val;
1046
1047 DEBUGFUNC("e1000_get_link_up_info_82575");
1048
1049 if (hw->phy.media_type != e1000_media_type_copper)
1050 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1051 duplex);
1052 else
1053 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1054 duplex);
1055
1056 return ret_val;
1057 }
1058
1059 /**
1060 * e1000_check_for_link_82575 - Check for link
1061 * @hw: pointer to the HW structure
1062 *
1063 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1064 * use the generic interface for determining link.
1065 **/
e1000_check_for_link_82575(struct e1000_hw * hw)1066 static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1067 {
1068 s32 ret_val;
1069 u16 speed, duplex;
1070
1071 DEBUGFUNC("e1000_check_for_link_82575");
1072
1073 if (hw->phy.media_type != e1000_media_type_copper) {
1074 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1075 &duplex);
1076 /*
1077 * Use this flag to determine if link needs to be checked or
1078 * not. If we have link clear the flag so that we do not
1079 * continue to check for link.
1080 */
1081 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1082
1083 /*
1084 * Configure Flow Control now that Auto-Neg has completed.
1085 * First, we need to restore the desired flow control
1086 * settings because we may have had to re-autoneg with a
1087 * different link partner.
1088 */
1089 ret_val = e1000_config_fc_after_link_up_generic(hw);
1090 if (ret_val)
1091 DEBUGOUT("Error configuring flow control\n");
1092 } else {
1093 ret_val = e1000_check_for_copper_link_generic(hw);
1094 }
1095
1096 return ret_val;
1097 }
1098
1099 /**
1100 * e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1101 * @hw: pointer to the HW structure
1102 *
1103 * Poll the M88E1112 interfaces to see which interface achieved link.
1104 */
e1000_check_for_link_media_swap(struct e1000_hw * hw)1105 static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1106 {
1107 struct e1000_phy_info *phy = &hw->phy;
1108 s32 ret_val;
1109 u16 data;
1110 u8 port = 0;
1111
1112 DEBUGFUNC("e1000_check_for_link_media_swap");
1113
1114 /* Check for copper. */
1115 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1116 if (ret_val)
1117 return ret_val;
1118
1119 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1120 if (ret_val)
1121 return ret_val;
1122
1123 if (data & E1000_M88E1112_STATUS_LINK)
1124 port = E1000_MEDIA_PORT_COPPER;
1125
1126 /* Check for other. */
1127 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1128 if (ret_val)
1129 return ret_val;
1130
1131 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1132 if (ret_val)
1133 return ret_val;
1134
1135 if (data & E1000_M88E1112_STATUS_LINK)
1136 port = E1000_MEDIA_PORT_OTHER;
1137
1138 /* Determine if a swap needs to happen. */
1139 if (port && (hw->dev_spec._82575.media_port != port)) {
1140 hw->dev_spec._82575.media_port = port;
1141 hw->dev_spec._82575.media_changed = true;
1142 }
1143
1144 if (port == E1000_MEDIA_PORT_COPPER) {
1145 /* reset page to 0 */
1146 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1147 if (ret_val)
1148 return ret_val;
1149 e1000_check_for_link_82575(hw);
1150 } else {
1151 e1000_check_for_link_82575(hw);
1152 /* reset page to 0 */
1153 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1154 if (ret_val)
1155 return ret_val;
1156 }
1157
1158 return E1000_SUCCESS;
1159 }
1160
1161 /**
1162 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1163 * @hw: pointer to the HW structure
1164 **/
e1000_power_up_serdes_link_82575(struct e1000_hw * hw)1165 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1166 {
1167 u32 reg;
1168
1169 DEBUGFUNC("e1000_power_up_serdes_link_82575");
1170
1171 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1172 !e1000_sgmii_active_82575(hw))
1173 return;
1174
1175 /* Enable PCS to turn on link */
1176 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1177 reg |= E1000_PCS_CFG_PCS_EN;
1178 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1179
1180 /* Power up the laser */
1181 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1182 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1183 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1184
1185 /* flush the write to verify completion */
1186 E1000_WRITE_FLUSH(hw);
1187 msec_delay(1);
1188 }
1189
1190 /**
1191 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1192 * @hw: pointer to the HW structure
1193 * @speed: stores the current speed
1194 * @duplex: stores the current duplex
1195 *
1196 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1197 * duplex, then store the values in the pointers provided.
1198 **/
e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw * hw,u16 * speed,u16 * duplex)1199 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1200 u16 *speed, u16 *duplex)
1201 {
1202 struct e1000_mac_info *mac = &hw->mac;
1203 u32 pcs;
1204 u32 status;
1205
1206 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1207
1208 /*
1209 * Read the PCS Status register for link state. For non-copper mode,
1210 * the status register is not accurate. The PCS status register is
1211 * used instead.
1212 */
1213 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1214
1215 /*
1216 * The link up bit determines when link is up on autoneg.
1217 */
1218 if (pcs & E1000_PCS_LSTS_LINK_OK) {
1219 mac->serdes_has_link = true;
1220
1221 /* Detect and store PCS speed */
1222 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1223 *speed = SPEED_1000;
1224 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1225 *speed = SPEED_100;
1226 else
1227 *speed = SPEED_10;
1228
1229 /* Detect and store PCS duplex */
1230 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1231 *duplex = FULL_DUPLEX;
1232 else
1233 *duplex = HALF_DUPLEX;
1234
1235 /* Check if it is an I354 2.5Gb backplane connection. */
1236 if (mac->type == e1000_i354) {
1237 status = E1000_READ_REG(hw, E1000_STATUS);
1238 if ((status & E1000_STATUS_2P5_SKU) &&
1239 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1240 *speed = SPEED_2500;
1241 *duplex = FULL_DUPLEX;
1242 DEBUGOUT("2500 Mbs, ");
1243 DEBUGOUT("Full Duplex\n");
1244 }
1245 }
1246
1247 } else {
1248 mac->serdes_has_link = false;
1249 *speed = 0;
1250 *duplex = 0;
1251 }
1252
1253 return E1000_SUCCESS;
1254 }
1255
1256 /**
1257 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1258 * @hw: pointer to the HW structure
1259 *
1260 * In the case of serdes shut down sfp and PCS on driver unload
1261 * when management pass thru is not enabled.
1262 **/
e1000_shutdown_serdes_link_82575(struct e1000_hw * hw)1263 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1264 {
1265 u32 reg;
1266
1267 DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1268
1269 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1270 !e1000_sgmii_active_82575(hw))
1271 return;
1272
1273 if (!e1000_enable_mng_pass_thru(hw)) {
1274 /* Disable PCS to turn off link */
1275 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1276 reg &= ~E1000_PCS_CFG_PCS_EN;
1277 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1278
1279 /* shutdown the laser */
1280 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1281 reg |= E1000_CTRL_EXT_SDP3_DATA;
1282 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1283
1284 /* flush the write to verify completion */
1285 E1000_WRITE_FLUSH(hw);
1286 msec_delay(1);
1287 }
1288
1289 return;
1290 }
1291
1292 /**
1293 * e1000_reset_hw_82575 - Reset hardware
1294 * @hw: pointer to the HW structure
1295 *
1296 * This resets the hardware into a known state.
1297 **/
e1000_reset_hw_82575(struct e1000_hw * hw)1298 static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1299 {
1300 u32 ctrl;
1301 s32 ret_val;
1302
1303 DEBUGFUNC("e1000_reset_hw_82575");
1304
1305 /*
1306 * Prevent the PCI-E bus from sticking if there is no TLP connection
1307 * on the last TLP read/write transaction when MAC is reset.
1308 */
1309 ret_val = e1000_disable_pcie_master_generic(hw);
1310 if (ret_val)
1311 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1312
1313 /* set the completion timeout for interface */
1314 ret_val = e1000_set_pcie_completion_timeout(hw);
1315 if (ret_val)
1316 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1317
1318 DEBUGOUT("Masking off all interrupts\n");
1319 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1320
1321 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1322 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1323 E1000_WRITE_FLUSH(hw);
1324
1325 msec_delay(10);
1326
1327 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1328
1329 DEBUGOUT("Issuing a global reset to MAC\n");
1330 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1331
1332 ret_val = e1000_get_auto_rd_done_generic(hw);
1333 if (ret_val) {
1334 /*
1335 * When auto config read does not complete, do not
1336 * return with an error. This can happen in situations
1337 * where there is no eeprom and prevents getting link.
1338 */
1339 DEBUGOUT("Auto Read Done did not complete\n");
1340 }
1341
1342 /* If EEPROM is not present, run manual init scripts */
1343 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1344 e1000_reset_init_script_82575(hw);
1345
1346 /* Clear any pending interrupt events. */
1347 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1348 E1000_READ_REG(hw, E1000_ICR);
1349
1350 /* Install any alternate MAC address into RAR0 */
1351 ret_val = e1000_check_alt_mac_addr_generic(hw);
1352
1353 return ret_val;
1354 }
1355
1356 /**
1357 * e1000_init_hw_82575 - Initialize hardware
1358 * @hw: pointer to the HW structure
1359 *
1360 * This inits the hardware readying it for operation.
1361 **/
e1000_init_hw_82575(struct e1000_hw * hw)1362 static s32 e1000_init_hw_82575(struct e1000_hw *hw)
1363 {
1364 struct e1000_mac_info *mac = &hw->mac;
1365 s32 ret_val;
1366
1367 DEBUGFUNC("e1000_init_hw_82575");
1368
1369 /* Initialize identification LED */
1370 ret_val = mac->ops.id_led_init(hw);
1371 if (ret_val) {
1372 DEBUGOUT("Error initializing identification LED\n");
1373 /* This is not fatal and we should not stop init due to this */
1374 }
1375
1376 /* Disabling VLAN filtering */
1377 DEBUGOUT("Initializing the IEEE VLAN\n");
1378 mac->ops.clear_vfta(hw);
1379
1380 ret_val = e1000_init_hw_base(hw);
1381
1382 /* Set the default MTU size */
1383 hw->dev_spec._82575.mtu = 1500;
1384
1385 /* Clear all of the statistics registers (clear on read). It is
1386 * important that we do this after we have tried to establish link
1387 * because the symbol error count will increment wildly if there
1388 * is no link.
1389 */
1390 e1000_clear_hw_cntrs_82575(hw);
1391
1392 return ret_val;
1393 }
1394 /**
1395 * e1000_setup_copper_link_82575 - Configure copper link settings
1396 * @hw: pointer to the HW structure
1397 *
1398 * Configures the link for auto-neg or forced speed and duplex. Then we check
1399 * for link, once link is established calls to configure collision distance
1400 * and flow control are called.
1401 **/
e1000_setup_copper_link_82575(struct e1000_hw * hw)1402 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1403 {
1404 u32 phpm_reg;
1405 u32 ctrl;
1406 s32 ret_val;
1407
1408 DEBUGFUNC("e1000_setup_copper_link_82575");
1409
1410 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1411 ctrl |= E1000_CTRL_SLU;
1412 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1413 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1414
1415 /* Clear Go Link Disconnect bit on supported devices */
1416 switch (hw->mac.type) {
1417 case e1000_82580:
1418 case e1000_i350:
1419 case e1000_i210:
1420 case e1000_i211:
1421 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1422 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1423 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1424 break;
1425 default:
1426 break;
1427 }
1428
1429 ret_val = e1000_setup_serdes_link_82575(hw);
1430 if (ret_val)
1431 goto out;
1432
1433 if (e1000_sgmii_active_82575(hw)) {
1434 /* allow time for SFP cage time to power up phy */
1435 msec_delay(300);
1436
1437 ret_val = hw->phy.ops.reset(hw);
1438 if (ret_val) {
1439 DEBUGOUT("Error resetting the PHY.\n");
1440 goto out;
1441 }
1442 }
1443 switch (hw->phy.type) {
1444 case e1000_phy_i210:
1445 /* FALLTHROUGH */
1446 case e1000_phy_m88:
1447 switch (hw->phy.id) {
1448 case I347AT4_E_PHY_ID:
1449 /* FALLTHROUGH */
1450 case M88E1112_E_PHY_ID:
1451 /* FALLTHROUGH */
1452 case M88E1340M_E_PHY_ID:
1453 /* FALLTHROUGH */
1454 case M88E1543_E_PHY_ID:
1455 /* FALLTHROUGH */
1456 case M88E1512_E_PHY_ID:
1457 /* FALLTHROUGH */
1458 case I210_I_PHY_ID:
1459 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1460 break;
1461 default:
1462 ret_val = e1000_copper_link_setup_m88(hw);
1463 break;
1464 }
1465 break;
1466 case e1000_phy_igp_3:
1467 ret_val = e1000_copper_link_setup_igp(hw);
1468 break;
1469 case e1000_phy_82580:
1470 ret_val = e1000_copper_link_setup_82577(hw);
1471 break;
1472 default:
1473 ret_val = -E1000_ERR_PHY;
1474 break;
1475 }
1476
1477 if (ret_val)
1478 goto out;
1479
1480 ret_val = e1000_setup_copper_link_generic(hw);
1481 out:
1482 return ret_val;
1483 }
1484
1485 /**
1486 * e1000_setup_serdes_link_82575 - Setup link for serdes
1487 * @hw: pointer to the HW structure
1488 *
1489 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1490 * used on copper connections where the serialized gigabit media independent
1491 * interface (sgmii), or serdes fiber is being used. Configures the link
1492 * for auto-negotiation or forces speed/duplex.
1493 **/
e1000_setup_serdes_link_82575(struct e1000_hw * hw)1494 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1495 {
1496 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1497 bool pcs_autoneg;
1498 s32 ret_val = E1000_SUCCESS;
1499 u16 data;
1500
1501 DEBUGFUNC("e1000_setup_serdes_link_82575");
1502
1503 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1504 !e1000_sgmii_active_82575(hw))
1505 return ret_val;
1506
1507 /*
1508 * On the 82575, SerDes loopback mode persists until it is
1509 * explicitly turned off or a power cycle is performed. A read to
1510 * the register does not indicate its status. Therefore, we ensure
1511 * loopback mode is disabled during initialization.
1512 */
1513 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1514
1515 /* power on the sfp cage if present */
1516 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1517 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1518 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1519
1520 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1521 ctrl_reg |= E1000_CTRL_SLU;
1522
1523 /* set both sw defined pins on 82575/82576*/
1524 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1525 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1526
1527 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1528
1529 /* default pcs_autoneg to the same setting as mac autoneg */
1530 pcs_autoneg = hw->mac.autoneg;
1531
1532 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1533 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1534 /* sgmii mode lets the phy handle forcing speed/duplex */
1535 pcs_autoneg = true;
1536 /* autoneg time out should be disabled for SGMII mode */
1537 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1538 break;
1539 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1540 /* disable PCS autoneg and support parallel detect only */
1541 pcs_autoneg = false;
1542 /* FALLTHROUGH */
1543 default:
1544 if (hw->mac.type == e1000_82575 ||
1545 hw->mac.type == e1000_82576) {
1546 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1547 if (ret_val) {
1548 DEBUGOUT("NVM Read Error\n");
1549 return ret_val;
1550 }
1551
1552 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1553 pcs_autoneg = false;
1554 }
1555
1556 /*
1557 * non-SGMII modes only supports a speed of 1000/Full for the
1558 * link so it is best to just force the MAC and let the pcs
1559 * link either autoneg or be forced to 1000/Full
1560 */
1561 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1562 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1563
1564 /* set speed of 1000/Full if speed/duplex is forced */
1565 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1566 break;
1567 }
1568
1569 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1570
1571 /*
1572 * New SerDes mode allows for forcing speed or autonegotiating speed
1573 * at 1gb. Autoneg should be default set by most drivers. This is the
1574 * mode that will be compatible with older link partners and switches.
1575 * However, both are supported by the hardware and some drivers/tools.
1576 */
1577 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1578 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1579
1580 if (pcs_autoneg) {
1581 /* Set PCS register for autoneg */
1582 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1583 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1584
1585 /* Disable force flow control for autoneg */
1586 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1587
1588 /* Configure flow control advertisement for autoneg */
1589 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1590 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1591
1592 switch (hw->fc.requested_mode) {
1593 case e1000_fc_full:
1594 case e1000_fc_rx_pause:
1595 anadv_reg |= E1000_TXCW_ASM_DIR;
1596 anadv_reg |= E1000_TXCW_PAUSE;
1597 break;
1598 case e1000_fc_tx_pause:
1599 anadv_reg |= E1000_TXCW_ASM_DIR;
1600 break;
1601 default:
1602 break;
1603 }
1604
1605 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1606
1607 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1608 } else {
1609 /* Set PCS register for forced link */
1610 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1611
1612 /* Force flow control for forced link */
1613 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1614
1615 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1616 }
1617
1618 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1619
1620 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1621 e1000_force_mac_fc_generic(hw);
1622
1623 return ret_val;
1624 }
1625
1626 /**
1627 * e1000_get_media_type_82575 - derives current media type.
1628 * @hw: pointer to the HW structure
1629 *
1630 * The media type is chosen reflecting few settings.
1631 * The following are taken into account:
1632 * - link mode set in the current port Init Control Word #3
1633 * - current link mode settings in CSR register
1634 * - MDIO vs. I2C PHY control interface chosen
1635 * - SFP module media type
1636 **/
e1000_get_media_type_82575(struct e1000_hw * hw)1637 static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1638 {
1639 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1640 s32 ret_val = E1000_SUCCESS;
1641 u32 ctrl_ext = 0;
1642 u32 link_mode = 0;
1643
1644 /* Set internal phy as default */
1645 dev_spec->sgmii_active = false;
1646 dev_spec->module_plugged = false;
1647
1648 /* Get CSR setting */
1649 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1650
1651 /* extract link mode setting */
1652 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1653
1654 switch (link_mode) {
1655 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1656 hw->phy.media_type = e1000_media_type_internal_serdes;
1657 break;
1658 case E1000_CTRL_EXT_LINK_MODE_GMII:
1659 hw->phy.media_type = e1000_media_type_copper;
1660 break;
1661 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1662 /* Get phy control interface type set (MDIO vs. I2C)*/
1663 if (e1000_sgmii_uses_mdio_82575(hw)) {
1664 hw->phy.media_type = e1000_media_type_copper;
1665 dev_spec->sgmii_active = true;
1666 break;
1667 }
1668 /* fall through for I2C based SGMII */
1669 /* FALLTHROUGH */
1670 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1671 /* read media type from SFP EEPROM */
1672 ret_val = e1000_set_sfp_media_type_82575(hw);
1673 if ((ret_val != E1000_SUCCESS) ||
1674 (hw->phy.media_type == e1000_media_type_unknown)) {
1675 /*
1676 * If media type was not identified then return media
1677 * type defined by the CTRL_EXT settings.
1678 */
1679 hw->phy.media_type = e1000_media_type_internal_serdes;
1680
1681 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1682 hw->phy.media_type = e1000_media_type_copper;
1683 dev_spec->sgmii_active = true;
1684 }
1685
1686 break;
1687 }
1688
1689 /* change current link mode setting */
1690 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1691
1692 if (dev_spec->sgmii_active)
1693 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1694 else
1695 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1696
1697 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1698
1699 break;
1700 default:
1701 DEBUGOUT("e1000_get_media_type_82575 unknown link type\n");
1702 break;
1703 }
1704
1705 return ret_val;
1706 }
1707
1708 /**
1709 * e1000_set_sfp_media_type_82575 - derives SFP module media type.
1710 * @hw: pointer to the HW structure
1711 *
1712 * The media type is chosen based on SFP module.
1713 * compatibility flags retrieved from SFP ID EEPROM.
1714 **/
e1000_set_sfp_media_type_82575(struct e1000_hw * hw)1715 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1716 {
1717 s32 ret_val = E1000_ERR_CONFIG;
1718 u32 ctrl_ext = 0;
1719 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1720 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1721 u8 tranceiver_type = 0;
1722 s32 timeout = 3;
1723
1724 /* Turn I2C interface ON and power on sfp cage */
1725 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1726 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1727 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1728
1729 E1000_WRITE_FLUSH(hw);
1730
1731 /* Read SFP module data */
1732 while (timeout) {
1733 ret_val = e1000_read_sfp_data_byte(hw,
1734 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1735 &tranceiver_type);
1736 if (ret_val == E1000_SUCCESS)
1737 break;
1738 msec_delay(100);
1739 timeout--;
1740 }
1741 if (ret_val != E1000_SUCCESS)
1742 goto out;
1743
1744 ret_val = e1000_read_sfp_data_byte(hw,
1745 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1746 (u8 *)eth_flags);
1747 if (ret_val != E1000_SUCCESS)
1748 goto out;
1749
1750 /* Check if there is some SFP module plugged and powered */
1751 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1752 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF))
1753 dev_spec->module_plugged = true;
1754 else
1755 DEBUGOUT("PHY module is not SFP/SFF %x\n", tranceiver_type);
1756
1757 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1758 hw->phy.media_type = e1000_media_type_internal_serdes;
1759 DEBUGOUT("PHY module is 1000_base_lxsx\n");
1760 } else if (eth_flags->e100_base_fx || eth_flags->e100_base_lx) {
1761 dev_spec->sgmii_active = true;
1762 hw->phy.media_type = e1000_media_type_internal_serdes;
1763 DEBUGOUT("PHY module is 100_base_fxlx\n");
1764 } else if (eth_flags->e1000_base_t) {
1765 dev_spec->sgmii_active = true;
1766 hw->phy.media_type = e1000_media_type_copper;
1767 DEBUGOUT("PHY module is 1000_base_t\n");
1768 } else {
1769 hw->phy.media_type = e1000_media_type_unknown;
1770 DEBUGOUT("PHY module has not been recognized\n");
1771 }
1772
1773 ret_val = E1000_SUCCESS;
1774 out:
1775 /* Restore I2C interface setting */
1776 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1777 return ret_val;
1778 }
1779
1780 /**
1781 * e1000_valid_led_default_82575 - Verify a valid default LED config
1782 * @hw: pointer to the HW structure
1783 * @data: pointer to the NVM (EEPROM)
1784 *
1785 * Read the EEPROM for the current default LED configuration. If the
1786 * LED configuration is not valid, set to a valid LED configuration.
1787 **/
e1000_valid_led_default_82575(struct e1000_hw * hw,u16 * data)1788 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1789 {
1790 s32 ret_val;
1791
1792 DEBUGFUNC("e1000_valid_led_default_82575");
1793
1794 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1795 if (ret_val) {
1796 DEBUGOUT("NVM Read Error\n");
1797 goto out;
1798 }
1799
1800 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1801 switch (hw->phy.media_type) {
1802 case e1000_media_type_internal_serdes:
1803 *data = ID_LED_DEFAULT_82575_SERDES;
1804 break;
1805 case e1000_media_type_copper:
1806 default:
1807 *data = ID_LED_DEFAULT;
1808 break;
1809 }
1810 }
1811 out:
1812 return ret_val;
1813 }
1814
1815 /**
1816 * e1000_sgmii_active_82575 - Return sgmii state
1817 * @hw: pointer to the HW structure
1818 *
1819 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1820 * which can be enabled for use in the embedded applications. Simply
1821 * return the current state of the sgmii interface.
1822 **/
e1000_sgmii_active_82575(struct e1000_hw * hw)1823 static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1824 {
1825 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1826 return dev_spec->sgmii_active;
1827 }
1828
1829 /**
1830 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1831 * @hw: pointer to the HW structure
1832 *
1833 * Inits recommended HW defaults after a reset when there is no EEPROM
1834 * detected. This is only for the 82575.
1835 **/
e1000_reset_init_script_82575(struct e1000_hw * hw)1836 s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1837 {
1838 DEBUGFUNC("e1000_reset_init_script_82575");
1839
1840 if (hw->mac.type == e1000_82575) {
1841 DEBUGOUT("Running reset init script for 82575\n");
1842 /* SerDes configuration via SERDESCTRL */
1843 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1844 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1845 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1846 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1847
1848 /* CCM configuration via CCMCTL register */
1849 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1850 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1851
1852 /* PCIe lanes configuration */
1853 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1854 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1855 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1856 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1857
1858 /* PCIe PLL Configuration */
1859 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1860 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1861 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1862 }
1863
1864 return E1000_SUCCESS;
1865 }
1866
1867 /**
1868 * e1000_read_mac_addr_82575 - Read device MAC address
1869 * @hw: pointer to the HW structure
1870 **/
e1000_read_mac_addr_82575(struct e1000_hw * hw)1871 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1872 {
1873 s32 ret_val;
1874
1875 DEBUGFUNC("e1000_read_mac_addr_82575");
1876
1877 /*
1878 * If there's an alternate MAC address place it in RAR0
1879 * so that it will override the Si installed default perm
1880 * address.
1881 */
1882 ret_val = e1000_check_alt_mac_addr_generic(hw);
1883 if (ret_val)
1884 goto out;
1885
1886 ret_val = e1000_read_mac_addr_generic(hw);
1887
1888 out:
1889 return ret_val;
1890 }
1891
1892 /**
1893 * e1000_config_collision_dist_82575 - Configure collision distance
1894 * @hw: pointer to the HW structure
1895 *
1896 * Configures the collision distance to the default value and is used
1897 * during link setup.
1898 **/
e1000_config_collision_dist_82575(struct e1000_hw * hw)1899 static void e1000_config_collision_dist_82575(struct e1000_hw *hw)
1900 {
1901 u32 tctl_ext;
1902
1903 DEBUGFUNC("e1000_config_collision_dist_82575");
1904
1905 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
1906
1907 tctl_ext &= ~E1000_TCTL_EXT_COLD;
1908 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
1909
1910 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
1911 E1000_WRITE_FLUSH(hw);
1912 }
1913
1914 /**
1915 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
1916 * @hw: pointer to the HW structure
1917 *
1918 * Clears the hardware counters by reading the counter registers.
1919 **/
e1000_clear_hw_cntrs_82575(struct e1000_hw * hw)1920 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
1921 {
1922 DEBUGFUNC("e1000_clear_hw_cntrs_82575");
1923
1924 e1000_clear_hw_cntrs_base_generic(hw);
1925
1926 E1000_READ_REG(hw, E1000_PRC64);
1927 E1000_READ_REG(hw, E1000_PRC127);
1928 E1000_READ_REG(hw, E1000_PRC255);
1929 E1000_READ_REG(hw, E1000_PRC511);
1930 E1000_READ_REG(hw, E1000_PRC1023);
1931 E1000_READ_REG(hw, E1000_PRC1522);
1932 E1000_READ_REG(hw, E1000_PTC64);
1933 E1000_READ_REG(hw, E1000_PTC127);
1934 E1000_READ_REG(hw, E1000_PTC255);
1935 E1000_READ_REG(hw, E1000_PTC511);
1936 E1000_READ_REG(hw, E1000_PTC1023);
1937 E1000_READ_REG(hw, E1000_PTC1522);
1938
1939 E1000_READ_REG(hw, E1000_ALGNERRC);
1940 E1000_READ_REG(hw, E1000_RXERRC);
1941 E1000_READ_REG(hw, E1000_TNCRS);
1942 E1000_READ_REG(hw, E1000_CEXTERR);
1943 E1000_READ_REG(hw, E1000_TSCTC);
1944 E1000_READ_REG(hw, E1000_TSCTFC);
1945
1946 E1000_READ_REG(hw, E1000_MGTPRC);
1947 E1000_READ_REG(hw, E1000_MGTPDC);
1948 E1000_READ_REG(hw, E1000_MGTPTC);
1949
1950 E1000_READ_REG(hw, E1000_IAC);
1951 E1000_READ_REG(hw, E1000_ICRXOC);
1952
1953 E1000_READ_REG(hw, E1000_ICRXPTC);
1954 E1000_READ_REG(hw, E1000_ICRXATC);
1955 E1000_READ_REG(hw, E1000_ICTXPTC);
1956 E1000_READ_REG(hw, E1000_ICTXATC);
1957 E1000_READ_REG(hw, E1000_ICTXQEC);
1958 E1000_READ_REG(hw, E1000_ICTXQMTC);
1959 E1000_READ_REG(hw, E1000_ICRXDMTC);
1960
1961 E1000_READ_REG(hw, E1000_CBTMPC);
1962 E1000_READ_REG(hw, E1000_HTDPMC);
1963 E1000_READ_REG(hw, E1000_CBRMPC);
1964 E1000_READ_REG(hw, E1000_RPTHC);
1965 E1000_READ_REG(hw, E1000_HGPTC);
1966 E1000_READ_REG(hw, E1000_HTCBDPC);
1967 E1000_READ_REG(hw, E1000_HGORCL);
1968 E1000_READ_REG(hw, E1000_HGORCH);
1969 E1000_READ_REG(hw, E1000_HGOTCL);
1970 E1000_READ_REG(hw, E1000_HGOTCH);
1971 E1000_READ_REG(hw, E1000_LENERRS);
1972
1973 /* This register should not be read in copper configurations */
1974 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
1975 e1000_sgmii_active_82575(hw))
1976 E1000_READ_REG(hw, E1000_SCVPC);
1977 }
1978
1979 /**
1980 * e1000_set_pcie_completion_timeout - set pci-e completion timeout
1981 * @hw: pointer to the HW structure
1982 *
1983 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1984 * however the hardware default for these parts is 500us to 1ms which is less
1985 * than the 10ms recommended by the pci-e spec. To address this we need to
1986 * increase the value to either 10ms to 200ms for capability version 1 config,
1987 * or 16ms to 55ms for version 2.
1988 **/
e1000_set_pcie_completion_timeout(struct e1000_hw * hw)1989 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
1990 {
1991 u32 gcr = E1000_READ_REG(hw, E1000_GCR);
1992 s32 ret_val = E1000_SUCCESS;
1993 u16 pcie_devctl2;
1994
1995 /* only take action if timeout value is defaulted to 0 */
1996 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1997 goto out;
1998
1999 /*
2000 * if capababilities version is type 1 we can write the
2001 * timeout of 10ms to 200ms through the GCR register
2002 */
2003 if (!(gcr & E1000_GCR_CAP_VER2)) {
2004 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2005 goto out;
2006 }
2007
2008 /*
2009 * for version 2 capabilities we need to write the config space
2010 * directly in order to set the completion timeout value for
2011 * 16ms to 55ms
2012 */
2013 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2014 &pcie_devctl2);
2015 if (ret_val)
2016 goto out;
2017
2018 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2019
2020 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2021 &pcie_devctl2);
2022 out:
2023 /* disable completion timeout resend */
2024 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2025
2026 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2027 return ret_val;
2028 }
2029
2030 /**
2031 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2032 * @hw: pointer to the hardware struct
2033 * @enable: state to enter, either enabled or disabled
2034 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2035 *
2036 * enables/disables L2 switch anti-spoofing functionality.
2037 **/
e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw * hw,bool enable,int pf)2038 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2039 {
2040 u32 reg_val, reg_offset;
2041
2042 switch (hw->mac.type) {
2043 case e1000_82576:
2044 reg_offset = E1000_DTXSWC;
2045 break;
2046 case e1000_i350:
2047 case e1000_i354:
2048 reg_offset = E1000_TXSWC;
2049 break;
2050 default:
2051 return;
2052 }
2053
2054 reg_val = E1000_READ_REG(hw, reg_offset);
2055 if (enable) {
2056 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2057 E1000_DTXSWC_VLAN_SPOOF_MASK);
2058 /* The PF can spoof - it has to in order to
2059 * support emulation mode NICs
2060 */
2061 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2062 } else {
2063 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2064 E1000_DTXSWC_VLAN_SPOOF_MASK);
2065 }
2066 E1000_WRITE_REG(hw, reg_offset, reg_val);
2067 }
2068
2069 /**
2070 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2071 * @hw: pointer to the hardware struct
2072 * @enable: state to enter, either enabled or disabled
2073 *
2074 * enables/disables L2 switch loopback functionality.
2075 **/
e1000_vmdq_set_loopback_pf(struct e1000_hw * hw,bool enable)2076 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2077 {
2078 u32 dtxswc;
2079
2080 switch (hw->mac.type) {
2081 case e1000_82576:
2082 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2083 if (enable)
2084 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2085 else
2086 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2087 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2088 break;
2089 case e1000_i350:
2090 case e1000_i354:
2091 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2092 if (enable)
2093 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2094 else
2095 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2096 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2097 break;
2098 default:
2099 /* Currently no other hardware supports loopback */
2100 break;
2101 }
2102
2103
2104 }
2105
2106 /**
2107 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2108 * @hw: pointer to the hardware struct
2109 * @enable: state to enter, either enabled or disabled
2110 *
2111 * enables/disables replication of packets across multiple pools.
2112 **/
e1000_vmdq_set_replication_pf(struct e1000_hw * hw,bool enable)2113 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2114 {
2115 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2116
2117 if (enable)
2118 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2119 else
2120 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2121
2122 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2123 }
2124
2125 /**
2126 * e1000_read_phy_reg_82580 - Read 82580 MDI control register
2127 * @hw: pointer to the HW structure
2128 * @offset: register offset to be read
2129 * @data: pointer to the read data
2130 *
2131 * Reads the MDI control register in the PHY at offset and stores the
2132 * information read to data.
2133 **/
e1000_read_phy_reg_82580(struct e1000_hw * hw,u32 offset,u16 * data)2134 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2135 {
2136 s32 ret_val;
2137
2138 DEBUGFUNC("e1000_read_phy_reg_82580");
2139
2140 ret_val = hw->phy.ops.acquire(hw);
2141 if (ret_val)
2142 goto out;
2143
2144 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2145
2146 hw->phy.ops.release(hw);
2147
2148 out:
2149 return ret_val;
2150 }
2151
2152 /**
2153 * e1000_write_phy_reg_82580 - Write 82580 MDI control register
2154 * @hw: pointer to the HW structure
2155 * @offset: register offset to write to
2156 * @data: data to write to register at offset
2157 *
2158 * Writes data to MDI control register in the PHY at offset.
2159 **/
e1000_write_phy_reg_82580(struct e1000_hw * hw,u32 offset,u16 data)2160 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2161 {
2162 s32 ret_val;
2163
2164 DEBUGFUNC("e1000_write_phy_reg_82580");
2165
2166 ret_val = hw->phy.ops.acquire(hw);
2167 if (ret_val)
2168 goto out;
2169
2170 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2171
2172 hw->phy.ops.release(hw);
2173
2174 out:
2175 return ret_val;
2176 }
2177
2178 /**
2179 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2180 * @hw: pointer to the HW structure
2181 *
2182 * This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2183 * the values found in the EEPROM. This addresses an issue in which these
2184 * bits are not restored from EEPROM after reset.
2185 **/
e1000_reset_mdicnfg_82580(struct e1000_hw * hw)2186 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2187 {
2188 s32 ret_val = E1000_SUCCESS;
2189 u32 mdicnfg;
2190 u16 nvm_data = 0;
2191
2192 DEBUGFUNC("e1000_reset_mdicnfg_82580");
2193
2194 if (hw->mac.type != e1000_82580)
2195 goto out;
2196 if (!e1000_sgmii_active_82575(hw))
2197 goto out;
2198
2199 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2200 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2201 &nvm_data);
2202 if (ret_val) {
2203 DEBUGOUT("NVM Read Error\n");
2204 goto out;
2205 }
2206
2207 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2208 if (nvm_data & NVM_WORD24_EXT_MDIO)
2209 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2210 if (nvm_data & NVM_WORD24_COM_MDIO)
2211 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2212 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2213 out:
2214 return ret_val;
2215 }
2216
2217 /**
2218 * e1000_reset_hw_82580 - Reset hardware
2219 * @hw: pointer to the HW structure
2220 *
2221 * This resets function or entire device (all ports, etc.)
2222 * to a known state.
2223 **/
e1000_reset_hw_82580(struct e1000_hw * hw)2224 static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2225 {
2226 s32 ret_val = E1000_SUCCESS;
2227 /* BH SW mailbox bit in SW_FW_SYNC */
2228 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2229 u32 ctrl;
2230 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2231
2232 DEBUGFUNC("e1000_reset_hw_82580");
2233
2234 hw->dev_spec._82575.global_device_reset = false;
2235
2236 /* 82580 does not reliably do global_device_reset due to hw errata */
2237 if (hw->mac.type == e1000_82580)
2238 global_device_reset = false;
2239
2240 /* Get current control state. */
2241 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2242
2243 /*
2244 * Prevent the PCI-E bus from sticking if there is no TLP connection
2245 * on the last TLP read/write transaction when MAC is reset.
2246 */
2247 ret_val = e1000_disable_pcie_master_generic(hw);
2248 if (ret_val)
2249 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2250
2251 DEBUGOUT("Masking off all interrupts\n");
2252 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2253 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2254 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2255 E1000_WRITE_FLUSH(hw);
2256
2257 msec_delay(10);
2258
2259 /* Determine whether or not a global dev reset is requested */
2260 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2261 swmbsw_mask))
2262 global_device_reset = false;
2263
2264 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2265 E1000_STAT_DEV_RST_SET))
2266 ctrl |= E1000_CTRL_DEV_RST;
2267 else
2268 ctrl |= E1000_CTRL_RST;
2269
2270 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2271
2272 switch (hw->device_id) {
2273 case E1000_DEV_ID_DH89XXCC_SGMII:
2274 break;
2275 default:
2276 E1000_WRITE_FLUSH(hw);
2277 break;
2278 }
2279
2280 /* Add delay to insure DEV_RST or RST has time to complete */
2281 msec_delay(5);
2282
2283 ret_val = e1000_get_auto_rd_done_generic(hw);
2284 if (ret_val) {
2285 /*
2286 * When auto config read does not complete, do not
2287 * return with an error. This can happen in situations
2288 * where there is no eeprom and prevents getting link.
2289 */
2290 DEBUGOUT("Auto Read Done did not complete\n");
2291 }
2292
2293 /* clear global device reset status bit */
2294 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2295
2296 /* Clear any pending interrupt events. */
2297 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2298 E1000_READ_REG(hw, E1000_ICR);
2299
2300 ret_val = e1000_reset_mdicnfg_82580(hw);
2301 if (ret_val)
2302 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2303
2304 /* Install any alternate MAC address into RAR0 */
2305 ret_val = e1000_check_alt_mac_addr_generic(hw);
2306
2307 /* Release semaphore */
2308 if (global_device_reset)
2309 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2310
2311 return ret_val;
2312 }
2313
2314 /**
2315 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2316 * @data: data received by reading RXPBS register
2317 *
2318 * The 82580 uses a table based approach for packet buffer allocation sizes.
2319 * This function converts the retrieved value into the correct table value
2320 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2321 * 0x0 36 72 144 1 2 4 8 16
2322 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2323 */
e1000_rxpbs_adjust_82580(u32 data)2324 u16 e1000_rxpbs_adjust_82580(u32 data)
2325 {
2326 u16 ret_val = 0;
2327
2328 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2329 ret_val = e1000_82580_rxpbs_table[data];
2330
2331 return ret_val;
2332 }
2333
2334 /**
2335 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2336 * checksum
2337 * @hw: pointer to the HW structure
2338 * @offset: offset in words of the checksum protected region
2339 *
2340 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2341 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2342 **/
e1000_validate_nvm_checksum_with_offset(struct e1000_hw * hw,u16 offset)2343 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2344 {
2345 s32 ret_val = E1000_SUCCESS;
2346 u16 checksum = 0;
2347 u16 i, nvm_data;
2348
2349 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2350
2351 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2352 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2353 if (ret_val) {
2354 DEBUGOUT("NVM Read Error\n");
2355 goto out;
2356 }
2357 checksum += nvm_data;
2358 }
2359
2360 if (checksum != (u16) NVM_SUM) {
2361 DEBUGOUT("NVM Checksum Invalid\n");
2362 ret_val = -E1000_ERR_NVM;
2363 goto out;
2364 }
2365
2366 out:
2367 return ret_val;
2368 }
2369
2370 /**
2371 * e1000_update_nvm_checksum_with_offset - Update EEPROM
2372 * checksum
2373 * @hw: pointer to the HW structure
2374 * @offset: offset in words of the checksum protected region
2375 *
2376 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2377 * up to the checksum. Then calculates the EEPROM checksum and writes the
2378 * value to the EEPROM.
2379 **/
e1000_update_nvm_checksum_with_offset(struct e1000_hw * hw,u16 offset)2380 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2381 {
2382 s32 ret_val;
2383 u16 checksum = 0;
2384 u16 i, nvm_data;
2385
2386 DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2387
2388 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2389 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2390 if (ret_val) {
2391 DEBUGOUT("NVM Read Error while updating checksum.\n");
2392 goto out;
2393 }
2394 checksum += nvm_data;
2395 }
2396 checksum = (u16) NVM_SUM - checksum;
2397 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2398 &checksum);
2399 if (ret_val)
2400 DEBUGOUT("NVM Write Error while updating checksum.\n");
2401
2402 out:
2403 return ret_val;
2404 }
2405
2406 /**
2407 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2408 * @hw: pointer to the HW structure
2409 *
2410 * Calculates the EEPROM section checksum by reading/adding each word of
2411 * the EEPROM and then verifies that the sum of the EEPROM is
2412 * equal to 0xBABA.
2413 **/
e1000_validate_nvm_checksum_82580(struct e1000_hw * hw)2414 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2415 {
2416 s32 ret_val;
2417 u16 eeprom_regions_count = 1;
2418 u16 j, nvm_data;
2419 u16 nvm_offset;
2420
2421 DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2422
2423 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2424 if (ret_val) {
2425 DEBUGOUT("NVM Read Error\n");
2426 goto out;
2427 }
2428
2429 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2430 /* if checksums compatibility bit is set validate checksums
2431 * for all 4 ports. */
2432 eeprom_regions_count = 4;
2433 }
2434
2435 for (j = 0; j < eeprom_regions_count; j++) {
2436 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2437 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2438 nvm_offset);
2439 if (ret_val != E1000_SUCCESS)
2440 goto out;
2441 }
2442
2443 out:
2444 return ret_val;
2445 }
2446
2447 /**
2448 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2449 * @hw: pointer to the HW structure
2450 *
2451 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2452 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2453 * checksum and writes the value to the EEPROM.
2454 **/
e1000_update_nvm_checksum_82580(struct e1000_hw * hw)2455 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2456 {
2457 s32 ret_val;
2458 u16 j, nvm_data;
2459 u16 nvm_offset;
2460
2461 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2462
2463 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2464 if (ret_val) {
2465 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2466 goto out;
2467 }
2468
2469 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2470 /* set compatibility bit to validate checksums appropriately */
2471 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2472 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2473 &nvm_data);
2474 if (ret_val) {
2475 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2476 goto out;
2477 }
2478 }
2479
2480 for (j = 0; j < 4; j++) {
2481 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2482 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2483 if (ret_val)
2484 goto out;
2485 }
2486
2487 out:
2488 return ret_val;
2489 }
2490
2491 /**
2492 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2493 * @hw: pointer to the HW structure
2494 *
2495 * Calculates the EEPROM section checksum by reading/adding each word of
2496 * the EEPROM and then verifies that the sum of the EEPROM is
2497 * equal to 0xBABA.
2498 **/
e1000_validate_nvm_checksum_i350(struct e1000_hw * hw)2499 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2500 {
2501 s32 ret_val = E1000_SUCCESS;
2502 u16 j;
2503 u16 nvm_offset;
2504
2505 DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2506
2507 for (j = 0; j < 4; j++) {
2508 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2509 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2510 nvm_offset);
2511 if (ret_val != E1000_SUCCESS)
2512 goto out;
2513 }
2514
2515 out:
2516 return ret_val;
2517 }
2518
2519 /**
2520 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2521 * @hw: pointer to the HW structure
2522 *
2523 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2524 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2525 * checksum and writes the value to the EEPROM.
2526 **/
e1000_update_nvm_checksum_i350(struct e1000_hw * hw)2527 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2528 {
2529 s32 ret_val = E1000_SUCCESS;
2530 u16 j;
2531 u16 nvm_offset;
2532
2533 DEBUGFUNC("e1000_update_nvm_checksum_i350");
2534
2535 for (j = 0; j < 4; j++) {
2536 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2537 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2538 if (ret_val != E1000_SUCCESS)
2539 goto out;
2540 }
2541
2542 out:
2543 return ret_val;
2544 }
2545
2546 /**
2547 * __e1000_access_emi_reg - Read/write EMI register
2548 * @hw: pointer to the HW structure
2549 * @address: EMI address to program
2550 * @data: pointer to value to read/write from/to the EMI address
2551 * @read: boolean flag to indicate read or write
2552 **/
__e1000_access_emi_reg(struct e1000_hw * hw,u16 address,u16 * data,bool read)2553 static s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2554 u16 *data, bool read)
2555 {
2556 s32 ret_val;
2557
2558 DEBUGFUNC("__e1000_access_emi_reg");
2559
2560 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2561 if (ret_val)
2562 return ret_val;
2563
2564 if (read)
2565 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2566 else
2567 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2568
2569 return ret_val;
2570 }
2571
2572 /**
2573 * e1000_read_emi_reg - Read Extended Management Interface register
2574 * @hw: pointer to the HW structure
2575 * @addr: EMI address to program
2576 * @data: value to be read from the EMI address
2577 **/
e1000_read_emi_reg(struct e1000_hw * hw,u16 addr,u16 * data)2578 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2579 {
2580 DEBUGFUNC("e1000_read_emi_reg");
2581
2582 return __e1000_access_emi_reg(hw, addr, data, true);
2583 }
2584
2585 /**
2586 * e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY
2587 * @hw: pointer to the HW structure
2588 *
2589 * Initialize Marvell 1512 to work correctly with Avoton.
2590 **/
e1000_initialize_M88E1512_phy(struct e1000_hw * hw)2591 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)
2592 {
2593 struct e1000_phy_info *phy = &hw->phy;
2594 s32 ret_val = E1000_SUCCESS;
2595
2596 DEBUGFUNC("e1000_initialize_M88E1512_phy");
2597
2598 /* Check if this is correct PHY. */
2599 if (phy->id != M88E1512_E_PHY_ID)
2600 goto out;
2601
2602 /* Switch to PHY page 0xFF. */
2603 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2604 if (ret_val)
2605 goto out;
2606
2607 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2608 if (ret_val)
2609 goto out;
2610
2611 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2612 if (ret_val)
2613 goto out;
2614
2615 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2616 if (ret_val)
2617 goto out;
2618
2619 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2620 if (ret_val)
2621 goto out;
2622
2623 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2624 if (ret_val)
2625 goto out;
2626
2627 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2628 if (ret_val)
2629 goto out;
2630
2631 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2632 if (ret_val)
2633 goto out;
2634
2635 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2636 if (ret_val)
2637 goto out;
2638
2639 /* Switch to PHY page 0xFB. */
2640 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2641 if (ret_val)
2642 goto out;
2643
2644 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2645 if (ret_val)
2646 goto out;
2647
2648 /* Switch to PHY page 0x12. */
2649 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2650 if (ret_val)
2651 goto out;
2652
2653 /* Change mode to SGMII-to-Copper */
2654 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2655 if (ret_val)
2656 goto out;
2657
2658 /* Return the PHY to page 0. */
2659 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2660 if (ret_val)
2661 goto out;
2662
2663 ret_val = phy->ops.commit(hw);
2664 if (ret_val) {
2665 DEBUGOUT("Error committing the PHY changes\n");
2666 return ret_val;
2667 }
2668
2669 msec_delay(1000);
2670 out:
2671 return ret_val;
2672 }
2673
2674 /**
2675 * e1000_initialize_M88E1543_phy - Initialize M88E1543 PHY
2676 * @hw: pointer to the HW structure
2677 *
2678 * Initialize Marvell 1543 to work correctly with Avoton.
2679 **/
e1000_initialize_M88E1543_phy(struct e1000_hw * hw)2680 s32 e1000_initialize_M88E1543_phy(struct e1000_hw *hw)
2681 {
2682 struct e1000_phy_info *phy = &hw->phy;
2683 s32 ret_val = E1000_SUCCESS;
2684
2685 DEBUGFUNC("e1000_initialize_M88E1543_phy");
2686
2687 /* Check if this is correct PHY. */
2688 if (phy->id != M88E1543_E_PHY_ID)
2689 goto out;
2690
2691 /* Switch to PHY page 0xFF. */
2692 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2693 if (ret_val)
2694 goto out;
2695
2696 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2697 if (ret_val)
2698 goto out;
2699
2700 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2701 if (ret_val)
2702 goto out;
2703
2704 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2705 if (ret_val)
2706 goto out;
2707
2708 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2709 if (ret_val)
2710 goto out;
2711
2712 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2713 if (ret_val)
2714 goto out;
2715
2716 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2717 if (ret_val)
2718 goto out;
2719
2720 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
2721 if (ret_val)
2722 goto out;
2723
2724 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2725 if (ret_val)
2726 goto out;
2727
2728 /* Switch to PHY page 0xFB. */
2729 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2730 if (ret_val)
2731 goto out;
2732
2733 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D);
2734 if (ret_val)
2735 goto out;
2736
2737 /* Switch to PHY page 0x12. */
2738 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2739 if (ret_val)
2740 goto out;
2741
2742 /* Change mode to SGMII-to-Copper */
2743 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2744 if (ret_val)
2745 goto out;
2746
2747 /* Switch to PHY page 1. */
2748 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
2749 if (ret_val)
2750 goto out;
2751
2752 /* Change mode to 1000BASE-X/SGMII and autoneg enable; reset */
2753 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
2754 if (ret_val)
2755 goto out;
2756
2757 /* Return the PHY to page 0. */
2758 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2759 if (ret_val)
2760 goto out;
2761
2762 ret_val = phy->ops.commit(hw);
2763 if (ret_val) {
2764 DEBUGOUT("Error committing the PHY changes\n");
2765 return ret_val;
2766 }
2767
2768 msec_delay(1000);
2769 out:
2770 return ret_val;
2771 }
2772
2773 /**
2774 * e1000_set_eee_i350 - Enable/disable EEE support
2775 * @hw: pointer to the HW structure
2776 * @adv1G: boolean flag enabling 1G EEE advertisement
2777 * @adv100M: boolean flag enabling 100M EEE advertisement
2778 *
2779 * Enable/disable EEE based on setting in dev_spec structure.
2780 *
2781 **/
e1000_set_eee_i350(struct e1000_hw * hw,bool adv1G,bool adv100M)2782 s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
2783 {
2784 u32 ipcnfg, eeer;
2785
2786 DEBUGFUNC("e1000_set_eee_i350");
2787
2788 if ((hw->mac.type < e1000_i350) ||
2789 (hw->phy.media_type != e1000_media_type_copper))
2790 goto out;
2791 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2792 eeer = E1000_READ_REG(hw, E1000_EEER);
2793
2794 /* enable or disable per user setting */
2795 if (!(hw->dev_spec._82575.eee_disable)) {
2796 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2797
2798 if (adv100M)
2799 ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
2800 else
2801 ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
2802
2803 if (adv1G)
2804 ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
2805 else
2806 ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
2807
2808 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2809 E1000_EEER_LPI_FC);
2810
2811 /* This bit should not be set in normal operation. */
2812 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2813 DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2814 } else {
2815 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2816 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2817 E1000_EEER_LPI_FC);
2818 }
2819 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2820 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2821 E1000_READ_REG(hw, E1000_IPCNFG);
2822 E1000_READ_REG(hw, E1000_EEER);
2823 out:
2824
2825 return E1000_SUCCESS;
2826 }
2827
2828 /**
2829 * e1000_set_eee_i354 - Enable/disable EEE support
2830 * @hw: pointer to the HW structure
2831 * @adv1G: boolean flag enabling 1G EEE advertisement
2832 * @adv100M: boolean flag enabling 100M EEE advertisement
2833 *
2834 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2835 *
2836 **/
e1000_set_eee_i354(struct e1000_hw * hw,bool adv1G,bool adv100M)2837 s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
2838 {
2839 struct e1000_phy_info *phy = &hw->phy;
2840 s32 ret_val = E1000_SUCCESS;
2841 u16 phy_data;
2842
2843 DEBUGFUNC("e1000_set_eee_i354");
2844
2845 if ((hw->phy.media_type != e1000_media_type_copper) ||
2846 ((phy->id != M88E1543_E_PHY_ID) &&
2847 (phy->id != M88E1512_E_PHY_ID)))
2848 goto out;
2849
2850 if (!hw->dev_spec._82575.eee_disable) {
2851 /* Switch to PHY page 18. */
2852 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2853 if (ret_val)
2854 goto out;
2855
2856 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2857 &phy_data);
2858 if (ret_val)
2859 goto out;
2860
2861 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2862 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2863 phy_data);
2864 if (ret_val)
2865 goto out;
2866
2867 /* Return the PHY to page 0. */
2868 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2869 if (ret_val)
2870 goto out;
2871
2872 /* Turn on EEE advertisement. */
2873 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2874 E1000_EEE_ADV_DEV_I354,
2875 &phy_data);
2876 if (ret_val)
2877 goto out;
2878
2879 if (adv100M)
2880 phy_data |= E1000_EEE_ADV_100_SUPPORTED;
2881 else
2882 phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
2883
2884 if (adv1G)
2885 phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
2886 else
2887 phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
2888
2889 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2890 E1000_EEE_ADV_DEV_I354,
2891 phy_data);
2892 } else {
2893 /* Turn off EEE advertisement. */
2894 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2895 E1000_EEE_ADV_DEV_I354,
2896 &phy_data);
2897 if (ret_val)
2898 goto out;
2899
2900 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2901 E1000_EEE_ADV_1000_SUPPORTED);
2902 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2903 E1000_EEE_ADV_DEV_I354,
2904 phy_data);
2905 }
2906
2907 out:
2908 return ret_val;
2909 }
2910
2911 /**
2912 * e1000_get_eee_status_i354 - Get EEE status
2913 * @hw: pointer to the HW structure
2914 * @status: EEE status
2915 *
2916 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2917 * been received.
2918 **/
e1000_get_eee_status_i354(struct e1000_hw * hw,bool * status)2919 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2920 {
2921 struct e1000_phy_info *phy = &hw->phy;
2922 s32 ret_val = E1000_SUCCESS;
2923 u16 phy_data;
2924
2925 DEBUGFUNC("e1000_get_eee_status_i354");
2926
2927 /* Check if EEE is supported on this device. */
2928 if ((hw->phy.media_type != e1000_media_type_copper) ||
2929 ((phy->id != M88E1543_E_PHY_ID) &&
2930 (phy->id != M88E1512_E_PHY_ID)))
2931 goto out;
2932
2933 ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2934 E1000_PCS_STATUS_DEV_I354,
2935 &phy_data);
2936 if (ret_val)
2937 goto out;
2938
2939 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2940 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2941
2942 out:
2943 return ret_val;
2944 }
2945
2946 /* Due to a hw errata, if the host tries to configure the VFTA register
2947 * while performing queries from the BMC or DMA, then the VFTA in some
2948 * cases won't be written.
2949 */
2950
2951 /**
2952 * e1000_clear_vfta_i350 - Clear VLAN filter table
2953 * @hw: pointer to the HW structure
2954 *
2955 * Clears the register array which contains the VLAN filter table by
2956 * setting all the values to 0.
2957 **/
e1000_clear_vfta_i350(struct e1000_hw * hw)2958 void e1000_clear_vfta_i350(struct e1000_hw *hw)
2959 {
2960 u32 offset;
2961 int i;
2962
2963 DEBUGFUNC("e1000_clear_vfta_350");
2964
2965 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
2966 for (i = 0; i < 10; i++)
2967 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
2968
2969 E1000_WRITE_FLUSH(hw);
2970 }
2971 }
2972
2973 /**
2974 * e1000_write_vfta_i350 - Write value to VLAN filter table
2975 * @hw: pointer to the HW structure
2976 * @offset: register offset in VLAN filter table
2977 * @value: register value written to VLAN filter table
2978 *
2979 * Writes value at the given offset in the register array which stores
2980 * the VLAN filter table.
2981 **/
e1000_write_vfta_i350(struct e1000_hw * hw,u32 offset,u32 value)2982 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
2983 {
2984 int i;
2985
2986 DEBUGFUNC("e1000_write_vfta_350");
2987
2988 for (i = 0; i < 10; i++)
2989 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
2990
2991 E1000_WRITE_FLUSH(hw);
2992 }
2993
2994
2995 /**
2996 * e1000_set_i2c_bb - Enable I2C bit-bang
2997 * @hw: pointer to the HW structure
2998 *
2999 * Enable I2C bit-bang interface
3000 *
3001 **/
e1000_set_i2c_bb(struct e1000_hw * hw)3002 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
3003 {
3004 s32 ret_val = E1000_SUCCESS;
3005 u32 ctrl_ext, i2cparams;
3006
3007 DEBUGFUNC("e1000_set_i2c_bb");
3008
3009 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3010 ctrl_ext |= E1000_CTRL_I2C_ENA;
3011 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3012 E1000_WRITE_FLUSH(hw);
3013
3014 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3015 i2cparams |= E1000_I2CBB_EN;
3016 i2cparams |= E1000_I2C_DATA_OE_N;
3017 i2cparams |= E1000_I2C_CLK_OE_N;
3018 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3019 E1000_WRITE_FLUSH(hw);
3020
3021 return ret_val;
3022 }
3023
3024 /**
3025 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3026 * @hw: pointer to hardware structure
3027 * @byte_offset: byte offset to read
3028 * @dev_addr: device address
3029 * @data: value read
3030 *
3031 * Performs byte read operation over I2C interface at
3032 * a specified device address.
3033 **/
e1000_read_i2c_byte_generic(struct e1000_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)3034 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3035 u8 dev_addr, u8 *data)
3036 {
3037 s32 status = E1000_SUCCESS;
3038 u32 max_retry = 10;
3039 u32 retry = 1;
3040 u16 swfw_mask = 0;
3041
3042 bool nack = true;
3043
3044 DEBUGFUNC("e1000_read_i2c_byte_generic");
3045
3046 swfw_mask = E1000_SWFW_PHY0_SM;
3047
3048 do {
3049 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3050 != E1000_SUCCESS) {
3051 status = E1000_ERR_SWFW_SYNC;
3052 goto read_byte_out;
3053 }
3054
3055 e1000_i2c_start(hw);
3056
3057 /* Device Address and write indication */
3058 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3059 if (status != E1000_SUCCESS)
3060 goto fail;
3061
3062 status = e1000_get_i2c_ack(hw);
3063 if (status != E1000_SUCCESS)
3064 goto fail;
3065
3066 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3067 if (status != E1000_SUCCESS)
3068 goto fail;
3069
3070 status = e1000_get_i2c_ack(hw);
3071 if (status != E1000_SUCCESS)
3072 goto fail;
3073
3074 e1000_i2c_start(hw);
3075
3076 /* Device Address and read indication */
3077 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3078 if (status != E1000_SUCCESS)
3079 goto fail;
3080
3081 status = e1000_get_i2c_ack(hw);
3082 if (status != E1000_SUCCESS)
3083 goto fail;
3084
3085 e1000_clock_in_i2c_byte(hw, data);
3086
3087 status = e1000_clock_out_i2c_bit(hw, nack);
3088 if (status != E1000_SUCCESS)
3089 goto fail;
3090
3091 e1000_i2c_stop(hw);
3092 break;
3093
3094 fail:
3095 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3096 msec_delay(100);
3097 e1000_i2c_bus_clear(hw);
3098 retry++;
3099 if (retry < max_retry)
3100 DEBUGOUT("I2C byte read error - Retrying.\n");
3101 else
3102 DEBUGOUT("I2C byte read error.\n");
3103
3104 } while (retry < max_retry);
3105
3106 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3107
3108 read_byte_out:
3109
3110 return status;
3111 }
3112
3113 /**
3114 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3115 * @hw: pointer to hardware structure
3116 * @byte_offset: byte offset to write
3117 * @dev_addr: device address
3118 * @data: value to write
3119 *
3120 * Performs byte write operation over I2C interface at
3121 * a specified device address.
3122 **/
e1000_write_i2c_byte_generic(struct e1000_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)3123 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3124 u8 dev_addr, u8 data)
3125 {
3126 s32 status = E1000_SUCCESS;
3127 u32 max_retry = 1;
3128 u32 retry = 0;
3129 u16 swfw_mask = 0;
3130
3131 DEBUGFUNC("e1000_write_i2c_byte_generic");
3132
3133 swfw_mask = E1000_SWFW_PHY0_SM;
3134
3135 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3136 status = E1000_ERR_SWFW_SYNC;
3137 goto write_byte_out;
3138 }
3139
3140 do {
3141 e1000_i2c_start(hw);
3142
3143 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3144 if (status != E1000_SUCCESS)
3145 goto fail;
3146
3147 status = e1000_get_i2c_ack(hw);
3148 if (status != E1000_SUCCESS)
3149 goto fail;
3150
3151 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3152 if (status != E1000_SUCCESS)
3153 goto fail;
3154
3155 status = e1000_get_i2c_ack(hw);
3156 if (status != E1000_SUCCESS)
3157 goto fail;
3158
3159 status = e1000_clock_out_i2c_byte(hw, data);
3160 if (status != E1000_SUCCESS)
3161 goto fail;
3162
3163 status = e1000_get_i2c_ack(hw);
3164 if (status != E1000_SUCCESS)
3165 goto fail;
3166
3167 e1000_i2c_stop(hw);
3168 break;
3169
3170 fail:
3171 e1000_i2c_bus_clear(hw);
3172 retry++;
3173 if (retry < max_retry)
3174 DEBUGOUT("I2C byte write error - Retrying.\n");
3175 else
3176 DEBUGOUT("I2C byte write error.\n");
3177 } while (retry < max_retry);
3178
3179 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3180
3181 write_byte_out:
3182
3183 return status;
3184 }
3185
3186 /**
3187 * e1000_i2c_start - Sets I2C start condition
3188 * @hw: pointer to hardware structure
3189 *
3190 * Sets I2C start condition (High -> Low on SDA while SCL is High)
3191 **/
e1000_i2c_start(struct e1000_hw * hw)3192 static void e1000_i2c_start(struct e1000_hw *hw)
3193 {
3194 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3195
3196 DEBUGFUNC("e1000_i2c_start");
3197
3198 /* Start condition must begin with data and clock high */
3199 e1000_set_i2c_data(hw, &i2cctl, 1);
3200 e1000_raise_i2c_clk(hw, &i2cctl);
3201
3202 /* Setup time for start condition (4.7us) */
3203 usec_delay(E1000_I2C_T_SU_STA);
3204
3205 e1000_set_i2c_data(hw, &i2cctl, 0);
3206
3207 /* Hold time for start condition (4us) */
3208 usec_delay(E1000_I2C_T_HD_STA);
3209
3210 e1000_lower_i2c_clk(hw, &i2cctl);
3211
3212 /* Minimum low period of clock is 4.7 us */
3213 usec_delay(E1000_I2C_T_LOW);
3214
3215 }
3216
3217 /**
3218 * e1000_i2c_stop - Sets I2C stop condition
3219 * @hw: pointer to hardware structure
3220 *
3221 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
3222 **/
e1000_i2c_stop(struct e1000_hw * hw)3223 static void e1000_i2c_stop(struct e1000_hw *hw)
3224 {
3225 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3226
3227 DEBUGFUNC("e1000_i2c_stop");
3228
3229 /* Stop condition must begin with data low and clock high */
3230 e1000_set_i2c_data(hw, &i2cctl, 0);
3231 e1000_raise_i2c_clk(hw, &i2cctl);
3232
3233 /* Setup time for stop condition (4us) */
3234 usec_delay(E1000_I2C_T_SU_STO);
3235
3236 e1000_set_i2c_data(hw, &i2cctl, 1);
3237
3238 /* bus free time between stop and start (4.7us)*/
3239 usec_delay(E1000_I2C_T_BUF);
3240 }
3241
3242 /**
3243 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3244 * @hw: pointer to hardware structure
3245 * @data: data byte to clock in
3246 *
3247 * Clocks in one byte data via I2C data/clock
3248 **/
e1000_clock_in_i2c_byte(struct e1000_hw * hw,u8 * data)3249 static void e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3250 {
3251 s32 i;
3252 bool bit = 0;
3253
3254 DEBUGFUNC("e1000_clock_in_i2c_byte");
3255
3256 *data = 0;
3257 for (i = 7; i >= 0; i--) {
3258 e1000_clock_in_i2c_bit(hw, &bit);
3259 *data |= bit << i;
3260 }
3261 }
3262
3263 /**
3264 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3265 * @hw: pointer to hardware structure
3266 * @data: data byte clocked out
3267 *
3268 * Clocks out one byte data via I2C data/clock
3269 **/
e1000_clock_out_i2c_byte(struct e1000_hw * hw,u8 data)3270 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3271 {
3272 s32 status = E1000_SUCCESS;
3273 s32 i;
3274 u32 i2cctl;
3275 bool bit = 0;
3276
3277 DEBUGFUNC("e1000_clock_out_i2c_byte");
3278
3279 for (i = 7; i >= 0; i--) {
3280 bit = (data >> i) & 0x1;
3281 status = e1000_clock_out_i2c_bit(hw, bit);
3282
3283 if (status != E1000_SUCCESS)
3284 break;
3285 }
3286
3287 /* Release SDA line (set high) */
3288 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3289
3290 i2cctl |= E1000_I2C_DATA_OE_N;
3291 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3292 E1000_WRITE_FLUSH(hw);
3293
3294 return status;
3295 }
3296
3297 /**
3298 * e1000_get_i2c_ack - Polls for I2C ACK
3299 * @hw: pointer to hardware structure
3300 *
3301 * Clocks in/out one bit via I2C data/clock
3302 **/
e1000_get_i2c_ack(struct e1000_hw * hw)3303 static s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3304 {
3305 s32 status = E1000_SUCCESS;
3306 u32 i = 0;
3307 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3308 u32 timeout = 10;
3309 bool ack = true;
3310
3311 DEBUGFUNC("e1000_get_i2c_ack");
3312
3313 e1000_raise_i2c_clk(hw, &i2cctl);
3314
3315 /* Minimum high period of clock is 4us */
3316 usec_delay(E1000_I2C_T_HIGH);
3317
3318 /* Wait until SCL returns high */
3319 for (i = 0; i < timeout; i++) {
3320 usec_delay(1);
3321 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3322 if (i2cctl & E1000_I2C_CLK_IN)
3323 break;
3324 }
3325 if (!(i2cctl & E1000_I2C_CLK_IN))
3326 return E1000_ERR_I2C;
3327
3328 ack = e1000_get_i2c_data(&i2cctl);
3329 if (ack) {
3330 DEBUGOUT("I2C ack was not received.\n");
3331 status = E1000_ERR_I2C;
3332 }
3333
3334 e1000_lower_i2c_clk(hw, &i2cctl);
3335
3336 /* Minimum low period of clock is 4.7 us */
3337 usec_delay(E1000_I2C_T_LOW);
3338
3339 return status;
3340 }
3341
3342 /**
3343 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3344 * @hw: pointer to hardware structure
3345 * @data: read data value
3346 *
3347 * Clocks in one bit via I2C data/clock
3348 **/
e1000_clock_in_i2c_bit(struct e1000_hw * hw,bool * data)3349 static void e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3350 {
3351 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3352
3353 DEBUGFUNC("e1000_clock_in_i2c_bit");
3354
3355 e1000_raise_i2c_clk(hw, &i2cctl);
3356
3357 /* Minimum high period of clock is 4us */
3358 usec_delay(E1000_I2C_T_HIGH);
3359
3360 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3361 *data = e1000_get_i2c_data(&i2cctl);
3362
3363 e1000_lower_i2c_clk(hw, &i2cctl);
3364
3365 /* Minimum low period of clock is 4.7 us */
3366 usec_delay(E1000_I2C_T_LOW);
3367 }
3368
3369 /**
3370 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3371 * @hw: pointer to hardware structure
3372 * @data: data value to write
3373 *
3374 * Clocks out one bit via I2C data/clock
3375 **/
e1000_clock_out_i2c_bit(struct e1000_hw * hw,bool data)3376 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3377 {
3378 s32 status;
3379 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3380
3381 DEBUGFUNC("e1000_clock_out_i2c_bit");
3382
3383 status = e1000_set_i2c_data(hw, &i2cctl, data);
3384 if (status == E1000_SUCCESS) {
3385 e1000_raise_i2c_clk(hw, &i2cctl);
3386
3387 /* Minimum high period of clock is 4us */
3388 usec_delay(E1000_I2C_T_HIGH);
3389
3390 e1000_lower_i2c_clk(hw, &i2cctl);
3391
3392 /* Minimum low period of clock is 4.7 us.
3393 * This also takes care of the data hold time.
3394 */
3395 usec_delay(E1000_I2C_T_LOW);
3396 } else {
3397 status = E1000_ERR_I2C;
3398 DEBUGOUT1("I2C data was not set to %X\n", data);
3399 }
3400
3401 return status;
3402 }
3403 /**
3404 * e1000_raise_i2c_clk - Raises the I2C SCL clock
3405 * @hw: pointer to hardware structure
3406 * @i2cctl: Current value of I2CCTL register
3407 *
3408 * Raises the I2C clock line '0'->'1'
3409 **/
e1000_raise_i2c_clk(struct e1000_hw * hw,u32 * i2cctl)3410 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3411 {
3412 DEBUGFUNC("e1000_raise_i2c_clk");
3413
3414 *i2cctl |= E1000_I2C_CLK_OUT;
3415 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3416 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3417 E1000_WRITE_FLUSH(hw);
3418
3419 /* SCL rise time (1000ns) */
3420 usec_delay(E1000_I2C_T_RISE);
3421 }
3422
3423 /**
3424 * e1000_lower_i2c_clk - Lowers the I2C SCL clock
3425 * @hw: pointer to hardware structure
3426 * @i2cctl: Current value of I2CCTL register
3427 *
3428 * Lowers the I2C clock line '1'->'0'
3429 **/
e1000_lower_i2c_clk(struct e1000_hw * hw,u32 * i2cctl)3430 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3431 {
3432
3433 DEBUGFUNC("e1000_lower_i2c_clk");
3434
3435 *i2cctl &= ~E1000_I2C_CLK_OUT;
3436 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3437 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3438 E1000_WRITE_FLUSH(hw);
3439
3440 /* SCL fall time (300ns) */
3441 usec_delay(E1000_I2C_T_FALL);
3442 }
3443
3444 /**
3445 * e1000_set_i2c_data - Sets the I2C data bit
3446 * @hw: pointer to hardware structure
3447 * @i2cctl: Current value of I2CCTL register
3448 * @data: I2C data value (0 or 1) to set
3449 *
3450 * Sets the I2C data bit
3451 **/
e1000_set_i2c_data(struct e1000_hw * hw,u32 * i2cctl,bool data)3452 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3453 {
3454 s32 status = E1000_SUCCESS;
3455
3456 DEBUGFUNC("e1000_set_i2c_data");
3457
3458 if (data)
3459 *i2cctl |= E1000_I2C_DATA_OUT;
3460 else
3461 *i2cctl &= ~E1000_I2C_DATA_OUT;
3462
3463 *i2cctl &= ~E1000_I2C_DATA_OE_N;
3464 *i2cctl |= E1000_I2C_CLK_OE_N;
3465 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3466 E1000_WRITE_FLUSH(hw);
3467
3468 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3469 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3470
3471 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3472 if (data != e1000_get_i2c_data(i2cctl)) {
3473 status = E1000_ERR_I2C;
3474 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3475 }
3476
3477 return status;
3478 }
3479
3480 /**
3481 * e1000_get_i2c_data - Reads the I2C SDA data bit
3482 * @i2cctl: Current value of I2CCTL register
3483 *
3484 * Returns the I2C data bit value
3485 **/
e1000_get_i2c_data(u32 * i2cctl)3486 static bool e1000_get_i2c_data(u32 *i2cctl)
3487 {
3488 bool data;
3489
3490 DEBUGFUNC("e1000_get_i2c_data");
3491
3492 if (*i2cctl & E1000_I2C_DATA_IN)
3493 data = 1;
3494 else
3495 data = 0;
3496
3497 return data;
3498 }
3499
3500 /**
3501 * e1000_i2c_bus_clear - Clears the I2C bus
3502 * @hw: pointer to hardware structure
3503 *
3504 * Clears the I2C bus by sending nine clock pulses.
3505 * Used when data line is stuck low.
3506 **/
e1000_i2c_bus_clear(struct e1000_hw * hw)3507 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3508 {
3509 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3510 u32 i;
3511
3512 DEBUGFUNC("e1000_i2c_bus_clear");
3513
3514 e1000_i2c_start(hw);
3515
3516 e1000_set_i2c_data(hw, &i2cctl, 1);
3517
3518 for (i = 0; i < 9; i++) {
3519 e1000_raise_i2c_clk(hw, &i2cctl);
3520
3521 /* Min high period of clock is 4us */
3522 usec_delay(E1000_I2C_T_HIGH);
3523
3524 e1000_lower_i2c_clk(hw, &i2cctl);
3525
3526 /* Min low period of clock is 4.7us*/
3527 usec_delay(E1000_I2C_T_LOW);
3528 }
3529
3530 e1000_i2c_start(hw);
3531
3532 /* Put the i2c bus back to default state */
3533 e1000_i2c_stop(hw);
3534 }
3535
3536