| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InstructionSelect.cpp | 178 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg); in runOnMachineFunction() local
241 auto DstRC = MRI.getRegClass(DstReg); in runOnMachineFunction() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 295 const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg); in selectCopy() local
323 const TargetRegisterClass *DstRC = in selectCopy() local
767 static bool canTurnIntoCOPY(const TargetRegisterClass *DstRC, in canTurnIntoCOPY()
776 const TargetRegisterClass *DstRC, const unsigned SrcReg, in selectTurnIntoCOPY()
811 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectTruncOrPtrToInt() local
940 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectAnyext() local
1170 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectUAddSub() local
1301 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI); in emitExtractSubreg() local
1341 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI); in emitInsertSubreg() local
1862 const TargetRegisterClass *DstRC = getRegClass(Ty, DstReg, MRI); in selectSelect() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFixSGPRCopies.cpp | 202 const TargetRegisterClass *DstRC = DstReg.isVirtual() in getCopyRegClasses() local
210 const TargetRegisterClass *DstRC, in isVGPRToSGPRCopy()
217 const TargetRegisterClass *DstRC, in isSGPRToVGPRCopy()
285 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence() local
630 const TargetRegisterClass *SrcRC, *DstRC; in runOnMachineFunction() local
763 const TargetRegisterClass *SrcRC, *DstRC; in runOnMachineFunction() local
913 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in analyzeVGPRToSGPRCopy() local
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| H A D | AMDGPUInstructionSelector.cpp | 112 const TargetRegisterClass *DstRC in constrainCopyLikeIntrin() local
512 const TargetRegisterClass *DstRC = in selectG_EXTRACT() local
551 const TargetRegisterClass *DstRC = in selectG_MERGE_VALUES() local
612 const TargetRegisterClass *DstRC = in selectG_UNMERGE_VALUES() local
812 const TargetRegisterClass *DstRC = in selectG_INSERT() local
1453 const TargetRegisterClass *DstRC = TRI.getRegClassForSizeOnBank(32, *DstBank); in selectRelocConstant() local
2219 const TargetRegisterClass *DstRC = in selectG_TRUNC() local
2367 const TargetRegisterClass *DstRC = in selectG_SZA_EXT() local
2602 const TargetRegisterClass *DstRC = in selectG_CONSTANT() local
2935 const TargetRegisterClass *DstRC = TRI.getRegClassForTypeOnBank(Ty, *DstRB); in selectG_PTRMASK() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | DetectDeadLanes.cpp | 69 const TargetRegisterClass *DstRC, in isCrossCopy()
354 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes() local
447 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in isUndefInput() local
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| H A D | MachineCombiner.cpp | 177 auto DstRC = MRI->getRegClass(Dst); in isTransientMI() local
186 auto DstRC = MRI->getRegClass(Dst); in isTransientMI() local
194 auto DstRC = MRI->getRegClass(Dst); in isTransientMI() local
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| H A D | RegisterCoalescer.cpp | 493 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in setRegisters() local
1388 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in reMaterializeTrivialDef() local
1982 auto DstRC = MRI->getRegClass(CP.getDstReg()); in joinCopy() local
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| H A D | MachineVerifier.cpp | 1171 const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(Dst); in verifyPreISelGenericInstruction() local
2259 const TargetRegisterClass *DstRC = in visitMachineInstrBefore() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXCopy.cpp | 120 const TargetRegisterClass *DstRC = &PPC::VSLRCRegClass; in processBlock() local
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| H A D | PPCVSXSwapRemoval.cpp | 924 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in handleSpecialSwappables() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostSelectOptimize.cpp | 134 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in foldSimpleCrossClassCopies() local
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| H A D | AArch64InstructionSelector.cpp | 1016 const TargetRegisterClass *DstRC; in selectCopy() local
3161 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB); in select() local
3474 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB); in select() local
3732 unsigned EltSize, const TargetRegisterClass *DstRC, Register Scalar, in emitScalarToVector()
3824 auto *DstRC = &AArch64::GPR64RegClass; in selectMergeValues() local
3895 const TargetRegisterClass *DstRC = in emitExtractVectorElt() local
4517 const TargetRegisterClass *DstRC = in emitVectorConcat() local
5147 const TargetRegisterClass *DstRC = &AArch64::FPR128RegClass; in emitLaneInsert() local
5740 const TargetRegisterClass *DstRC = in tryOptBuildVecToSubregToReg() local
5773 const TargetRegisterClass *DstRC = &AArch64::FPR128RegClass; in selectBuildVector() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.cpp | 315 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | FastISelEmitter.cpp | 219 const CodeGenRegisterClass *DstRC = nullptr; in initialize() local
494 const CodeGenRegisterClass *DstRC = nullptr; in collectPatterns() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 355 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.cpp | 382 const TargetRegisterClass *DstRC, in shouldCoalesce() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVInstructionSelector.cpp | 896 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank( in selectCopy() local
919 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank( in selectImplicitDef() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCInstructionSelector.cpp | 139 const TargetRegisterClass *DstRC = in selectCopy() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 154 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; in EmitCopyFromReg() local
642 const TargetRegisterClass *DstRC = in EmitCopyToRegClassNode() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.cpp | 1068 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.cpp | 880 const TargetRegisterClass *DstRC, in shouldCoalesce()
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| H A D | ARMFastISel.cpp | 2041 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT); in FinishCall() local
2061 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); in FinishCall() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 262 const TargetRegisterClass *DstRC = RegInfo.getMinimalPhysRegClass(Dst); in expandCopyACC() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 1116 const TargetRegisterClass *DstRC, in shouldCoalesce()
|