1 //===-- RISCVDisassembler.cpp - Disassembler for RISC-V -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RISCVDisassembler class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "MCTargetDesc/RISCVBaseInfo.h"
14 #include "MCTargetDesc/RISCVMCTargetDesc.h"
15 #include "TargetInfo/RISCVTargetInfo.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCDecoderOps.h"
18 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/TargetRegistry.h"
24 #include "llvm/Support/Compiler.h"
25 #include "llvm/Support/Endian.h"
26
27 using namespace llvm;
28
29 #define DEBUG_TYPE "riscv-disassembler"
30
31 typedef MCDisassembler::DecodeStatus DecodeStatus;
32
33 namespace {
34 class RISCVDisassembler : public MCDisassembler {
35 std::unique_ptr<MCInstrInfo const> const MCII;
36
37 public:
RISCVDisassembler(const MCSubtargetInfo & STI,MCContext & Ctx,MCInstrInfo const * MCII)38 RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
39 MCInstrInfo const *MCII)
40 : MCDisassembler(STI, Ctx), MCII(MCII) {}
41
42 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
43 ArrayRef<uint8_t> Bytes, uint64_t Address,
44 raw_ostream &CStream) const override;
45
46 private:
47 void addSPOperands(MCInst &MI) const;
48
49 DecodeStatus getInstruction48(MCInst &Instr, uint64_t &Size,
50 ArrayRef<uint8_t> Bytes, uint64_t Address,
51 raw_ostream &CStream) const;
52
53 DecodeStatus getInstruction32(MCInst &Instr, uint64_t &Size,
54 ArrayRef<uint8_t> Bytes, uint64_t Address,
55 raw_ostream &CStream) const;
56 DecodeStatus getInstruction16(MCInst &Instr, uint64_t &Size,
57 ArrayRef<uint8_t> Bytes, uint64_t Address,
58 raw_ostream &CStream) const;
59 };
60 } // end anonymous namespace
61
createRISCVDisassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)62 static MCDisassembler *createRISCVDisassembler(const Target &T,
63 const MCSubtargetInfo &STI,
64 MCContext &Ctx) {
65 return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo());
66 }
67
68 extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
LLVMInitializeRISCVDisassembler()69 LLVMInitializeRISCVDisassembler() {
70 // Register the disassembler for each target.
71 TargetRegistry::RegisterMCDisassembler(getTheRISCV32Target(),
72 createRISCVDisassembler);
73 TargetRegistry::RegisterMCDisassembler(getTheRISCV64Target(),
74 createRISCVDisassembler);
75 }
76
DecodeGPRRegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder)77 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo,
78 uint64_t Address,
79 const MCDisassembler *Decoder) {
80 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
81
82 if (RegNo >= 32 || (IsRVE && RegNo >= 16))
83 return MCDisassembler::Fail;
84
85 MCRegister Reg = RISCV::X0 + RegNo;
86 Inst.addOperand(MCOperand::createReg(Reg));
87 return MCDisassembler::Success;
88 }
89
DecodeGPRF16RegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder)90 static DecodeStatus DecodeGPRF16RegisterClass(MCInst &Inst, uint32_t RegNo,
91 uint64_t Address,
92 const MCDisassembler *Decoder) {
93 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
94
95 if (RegNo >= 32 || (IsRVE && RegNo >= 16))
96 return MCDisassembler::Fail;
97
98 MCRegister Reg = RISCV::X0_H + RegNo;
99 Inst.addOperand(MCOperand::createReg(Reg));
100 return MCDisassembler::Success;
101 }
102
DecodeGPRF32RegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder)103 static DecodeStatus DecodeGPRF32RegisterClass(MCInst &Inst, uint32_t RegNo,
104 uint64_t Address,
105 const MCDisassembler *Decoder) {
106 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
107
108 if (RegNo >= 32 || (IsRVE && RegNo >= 16))
109 return MCDisassembler::Fail;
110
111 MCRegister Reg = RISCV::X0_W + RegNo;
112 Inst.addOperand(MCOperand::createReg(Reg));
113 return MCDisassembler::Success;
114 }
115
DecodeGPRX1X5RegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder)116 static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo,
117 uint64_t Address,
118 const MCDisassembler *Decoder) {
119 MCRegister Reg = RISCV::X0 + RegNo;
120 if (Reg != RISCV::X1 && Reg != RISCV::X5)
121 return MCDisassembler::Fail;
122
123 Inst.addOperand(MCOperand::createReg(Reg));
124 return MCDisassembler::Success;
125 }
126
DecodeFPR16RegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder)127 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo,
128 uint64_t Address,
129 const MCDisassembler *Decoder) {
130 if (RegNo >= 32)
131 return MCDisassembler::Fail;
132
133 MCRegister Reg = RISCV::F0_H + RegNo;
134 Inst.addOperand(MCOperand::createReg(Reg));
135 return MCDisassembler::Success;
136 }
137
DecodeFPR32RegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder)138 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint32_t RegNo,
139 uint64_t Address,
140 const MCDisassembler *Decoder) {
141 if (RegNo >= 32)
142 return MCDisassembler::Fail;
143
144 MCRegister Reg = RISCV::F0_F + RegNo;
145 Inst.addOperand(MCOperand::createReg(Reg));
146 return MCDisassembler::Success;
147 }
148
DecodeFPR32CRegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder)149 static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint32_t RegNo,
150 uint64_t Address,
151 const MCDisassembler *Decoder) {
152 if (RegNo >= 8) {
153 return MCDisassembler::Fail;
154 }
155 MCRegister Reg = RISCV::F8_F + RegNo;
156 Inst.addOperand(MCOperand::createReg(Reg));
157 return MCDisassembler::Success;
158 }
159
DecodeFPR64RegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder)160 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint32_t RegNo,
161 uint64_t Address,
162 const MCDisassembler *Decoder) {
163 if (RegNo >= 32)
164 return MCDisassembler::Fail;
165
166 MCRegister Reg = RISCV::F0_D + RegNo;
167 Inst.addOperand(MCOperand::createReg(Reg));
168 return MCDisassembler::Success;
169 }
170
DecodeFPR64CRegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder)171 static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint32_t RegNo,
172 uint64_t Address,
173 const MCDisassembler *Decoder) {
174 if (RegNo >= 8) {
175 return MCDisassembler::Fail;
176 }
177 MCRegister Reg = RISCV::F8_D + RegNo;
178 Inst.addOperand(MCOperand::createReg(Reg));
179 return MCDisassembler::Success;
180 }
181
DecodeFPR128RegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder)182 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, uint32_t RegNo,
183 uint64_t Address,
184 const MCDisassembler *Decoder) {
185 if (RegNo >= 32)
186 return MCDisassembler::Fail;
187
188 MCRegister Reg = RISCV::F0_Q + RegNo;
189 Inst.addOperand(MCOperand::createReg(Reg));
190 return MCDisassembler::Success;
191 }
192
DecodeGPRNoX0RegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder)193 static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo,
194 uint64_t Address,
195 const MCDisassembler *Decoder) {
196 if (RegNo == 0) {
197 return MCDisassembler::Fail;
198 }
199
200 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
201 }
202
203 static DecodeStatus
DecodeGPRNoX0X2RegisterClass(MCInst & Inst,uint64_t RegNo,uint32_t Address,const MCDisassembler * Decoder)204 DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint32_t Address,
205 const MCDisassembler *Decoder) {
206 if (RegNo == 2) {
207 return MCDisassembler::Fail;
208 }
209
210 return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);
211 }
212
DecodeGPRNoX31RegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder)213 static DecodeStatus DecodeGPRNoX31RegisterClass(MCInst &Inst, uint32_t RegNo,
214 uint64_t Address,
215 const MCDisassembler *Decoder) {
216 if (RegNo == 31) {
217 return MCDisassembler::Fail;
218 }
219
220 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
221 }
222
DecodeGPRCRegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder)223 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo,
224 uint64_t Address,
225 const MCDisassembler *Decoder) {
226 if (RegNo >= 8)
227 return MCDisassembler::Fail;
228
229 MCRegister Reg = RISCV::X8 + RegNo;
230 Inst.addOperand(MCOperand::createReg(Reg));
231 return MCDisassembler::Success;
232 }
233
DecodeGPRPairRegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder)234 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo,
235 uint64_t Address,
236 const MCDisassembler *Decoder) {
237 if (RegNo >= 32 || RegNo % 2)
238 return MCDisassembler::Fail;
239
240 const RISCVDisassembler *Dis =
241 static_cast<const RISCVDisassembler *>(Decoder);
242 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
243 MCRegister Reg = RI->getMatchingSuperReg(
244 RISCV::X0 + RegNo, RISCV::sub_gpr_even,
245 &RISCVMCRegisterClasses[RISCV::GPRPairRegClassID]);
246 Inst.addOperand(MCOperand::createReg(Reg));
247 return MCDisassembler::Success;
248 }
249
DecodeGPRPairCRegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder)250 static DecodeStatus DecodeGPRPairCRegisterClass(MCInst &Inst, uint32_t RegNo,
251 uint64_t Address,
252 const MCDisassembler *Decoder) {
253 if (RegNo >= 8 || RegNo % 2)
254 return MCDisassembler::Fail;
255
256 const RISCVDisassembler *Dis =
257 static_cast<const RISCVDisassembler *>(Decoder);
258 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
259 MCRegister Reg = RI->getMatchingSuperReg(
260 RISCV::X8 + RegNo, RISCV::sub_gpr_even,
261 &RISCVMCRegisterClasses[RISCV::GPRPairCRegClassID]);
262 Inst.addOperand(MCOperand::createReg(Reg));
263 return MCDisassembler::Success;
264 }
265
DecodeSR07RegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const void * Decoder)266 static DecodeStatus DecodeSR07RegisterClass(MCInst &Inst, uint32_t RegNo,
267 uint64_t Address,
268 const void *Decoder) {
269 if (RegNo >= 8)
270 return MCDisassembler::Fail;
271
272 MCRegister Reg = (RegNo < 2) ? (RegNo + RISCV::X8) : (RegNo - 2 + RISCV::X18);
273 Inst.addOperand(MCOperand::createReg(Reg));
274 return MCDisassembler::Success;
275 }
276
DecodeVRRegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder)277 static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo,
278 uint64_t Address,
279 const MCDisassembler *Decoder) {
280 if (RegNo >= 32)
281 return MCDisassembler::Fail;
282
283 MCRegister Reg = RISCV::V0 + RegNo;
284 Inst.addOperand(MCOperand::createReg(Reg));
285 return MCDisassembler::Success;
286 }
287
DecodeVRM2RegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder)288 static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo,
289 uint64_t Address,
290 const MCDisassembler *Decoder) {
291 if (RegNo >= 32 || RegNo % 2)
292 return MCDisassembler::Fail;
293
294 const RISCVDisassembler *Dis =
295 static_cast<const RISCVDisassembler *>(Decoder);
296 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
297 MCRegister Reg =
298 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
299 &RISCVMCRegisterClasses[RISCV::VRM2RegClassID]);
300
301 Inst.addOperand(MCOperand::createReg(Reg));
302 return MCDisassembler::Success;
303 }
304
DecodeVRM4RegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder)305 static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint32_t RegNo,
306 uint64_t Address,
307 const MCDisassembler *Decoder) {
308 if (RegNo >= 32 || RegNo % 4)
309 return MCDisassembler::Fail;
310
311 const RISCVDisassembler *Dis =
312 static_cast<const RISCVDisassembler *>(Decoder);
313 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
314 MCRegister Reg =
315 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
316 &RISCVMCRegisterClasses[RISCV::VRM4RegClassID]);
317
318 Inst.addOperand(MCOperand::createReg(Reg));
319 return MCDisassembler::Success;
320 }
321
DecodeVRM8RegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder)322 static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo,
323 uint64_t Address,
324 const MCDisassembler *Decoder) {
325 if (RegNo >= 32 || RegNo % 8)
326 return MCDisassembler::Fail;
327
328 const RISCVDisassembler *Dis =
329 static_cast<const RISCVDisassembler *>(Decoder);
330 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
331 MCRegister Reg =
332 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
333 &RISCVMCRegisterClasses[RISCV::VRM8RegClassID]);
334
335 Inst.addOperand(MCOperand::createReg(Reg));
336 return MCDisassembler::Success;
337 }
338
DecodeVMV0RegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder)339 static DecodeStatus DecodeVMV0RegisterClass(MCInst &Inst, uint32_t RegNo,
340 uint64_t Address,
341 const MCDisassembler *Decoder) {
342 if (RegNo)
343 return MCDisassembler::Fail;
344
345 Inst.addOperand(MCOperand::createReg(RISCV::V0));
346 return MCDisassembler::Success;
347 }
348
DecodeTRRegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder)349 static DecodeStatus DecodeTRRegisterClass(MCInst &Inst, uint32_t RegNo,
350 uint64_t Address,
351 const MCDisassembler *Decoder) {
352 if (RegNo > 15)
353 return MCDisassembler::Fail;
354
355 MCRegister Reg = RISCV::T0 + RegNo;
356 Inst.addOperand(MCOperand::createReg(Reg));
357 return MCDisassembler::Success;
358 }
359
DecodeTRM2RegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder)360 static DecodeStatus DecodeTRM2RegisterClass(MCInst &Inst, uint32_t RegNo,
361 uint64_t Address,
362 const MCDisassembler *Decoder) {
363 if (RegNo > 15 || RegNo % 2)
364 return MCDisassembler::Fail;
365
366 MCRegister Reg = RISCV::T0 + RegNo;
367 Inst.addOperand(MCOperand::createReg(Reg));
368 return MCDisassembler::Success;
369 }
370
DecodeTRM4RegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder)371 static DecodeStatus DecodeTRM4RegisterClass(MCInst &Inst, uint32_t RegNo,
372 uint64_t Address,
373 const MCDisassembler *Decoder) {
374 if (RegNo > 15 || RegNo % 4)
375 return MCDisassembler::Fail;
376
377 MCRegister Reg = RISCV::T0 + RegNo;
378 Inst.addOperand(MCOperand::createReg(Reg));
379 return MCDisassembler::Success;
380 }
381
decodeVMaskReg(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder)382 static DecodeStatus decodeVMaskReg(MCInst &Inst, uint32_t RegNo,
383 uint64_t Address,
384 const MCDisassembler *Decoder) {
385 if (RegNo >= 2)
386 return MCDisassembler::Fail;
387
388 MCRegister Reg = (RegNo == 0) ? RISCV::V0 : RISCV::NoRegister;
389
390 Inst.addOperand(MCOperand::createReg(Reg));
391 return MCDisassembler::Success;
392 }
393
394 template <unsigned N>
decodeUImmOperand(MCInst & Inst,uint32_t Imm,int64_t Address,const MCDisassembler * Decoder)395 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm,
396 int64_t Address,
397 const MCDisassembler *Decoder) {
398 assert(isUInt<N>(Imm) && "Invalid immediate");
399 Inst.addOperand(MCOperand::createImm(Imm));
400 return MCDisassembler::Success;
401 }
402
403 template <unsigned Width, unsigned LowerBound>
decodeUImmOperandGE(MCInst & Inst,uint32_t Imm,int64_t Address,const MCDisassembler * Decoder)404 static DecodeStatus decodeUImmOperandGE(MCInst &Inst, uint32_t Imm,
405 int64_t Address,
406 const MCDisassembler *Decoder) {
407 assert(isUInt<Width>(Imm) && "Invalid immediate");
408
409 if (Imm < LowerBound)
410 return MCDisassembler::Fail;
411
412 Inst.addOperand(MCOperand::createImm(Imm));
413 return MCDisassembler::Success;
414 }
415
416 template <unsigned Width, unsigned LowerBound>
decodeUImmPlus1OperandGE(MCInst & Inst,uint32_t Imm,int64_t Address,const MCDisassembler * Decoder)417 static DecodeStatus decodeUImmPlus1OperandGE(MCInst &Inst, uint32_t Imm,
418 int64_t Address,
419 const MCDisassembler *Decoder) {
420 assert(isUInt<Width>(Imm) && "Invalid immediate");
421
422 if ((Imm + 1) < LowerBound)
423 return MCDisassembler::Fail;
424
425 Inst.addOperand(MCOperand::createImm(Imm + 1));
426 return MCDisassembler::Success;
427 }
428
decodeUImmSlistOperand(MCInst & Inst,uint32_t Imm,int64_t Address,const MCDisassembler * Decoder)429 static DecodeStatus decodeUImmSlistOperand(MCInst &Inst, uint32_t Imm,
430 int64_t Address,
431 const MCDisassembler *Decoder) {
432 assert(isUInt<3>(Imm) && "Invalid Slist immediate");
433 const uint8_t Slist[] = {0, 1, 2, 4, 8, 16, 15, 31};
434 Inst.addOperand(MCOperand::createImm(Slist[Imm]));
435 return MCDisassembler::Success;
436 }
437
decodeUImmLog2XLenOperand(MCInst & Inst,uint32_t Imm,int64_t Address,const MCDisassembler * Decoder)438 static DecodeStatus decodeUImmLog2XLenOperand(MCInst &Inst, uint32_t Imm,
439 int64_t Address,
440 const MCDisassembler *Decoder) {
441 assert(isUInt<6>(Imm) && "Invalid immediate");
442
443 if (!Decoder->getSubtargetInfo().hasFeature(RISCV::Feature64Bit) &&
444 !isUInt<5>(Imm))
445 return MCDisassembler::Fail;
446
447 Inst.addOperand(MCOperand::createImm(Imm));
448 return MCDisassembler::Success;
449 }
450
451 template <unsigned N>
decodeUImmNonZeroOperand(MCInst & Inst,uint32_t Imm,int64_t Address,const MCDisassembler * Decoder)452 static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
453 int64_t Address,
454 const MCDisassembler *Decoder) {
455 if (Imm == 0)
456 return MCDisassembler::Fail;
457 return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
458 }
459
460 static DecodeStatus
decodeUImmLog2XLenNonZeroOperand(MCInst & Inst,uint32_t Imm,int64_t Address,const MCDisassembler * Decoder)461 decodeUImmLog2XLenNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address,
462 const MCDisassembler *Decoder) {
463 if (Imm == 0)
464 return MCDisassembler::Fail;
465 return decodeUImmLog2XLenOperand(Inst, Imm, Address, Decoder);
466 }
467
468 template <unsigned N>
decodeUImmPlus1Operand(MCInst & Inst,uint32_t Imm,int64_t Address,const MCDisassembler * Decoder)469 static DecodeStatus decodeUImmPlus1Operand(MCInst &Inst, uint32_t Imm,
470 int64_t Address,
471 const MCDisassembler *Decoder) {
472 assert(isUInt<N>(Imm) && "Invalid immediate");
473 Inst.addOperand(MCOperand::createImm(Imm + 1));
474 return MCDisassembler::Success;
475 }
476
477 template <unsigned N>
decodeSImmOperand(MCInst & Inst,uint32_t Imm,int64_t Address,const MCDisassembler * Decoder)478 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm,
479 int64_t Address,
480 const MCDisassembler *Decoder) {
481 assert(isUInt<N>(Imm) && "Invalid immediate");
482 // Sign-extend the number in the bottom N bits of Imm
483 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
484 return MCDisassembler::Success;
485 }
486
487 template <unsigned N>
decodeSImmNonZeroOperand(MCInst & Inst,uint32_t Imm,int64_t Address,const MCDisassembler * Decoder)488 static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
489 int64_t Address,
490 const MCDisassembler *Decoder) {
491 if (Imm == 0)
492 return MCDisassembler::Fail;
493 return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
494 }
495
496 template <unsigned T, unsigned N>
decodeSImmOperandAndLslN(MCInst & Inst,uint32_t Imm,int64_t Address,const MCDisassembler * Decoder)497 static DecodeStatus decodeSImmOperandAndLslN(MCInst &Inst, uint32_t Imm,
498 int64_t Address,
499 const MCDisassembler *Decoder) {
500 assert(isUInt<T - N + 1>(Imm) && "Invalid immediate");
501 // Sign-extend the number in the bottom T bits of Imm after accounting for
502 // the fact that the T bit immediate is stored in T-N bits (the LSB is
503 // always zero)
504 Inst.addOperand(MCOperand::createImm(SignExtend64<T>(Imm << N)));
505 return MCDisassembler::Success;
506 }
507
decodeCLUIImmOperand(MCInst & Inst,uint32_t Imm,int64_t Address,const MCDisassembler * Decoder)508 static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint32_t Imm,
509 int64_t Address,
510 const MCDisassembler *Decoder) {
511 assert(isUInt<6>(Imm) && "Invalid immediate");
512 if (Imm == 0)
513 return MCDisassembler::Fail;
514 Imm = SignExtend64<6>(Imm) & 0xfffff;
515 Inst.addOperand(MCOperand::createImm(Imm));
516 return MCDisassembler::Success;
517 }
518
decodeFRMArg(MCInst & Inst,uint32_t Imm,int64_t Address,const MCDisassembler * Decoder)519 static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address,
520 const MCDisassembler *Decoder) {
521 assert(isUInt<3>(Imm) && "Invalid immediate");
522 if (!llvm::RISCVFPRndMode::isValidRoundingMode(Imm))
523 return MCDisassembler::Fail;
524
525 Inst.addOperand(MCOperand::createImm(Imm));
526 return MCDisassembler::Success;
527 }
528
decodeRTZArg(MCInst & Inst,uint32_t Imm,int64_t Address,const MCDisassembler * Decoder)529 static DecodeStatus decodeRTZArg(MCInst &Inst, uint32_t Imm, int64_t Address,
530 const MCDisassembler *Decoder) {
531 assert(isUInt<3>(Imm) && "Invalid immediate");
532 if (Imm != RISCVFPRndMode::RTZ)
533 return MCDisassembler::Fail;
534
535 Inst.addOperand(MCOperand::createImm(Imm));
536 return MCDisassembler::Success;
537 }
538
539 static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
540 uint64_t Address,
541 const MCDisassembler *Decoder);
542
543 static DecodeStatus decodeRVCInstrRdSImm6(MCInst &Inst, uint32_t Insn,
544 uint64_t Address,
545 const MCDisassembler *Decoder);
546
547 static DecodeStatus decodeRVCInstrRdCLUIImm(MCInst &Inst, uint32_t Insn,
548 uint64_t Address,
549 const MCDisassembler *Decoder);
550
551 static DecodeStatus
552 decodeRVCInstrRdRs1UImmLog2XLenNonZero(MCInst &Inst, uint32_t Insn,
553 uint64_t Address,
554 const MCDisassembler *Decoder);
555
556 static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn,
557 uint64_t Address,
558 const MCDisassembler *Decoder);
559
560 static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn,
561 uint64_t Address,
562 const MCDisassembler *Decoder);
563
564 static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
565 uint64_t Address,
566 const MCDisassembler *Decoder);
567
568 static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm,
569 uint64_t Address,
570 const MCDisassembler *Decoder);
571
572 static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm,
573 uint64_t Address,
574 const MCDisassembler *Decoder);
575
576 static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
577 uint64_t Address,
578 const MCDisassembler *Decoder);
579
580 #include "RISCVGenDisassemblerTables.inc"
581
decodeRVCInstrRdRs1ImmZero(MCInst & Inst,uint32_t Insn,uint64_t Address,const MCDisassembler * Decoder)582 static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
583 uint64_t Address,
584 const MCDisassembler *Decoder) {
585 DecodeStatus S = MCDisassembler::Success;
586 uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
587 if (!Check(S, DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder)))
588 return MCDisassembler::Fail;
589 Inst.addOperand(Inst.getOperand(0));
590 Inst.addOperand(MCOperand::createImm(0));
591 return S;
592 }
593
decodeCSSPushPopchk(MCInst & Inst,uint32_t Insn,uint64_t Address,const MCDisassembler * Decoder)594 static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
595 uint64_t Address,
596 const MCDisassembler *Decoder) {
597 uint32_t Rs1 = fieldFromInstruction(Insn, 7, 5);
598 [[maybe_unused]] DecodeStatus Result =
599 DecodeGPRX1X5RegisterClass(Inst, Rs1, Address, Decoder);
600 assert(Result == MCDisassembler::Success && "Invalid register");
601 return MCDisassembler::Success;
602 }
603
decodeRVCInstrRdSImm6(MCInst & Inst,uint32_t Insn,uint64_t Address,const MCDisassembler * Decoder)604 static DecodeStatus decodeRVCInstrRdSImm6(MCInst &Inst, uint32_t Insn,
605 uint64_t Address,
606 const MCDisassembler *Decoder) {
607 Inst.addOperand(MCOperand::createReg(RISCV::X0));
608 uint32_t Imm =
609 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
610 [[maybe_unused]] DecodeStatus Result =
611 decodeSImmOperand<6>(Inst, Imm, Address, Decoder);
612 assert(Result == MCDisassembler::Success && "Invalid immediate");
613 return MCDisassembler::Success;
614 }
615
decodeRVCInstrRdCLUIImm(MCInst & Inst,uint32_t Insn,uint64_t Address,const MCDisassembler * Decoder)616 static DecodeStatus decodeRVCInstrRdCLUIImm(MCInst &Inst, uint32_t Insn,
617 uint64_t Address,
618 const MCDisassembler *Decoder) {
619 Inst.addOperand(MCOperand::createReg(RISCV::X0));
620 uint32_t Imm =
621 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
622 return decodeCLUIImmOperand(Inst, Imm, Address, Decoder);
623 }
624
625 static DecodeStatus
decodeRVCInstrRdRs1UImmLog2XLenNonZero(MCInst & Inst,uint32_t Insn,uint64_t Address,const MCDisassembler * Decoder)626 decodeRVCInstrRdRs1UImmLog2XLenNonZero(MCInst &Inst, uint32_t Insn,
627 uint64_t Address,
628 const MCDisassembler *Decoder) {
629 Inst.addOperand(MCOperand::createReg(RISCV::X0));
630 Inst.addOperand(Inst.getOperand(0));
631
632 uint32_t UImm6 =
633 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
634 return decodeUImmLog2XLenNonZeroOperand(Inst, UImm6, Address, Decoder);
635 }
636
decodeRVCInstrRdRs2(MCInst & Inst,uint32_t Insn,uint64_t Address,const MCDisassembler * Decoder)637 static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn,
638 uint64_t Address,
639 const MCDisassembler *Decoder) {
640 DecodeStatus S = MCDisassembler::Success;
641 uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
642 uint32_t Rs2 = fieldFromInstruction(Insn, 2, 5);
643 if (!Check(S, DecodeGPRRegisterClass(Inst, Rd, Address, Decoder)))
644 return MCDisassembler::Fail;
645 if (!Check(S, DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder)))
646 return MCDisassembler::Fail;
647 return S;
648 }
649
decodeRVCInstrRdRs1Rs2(MCInst & Inst,uint32_t Insn,uint64_t Address,const MCDisassembler * Decoder)650 static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn,
651 uint64_t Address,
652 const MCDisassembler *Decoder) {
653 DecodeStatus S = MCDisassembler::Success;
654 uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
655 uint32_t Rs2 = fieldFromInstruction(Insn, 2, 5);
656 if (!Check(S, DecodeGPRRegisterClass(Inst, Rd, Address, Decoder)))
657 return MCDisassembler::Fail;
658 Inst.addOperand(Inst.getOperand(0));
659 if (!Check(S, DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder)))
660 return MCDisassembler::Fail;
661 return S;
662 }
663
decodeXTHeadMemPair(MCInst & Inst,uint32_t Insn,uint64_t Address,const MCDisassembler * Decoder)664 static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
665 uint64_t Address,
666 const MCDisassembler *Decoder) {
667 DecodeStatus S = MCDisassembler::Success;
668 uint32_t Rd1 = fieldFromInstruction(Insn, 7, 5);
669 uint32_t Rs1 = fieldFromInstruction(Insn, 15, 5);
670 uint32_t Rd2 = fieldFromInstruction(Insn, 20, 5);
671 uint32_t UImm2 = fieldFromInstruction(Insn, 25, 2);
672 if (!Check(S, DecodeGPRRegisterClass(Inst, Rd1, Address, Decoder)))
673 return MCDisassembler::Fail;
674 if (!Check(S, DecodeGPRRegisterClass(Inst, Rd2, Address, Decoder)))
675 return MCDisassembler::Fail;
676 if (!Check(S, DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder)))
677 return MCDisassembler::Fail;
678 [[maybe_unused]] DecodeStatus Result =
679 decodeUImmOperand<2>(Inst, UImm2, Address, Decoder);
680 assert(Result == MCDisassembler::Success && "Invalid immediate");
681
682 // Disassemble the final operand which is implicit.
683 unsigned Opcode = Inst.getOpcode();
684 bool IsWordOp = (Opcode == RISCV::TH_LWD || Opcode == RISCV::TH_LWUD ||
685 Opcode == RISCV::TH_SWD);
686 if (IsWordOp)
687 Inst.addOperand(MCOperand::createImm(3));
688 else
689 Inst.addOperand(MCOperand::createImm(4));
690
691 return S;
692 }
693
decodeZcmpRlist(MCInst & Inst,uint32_t Imm,uint64_t Address,const MCDisassembler * Decoder)694 static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm,
695 uint64_t Address,
696 const MCDisassembler *Decoder) {
697 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
698 if (Imm < RISCVZC::RA || (IsRVE && Imm >= RISCVZC::RA_S0_S2))
699 return MCDisassembler::Fail;
700 Inst.addOperand(MCOperand::createImm(Imm));
701 return MCDisassembler::Success;
702 }
703
decodeXqccmpRlistS0(MCInst & Inst,uint32_t Imm,uint64_t Address,const MCDisassembler * Decoder)704 static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm,
705 uint64_t Address,
706 const MCDisassembler *Decoder) {
707 if (Imm < RISCVZC::RA_S0)
708 return MCDisassembler::Fail;
709 return decodeZcmpRlist(Inst, Imm, Address, Decoder);
710 }
711
712 // Add implied SP operand for C.*SP compressed instructions. The SP operand
713 // isn't explicitly encoded in the instruction.
addSPOperands(MCInst & MI) const714 void RISCVDisassembler::addSPOperands(MCInst &MI) const {
715 const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
716 for (unsigned i = 0; i < MCID.getNumOperands(); i++)
717 if (MCID.operands()[i].RegClass == RISCV::SPRegClassID)
718 MI.insert(MI.begin() + i, MCOperand::createReg(RISCV::X2));
719 }
720
721 namespace {
722
723 struct DecoderListEntry {
724 const uint8_t *Table;
725 FeatureBitset ContainedFeatures;
726 const char *Desc;
727
haveContainedFeatures__anonccb4078e0211::DecoderListEntry728 bool haveContainedFeatures(const FeatureBitset &ActiveFeatures) const {
729 return ContainedFeatures.none() ||
730 (ContainedFeatures & ActiveFeatures).any();
731 }
732 };
733
734 } // end anonymous namespace
735
736 static constexpr FeatureBitset XCVFeatureGroup = {
737 RISCV::FeatureVendorXCVbitmanip, RISCV::FeatureVendorXCVelw,
738 RISCV::FeatureVendorXCVmac, RISCV::FeatureVendorXCVmem,
739 RISCV::FeatureVendorXCValu, RISCV::FeatureVendorXCVsimd,
740 RISCV::FeatureVendorXCVbi};
741
742 static constexpr FeatureBitset XRivosFeatureGroup = {
743 RISCV::FeatureVendorXRivosVisni,
744 RISCV::FeatureVendorXRivosVizip,
745 };
746
747 static constexpr FeatureBitset XqciFeatureGroup = {
748 RISCV::FeatureVendorXqcia, RISCV::FeatureVendorXqciac,
749 RISCV::FeatureVendorXqcibi, RISCV::FeatureVendorXqcibm,
750 RISCV::FeatureVendorXqcicli, RISCV::FeatureVendorXqcicm,
751 RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr,
752 RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqciio,
753 RISCV::FeatureVendorXqcilb, RISCV::FeatureVendorXqcili,
754 RISCV::FeatureVendorXqcilia, RISCV::FeatureVendorXqcilo,
755 RISCV::FeatureVendorXqcilsm, RISCV::FeatureVendorXqcisim,
756 RISCV::FeatureVendorXqcisls, RISCV::FeatureVendorXqcisync,
757 };
758
759 static constexpr FeatureBitset XSfVectorGroup = {
760 RISCV::FeatureVendorXSfvcp, RISCV::FeatureVendorXSfvqmaccdod,
761 RISCV::FeatureVendorXSfvqmaccqoq, RISCV::FeatureVendorXSfvfwmaccqqq,
762 RISCV::FeatureVendorXSfvfnrclipxfqf, RISCV::FeatureVendorXSfmmbase};
763 static constexpr FeatureBitset XSfSystemGroup = {
764 RISCV::FeatureVendorXSiFivecdiscarddlone,
765 RISCV::FeatureVendorXSiFivecflushdlone,
766 };
767
768 static constexpr FeatureBitset XTHeadGroup = {
769 RISCV::FeatureVendorXTHeadBa, RISCV::FeatureVendorXTHeadBb,
770 RISCV::FeatureVendorXTHeadBs, RISCV::FeatureVendorXTHeadCondMov,
771 RISCV::FeatureVendorXTHeadCmo, RISCV::FeatureVendorXTHeadFMemIdx,
772 RISCV::FeatureVendorXTHeadMac, RISCV::FeatureVendorXTHeadMemIdx,
773 RISCV::FeatureVendorXTHeadMemPair, RISCV::FeatureVendorXTHeadSync,
774 RISCV::FeatureVendorXTHeadVdot};
775
776 static constexpr FeatureBitset XAndesGroup = {
777 RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesBFHCvt,
778 RISCV::FeatureVendorXAndesVBFHCvt,
779 RISCV::FeatureVendorXAndesVSIntLoad, RISCV::FeatureVendorXAndesVPackFPH,
780 RISCV::FeatureVendorXAndesVDot};
781
782 static constexpr DecoderListEntry DecoderList32[]{
783 // Vendor Extensions
784 {DecoderTableXVentana32,
785 {RISCV::FeatureVendorXVentanaCondOps},
786 "XVentanaCondOps"},
787 {DecoderTableXTHead32, XTHeadGroup, "T-Head extensions"},
788 {DecoderTableXSfvector32, XSfVectorGroup, "SiFive vector extensions"},
789 {DecoderTableXSfsystem32, XSfSystemGroup, "SiFive system extensions"},
790 {DecoderTableXSfcease32, {RISCV::FeatureVendorXSfcease}, "SiFive sf.cease"},
791 {DecoderTableXmipslsp32, {RISCV::FeatureVendorXMIPSLSP}, "MIPS mips.lsp"},
792 {DecoderTableXmipscmov32,
793 {RISCV::FeatureVendorXMIPSCMov},
794 "MIPS mips.ccmov"},
795 {DecoderTableXmipscbop32,
796 {RISCV::FeatureVendorXMIPSCBOP},
797 "MIPS mips.pref"},
798 {DecoderTableXAndes32, XAndesGroup, "Andes extensions"},
799 // Standard Extensions
800 {DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"},
801 {DecoderTableXqci32, XqciFeatureGroup, "Qualcomm uC Extensions"},
802 {DecoderTableXRivos32, XRivosFeatureGroup, "Rivos"},
803 {DecoderTable32, {}, "standard 32-bit instructions"},
804 {DecoderTableRV32Only32, {}, "RV32-only standard 32-bit instructions"},
805 {DecoderTableZfinx32, {}, "Zfinx (Float in Integer)"},
806 {DecoderTableZdinxRV32Only32, {}, "RV32-only Zdinx (Double in Integer)"},
807 };
808
getInstruction32(MCInst & MI,uint64_t & Size,ArrayRef<uint8_t> Bytes,uint64_t Address,raw_ostream & CS) const809 DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
810 ArrayRef<uint8_t> Bytes,
811 uint64_t Address,
812 raw_ostream &CS) const {
813 if (Bytes.size() < 4) {
814 Size = 0;
815 return MCDisassembler::Fail;
816 }
817 Size = 4;
818
819 // Use uint64_t to match getInstruction48. decodeInstruction is templated
820 // on the Insn type.
821 uint64_t Insn = support::endian::read32le(Bytes.data());
822
823 for (const DecoderListEntry &Entry : DecoderList32) {
824 if (!Entry.haveContainedFeatures(STI.getFeatureBits()))
825 continue;
826
827 LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
828 DecodeStatus Result =
829 decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);
830 if (Result == MCDisassembler::Fail)
831 continue;
832
833 return Result;
834 }
835
836 return MCDisassembler::Fail;
837 }
838
839 static constexpr DecoderListEntry DecoderList16[]{
840 // Vendor Extensions
841 {DecoderTableXqci16, XqciFeatureGroup, "Qualcomm uC 16-bit"},
842 {DecoderTableXqccmp16,
843 {RISCV::FeatureVendorXqccmp},
844 "Xqccmp (Qualcomm 16-bit Push/Pop & Double Move Instructions)"},
845 {DecoderTableXwchc16, {RISCV::FeatureVendorXwchc}, "WCH QingKe XW"},
846 // Standard Extensions
847 // DecoderTableZicfiss16 must be checked before DecoderTable16.
848 {DecoderTableZicfiss16, {}, "Zicfiss (Shadow Stack 16-bit)"},
849 {DecoderTable16, {}, "standard 16-bit instructions"},
850 {DecoderTableRV32Only16, {}, "RV32-only 16-bit instructions"},
851 // Zc* instructions incompatible with Zcf or Zcd
852 {DecoderTableZcOverlap16,
853 {},
854 "ZcOverlap (16-bit Instructions overlapping with Zcf/Zcd)"},
855 };
856
getInstruction16(MCInst & MI,uint64_t & Size,ArrayRef<uint8_t> Bytes,uint64_t Address,raw_ostream & CS) const857 DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size,
858 ArrayRef<uint8_t> Bytes,
859 uint64_t Address,
860 raw_ostream &CS) const {
861 if (Bytes.size() < 2) {
862 Size = 0;
863 return MCDisassembler::Fail;
864 }
865 Size = 2;
866
867 // Use uint64_t to match getInstruction48. decodeInstruction is templated
868 // on the Insn type.
869 uint64_t Insn = support::endian::read16le(Bytes.data());
870
871 for (const DecoderListEntry &Entry : DecoderList16) {
872 if (!Entry.haveContainedFeatures(STI.getFeatureBits()))
873 continue;
874
875 LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
876 DecodeStatus Result =
877 decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);
878 if (Result == MCDisassembler::Fail)
879 continue;
880
881 addSPOperands(MI);
882
883 return Result;
884 }
885
886 return MCDisassembler::Fail;
887 }
888
889 static constexpr DecoderListEntry DecoderList48[]{
890 {DecoderTableXqci48, XqciFeatureGroup, "Qualcomm uC 48bit"},
891 };
892
getInstruction48(MCInst & MI,uint64_t & Size,ArrayRef<uint8_t> Bytes,uint64_t Address,raw_ostream & CS) const893 DecodeStatus RISCVDisassembler::getInstruction48(MCInst &MI, uint64_t &Size,
894 ArrayRef<uint8_t> Bytes,
895 uint64_t Address,
896 raw_ostream &CS) const {
897 if (Bytes.size() < 6) {
898 Size = 0;
899 return MCDisassembler::Fail;
900 }
901 Size = 6;
902
903 uint64_t Insn = 0;
904 for (size_t i = Size; i-- != 0;)
905 Insn += (static_cast<uint64_t>(Bytes[i]) << 8 * i);
906
907 for (const DecoderListEntry &Entry : DecoderList48) {
908 if (!Entry.haveContainedFeatures(STI.getFeatureBits()))
909 continue;
910
911 LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
912 DecodeStatus Result =
913 decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);
914 if (Result == MCDisassembler::Fail)
915 continue;
916
917 return Result;
918 }
919
920 return MCDisassembler::Fail;
921 }
922
getInstruction(MCInst & MI,uint64_t & Size,ArrayRef<uint8_t> Bytes,uint64_t Address,raw_ostream & CS) const923 DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
924 ArrayRef<uint8_t> Bytes,
925 uint64_t Address,
926 raw_ostream &CS) const {
927 CommentStream = &CS;
928 // It's a 16 bit instruction if bit 0 and 1 are not 0b11.
929 if ((Bytes[0] & 0b11) != 0b11)
930 return getInstruction16(MI, Size, Bytes, Address, CS);
931
932 // It's a 32 bit instruction if bit 1:0 are 0b11(checked above) and bits 4:2
933 // are not 0b111.
934 if ((Bytes[0] & 0b1'1100) != 0b1'1100)
935 return getInstruction32(MI, Size, Bytes, Address, CS);
936
937 // 48-bit instructions are encoded as 0bxx011111.
938 if ((Bytes[0] & 0b11'1111) == 0b01'1111) {
939 return getInstruction48(MI, Size, Bytes, Address, CS);
940 }
941
942 // 64-bit instructions are encoded as 0x0111111.
943 if ((Bytes[0] & 0b111'1111) == 0b011'1111) {
944 Size = Bytes.size() >= 8 ? 8 : 0;
945 return MCDisassembler::Fail;
946 }
947
948 // Remaining cases need to check a second byte.
949 if (Bytes.size() < 2) {
950 Size = 0;
951 return MCDisassembler::Fail;
952 }
953
954 // 80-bit through 176-bit instructions are encoded as 0bxnnnxxxx_x1111111.
955 // Where the number of bits is (80 + (nnn * 16)) for nnn != 0b111.
956 unsigned nnn = (Bytes[1] >> 4) & 0b111;
957 if (nnn != 0b111) {
958 Size = 10 + (nnn * 2);
959 if (Bytes.size() < Size)
960 Size = 0;
961 return MCDisassembler::Fail;
962 }
963
964 // Remaining encodings are reserved for > 176-bit instructions.
965 Size = 0;
966 return MCDisassembler::Fail;
967 }
968