1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_DP_TYPES_H 27 #define DC_DP_TYPES_H 28 29 #include "os_types.h" 30 #include "dc_ddc_types.h" 31 32 enum dc_lane_count { 33 LANE_COUNT_UNKNOWN = 0, 34 LANE_COUNT_ONE = 1, 35 LANE_COUNT_TWO = 2, 36 LANE_COUNT_FOUR = 4, 37 LANE_COUNT_EIGHT = 8, 38 LANE_COUNT_DP_MAX = LANE_COUNT_FOUR 39 }; 40 41 /* This is actually a reference clock (27MHz) multiplier 42 * 162MBps bandwidth for 1.62GHz like rate, 43 * 270MBps for 2.70GHz, 44 * 324MBps for 3.24Ghz, 45 * 540MBps for 5.40GHz 46 * 810MBps for 8.10GHz 47 */ 48 enum dc_link_rate { 49 LINK_RATE_UNKNOWN = 0, 50 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane 51 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane 52 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane 53 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane 54 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane 55 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane 56 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2) - 5.40 Gbps/Lane 57 LINK_RATE_RATE_8 = 0x19, // Rate_8 - 6.75 Gbps/Lane 58 LINK_RATE_HIGH3 = 0x1E, // Rate_9 (HBR3) - 8.10 Gbps/Lane 59 /* Starting from DP2.0 link rate enum directly represents actual 60 * link rate value in unit of 10 mbps 61 */ 62 LINK_RATE_UHBR10 = 1000, // UHBR10 - 10.0 Gbps/Lane 63 LINK_RATE_UHBR13_5 = 1350, // UHBR13.5 - 13.5 Gbps/Lane 64 LINK_RATE_UHBR20 = 2000, // UHBR20 - 20.0 Gbps/Lane 65 }; 66 67 enum dc_link_spread { 68 LINK_SPREAD_DISABLED = 0x00, 69 /* 0.5 % downspread 30 kHz */ 70 LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10, 71 /* 0.5 % downspread 33 kHz */ 72 LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11 73 }; 74 75 enum dc_voltage_swing { 76 VOLTAGE_SWING_LEVEL0 = 0, /* direct HW translation! */ 77 VOLTAGE_SWING_LEVEL1, 78 VOLTAGE_SWING_LEVEL2, 79 VOLTAGE_SWING_LEVEL3, 80 VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3 81 }; 82 83 enum dc_pre_emphasis { 84 PRE_EMPHASIS_DISABLED = 0, /* direct HW translation! */ 85 PRE_EMPHASIS_LEVEL1, 86 PRE_EMPHASIS_LEVEL2, 87 PRE_EMPHASIS_LEVEL3, 88 PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3 89 }; 90 /* Post Cursor 2 is optional for transmitter 91 * and it applies only to the main link operating at HBR2 92 */ 93 enum dc_post_cursor2 { 94 POST_CURSOR2_DISABLED = 0, /* direct HW translation! */ 95 POST_CURSOR2_LEVEL1, 96 POST_CURSOR2_LEVEL2, 97 POST_CURSOR2_LEVEL3, 98 POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3, 99 }; 100 101 enum dc_dp_ffe_preset_level { 102 DP_FFE_PRESET_LEVEL0 = 0, 103 DP_FFE_PRESET_LEVEL1, 104 DP_FFE_PRESET_LEVEL2, 105 DP_FFE_PRESET_LEVEL3, 106 DP_FFE_PRESET_LEVEL4, 107 DP_FFE_PRESET_LEVEL5, 108 DP_FFE_PRESET_LEVEL6, 109 DP_FFE_PRESET_LEVEL7, 110 DP_FFE_PRESET_LEVEL8, 111 DP_FFE_PRESET_LEVEL9, 112 DP_FFE_PRESET_LEVEL10, 113 DP_FFE_PRESET_LEVEL11, 114 DP_FFE_PRESET_LEVEL12, 115 DP_FFE_PRESET_LEVEL13, 116 DP_FFE_PRESET_LEVEL14, 117 DP_FFE_PRESET_LEVEL15, 118 DP_FFE_PRESET_MAX_LEVEL = DP_FFE_PRESET_LEVEL15, 119 }; 120 121 enum dc_dp_training_pattern { 122 DP_TRAINING_PATTERN_SEQUENCE_1 = 0, 123 DP_TRAINING_PATTERN_SEQUENCE_2, 124 DP_TRAINING_PATTERN_SEQUENCE_3, 125 DP_TRAINING_PATTERN_SEQUENCE_4, 126 DP_TRAINING_PATTERN_VIDEOIDLE, 127 DP_128b_132b_TPS1, 128 DP_128b_132b_TPS2, 129 DP_128b_132b_TPS2_CDS, 130 }; 131 132 enum dp_link_encoding { 133 DP_UNKNOWN_ENCODING = 0, 134 DP_8b_10b_ENCODING = 1, 135 DP_128b_132b_ENCODING = 2, 136 }; 137 138 enum dp_test_link_rate { 139 DP_TEST_LINK_RATE_RBR = 0x06, 140 DP_TEST_LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane 141 DP_TEST_LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane 142 DP_TEST_LINK_RATE_HBR = 0x0A, 143 DP_TEST_LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane 144 DP_TEST_LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane 145 DP_TEST_LINK_RATE_HBR2 = 0x14, 146 DP_TEST_LINK_RATE_RATE_8 = 0x19, // Rate_8 - 6.75 Gbps/Lane 147 DP_TEST_LINK_RATE_HBR3 = 0x1E, 148 DP_TEST_LINK_RATE_UHBR10 = 0x01, 149 DP_TEST_LINK_RATE_UHBR20 = 0x02, 150 DP_TEST_LINK_RATE_UHBR13_5_LEGACY = 0x03, /* For backward compatibility*/ 151 DP_TEST_LINK_RATE_UHBR13_5 = 0x04, 152 }; 153 154 struct dc_link_settings { 155 enum dc_lane_count lane_count; 156 enum dc_link_rate link_rate; 157 enum dc_link_spread link_spread; 158 bool use_link_rate_set; 159 uint8_t link_rate_set; 160 }; 161 162 struct dc_tunnel_settings { 163 bool should_enable_dp_tunneling; 164 bool should_use_dp_bw_allocation; 165 }; 166 167 union dc_dp_ffe_preset { 168 struct { 169 uint8_t level : 4; 170 uint8_t reserved : 1; 171 uint8_t no_preshoot : 1; 172 uint8_t no_deemphasis : 1; 173 uint8_t method2 : 1; 174 } settings; 175 uint8_t raw; 176 }; 177 178 struct dc_lane_settings { 179 enum dc_voltage_swing VOLTAGE_SWING; 180 enum dc_pre_emphasis PRE_EMPHASIS; 181 enum dc_post_cursor2 POST_CURSOR2; 182 union dc_dp_ffe_preset FFE_PRESET; 183 }; 184 185 struct dc_link_training_overrides { 186 enum dc_voltage_swing *voltage_swing; 187 enum dc_pre_emphasis *pre_emphasis; 188 enum dc_post_cursor2 *post_cursor2; 189 union dc_dp_ffe_preset *ffe_preset; 190 191 uint16_t *cr_pattern_time; 192 uint16_t *eq_pattern_time; 193 enum dc_dp_training_pattern *pattern_for_cr; 194 enum dc_dp_training_pattern *pattern_for_eq; 195 196 enum dc_link_spread *downspread; 197 bool *alternate_scrambler_reset; 198 bool *enhanced_framing; 199 bool *mst_enable; 200 bool *fec_enable; 201 }; 202 203 union payload_table_update_status { 204 struct { 205 uint8_t VC_PAYLOAD_TABLE_UPDATED:1; 206 uint8_t ACT_HANDLED:1; 207 } bits; 208 uint8_t raw; 209 }; 210 211 union dpcd_rev { 212 struct { 213 uint8_t MINOR:4; 214 uint8_t MAJOR:4; 215 } bits; 216 uint8_t raw; 217 }; 218 219 union max_lane_count { 220 struct { 221 uint8_t MAX_LANE_COUNT:5; 222 uint8_t POST_LT_ADJ_REQ_SUPPORTED:1; 223 uint8_t TPS3_SUPPORTED:1; 224 uint8_t ENHANCED_FRAME_CAP:1; 225 } bits; 226 uint8_t raw; 227 }; 228 229 union max_down_spread { 230 struct { 231 uint8_t MAX_DOWN_SPREAD:1; 232 uint8_t RESERVED:5; 233 uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1; 234 uint8_t TPS4_SUPPORTED:1; 235 } bits; 236 uint8_t raw; 237 }; 238 239 union mstm_cap { 240 struct { 241 uint8_t MST_CAP:1; 242 uint8_t RESERVED:7; 243 } bits; 244 uint8_t raw; 245 }; 246 247 union lane_count_set { 248 struct { 249 uint8_t LANE_COUNT_SET:5; 250 uint8_t POST_LT_ADJ_REQ_GRANTED:1; 251 uint8_t RESERVED:1; 252 uint8_t ENHANCED_FRAMING:1; 253 } bits; 254 uint8_t raw; 255 }; 256 257 union lane_status { 258 struct { 259 uint8_t CR_DONE_0:1; 260 uint8_t CHANNEL_EQ_DONE_0:1; 261 uint8_t SYMBOL_LOCKED_0:1; 262 uint8_t RESERVED0:1; 263 uint8_t CR_DONE_1:1; 264 uint8_t CHANNEL_EQ_DONE_1:1; 265 uint8_t SYMBOL_LOCKED_1:1; 266 uint8_t RESERVED_1:1; 267 } bits; 268 uint8_t raw; 269 }; 270 271 union device_service_irq { 272 struct { 273 uint8_t REMOTE_CONTROL_CMD_PENDING:1; 274 uint8_t AUTOMATED_TEST:1; 275 uint8_t CP_IRQ:1; 276 uint8_t MCCS_IRQ:1; 277 uint8_t DOWN_REP_MSG_RDY:1; 278 uint8_t UP_REQ_MSG_RDY:1; 279 uint8_t SINK_SPECIFIC:1; 280 uint8_t reserved:1; 281 } bits; 282 uint8_t raw; 283 }; 284 285 union sink_count { 286 struct { 287 uint8_t SINK_COUNT:6; 288 uint8_t CPREADY:1; 289 uint8_t RESERVED:1; 290 } bits; 291 uint8_t raw; 292 }; 293 294 union lane_align_status_updated { 295 struct { 296 uint8_t INTERLANE_ALIGN_DONE:1; 297 uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1; 298 uint8_t EQ_INTERLANE_ALIGN_DONE_128b_132b:1; 299 uint8_t CDS_INTERLANE_ALIGN_DONE_128b_132b:1; 300 uint8_t LT_FAILED_128b_132b:1; 301 uint8_t RESERVED:1; 302 uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1; 303 uint8_t LINK_STATUS_UPDATED:1; 304 } bits; 305 uint8_t raw; 306 }; 307 308 union link_service_irq_vector_esi0 { 309 struct { 310 uint8_t DP_LINK_RX_CAP_CHANGED:1; 311 uint8_t DP_LINK_STATUS_CHANGED:1; 312 uint8_t DP_LINK_STREAM_STATUS_CHANGED:1; 313 uint8_t DP_LINK_HDMI_LINK_STATUS_CHANGED:1; 314 uint8_t DP_LINK_CONNECTED_OFF_ENTRY_REQUESTED:1; 315 uint8_t DP_LINK_TUNNELING_IRQ:1; 316 uint8_t reserved:2; 317 } bits; 318 uint8_t raw; 319 }; 320 321 union lane_adjust { 322 struct { 323 uint8_t VOLTAGE_SWING_LANE:2; 324 uint8_t PRE_EMPHASIS_LANE:2; 325 uint8_t RESERVED:4; 326 } bits; 327 struct { 328 uint8_t PRESET_VALUE :4; 329 uint8_t RESERVED :4; 330 } tx_ffe; 331 uint8_t raw; 332 }; 333 334 union dpcd_training_pattern { 335 struct { 336 uint8_t TRAINING_PATTERN_SET:4; 337 uint8_t RECOVERED_CLOCK_OUT_EN:1; 338 uint8_t SCRAMBLING_DISABLE:1; 339 uint8_t SYMBOL_ERROR_COUNT_SEL:2; 340 } v1_4; 341 struct { 342 uint8_t TRAINING_PATTERN_SET:2; 343 uint8_t LINK_QUAL_PATTERN_SET:2; 344 uint8_t RESERVED:4; 345 } v1_3; 346 uint8_t raw; 347 }; 348 349 /* Training Lane is used to configure downstream DP device's voltage swing 350 and pre-emphasis levels*/ 351 /* The DPCD addresses are from 0x103 to 0x106*/ 352 union dpcd_training_lane { 353 struct { 354 uint8_t VOLTAGE_SWING_SET:2; 355 uint8_t MAX_SWING_REACHED:1; 356 uint8_t PRE_EMPHASIS_SET:2; 357 uint8_t MAX_PRE_EMPHASIS_REACHED:1; 358 uint8_t RESERVED:2; 359 } bits; 360 struct { 361 uint8_t PRESET_VALUE :4; 362 uint8_t RESERVED :4; 363 } tx_ffe; 364 uint8_t raw; 365 }; 366 367 /* TMDS-converter related */ 368 union dwnstream_port_caps_byte0 { 369 struct { 370 uint8_t DWN_STRM_PORTX_TYPE:3; 371 uint8_t DWN_STRM_PORTX_HPD:1; 372 uint8_t RESERVERD:4; 373 } bits; 374 uint8_t raw; 375 }; 376 377 /* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/ 378 enum dpcd_downstream_port_detailed_type { 379 DOWN_STREAM_DETAILED_DP = 0, 380 DOWN_STREAM_DETAILED_VGA, 381 DOWN_STREAM_DETAILED_DVI, 382 DOWN_STREAM_DETAILED_HDMI, 383 DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/ 384 DOWN_STREAM_DETAILED_DP_PLUS_PLUS 385 }; 386 387 union dwnstream_port_caps_byte2 { 388 struct { 389 uint8_t MAX_BITS_PER_COLOR_COMPONENT:2; 390 uint8_t MAX_ENCODED_LINK_BW_SUPPORT:3; 391 uint8_t SOURCE_CONTROL_MODE_SUPPORT:1; 392 uint8_t CONCURRENT_LINK_BRING_UP_SEQ_SUPPORT:1; 393 uint8_t RESERVED:1; 394 } bits; 395 uint8_t raw; 396 }; 397 398 union dp_downstream_port_present { 399 uint8_t byte; 400 struct { 401 uint8_t PORT_PRESENT:1; 402 uint8_t PORT_TYPE:2; 403 uint8_t FMT_CONVERSION:1; 404 uint8_t DETAILED_CAPS:1; 405 uint8_t RESERVED:3; 406 } fields; 407 }; 408 409 union dwnstream_port_caps_byte3_dvi { 410 struct { 411 uint8_t RESERVED1:1; 412 uint8_t DUAL_LINK:1; 413 uint8_t HIGH_COLOR_DEPTH:1; 414 uint8_t RESERVED2:5; 415 } bits; 416 uint8_t raw; 417 }; 418 419 union dwnstream_port_caps_byte3_hdmi { 420 struct { 421 uint8_t FRAME_SEQ_TO_FRAME_PACK:1; 422 uint8_t YCrCr422_PASS_THROUGH:1; 423 uint8_t YCrCr420_PASS_THROUGH:1; 424 uint8_t YCrCr422_CONVERSION:1; 425 uint8_t YCrCr420_CONVERSION:1; 426 uint8_t RESERVED:3; 427 } bits; 428 uint8_t raw; 429 }; 430 431 union hdmi_encoded_link_bw { 432 struct { 433 uint8_t FRL_MODE:1; // Bit 0 434 uint8_t BW_9Gbps:1; 435 uint8_t BW_18Gbps:1; 436 uint8_t BW_24Gbps:1; 437 uint8_t BW_32Gbps:1; 438 uint8_t BW_40Gbps:1; 439 uint8_t BW_48Gbps:1; 440 uint8_t FRL_LINK_TRAINING_FINISHED:1; // Bit 7 441 } bits; 442 uint8_t raw; 443 }; 444 445 union hdmi_tx_link_status { 446 struct { 447 uint8_t HDMI_TX_LINK_ACTIVE_STATUS:1; 448 uint8_t HDMI_TX_READY_STATUS:1; 449 uint8_t RESERVED:6; 450 } bits; 451 uint8_t raw; 452 }; 453 454 union autonomous_mode_and_frl_link_status { 455 struct { 456 uint8_t FRL_LT_IN_PROGRESS_STATUS:1; 457 uint8_t FRL_LT_LINK_CONFIG_IN_PROGRESS:3; 458 uint8_t RESERVED:1; 459 uint8_t FALLBACK_POLICY:1; 460 uint8_t FALLBACK_POLICY_VALID:1; 461 uint8_t REGULATED_AUTONOMOUS_MODE_SUPPORTED:1; 462 } bits; 463 uint8_t raw; 464 }; 465 466 /*4-byte structure for detailed capabilities of a down-stream port 467 (DP-to-TMDS converter).*/ 468 union dwnstream_portxcaps { 469 struct { 470 union dwnstream_port_caps_byte0 byte0; 471 unsigned char max_TMDS_clock; //byte1 472 union dwnstream_port_caps_byte2 byte2; 473 474 union { 475 union dwnstream_port_caps_byte3_dvi byteDVI; 476 union dwnstream_port_caps_byte3_hdmi byteHDMI; 477 } byte3; 478 } bytes; 479 480 unsigned char raw[4]; 481 }; 482 483 union downstream_port { 484 struct { 485 unsigned char present:1; 486 unsigned char type:2; 487 unsigned char format_conv:1; 488 unsigned char detailed_caps:1; 489 unsigned char reserved:3; 490 } bits; 491 unsigned char raw; 492 }; 493 494 495 union sink_status { 496 struct { 497 uint8_t RX_PORT0_STATUS:1; 498 uint8_t RX_PORT1_STATUS:1; 499 uint8_t RESERVED:6; 500 } bits; 501 uint8_t raw; 502 }; 503 504 /* 7-byte structure corresponding to 6 registers (200h-205h) 505 * and LINK_SERVICE_IRQ_ESI0 (2005h) for tunneling IRQ 506 * read during handling of HPD-IRQ 507 */ 508 union hpd_irq_data { 509 struct { 510 union sink_count sink_cnt;/* 200h */ 511 union device_service_irq device_service_irq;/* 201h */ 512 union lane_status lane01_status;/* 202h */ 513 union lane_status lane23_status;/* 203h */ 514 union lane_align_status_updated lane_status_updated;/* 204h */ 515 union sink_status sink_status;/* 205h */ 516 union link_service_irq_vector_esi0 link_service_irq_esi0;/* 2005h */ 517 } bytes; 518 uint8_t raw[7]; 519 }; 520 521 union down_stream_port_count { 522 struct { 523 uint8_t DOWN_STR_PORT_COUNT:4; 524 uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/ 525 /*Bit 6 = MSA_TIMING_PAR_IGNORED 526 0 = Sink device requires the MSA timing parameters 527 1 = Sink device is capable of rendering incoming video 528 stream without MSA timing parameters*/ 529 uint8_t IGNORE_MSA_TIMING_PARAM:1; 530 /*Bit 7 = OUI Support 531 0 = OUI not supported 532 1 = OUI supported 533 (OUI and Device Identification mandatory for DP 1.2)*/ 534 uint8_t OUI_SUPPORT:1; 535 } bits; 536 uint8_t raw; 537 }; 538 539 union down_spread_ctrl { 540 struct { 541 uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/ 542 /* Bits 4 = SPREAD_AMP. Spreading amplitude 543 0 = Main link signal is not downspread 544 1 = Main link signal is downspread <= 0.5% 545 with frequency in the range of 30kHz ~ 33kHz*/ 546 uint8_t SPREAD_AMP:1; 547 uint8_t RESERVED2:1;/*Bit 5 = RESERVED. Read all 0s*/ 548 /* Bit 6 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE. 549 0 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE is not enabled by the Source device (default) 550 1 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE is enabled by Source device */ 551 uint8_t FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE:1; 552 /*Bit 7 = MSA_TIMING_PAR_IGNORE_EN 553 0 = Source device will send valid data for the MSA Timing Params 554 1 = Source device may send invalid data for these MSA Timing Params*/ 555 uint8_t IGNORE_MSA_TIMING_PARAM:1; 556 } bits; 557 uint8_t raw; 558 }; 559 560 union dpcd_edp_config { 561 struct { 562 uint8_t PANEL_MODE_EDP:1; 563 uint8_t FRAMING_CHANGE_ENABLE:1; 564 uint8_t RESERVED:5; 565 uint8_t PANEL_SELF_TEST_ENABLE:1; 566 } bits; 567 uint8_t raw; 568 }; 569 570 struct dp_device_vendor_id { 571 uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ 572 uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ 573 }; 574 575 struct dp_sink_hw_fw_revision { 576 uint8_t ieee_hw_rev; 577 uint8_t ieee_fw_rev[2]; 578 }; 579 580 struct dpcd_vendor_signature { 581 bool is_valid; 582 583 union dpcd_ieee_vendor_signature { 584 struct { 585 uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ 586 uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ 587 uint8_t ieee_hw_rev; 588 uint8_t ieee_fw_rev[2]; 589 }; 590 uint8_t raw[12]; 591 } data; 592 }; 593 594 struct dpcd_amd_signature { 595 uint8_t AMD_IEEE_TxSignature_byte1; 596 uint8_t AMD_IEEE_TxSignature_byte2; 597 uint8_t AMD_IEEE_TxSignature_byte3; 598 }; 599 600 struct dpcd_amd_device_id { 601 uint8_t device_id_byte1; 602 uint8_t device_id_byte2; 603 uint8_t zero[4]; 604 uint8_t dce_version; 605 uint8_t dal_version_byte1; 606 uint8_t dal_version_byte2; 607 }; 608 609 struct target_luminance_value { 610 uint8_t byte0; 611 uint8_t byte1; 612 uint8_t byte2; 613 }; 614 615 struct dpcd_source_backlight_set { 616 struct { 617 uint8_t byte0; 618 uint8_t byte1; 619 uint8_t byte2; 620 uint8_t byte3; 621 } backlight_level_millinits; 622 623 struct { 624 uint8_t byte0; 625 uint8_t byte1; 626 } backlight_transition_time_ms; 627 }; 628 629 union dpcd_source_backlight_get { 630 struct { 631 uint32_t backlight_millinits_peak; /* 326h */ 632 uint32_t backlight_millinits_avg; /* 32Ah */ 633 } bytes; 634 uint8_t raw[8]; 635 }; 636 637 /*DPCD register of DP receiver capability field bits-*/ 638 union edp_configuration_cap { 639 struct { 640 uint8_t ALT_SCRAMBLER_RESET:1; 641 uint8_t FRAMING_CHANGE:1; 642 uint8_t RESERVED:1; 643 uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1; 644 uint8_t RESERVED2:4; 645 } bits; 646 uint8_t raw; 647 }; 648 649 union dprx_feature { 650 struct { 651 uint8_t GTC_CAP:1; // bit 0: DP 1.3+ 652 uint8_t SST_SPLIT_SDP_CAP:1; // bit 1: DP 1.4 653 uint8_t AV_SYNC_CAP:1; // bit 2: DP 1.3+ 654 uint8_t VSC_SDP_COLORIMETRY_SUPPORTED:1; // bit 3: DP 1.3+ 655 uint8_t VSC_EXT_VESA_SDP_SUPPORTED:1; // bit 4: DP 1.4 656 uint8_t VSC_EXT_VESA_SDP_CHAINING_SUPPORTED:1; // bit 5: DP 1.4 657 uint8_t VSC_EXT_CEA_SDP_SUPPORTED:1; // bit 6: DP 1.4 658 uint8_t VSC_EXT_CEA_SDP_CHAINING_SUPPORTED:1; // bit 7: DP 1.4 659 } bits; 660 uint8_t raw; 661 }; 662 663 union training_aux_rd_interval { 664 struct { 665 uint8_t TRAINIG_AUX_RD_INTERVAL:7; 666 uint8_t EXT_RECEIVER_CAP_FIELD_PRESENT:1; 667 } bits; 668 uint8_t raw; 669 }; 670 671 /* Automated test structures */ 672 union test_request { 673 struct { 674 uint8_t LINK_TRAINING :1; 675 uint8_t LINK_TEST_PATTRN :1; 676 uint8_t EDID_READ :1; 677 uint8_t PHY_TEST_PATTERN :1; 678 uint8_t PHY_TEST_CHANNEL_CODING_TYPE :2; 679 uint8_t AUDIO_TEST_PATTERN :1; 680 uint8_t TEST_AUDIO_DISABLED_VIDEO :1; 681 } bits; 682 uint8_t raw; 683 }; 684 685 union test_response { 686 struct { 687 uint8_t ACK :1; 688 uint8_t NO_ACK :1; 689 uint8_t EDID_CHECKSUM_WRITE:1; 690 uint8_t RESERVED :5; 691 } bits; 692 uint8_t raw; 693 }; 694 695 union phy_test_pattern { 696 struct { 697 /* This field is 7 bits for DP2.0 */ 698 uint8_t PATTERN :7; 699 uint8_t RESERVED :1; 700 } bits; 701 uint8_t raw; 702 }; 703 704 /* States of Compliance Test Specification (CTS DP1.2). */ 705 union compliance_test_state { 706 struct { 707 unsigned char STEREO_3D_RUNNING : 1; 708 unsigned char RESERVED : 7; 709 } bits; 710 unsigned char raw; 711 }; 712 713 union link_test_pattern { 714 struct { 715 /* dpcd_link_test_patterns */ 716 unsigned char PATTERN :2; 717 unsigned char RESERVED:6; 718 } bits; 719 unsigned char raw; 720 }; 721 722 union test_misc { 723 struct dpcd_test_misc_bits { 724 unsigned char SYNC_CLOCK :1; 725 /* dpcd_test_color_format */ 726 unsigned char CLR_FORMAT :2; 727 /* dpcd_test_dyn_range */ 728 unsigned char DYN_RANGE :1; 729 unsigned char YCBCR_COEFS :1; 730 /* dpcd_test_bit_depth */ 731 unsigned char BPC :3; 732 } bits; 733 unsigned char raw; 734 }; 735 736 union audio_test_mode { 737 struct { 738 unsigned char sampling_rate :4; 739 unsigned char channel_count :4; 740 } bits; 741 unsigned char raw; 742 }; 743 744 union audio_test_pattern_period { 745 struct { 746 unsigned char pattern_period :4; 747 unsigned char reserved :4; 748 } bits; 749 unsigned char raw; 750 }; 751 752 struct audio_test_pattern_type { 753 unsigned char value; 754 }; 755 756 struct dp_audio_test_data_flags { 757 uint8_t test_requested :1; 758 uint8_t disable_video :1; 759 }; 760 761 struct dp_audio_test_data { 762 763 struct dp_audio_test_data_flags flags; 764 uint8_t sampling_rate; 765 uint8_t channel_count; 766 uint8_t pattern_type; 767 uint8_t pattern_period[8]; 768 }; 769 770 /* FEC capability DPCD register field bits-*/ 771 union dpcd_fec_capability { 772 struct { 773 uint8_t FEC_CAPABLE:1; 774 uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; 775 uint8_t CORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; 776 uint8_t BIT_ERROR_COUNT_CAPABLE:1; 777 uint8_t PARITY_BLOCK_ERROR_COUNT_CAPABLE:1; 778 uint8_t ARITY_BIT_ERROR_COUNT_CAPABLE:1; 779 uint8_t FEC_RUNNING_INDICATOR_SUPPORTED:1; 780 uint8_t FEC_ERROR_REPORTING_POLICY_SUPPORTED:1; 781 } bits; 782 uint8_t raw; 783 }; 784 785 /* DSC capability DPCD register field bits-*/ 786 struct dpcd_dsc_support { 787 uint8_t DSC_SUPPORT :1; 788 uint8_t DSC_PASSTHROUGH_SUPPORT :1; 789 uint8_t RESERVED :6; 790 }; 791 792 struct dpcd_dsc_algorithm_revision { 793 uint8_t DSC_VERSION_MAJOR :4; 794 uint8_t DSC_VERSION_MINOR :4; 795 }; 796 797 struct dpcd_dsc_rc_buffer_block_size { 798 uint8_t RC_BLOCK_BUFFER_SIZE :2; 799 uint8_t RESERVED :6; 800 }; 801 802 struct dpcd_dsc_slice_capability1 { 803 uint8_t ONE_SLICE_PER_DP_DSC_SINK_DEVICE :1; 804 uint8_t TWO_SLICES_PER_DP_DSC_SINK_DEVICE :1; 805 uint8_t RESERVED :1; 806 uint8_t FOUR_SLICES_PER_DP_DSC_SINK_DEVICE :1; 807 uint8_t SIX_SLICES_PER_DP_DSC_SINK_DEVICE :1; 808 uint8_t EIGHT_SLICES_PER_DP_DSC_SINK_DEVICE :1; 809 uint8_t TEN_SLICES_PER_DP_DSC_SINK_DEVICE :1; 810 uint8_t TWELVE_SLICES_PER_DP_DSC_SINK_DEVICE :1; 811 }; 812 813 struct dpcd_dsc_line_buffer_bit_depth { 814 uint8_t LINE_BUFFER_BIT_DEPTH :4; 815 uint8_t RESERVED :4; 816 }; 817 818 struct dpcd_dsc_block_prediction_support { 819 uint8_t BLOCK_PREDICTION_SUPPORT:1; 820 uint8_t RESERVED :7; 821 }; 822 823 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor { 824 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_LOW :7; 825 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_HIGH :7; 826 uint8_t RESERVED :2; 827 }; 828 829 struct dpcd_dsc_decoder_color_format_capabilities { 830 uint8_t RGB_SUPPORT :1; 831 uint8_t Y_CB_CR_444_SUPPORT :1; 832 uint8_t Y_CB_CR_SIMPLE_422_SUPPORT :1; 833 uint8_t Y_CB_CR_NATIVE_422_SUPPORT :1; 834 uint8_t Y_CB_CR_NATIVE_420_SUPPORT :1; 835 uint8_t RESERVED :3; 836 }; 837 838 struct dpcd_dsc_decoder_color_depth_capabilities { 839 uint8_t RESERVED0 :1; 840 uint8_t EIGHT_BITS_PER_COLOR_SUPPORT :1; 841 uint8_t TEN_BITS_PER_COLOR_SUPPORT :1; 842 uint8_t TWELVE_BITS_PER_COLOR_SUPPORT :1; 843 uint8_t RESERVED1 :4; 844 }; 845 846 struct dpcd_peak_dsc_throughput_dsc_sink { 847 uint8_t THROUGHPUT_MODE_0:4; 848 uint8_t THROUGHPUT_MODE_1:4; 849 }; 850 851 struct dpcd_dsc_slice_capabilities_2 { 852 uint8_t SIXTEEN_SLICES_PER_DSC_SINK_DEVICE :1; 853 uint8_t TWENTY_SLICES_PER_DSC_SINK_DEVICE :1; 854 uint8_t TWENTYFOUR_SLICES_PER_DSC_SINK_DEVICE :1; 855 uint8_t RESERVED :5; 856 }; 857 858 struct dpcd_bits_per_pixel_increment{ 859 uint8_t INCREMENT_OF_BITS_PER_PIXEL_SUPPORTED :3; 860 uint8_t RESERVED :5; 861 }; 862 union dpcd_dsc_basic_capabilities { 863 struct { 864 struct dpcd_dsc_support dsc_support; 865 struct dpcd_dsc_algorithm_revision dsc_algorithm_revision; 866 struct dpcd_dsc_rc_buffer_block_size dsc_rc_buffer_block_size; 867 uint8_t dsc_rc_buffer_size; 868 struct dpcd_dsc_slice_capability1 dsc_slice_capabilities_1; 869 struct dpcd_dsc_line_buffer_bit_depth dsc_line_buffer_bit_depth; 870 struct dpcd_dsc_block_prediction_support dsc_block_prediction_support; 871 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor maximum_bits_per_pixel_supported_by_the_decompressor; 872 struct dpcd_dsc_decoder_color_format_capabilities dsc_decoder_color_format_capabilities; 873 struct dpcd_dsc_decoder_color_depth_capabilities dsc_decoder_color_depth_capabilities; 874 struct dpcd_peak_dsc_throughput_dsc_sink peak_dsc_throughput_dsc_sink; 875 uint8_t dsc_maximum_slice_width; 876 struct dpcd_dsc_slice_capabilities_2 dsc_slice_capabilities_2; 877 uint8_t reserved; 878 struct dpcd_bits_per_pixel_increment bits_per_pixel_increment; 879 } fields; 880 uint8_t raw[16]; 881 }; 882 883 union dpcd_dsc_branch_decoder_capabilities { 884 struct { 885 uint8_t BRANCH_OVERALL_THROUGHPUT_0; 886 uint8_t BRANCH_OVERALL_THROUGHPUT_1; 887 uint8_t BRANCH_MAX_LINE_WIDTH; 888 } fields; 889 uint8_t raw[3]; 890 }; 891 892 struct dpcd_dsc_capabilities { 893 union dpcd_dsc_basic_capabilities dsc_basic_caps; 894 union dpcd_dsc_branch_decoder_capabilities dsc_branch_decoder_caps; 895 }; 896 897 /* These parameters are from PSR capabilities reported by Sink DPCD */ 898 struct psr_caps { 899 unsigned char psr_version; 900 unsigned int psr_rfb_setup_time; 901 bool psr_exit_link_training_required; 902 unsigned char edp_revision; 903 unsigned char support_ver; 904 bool su_granularity_required; 905 bool y_coordinate_required; 906 uint8_t su_y_granularity; 907 bool alpm_cap; 908 bool standby_support; 909 uint8_t rate_control_caps; 910 unsigned int psr_power_opt_flag; 911 }; 912 913 union dpcd_dprx_feature_enumeration_list_cont_1 { 914 struct { 915 uint8_t ADAPTIVE_SYNC_SDP_SUPPORT:1; 916 uint8_t AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED: 1; 917 uint8_t RESERVED0: 2; 918 uint8_t VSC_EXT_SDP_VER1_SUPPORT: 1; 919 uint8_t RESERVED1: 3; 920 } bits; 921 uint8_t raw; 922 }; 923 924 struct adaptive_sync_caps { 925 union dpcd_dprx_feature_enumeration_list_cont_1 dp_adap_sync_caps; 926 }; 927 928 /* Length of router topology ID read from DPCD in bytes. */ 929 #define DPCD_USB4_TOPOLOGY_ID_LEN 5 930 931 /* DPCD[0xE000D] DP_TUNNELING_CAPABILITIES SUPPORT register. */ 932 union dp_tun_cap_support { 933 struct { 934 uint8_t dp_tunneling :1; 935 uint8_t rsvd :5; 936 uint8_t panel_replay_tun_opt :1; 937 uint8_t dpia_bw_alloc :1; 938 } bits; 939 uint8_t raw; 940 }; 941 942 /* DPCD[0xE000E] DP_IN_ADAPTER_INFO register. */ 943 union dpia_info { 944 struct { 945 uint8_t dpia_num :5; 946 uint8_t rsvd :3; 947 } bits; 948 uint8_t raw; 949 }; 950 951 /* DPCD[0xE0020] USB4_DRIVER_BW_CAPABILITY register. */ 952 union usb4_driver_bw_cap { 953 struct { 954 uint8_t rsvd :7; 955 uint8_t driver_bw_alloc_support :1; 956 } bits; 957 uint8_t raw; 958 }; 959 960 /* DP Tunneling over USB4 */ 961 struct dpcd_usb4_dp_tunneling_info { 962 union dp_tun_cap_support dp_tun_cap; 963 union dpia_info dpia_info; 964 union usb4_driver_bw_cap driver_bw_cap; 965 uint8_t usb4_driver_id; 966 uint8_t usb4_topology_id[DPCD_USB4_TOPOLOGY_ID_LEN]; 967 }; 968 969 union dp_main_line_channel_coding_cap { 970 struct { 971 uint8_t DP_8b_10b_SUPPORTED :1; 972 uint8_t DP_128b_132b_SUPPORTED :1; 973 uint8_t RESERVED :6; 974 } bits; 975 uint8_t raw; 976 }; 977 978 union dp_main_link_channel_coding_lttpr_cap { 979 struct { 980 uint8_t DP_128b_132b_SUPPORTED :1; 981 uint8_t RESERVED :7; 982 } bits; 983 uint8_t raw; 984 }; 985 986 union dp_128b_132b_supported_link_rates { 987 struct { 988 uint8_t UHBR10 :1; 989 uint8_t UHBR20 :1; 990 uint8_t UHBR13_5:1; 991 uint8_t RESERVED:5; 992 } bits; 993 uint8_t raw; 994 }; 995 996 union dp_128b_132b_supported_lttpr_link_rates { 997 struct { 998 uint8_t UHBR10 :1; 999 uint8_t UHBR20 :1; 1000 uint8_t UHBR13_5:1; 1001 uint8_t RESERVED:5; 1002 } bits; 1003 uint8_t raw; 1004 }; 1005 1006 union dp_alpm_lttpr_cap { 1007 struct { 1008 uint8_t AUX_LESS_ALPM_SUPPORTED :1; 1009 uint8_t RESERVED :7; 1010 } bits; 1011 uint8_t raw; 1012 }; 1013 1014 union dp_sink_video_fallback_formats { 1015 struct { 1016 uint8_t dp_1024x768_60Hz_24bpp_support :1; 1017 uint8_t dp_1280x720_60Hz_24bpp_support :1; 1018 uint8_t dp_1920x1080_60Hz_24bpp_support :1; 1019 uint8_t RESERVED :5; 1020 } bits; 1021 uint8_t raw; 1022 }; 1023 1024 union dp_receive_port0_cap { 1025 struct { 1026 uint8_t RESERVED :1; 1027 uint8_t LOCAL_EDID_PRESENT :1; 1028 uint8_t ASSOCIATED_TO_PRECEDING_PORT:1; 1029 uint8_t HBLANK_EXPANSION_CAPABLE :1; 1030 uint8_t BUFFER_SIZE_UNIT :1; 1031 uint8_t BUFFER_SIZE_PER_PORT :1; 1032 uint8_t HBLANK_REDUCTION_CAPABLE :1; 1033 uint8_t RESERVED2:1; 1034 uint8_t BUFFER_SIZE:8; 1035 } bits; 1036 uint8_t raw[2]; 1037 }; 1038 1039 union dpcd_max_uncompressed_pixel_rate_cap { 1040 struct { 1041 uint16_t max_uncompressed_pixel_rate_cap :15; 1042 uint16_t valid :1; 1043 } bits; 1044 uint8_t raw[2]; 1045 }; 1046 1047 union dp_fec_capability1 { 1048 struct { 1049 uint8_t AGGREGATED_ERROR_COUNTERS_CAPABLE :1; 1050 uint8_t RESERVED :7; 1051 } bits; 1052 uint8_t raw; 1053 }; 1054 1055 union dp_cable_id { 1056 struct { 1057 uint8_t UHBR10_20_CAPABILITY :2; 1058 uint8_t UHBR13_5_CAPABILITY :1; 1059 uint8_t CABLE_TYPE :3; 1060 uint8_t RESERVED :2; 1061 } bits; 1062 uint8_t raw; 1063 }; 1064 1065 struct dp_color_depth_caps { 1066 uint8_t support_6bpc :1; 1067 uint8_t support_8bpc :1; 1068 uint8_t support_10bpc :1; 1069 uint8_t support_12bpc :1; 1070 uint8_t support_16bpc :1; 1071 uint8_t RESERVED :3; 1072 }; 1073 1074 struct dp_encoding_format_caps { 1075 uint8_t support_rgb :1; 1076 uint8_t support_ycbcr444:1; 1077 uint8_t support_ycbcr422:1; 1078 uint8_t support_ycbcr420:1; 1079 uint8_t RESERVED :4; 1080 }; 1081 1082 union dp_dfp_cap_ext { 1083 struct { 1084 uint8_t supported; 1085 uint8_t max_pixel_rate_in_mps[2]; 1086 uint8_t max_video_h_active_width[2]; 1087 uint8_t max_video_v_active_height[2]; 1088 struct dp_encoding_format_caps encoding_format_caps; 1089 struct dp_color_depth_caps rgb_color_depth_caps; 1090 struct dp_color_depth_caps ycbcr444_color_depth_caps; 1091 struct dp_color_depth_caps ycbcr422_color_depth_caps; 1092 struct dp_color_depth_caps ycbcr420_color_depth_caps; 1093 } fields; 1094 uint8_t raw[12]; 1095 }; 1096 1097 union dp_128b_132b_training_aux_rd_interval { 1098 struct { 1099 uint8_t VALUE :7; 1100 uint8_t UNIT :1; 1101 } bits; 1102 uint8_t raw; 1103 }; 1104 1105 union edp_alpm_caps { 1106 struct { 1107 uint8_t AUX_WAKE_ALPM_CAP :1; 1108 uint8_t PM_STATE_2A_SUPPORT :1; 1109 uint8_t AUX_LESS_ALPM_CAP :1; 1110 uint8_t RESERVED :5; 1111 } bits; 1112 uint8_t raw; 1113 }; 1114 1115 union edp_psr_dpcd_caps { 1116 struct { 1117 uint8_t LINK_TRAINING_ON_EXIT_NOT_REQUIRED :1; 1118 uint8_t PSR_SETUP_TIME :3; 1119 uint8_t Y_COORDINATE_REQUIRED :1; 1120 uint8_t SU_GRANULARITY_REQUIRED :1; 1121 uint8_t FRAME_SYNC_IS_NOT_NEEDED_FOR_SU :1; 1122 uint8_t RESERVED :1; 1123 } bits; 1124 uint8_t raw; 1125 }; 1126 1127 struct edp_psr_info { 1128 uint8_t psr_version; 1129 union edp_psr_dpcd_caps psr_dpcd_caps; 1130 uint8_t psr2_su_y_granularity_cap; 1131 uint8_t force_psrsu_cap; 1132 }; 1133 1134 struct replay_info { 1135 uint8_t pixel_deviation_per_line; 1136 uint8_t max_deviation_line; 1137 }; 1138 1139 struct dprx_states { 1140 bool cable_id_written; 1141 }; 1142 1143 enum dpcd_downstream_port_max_bpc { 1144 DOWN_STREAM_MAX_8BPC = 0, 1145 DOWN_STREAM_MAX_10BPC, 1146 DOWN_STREAM_MAX_12BPC, 1147 DOWN_STREAM_MAX_16BPC 1148 }; 1149 1150 enum link_training_offset { 1151 DPRX = 0, 1152 LTTPR_PHY_REPEATER1 = 1, 1153 LTTPR_PHY_REPEATER2 = 2, 1154 LTTPR_PHY_REPEATER3 = 3, 1155 LTTPR_PHY_REPEATER4 = 4, 1156 LTTPR_PHY_REPEATER5 = 5, 1157 LTTPR_PHY_REPEATER6 = 6, 1158 LTTPR_PHY_REPEATER7 = 7, 1159 LTTPR_PHY_REPEATER8 = 8 1160 }; 1161 1162 #define MAX_REPEATER_CNT 8 1163 1164 struct dc_lttpr_caps { 1165 union dpcd_rev revision; 1166 uint8_t mode; 1167 uint8_t max_lane_count; 1168 uint8_t max_link_rate; 1169 uint8_t phy_repeater_cnt; 1170 uint8_t max_ext_timeout; 1171 union dp_main_link_channel_coding_lttpr_cap main_link_channel_coding; 1172 union dp_128b_132b_supported_lttpr_link_rates supported_128b_132b_rates; 1173 union dp_alpm_lttpr_cap alpm; 1174 uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1]; 1175 uint8_t lttpr_ieee_oui[3]; // Always read from closest LTTPR to host 1176 uint8_t lttpr_device_id[6]; // Always read from closest LTTPR to host 1177 }; 1178 1179 struct dc_dongle_dfp_cap_ext { 1180 bool supported; 1181 uint16_t max_pixel_rate_in_mps; 1182 uint16_t max_video_h_active_width; 1183 uint16_t max_video_v_active_height; 1184 struct dp_encoding_format_caps encoding_format_caps; 1185 struct dp_color_depth_caps rgb_color_depth_caps; 1186 struct dp_color_depth_caps ycbcr444_color_depth_caps; 1187 struct dp_color_depth_caps ycbcr422_color_depth_caps; 1188 struct dp_color_depth_caps ycbcr420_color_depth_caps; 1189 }; 1190 1191 struct dc_dongle_caps { 1192 /* dongle type (DP converter, CV smart dongle) */ 1193 enum display_dongle_type dongle_type; 1194 bool extendedCapValid; 1195 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1196 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1197 bool is_dp_hdmi_s3d_converter; 1198 bool is_dp_hdmi_ycbcr422_pass_through; 1199 bool is_dp_hdmi_ycbcr420_pass_through; 1200 bool is_dp_hdmi_ycbcr422_converter; 1201 bool is_dp_hdmi_ycbcr420_converter; 1202 uint32_t dp_hdmi_max_bpc; 1203 uint32_t dp_hdmi_max_pixel_clk_in_khz; 1204 uint32_t dp_hdmi_frl_max_link_bw_in_kbps; 1205 uint32_t dp_hdmi_regulated_autonomous_mode_support; 1206 struct dc_dongle_dfp_cap_ext dfp_cap_ext; 1207 }; 1208 1209 struct dpcd_caps { 1210 union dpcd_rev dpcd_rev; 1211 union max_lane_count max_ln_count; 1212 union max_down_spread max_down_spread; 1213 union dprx_feature dprx_feature; 1214 1215 /* valid only for eDP v1.4 or higher*/ 1216 uint8_t edp_supported_link_rates_count; 1217 enum dc_link_rate edp_supported_link_rates[8]; 1218 1219 /* dongle type (DP converter, CV smart dongle) */ 1220 enum display_dongle_type dongle_type; 1221 bool is_dongle_type_one; 1222 /* branch device or sink device */ 1223 bool is_branch_dev; 1224 /* Dongle's downstream count. */ 1225 union sink_count sink_count; 1226 bool is_mst_capable; 1227 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1228 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1229 struct dc_dongle_caps dongle_caps; 1230 1231 uint32_t sink_dev_id; 1232 int8_t sink_dev_id_str[6]; 1233 int8_t sink_hw_revision; 1234 int8_t sink_fw_revision[2]; 1235 1236 uint32_t branch_dev_id; 1237 int8_t branch_dev_name[6]; 1238 int8_t branch_hw_revision; 1239 int8_t branch_fw_revision[2]; 1240 int8_t branch_vendor_specific_data[4]; 1241 1242 bool allow_invalid_MSA_timing_param; 1243 bool panel_mode_edp; 1244 bool dpcd_display_control_capable; 1245 bool ext_receiver_cap_field_present; 1246 bool set_power_state_capable_edp; 1247 bool dynamic_backlight_capable_edp; 1248 union dpcd_fec_capability fec_cap; 1249 struct dpcd_dsc_capabilities dsc_caps; 1250 struct dc_lttpr_caps lttpr_caps; 1251 struct adaptive_sync_caps adaptive_sync_caps; 1252 struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; 1253 union dpcd_max_uncompressed_pixel_rate_cap max_uncompressed_pixel_rate_cap; 1254 1255 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; 1256 union dp_main_line_channel_coding_cap channel_coding_cap; 1257 union dp_sink_video_fallback_formats fallback_formats; 1258 union dp_fec_capability1 fec_cap1; 1259 bool panel_luminance_control; 1260 union dp_cable_id cable_id; 1261 uint8_t edp_rev; 1262 union edp_alpm_caps alpm_caps; 1263 struct edp_psr_info psr_info; 1264 1265 struct replay_info pr_info; 1266 uint16_t edp_oled_emission_rate; 1267 union dp_receive_port0_cap receive_port0_cap; 1268 /* Indicates the number of SST links supported by MSO (Multi-Stream Output) */ 1269 uint8_t mso_cap_sst_links_supported; 1270 }; 1271 1272 union dpcd_sink_ext_caps { 1273 struct { 1274 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1275 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1276 */ 1277 uint8_t sdr_aux_backlight_control : 1; 1278 uint8_t hdr_aux_backlight_control : 1; 1279 uint8_t reserved_1 : 2; 1280 uint8_t oled : 1; 1281 uint8_t reserved_2 : 1; 1282 uint8_t miniled : 1; 1283 uint8_t emission_output : 1; 1284 } bits; 1285 uint8_t raw; 1286 }; 1287 1288 enum dc_link_fec_state { 1289 dc_link_fec_not_ready, 1290 dc_link_fec_ready, 1291 dc_link_fec_enabled 1292 }; 1293 1294 union dpcd_psr_configuration { 1295 struct { 1296 unsigned char ENABLE : 1; 1297 unsigned char TRANSMITTER_ACTIVE_IN_PSR : 1; 1298 unsigned char CRC_VERIFICATION : 1; 1299 unsigned char FRAME_CAPTURE_INDICATION : 1; 1300 /* For eDP 1.4, PSR v2*/ 1301 unsigned char LINE_CAPTURE_INDICATION : 1; 1302 /* For eDP 1.4, PSR v2*/ 1303 unsigned char IRQ_HPD_WITH_CRC_ERROR : 1; 1304 unsigned char ENABLE_PSR2 : 1; 1305 unsigned char EARLY_TRANSPORT_ENABLE : 1; 1306 } bits; 1307 unsigned char raw; 1308 }; 1309 1310 union replay_enable_and_configuration { 1311 struct { 1312 unsigned char FREESYNC_PANEL_REPLAY_MODE :1; 1313 unsigned char TIMING_DESYNC_ERROR_VERIFICATION :1; 1314 unsigned char STATE_TRANSITION_ERROR_DETECTION :1; 1315 unsigned char RESERVED :5; 1316 } bits; 1317 unsigned char raw; 1318 }; 1319 1320 union dpcd_replay_configuration { 1321 struct { 1322 unsigned char STATE_TRANSITION_ERROR_STATUS : 1; 1323 unsigned char DESYNC_ERROR_STATUS : 1; 1324 unsigned char SINK_DEVICE_REPLAY_STATUS : 3; 1325 unsigned char SINK_FRAME_LOCKED : 2; 1326 unsigned char RESERVED : 1; 1327 } bits; 1328 unsigned char raw; 1329 }; 1330 1331 union dpcd_alpm_configuration { 1332 struct { 1333 unsigned char ENABLE : 1; 1334 unsigned char IRQ_HPD_ENABLE : 1; 1335 unsigned char RESERVED : 6; 1336 } bits; 1337 unsigned char raw; 1338 }; 1339 1340 union dpcd_sink_active_vtotal_control_mode { 1341 struct { 1342 unsigned char ENABLE : 1; 1343 unsigned char RESERVED : 7; 1344 } bits; 1345 unsigned char raw; 1346 }; 1347 1348 union psr_error_status { 1349 struct { 1350 unsigned char LINK_CRC_ERROR :1; 1351 unsigned char RFB_STORAGE_ERROR :1; 1352 unsigned char VSC_SDP_ERROR :1; 1353 unsigned char RESERVED :5; 1354 } bits; 1355 unsigned char raw; 1356 }; 1357 1358 union psr_sink_psr_status { 1359 struct { 1360 unsigned char SINK_SELF_REFRESH_STATUS :3; 1361 unsigned char RESERVED :5; 1362 } bits; 1363 unsigned char raw; 1364 }; 1365 1366 struct edp_trace_power_timestamps { 1367 uint64_t poweroff; 1368 uint64_t poweron; 1369 }; 1370 1371 struct dp_trace_lt_counts { 1372 unsigned int total; 1373 unsigned int fail; 1374 }; 1375 1376 enum link_training_result { 1377 LINK_TRAINING_SUCCESS, 1378 LINK_TRAINING_CR_FAIL_LANE0, 1379 LINK_TRAINING_CR_FAIL_LANE1, 1380 LINK_TRAINING_CR_FAIL_LANE23, 1381 /* CR DONE bit is cleared during EQ step */ 1382 LINK_TRAINING_EQ_FAIL_CR, 1383 /* CR DONE bit is cleared but LANE0_CR_DONE is set during EQ step */ 1384 LINK_TRAINING_EQ_FAIL_CR_PARTIAL, 1385 /* other failure during EQ step */ 1386 LINK_TRAINING_EQ_FAIL_EQ, 1387 LINK_TRAINING_LQA_FAIL, 1388 /* one of the CR,EQ or symbol lock is dropped */ 1389 LINK_TRAINING_LINK_LOSS, 1390 /* Abort link training (because sink unplugged) */ 1391 LINK_TRAINING_ABORT, 1392 DP_128b_132b_LT_FAILED, 1393 DP_128b_132b_MAX_LOOP_COUNT_REACHED, 1394 DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT, 1395 DP_128b_132b_CDS_DONE_TIMEOUT, 1396 }; 1397 1398 struct dp_trace_lt { 1399 struct dp_trace_lt_counts counts; 1400 struct dp_trace_timestamps { 1401 unsigned long long start; 1402 unsigned long long end; 1403 } timestamps; 1404 enum link_training_result result; 1405 bool is_logged; 1406 }; 1407 1408 struct dp_trace { 1409 struct dp_trace_lt detect_lt_trace; 1410 struct dp_trace_lt commit_lt_trace; 1411 unsigned int link_loss_count; 1412 bool is_initialized; 1413 struct edp_trace_power_timestamps edp_trace_power_timestamps; 1414 }; 1415 1416 /* TODO - This is a temporary location for any new DPCD definitions. 1417 * We should move these to drm_dp header. 1418 */ 1419 #ifndef DP_LINK_SQUARE_PATTERN 1420 #define DP_LINK_SQUARE_PATTERN 0x10F 1421 #endif 1422 #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX 1423 #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX 0x2217 1424 #endif 1425 #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX 1426 #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX 0x110 1427 #endif 1428 #ifndef DPCD_MAX_UNCOMPRESSED_PIXEL_RATE_CAP 1429 #define DPCD_MAX_UNCOMPRESSED_PIXEL_RATE_CAP 0x221c 1430 #endif 1431 #ifndef DP_LTTPR_ALPM_CAPABILITIES 1432 #define DP_LTTPR_ALPM_CAPABILITIES 0xF0009 1433 #endif 1434 #ifndef DP_REGULATED_AUTONOMOUS_MODE_SUPPORTED_AND_HDMI_LINK_TRAINING_STATUS 1435 #define DP_REGULATED_AUTONOMOUS_MODE_SUPPORTED_AND_HDMI_LINK_TRAINING_STATUS 0x303C 1436 #endif 1437 #ifndef DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 1438 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50 1439 #endif 1440 #ifndef DP_TUNNELING_IRQ 1441 #define DP_TUNNELING_IRQ (1 << 5) 1442 #endif 1443 #ifndef DP_BRANCH_VENDOR_SPECIFIC_START 1444 #define DP_BRANCH_VENDOR_SPECIFIC_START 0x50C 1445 #endif 1446 #ifndef DP_LTTPR_IEEE_OUI 1447 #define DP_LTTPR_IEEE_OUI 0xF003D 1448 #endif 1449 #ifndef DP_LTTPR_DEVICE_ID 1450 #define DP_LTTPR_DEVICE_ID 0xF0040 1451 #endif 1452 /** USB4 DPCD BW Allocation Registers Chapter 10.7 **/ 1453 #ifndef DP_TUNNELING_CAPABILITIES 1454 #define DP_TUNNELING_CAPABILITIES 0xE000D /* 1.4a */ 1455 #endif 1456 #ifndef USB4_DRIVER_ID 1457 #define USB4_DRIVER_ID 0xE000F /* 1.4a */ 1458 #endif 1459 #ifndef USB4_DRIVER_BW_CAPABILITY 1460 #define USB4_DRIVER_BW_CAPABILITY 0xE0020 /* 1.4a */ 1461 #endif 1462 #ifndef DP_IN_ADAPTER_TUNNEL_INFO 1463 #define DP_IN_ADAPTER_TUNNEL_INFO 0xE0021 /* 1.4a */ 1464 #endif 1465 #ifndef DP_BW_GRANULALITY 1466 #define DP_BW_GRANULALITY 0xE0022 /* 1.4a */ 1467 #endif 1468 #ifndef ESTIMATED_BW 1469 #define ESTIMATED_BW 0xE0023 /* 1.4a */ 1470 #endif 1471 #ifndef ALLOCATED_BW 1472 #define ALLOCATED_BW 0xE0024 /* 1.4a */ 1473 #endif 1474 #ifndef DP_TUNNELING_STATUS 1475 #define DP_TUNNELING_STATUS 0xE0025 /* 1.4a */ 1476 #endif 1477 #ifndef DP_TUNNELING_MAX_LINK_RATE 1478 #define DP_TUNNELING_MAX_LINK_RATE 0xE0028 /* 1.4a */ 1479 #endif 1480 #ifndef DP_TUNNELING_MAX_LANE_COUNT 1481 #define DP_TUNNELING_MAX_LANE_COUNT 0xE0029 /* 1.4a */ 1482 #endif 1483 #ifndef DPTX_BW_ALLOCATION_MODE_CONTROL 1484 #define DPTX_BW_ALLOCATION_MODE_CONTROL 0xE0030 /* 1.4a */ 1485 #endif 1486 #ifndef REQUESTED_BW 1487 #define REQUESTED_BW 0xE0031 /* 1.4a */ 1488 #endif 1489 # ifndef DP_TUNNELING_BW_ALLOC_BITS_MASK 1490 # define DP_TUNNELING_BW_ALLOC_BITS_MASK (0x0F << 0) 1491 # endif 1492 # ifndef DP_TUNNELING_BW_REQUEST_FAILED 1493 # define DP_TUNNELING_BW_REQUEST_FAILED (1 << 0) 1494 # endif 1495 # ifndef DP_TUNNELING_BW_REQUEST_SUCCEEDED 1496 # define DP_TUNNELING_BW_REQUEST_SUCCEEDED (1 << 1) 1497 # endif 1498 # ifndef DP_TUNNELING_ESTIMATED_BW_CHANGED 1499 # define DP_TUNNELING_ESTIMATED_BW_CHANGED (1 << 2) 1500 # endif 1501 # ifndef DP_TUNNELING_BW_ALLOC_CAP_CHANGED 1502 # define DP_TUNNELING_BW_ALLOC_CAP_CHANGED (1 << 3) 1503 # endif 1504 # ifndef DPTX_BW_ALLOC_UNMASK_IRQ 1505 # define DPTX_BW_ALLOC_UNMASK_IRQ (1 << 6) 1506 # endif 1507 # ifndef DPTX_BW_ALLOC_MODE_ENABLE 1508 # define DPTX_BW_ALLOC_MODE_ENABLE (1 << 7) 1509 # endif 1510 1511 #endif /* DC_DP_TYPES_H */ 1512