xref: /illumos-gate/usr/src/uts/sun/sys/scsi/adapters/fasdma.h (revision 7c478bd95313f5f23a4c958a745db2134aa03244)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright (c) 1996, by Sun Microsystems, Inc.
24  * All rights reserved.
25  */
26 
27 #ifndef	_SYS_SCSI_ADAPTERS_FASDMA_H
28 #define	_SYS_SCSI_ADAPTERS_FASDMA_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 /*
33  * SCSI	Channel	Engine (fas SCSI DVMA) definitions
34  */
35 #include <sys/note.h>
36 
37 #ifdef	__cplusplus
38 extern "C" {
39 #endif
40 
41 /*
42  * for historical reasons, we call the scsi channel engine
43  * dma for now
44  */
45 struct dma {
46 	uint32_t dma_csr;		/* control/status register */
47 	uint32_t dma_addr;		/* dma address register	*/
48 	uint32_t dma_count;		/* count register */
49 	uint32_t dma_test;		/* test csr register */
50 };
51 
52 
53 /*
54  * dma_csr bits
55  */
56 #define	DMA_INTPEND	0x0001	/* (R) interrupt pending from fas or dma */
57 #define	DMA_ERRPEND	0x0002	/* (R) error pending from dma */
58 #define	DMA_DRAINING	0x0004	/* (R) if set, buffers aredraining to mem */
59 #define	DMA_INTEN	0x0010	/* (RW)	enable interrupts */
60 #define	DMA_RESET	0x0080	/* (RW)	invalidates the	buffers, resets	CE */
61 #define	DMA_WRITE	0x0100	/* (RW)	write to memory	*/
62 #define	DMA_ENDVMA	0x0200	/* (RW)	enable dvma */
63 #define	DMA_REQPEND	0x0400	/* (R) do not assert reset when	set! */
64 #define	DMA_DMAREV	0x7800	/* (R) dma revision */
65 #define	DMA_WIDE_EN	0x8000	/* (RW)	enable wide SBus DVMA mode */
66 #define	DMA_DSBL_DRAIN  0x00020000	/* (RW)	disable	draining on slave */
67 					/*	accesses */
68 #define	DMA_BURSTS  	0x000c0000	/* (RW)	burst sizes */
69 #define	DMA_TWO_CYCLE	0x00200000	/* (RW)	2 cycle	dma access to 366 */
70 #define	DMA_DSBL_PARITY	0x02000000	/* (RW)	disables checking for parity */
71 #define	DMA_PAUSE_FAS	0x04000000	/* (RW)	pause  fas */
72 #define	DMA_RESET_FAS	0x08000000	/* (RW)	hardware reset to fas */
73 #define	DMA_DEV_ID	0xf0000000	/* (R)	Device ID (0xb)	*/
74 
75 #define	DMA_INT_MASK  (DMA_INTPEND | DMA_ERRPEND)
76 
77 #define	DMA_BITS	\
78 "\20\34RST\33PSE\31DSBLPAR\26TWOCYC\24BRST1\23BST0\
79 \22DSBLEDRN\20WIDE\13REQPEND\12ENBLE\11WR\10RST\05INTEN\
80 \03DRNING\02ERRPEND\01INTPND"
81 
82 #define	DMAREV(dmap)	(((dmap->dma_csr) & DMA_DMAREV) >> 11)
83 
84 /*
85  * burst sizes for dma
86  */
87 #define	DMA_BURST16	0x00000000
88 #define	DMA_BURST32	0x00040000
89 #define	DMA_BURST64	0x000c0000
90 #define	DMA_CE_ID	0xb0000000	/* SCSI	CE device ID */
91 
92 /*
93  * burst sizes for dma attr
94  */
95 #define	BURST1		0x01
96 #define	BURST2		0x02
97 #define	BURST4		0x04
98 #define	BURST8		0x08
99 #define	BURST16		0x10
100 #define	BURST32		0x20
101 #define	BURST64		0x40
102 #define	BURSTSIZE_MASK	0x7f
103 #define	DEFAULT_BURSTSIZE \
104 		BURST64|BURST32|BURST16|BURST8|BURST4|BURST2|BURST1
105 
106 #ifdef	__cplusplus
107 }
108 #endif
109 
110 #endif	/* _SYS_SCSI_ADAPTERS_FASDMA_H */
111