xref: /linux/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h (revision 7ae9fb1b7ecbb5d85d07857943f677fd1a559b18)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 
6 #ifndef __INTEL_DKL_PHY_REGS__
7 #define __INTEL_DKL_PHY_REGS__
8 
9 #include <linux/types.h>
10 
11 struct intel_dkl_phy_reg {
12 	u32 reg:24;
13 	u32 bank_idx:4;
14 };
15 
16 #define _DKL_PHY1_BASE					0x168000
17 #define _DKL_PHY2_BASE					0x169000
18 #define _DKL_PHY3_BASE					0x16A000
19 #define _DKL_PHY4_BASE					0x16B000
20 #define _DKL_PHY5_BASE					0x16C000
21 #define _DKL_PHY6_BASE					0x16D000
22 
23 #define DKL_REG_TC_PORT(__reg) \
24 	(TC_PORT_1 + ((__reg).reg - _DKL_PHY1_BASE) / (_DKL_PHY2_BASE - _DKL_PHY1_BASE))
25 
26 /* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
27 #define DKL_REG_MMIO(__reg)				_MMIO((__reg).reg)
28 
29 #define _DKL_REG_PHY_BASE(tc_port)			_PORT(tc_port, \
30 							      _DKL_PHY1_BASE, \
31 							      _DKL_PHY2_BASE)
32 
33 #define _DKL_BANK_SHIFT					12
34 #define _DKL_REG_BANK_OFFSET(phy_offset) \
35 	((phy_offset) & ((1 << _DKL_BANK_SHIFT) - 1))
36 #define _DKL_REG_BANK_IDX(phy_offset) \
37 	(((phy_offset) >> _DKL_BANK_SHIFT) & 0xf)
38 
39 #define _DKL_REG(tc_port, phy_offset)	\
40 	((const struct intel_dkl_phy_reg) { \
41 		.reg = _DKL_REG_PHY_BASE(tc_port) + \
42 		       _DKL_REG_BANK_OFFSET(phy_offset), \
43 		.bank_idx = _DKL_REG_BANK_IDX(phy_offset), \
44 	})
45 
46 #define _DKL_REG_LN(tc_port, ln_idx, ln0_offs, ln1_offs) \
47 	_DKL_REG(tc_port, (ln0_offs) + (ln_idx) * ((ln1_offs) - (ln0_offs)))
48 
49 #define _DKL_PCS_DW5_LN0				0x0014
50 #define _DKL_PCS_DW5_LN1				0x1014
51 #define DKL_PCS_DW5(tc_port, ln)			_DKL_REG_LN(tc_port, ln, \
52 								    _DKL_PCS_DW5_LN0, \
53 								    _DKL_PCS_DW5_LN1)
54 #define   DKL_PCS_DW5_CORE_SOFTRESET			REG_BIT(11)
55 
56 #define _DKL_PLL_DIV0					0x2200
57 #define DKL_PLL_DIV0(tc_port)				_DKL_REG(tc_port, \
58 								 _DKL_PLL_DIV0)
59 #define   DKL_PLL_DIV0_AFC_STARTUP_MASK			REG_GENMASK(27, 25)
60 #define   DKL_PLL_DIV0_AFC_STARTUP(val)			REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val))
61 #define   DKL_PLL_DIV0_INTEG_COEFF(x)			((x) << 16)
62 #define   DKL_PLL_DIV0_INTEG_COEFF_MASK			(0x1F << 16)
63 #define   DKL_PLL_DIV0_PROP_COEFF(x)			((x) << 12)
64 #define   DKL_PLL_DIV0_PROP_COEFF_MASK			(0xF << 12)
65 #define   DKL_PLL_DIV0_FBPREDIV_SHIFT			(8)
66 #define   DKL_PLL_DIV0_FBPREDIV(x)			((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT)
67 #define   DKL_PLL_DIV0_FBPREDIV_MASK			(0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT)
68 #define   DKL_PLL_DIV0_FBDIV_INT(x)			((x) << 0)
69 #define   DKL_PLL_DIV0_FBDIV_INT_MASK			(0xFF << 0)
70 #define   DKL_PLL_DIV0_MASK				(DKL_PLL_DIV0_INTEG_COEFF_MASK | \
71 							 DKL_PLL_DIV0_PROP_COEFF_MASK | \
72 							 DKL_PLL_DIV0_FBPREDIV_MASK | \
73 							 DKL_PLL_DIV0_FBDIV_INT_MASK)
74 
75 #define _DKL_PLL_DIV1					0x2204
76 #define DKL_PLL_DIV1(tc_port)				_DKL_REG(tc_port, \
77 								 _DKL_PLL_DIV1)
78 #define   DKL_PLL_DIV1_IREF_TRIM(x)			((x) << 16)
79 #define   DKL_PLL_DIV1_IREF_TRIM_MASK			(0x1F << 16)
80 #define   DKL_PLL_DIV1_TDC_TARGET_CNT(x)		((x) << 0)
81 #define   DKL_PLL_DIV1_TDC_TARGET_CNT_MASK		(0xFF << 0)
82 
83 #define _DKL_PLL_SSC					0x2210
84 #define DKL_PLL_SSC(tc_port)				_DKL_REG(tc_port, \
85 								 _DKL_PLL_SSC)
86 #define   DKL_PLL_SSC_IREF_NDIV_RATIO(x)		((x) << 29)
87 #define   DKL_PLL_SSC_IREF_NDIV_RATIO_MASK		(0x7 << 29)
88 #define   DKL_PLL_SSC_STEP_LEN(x)			((x) << 16)
89 #define   DKL_PLL_SSC_STEP_LEN_MASK			(0xFF << 16)
90 #define   DKL_PLL_SSC_STEP_NUM(x)			((x) << 11)
91 #define   DKL_PLL_SSC_STEP_NUM_MASK			(0x7 << 11)
92 #define   DKL_PLL_SSC_EN				(1 << 9)
93 
94 #define _DKL_PLL_BIAS					0x2214
95 #define DKL_PLL_BIAS(tc_port)				_DKL_REG(tc_port, \
96 								 _DKL_PLL_BIAS)
97 #define   DKL_PLL_BIAS_FRAC_EN_H			(1 << 30)
98 #define   DKL_PLL_BIAS_FBDIV_SHIFT			(8)
99 #define   DKL_PLL_BIAS_FBDIV_FRAC(x)			((x) << DKL_PLL_BIAS_FBDIV_SHIFT)
100 #define   DKL_PLL_BIAS_FBDIV_FRAC_MASK			(0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT)
101 
102 #define _DKL_PLL_TDC_COLDST_BIAS			0x2218
103 #define DKL_PLL_TDC_COLDST_BIAS(tc_port)		_DKL_REG(tc_port, \
104 								 _DKL_PLL_TDC_COLDST_BIAS)
105 #define   DKL_PLL_TDC_SSC_STEP_SIZE(x)			((x) << 8)
106 #define   DKL_PLL_TDC_SSC_STEP_SIZE_MASK		(0xFF << 8)
107 #define   DKL_PLL_TDC_FEED_FWD_GAIN(x)			((x) << 0)
108 #define   DKL_PLL_TDC_FEED_FWD_GAIN_MASK		(0xFF << 0)
109 
110 #define _DKL_REFCLKIN_CTL				0x212C
111 #define DKL_REFCLKIN_CTL(tc_port)			_DKL_REG(tc_port, \
112 								 _DKL_REFCLKIN_CTL)
113 /* Bits are the same as MG_REFCLKIN_CTL */
114 
115 #define _DKL_CLKTOP2_HSCLKCTL				0x20D4
116 #define DKL_CLKTOP2_HSCLKCTL(rc_port)			_DKL_REG(tc_port, \
117 								 _DKL_CLKTOP2_HSCLKCTL)
118 /* Bits are the same as MG_CLKTOP2_HSCLKCTL */
119 
120 #define _DKL_CLKTOP2_CORECLKCTL1			0x20D8
121 #define DKL_CLKTOP2_CORECLKCTL1(tc_port)		_DKL_REG(tc_port, \
122 								 _DKL_CLKTOP2_CORECLKCTL1)
123 /* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */
124 
125 #define _DKL_TX_DPCNTL0_LN0				0x02C0
126 #define _DKL_TX_DPCNTL0_LN1				0x12C0
127 #define DKL_TX_DPCNTL0(tc_port, ln)			_DKL_REG_LN(tc_port, ln, \
128 								    _DKL_TX_DPCNTL0_LN0, \
129 								    _DKL_TX_DPCNTL0_LN1)
130 #define  DKL_TX_PRESHOOT_COEFF(x)			((x) << 13)
131 #define  DKL_TX_PRESHOOT_COEFF_MASK			(0x1f << 13)
132 #define  DKL_TX_DE_EMPHASIS_COEFF(x)			((x) << 8)
133 #define  DKL_TX_DE_EMPAHSIS_COEFF_MASK			(0x1f << 8)
134 #define  DKL_TX_VSWING_CONTROL(x)			((x) << 0)
135 #define  DKL_TX_VSWING_CONTROL_MASK			(0x7 << 0)
136 
137 #define _DKL_TX_DPCNTL1_LN0				0x02C4
138 #define _DKL_TX_DPCNTL1_LN1				0x12C4
139 #define DKL_TX_DPCNTL1(tc_port, ln)			_DKL_REG_LN(tc_port, ln, \
140 								    _DKL_TX_DPCNTL1_LN0, \
141 								    _DKL_TX_DPCNTL1_LN1)
142 /* Bits are the same as DKL_TX_DPCNTRL0 */
143 
144 #define _DKL_TX_DPCNTL2_LN0				0x02C8
145 #define _DKL_TX_DPCNTL2_LN1				0x12C8
146 #define DKL_TX_DPCNTL2(tc_port, ln)			_DKL_REG_LN(tc_port, ln, \
147 								    _DKL_TX_DPCNTL2_LN0, \
148 								    _DKL_TX_DPCNTL2_LN1)
149 #define  DKL_TX_DP20BITMODE				REG_BIT(2)
150 #define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK	REG_GENMASK(4, 3)
151 #define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val)	REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val))
152 #define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK	REG_GENMASK(6, 5)
153 #define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val)	REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val))
154 
155 #define _DKL_TX_FW_CALIB_LN0				0x02F8
156 #define _DKL_TX_FW_CALIB_LN1				0x12F8
157 #define DKL_TX_FW_CALIB(tc_port, ln)			_DKL_REG_LN(tc_port, ln, \
158 								    _DKL_TX_FW_CALIB_LN0, \
159 								    _DKL_TX_FW_CALIB_LN1)
160 #define  DKL_TX_CFG_DISABLE_WAIT_INIT			(1 << 7)
161 
162 #define _DKL_TX_PMD_LANE_SUS_LN0			0x0D00
163 #define _DKL_TX_PMD_LANE_SUS_LN1			0x1D00
164 #define DKL_TX_PMD_LANE_SUS(tc_port, ln)		_DKL_REG_LN(tc_port, ln, \
165 								    _DKL_TX_PMD_LANE_SUS_LN0, \
166 								    _DKL_TX_PMD_LANE_SUS_LN1)
167 
168 #define _DKL_TX_DW17_LN0				0x0DC4
169 #define _DKL_TX_DW17_LN1				0x1DC4
170 #define DKL_TX_DW17(tc_port, ln)			_DKL_REG_LN(tc_port, ln, \
171 								    _DKL_TX_DW17_LN0, \
172 								    _DKL_TX_DW17_LN1)
173 
174 #define _DKL_TX_DW18_LN0				0x0DC8
175 #define _DKL_TX_DW18_LN1				0x1DC8
176 #define DKL_TX_DW18(tc_port, ln)			_DKL_REG_LN(tc_port, ln, \
177 								    _DKL_TX_DW18_LN0, \
178 								    _DKL_TX_DW18_LN1)
179 
180 #define _DKL_DP_MODE_LN0				0x00A0
181 #define _DKL_DP_MODE_LN1				0x10A0
182 #define DKL_DP_MODE(tc_port, ln)			_DKL_REG_LN(tc_port, ln, \
183 								    _DKL_DP_MODE_LN0, \
184 								    _DKL_DP_MODE_LN1)
185 
186 #define _DKL_CMN_UC_DW27				0x236C
187 #define DKL_CMN_UC_DW_27(tc_port)			_DKL_REG(tc_port, \
188 								 _DKL_CMN_UC_DW27)
189 #define  DKL_CMN_UC_DW27_UC_HEALTH			(0x1 << 15)
190 
191 /*
192  * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than
193  * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0
194  * or HIP_INDEX_REG1, based on the port number, to set the upper 2 address
195  * bits that point the 4KB window into the full PHY register space.
196  */
197 #define _HIP_INDEX_REG0					0x1010A0
198 #define _HIP_INDEX_REG1					0x1010A4
199 #define HIP_INDEX_REG(tc_port)				_MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \
200 							      : _HIP_INDEX_REG1)
201 #define _HIP_INDEX_SHIFT(tc_port)			(8 * ((tc_port) % 4))
202 #define HIP_INDEX_VAL(tc_port, val)			((val) << _HIP_INDEX_SHIFT(tc_port))
203 
204 #endif /* __INTEL_DKL_PHY_REGS__ */
205