1 /*-
2 * Copyright (c) 2016 Justin Hibbits
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/param.h>
28 #include <sys/systm.h>
29 #include <sys/bus.h>
30 #include <sys/endian.h>
31 #include <sys/kernel.h>
32 #include <sys/module.h>
33 #include <sys/malloc.h>
34 #include <sys/rman.h>
35 #include <sys/fbio.h>
36 #include <sys/consio.h>
37
38 #include <vm/vm.h>
39 #include <vm/pmap.h>
40
41 #include <dev/fdt/fdt_common.h>
42 #include <dev/ofw/openfirm.h>
43 #include <dev/ofw/ofw_bus.h>
44 #include <dev/ofw/ofw_bus_subr.h>
45
46 #include <dev/videomode/videomode.h>
47 #include <dev/videomode/edidvar.h>
48
49 #include <dev/vt/vt.h>
50 #include <dev/vt/colors/vt_termcolors.h>
51
52 #include <powerpc/mpc85xx/mpc85xx.h>
53
54 #include <machine/bus.h>
55 #include <machine/cpu.h>
56
57 #include "fb_if.h"
58
59 #define DIU_DESC_1 0x000 /* Plane1 Area Descriptor Pointer Register */
60 #define DIU_DESC_2 0x004 /* Plane2 Area Descriptor Pointer Register */
61 #define DIU_DESC_3 0x008 /* Plane3 Area Descriptor Pointer Register */
62 #define DIU_GAMMA 0x00C /* Gamma Register */
63 #define DIU_PALETTE 0x010 /* Palette Register */
64 #define DIU_CURSOR 0x014 /* Cursor Register */
65 #define DIU_CURS_POS 0x018 /* Cursor Position Register */
66 #define CURSOR_Y_SHIFT 16
67 #define CURSOR_X_SHIFT 0
68 #define DIU_DIU_MODE 0x01C /* DIU4 Mode */
69 #define DIU_MODE_M 0x7
70 #define DIU_MODE_S 0
71 #define DIU_MODE_NORMAL 0x1
72 #define DIU_MODE_2 0x2
73 #define DIU_MODE_3 0x3
74 #define DIU_MODE_COLBAR 0x4
75 #define DIU_BGND 0x020 /* Background */
76 #define DIU_BGND_WB 0x024 /* Background Color in write back Mode Register */
77 #define DIU_DISP_SIZE 0x028 /* Display Size */
78 #define DELTA_Y_S 16
79 #define DELTA_X_S 0
80 #define DIU_WB_SIZE 0x02C /* Write back Plane Size Register */
81 #define DELTA_Y_WB_S 16
82 #define DELTA_X_WB_S 0
83 #define DIU_WB_MEM_ADDR 0x030 /* Address to Store the write back Plane Register */
84 #define DIU_HSYN_PARA 0x034 /* Horizontal Sync Parameter */
85 #define BP_H_SHIFT 22
86 #define PW_H_SHIFT 11
87 #define FP_H_SHIFT 0
88 #define DIU_VSYN_PARA 0x038 /* Vertical Sync Parameter */
89 #define BP_V_SHIFT 22
90 #define PW_V_SHIFT 11
91 #define FP_V_SHIFT 0
92 #define DIU_SYNPOL 0x03C /* Synchronize Polarity */
93 #define BP_VS (1 << 4)
94 #define BP_HS (1 << 3)
95 #define INV_CS (1 << 2)
96 #define INV_VS (1 << 1)
97 #define INV_HS (1 << 0)
98 #define INV_PDI_VS (1 << 8) /* Polarity of PDI input VSYNC. */
99 #define INV_PDI_HS (1 << 9) /* Polarity of PDI input HSYNC. */
100 #define INV_PDI_DE (1 << 10) /* Polarity of PDI input DE. */
101 #define DIU_THRESHOLD 0x040 /* Threshold */
102 #define LS_BF_VS_SHIFT 16
103 #define OUT_BUF_LOW_SHIFT 0
104 #define DIU_INT_STATUS 0x044 /* Interrupt Status */
105 #define DIU_INT_MASK 0x048 /* Interrupt Mask */
106 #define DIU_COLBAR_1 0x04C /* COLBAR_1 */
107 #define DIU_COLORBARn_R(x) ((x & 0xff) << 16)
108 #define DIU_COLORBARn_G(x) ((x & 0xff) << 8)
109 #define DIU_COLORBARn_B(x) ((x & 0xff) << 0)
110 #define DIU_COLBAR_2 0x050 /* COLBAR_2 */
111 #define DIU_COLBAR_3 0x054 /* COLBAR_3 */
112 #define DIU_COLBAR_4 0x058 /* COLBAR_4 */
113 #define DIU_COLBAR_5 0x05c /* COLBAR_5 */
114 #define DIU_COLBAR_6 0x060 /* COLBAR_6 */
115 #define DIU_COLBAR_7 0x064 /* COLBAR_7 */
116 #define DIU_COLBAR_8 0x068 /* COLBAR_8 */
117 #define DIU_FILLING 0x06C /* Filling Register */
118 #define DIU_PLUT 0x070 /* Priority Look Up Table Register */
119
120 /* Control Descriptor */
121 #define DIU_CTRLDESCL(n, m) 0x200 + (0x40 * n) + 0x4 * (m - 1)
122 #define DIU_CTRLDESCLn_1(n) DIU_CTRLDESCL(n, 1)
123 #define DIU_CTRLDESCLn_2(n) DIU_CTRLDESCL(n, 2)
124 #define DIU_CTRLDESCLn_3(n) DIU_CTRLDESCL(n, 3)
125 #define TRANS_SHIFT 20
126 #define DIU_CTRLDESCLn_4(n) DIU_CTRLDESCL(n, 4)
127 #define BPP_MASK 0xf /* Bit per pixel Mask */
128 #define BPP_SHIFT 16 /* Bit per pixel Shift */
129 #define BPP24 0x5
130 #define EN_LAYER (1 << 31) /* Enable the layer */
131 #define DIU_CTRLDESCLn_5(n) DIU_CTRLDESCL(n, 5)
132 #define DIU_CTRLDESCLn_6(n) DIU_CTRLDESCL(n, 6)
133 #define DIU_CTRLDESCLn_7(n) DIU_CTRLDESCL(n, 7)
134 #define DIU_CTRLDESCLn_8(n) DIU_CTRLDESCL(n, 8)
135 #define DIU_CTRLDESCLn_9(n) DIU_CTRLDESCL(n, 9)
136
137 #define NUM_LAYERS 1
138
139 struct panel_info {
140 uint32_t panel_width;
141 uint32_t panel_height;
142 uint32_t panel_hbp;
143 uint32_t panel_hpw;
144 uint32_t panel_hfp;
145 uint32_t panel_vbp;
146 uint32_t panel_vpw;
147 uint32_t panel_vfp;
148 uint32_t panel_freq;
149 uint32_t clk_div;
150 };
151
152 struct diu_area_descriptor {
153 uint32_t pixel_format;
154 uint32_t bitmap_address;
155 uint32_t source_size;
156 uint32_t aoi_size;
157 uint32_t aoi_offset;
158 uint32_t display_offset;
159 uint32_t chroma_key_max;
160 uint32_t chroma_key_min;
161 uint32_t next_ad_addr;
162 } __aligned(32);
163
164 struct diu_softc {
165 struct resource *res[2];
166 void *ih;
167 device_t sc_dev;
168 device_t sc_fbd; /* fbd child */
169 struct fb_info sc_info;
170 struct panel_info sc_panel;
171 struct diu_area_descriptor *sc_planes[3];
172 uint8_t *sc_gamma;
173 uint8_t *sc_cursor;
174 };
175
176 static struct resource_spec diu_spec[] = {
177 { SYS_RES_MEMORY, 0, RF_ACTIVE },
178 { SYS_RES_IRQ, 0, RF_ACTIVE },
179 { -1, 0 }
180 };
181
182 static int
diu_probe(device_t dev)183 diu_probe(device_t dev)
184 {
185
186 if (!ofw_bus_status_okay(dev))
187 return (ENXIO);
188
189 if (!ofw_bus_is_compatible(dev, "fsl,diu"))
190 return (ENXIO);
191
192 device_set_desc(dev, "Freescale Display Interface Unit");
193 return (BUS_PROBE_DEFAULT);
194 }
195
196 static void
diu_intr(void * arg)197 diu_intr(void *arg)
198 {
199 struct diu_softc *sc;
200 int reg;
201
202 sc = arg;
203
204 /* Ack interrupts */
205 reg = bus_read_4(sc->res[0], DIU_INT_STATUS);
206 bus_write_4(sc->res[0], DIU_INT_STATUS, reg);
207
208 /* TODO interrupt handler */
209 }
210
211 static int
diu_set_pxclk(device_t dev,unsigned int freq)212 diu_set_pxclk(device_t dev, unsigned int freq)
213 {
214 unsigned long bus_freq;
215 uint32_t pxclk_set;
216 uint32_t clkdvd;
217
218 if ((bus_freq = mpc85xx_get_platform_clock()) <= 0) {
219 device_printf(dev, "Unable to get bus frequency\n");
220 return (ENXIO);
221 }
222
223 /* freq is in kHz */
224 freq *= 1000;
225 /* adding freq/2 to round-to-closest */
226 pxclk_set = min(max((bus_freq + freq/2) / freq, 2), 255) << 16;
227 pxclk_set |= OCP85XX_CLKDVDR_PXCKEN;
228 clkdvd = ccsr_read4(OCP85XX_CLKDVDR);
229 clkdvd &= ~(OCP85XX_CLKDVDR_PXCKEN | OCP85XX_CLKDVDR_PXCKINV |
230 OCP85XX_CLKDVDR_PXCLK_MASK);
231 ccsr_write4(OCP85XX_CLKDVDR, clkdvd);
232 ccsr_write4(OCP85XX_CLKDVDR, clkdvd | pxclk_set);
233
234 return (0);
235 }
236
237 static int
diu_init(struct diu_softc * sc)238 diu_init(struct diu_softc *sc)
239 {
240 struct panel_info *panel;
241 int reg;
242
243 panel = &sc->sc_panel;
244
245 /* Temporarily disable the DIU while configuring */
246 reg = bus_read_4(sc->res[0], DIU_DIU_MODE);
247 reg &= ~(DIU_MODE_M << DIU_MODE_S);
248 bus_write_4(sc->res[0], DIU_DIU_MODE, reg);
249
250 if (diu_set_pxclk(sc->sc_dev, panel->panel_freq) < 0) {
251 return (ENXIO);
252 }
253
254 /* Configure DIU */
255 /* Need to set these somehow later... */
256 bus_write_4(sc->res[0], DIU_GAMMA, vtophys(sc->sc_gamma));
257 bus_write_4(sc->res[0], DIU_CURSOR, vtophys(sc->sc_cursor));
258 bus_write_4(sc->res[0], DIU_CURS_POS, 0);
259
260 reg = ((sc->sc_info.fb_height) << DELTA_Y_S);
261 reg |= sc->sc_info.fb_width;
262 bus_write_4(sc->res[0], DIU_DISP_SIZE, reg);
263
264 reg = (panel->panel_hbp << BP_H_SHIFT);
265 reg |= (panel->panel_hpw << PW_H_SHIFT);
266 reg |= (panel->panel_hfp << FP_H_SHIFT);
267 bus_write_4(sc->res[0], DIU_HSYN_PARA, reg);
268
269 reg = (panel->panel_vbp << BP_V_SHIFT);
270 reg |= (panel->panel_vpw << PW_V_SHIFT);
271 reg |= (panel->panel_vfp << FP_V_SHIFT);
272 bus_write_4(sc->res[0], DIU_VSYN_PARA, reg);
273
274 bus_write_4(sc->res[0], DIU_BGND, 0);
275
276 /* Mask all the interrupts */
277 bus_write_4(sc->res[0], DIU_INT_MASK, 0x3f);
278
279 /* Reset all layers */
280 sc->sc_planes[0] = contigmalloc(sizeof(struct diu_area_descriptor),
281 M_DEVBUF, M_ZERO, 0, BUS_SPACE_MAXADDR_32BIT, 32, 0);
282 bus_write_4(sc->res[0], DIU_DESC_1, vtophys(sc->sc_planes[0]));
283 bus_write_4(sc->res[0], DIU_DESC_2, 0);
284 bus_write_4(sc->res[0], DIU_DESC_3, 0);
285
286 /* Setup first plane */
287 /* Area descriptor fields are little endian, so byte swap. */
288 /* Word 0: Pixel format */
289 /* Set to 8:8:8:8 ARGB, 4 bytes per pixel, no flip. */
290 #define MAKE_PXLFMT(as,rs,gs,bs,a,r,g,b,f,s) \
291 htole32((as << (4 * a)) | (rs << 4 * r) | \
292 (gs << 4 * g) | (bs << 4 * b) | \
293 (f << 28) | (s << 16) | \
294 (a << 25) | (r << 19) | \
295 (g << 21) | (b << 24))
296 reg = MAKE_PXLFMT(8, 8, 8, 8, 3, 2, 1, 0, 1, 3);
297 sc->sc_planes[0]->pixel_format = reg;
298 /* Word 1: Bitmap address */
299 sc->sc_planes[0]->bitmap_address = htole32(sc->sc_info.fb_pbase);
300 /* Word 2: Source size/global alpha */
301 reg = (sc->sc_info.fb_width | (sc->sc_info.fb_height << 12));
302 sc->sc_planes[0]->source_size = htole32(reg);
303 /* Word 3: AOI Size */
304 reg = (sc->sc_info.fb_width | (sc->sc_info.fb_height << 16));
305 sc->sc_planes[0]->aoi_size = htole32(reg);
306 /* Word 4: AOI Offset */
307 sc->sc_planes[0]->aoi_offset = 0;
308 /* Word 5: Display offset */
309 sc->sc_planes[0]->display_offset = 0;
310 /* Word 6: Chroma key max */
311 sc->sc_planes[0]->chroma_key_max = 0;
312 /* Word 7: Chroma key min */
313 reg = 255 << 16 | 255 << 8 | 255;
314 sc->sc_planes[0]->chroma_key_min = htole32(reg);
315 /* Word 8: Next AD */
316 sc->sc_planes[0]->next_ad_addr = 0;
317
318 /* TODO: derive this from the panel size */
319 bus_write_4(sc->res[0], DIU_PLUT, 0x1f5f666);
320
321 /* Enable DIU in normal mode */
322 reg = bus_read_4(sc->res[0], DIU_DIU_MODE);
323 reg &= ~(DIU_MODE_M << DIU_MODE_S);
324 reg |= (DIU_MODE_NORMAL << DIU_MODE_S);
325 bus_write_4(sc->res[0], DIU_DIU_MODE, reg);
326
327 return (0);
328 }
329
330 static int
diu_attach(device_t dev)331 diu_attach(device_t dev)
332 {
333 struct edid_info edid;
334 struct diu_softc *sc;
335 const struct videomode *videomode;
336 void *edid_cells;
337 const char *vm_name;
338 phandle_t node;
339 int h, r, w;
340 int err, i;
341
342 sc = device_get_softc(dev);
343 sc->sc_dev = dev;
344
345 if (bus_alloc_resources(dev, diu_spec, sc->res)) {
346 device_printf(dev, "could not allocate resources\n");
347 return (ENXIO);
348 }
349
350 node = ofw_bus_get_node(dev);
351 /* Setup interrupt handler */
352 err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_BIO | INTR_MPSAFE,
353 NULL, diu_intr, sc, &sc->ih);
354 if (err) {
355 device_printf(dev, "Unable to alloc interrupt resource.\n");
356 return (ENXIO);
357 }
358
359 /* TODO: Eventually, allow EDID to be dynamically provided. */
360 if (OF_getprop_alloc(node, "edid", &edid_cells) <= 0) {
361 /* Get a resource hint: hint.fb.N.mode */
362 if (resource_string_value(device_get_name(dev),
363 device_get_unit(dev), "mode", &vm_name) != 0) {
364 device_printf(dev,
365 "No EDID data and no video-mode env set\n");
366 return (ENXIO);
367 }
368 }
369 if (edid_cells != NULL) {
370 if (edid_parse(edid_cells, &edid) != 0) {
371 device_printf(dev, "Error parsing EDID\n");
372 OF_prop_free(edid_cells);
373 return (ENXIO);
374 }
375 videomode = edid.edid_preferred_mode;
376 } else {
377 /* Parse video-mode kenv variable. */
378 if ((err = sscanf(vm_name, "%dx%d@%d", &w, &h, &r)) != 3) {
379 device_printf(dev,
380 "Cannot parse video mode: %s\n", vm_name);
381 return (ENXIO);
382 }
383 videomode = pick_mode_by_ref(w, h, r);
384 if (videomode == NULL) {
385 device_printf(dev,
386 "Cannot find mode for %dx%d@%d", w, h, r);
387 return (ENXIO);
388 }
389 }
390
391 sc->sc_panel.panel_width = videomode->hdisplay;
392 sc->sc_panel.panel_height = videomode->vdisplay;
393 sc->sc_panel.panel_hbp = videomode->hsync_start - videomode->hdisplay;
394 sc->sc_panel.panel_hfp = videomode->htotal - videomode->hsync_end;
395 sc->sc_panel.panel_hpw = videomode->hsync_end - videomode->hsync_start;
396 sc->sc_panel.panel_vbp = videomode->vsync_start - videomode->vdisplay;
397 sc->sc_panel.panel_vfp = videomode->vtotal - videomode->vsync_end;
398 sc->sc_panel.panel_vpw = videomode->vsync_end - videomode->vsync_start;
399 sc->sc_panel.panel_freq = videomode->dot_clock;
400
401 sc->sc_info.fb_width = sc->sc_panel.panel_width;
402 sc->sc_info.fb_height = sc->sc_panel.panel_height;
403 sc->sc_info.fb_stride = sc->sc_info.fb_width * 4;
404 sc->sc_info.fb_bpp = sc->sc_info.fb_depth = 32;
405 sc->sc_info.fb_size = sc->sc_info.fb_height * sc->sc_info.fb_stride;
406 sc->sc_info.fb_vbase = (intptr_t)contigmalloc(sc->sc_info.fb_size,
407 M_DEVBUF, M_ZERO, 0, BUS_SPACE_MAXADDR_32BIT, PAGE_SIZE, 0);
408 sc->sc_info.fb_pbase = (intptr_t)vtophys(sc->sc_info.fb_vbase);
409 sc->sc_info.fb_flags = FB_FLAG_MEMATTR;
410 sc->sc_info.fb_memattr = VM_MEMATTR_DEFAULT;
411
412 /* Gamma table is 3 consecutive segments of 256 bytes. */
413 sc->sc_gamma = contigmalloc(3 * 256, M_DEVBUF, 0, 0,
414 BUS_SPACE_MAXADDR_32BIT, PAGE_SIZE, 0);
415 /* Initialize gamma to default */
416 for (i = 0; i < 3 * 256; i++)
417 sc->sc_gamma[i] = (i % 256);
418
419 /* Cursor format is 32x32x16bpp */
420 sc->sc_cursor = contigmalloc(32 * 32 * 2, M_DEVBUF, M_ZERO, 0,
421 BUS_SPACE_MAXADDR_32BIT, PAGE_SIZE, 0);
422
423 diu_init(sc);
424
425 sc->sc_info.fb_name = device_get_nameunit(dev);
426
427 /* Ask newbus to attach framebuffer device to me. */
428 sc->sc_fbd = device_add_child(dev, "fbd", device_get_unit(dev));
429 if (sc->sc_fbd == NULL)
430 device_printf(dev, "Can't attach fbd device\n");
431
432 if ((err = device_probe_and_attach(sc->sc_fbd)) != 0) {
433 device_printf(dev, "Failed to attach fbd device: %d\n", err);
434 }
435
436 return (0);
437 }
438
439 static struct fb_info *
diu_fb_getinfo(device_t dev)440 diu_fb_getinfo(device_t dev)
441 {
442 struct diu_softc *sc = device_get_softc(dev);
443
444 return (&sc->sc_info);
445 }
446
447 static device_method_t diu_methods[] = {
448 DEVMETHOD(device_probe, diu_probe),
449 DEVMETHOD(device_attach, diu_attach),
450
451 /* Framebuffer service methods */
452 DEVMETHOD(fb_getinfo, diu_fb_getinfo),
453 { 0, 0 }
454 };
455
456 static driver_t diu_driver = {
457 "fb",
458 diu_methods,
459 sizeof(struct diu_softc),
460 };
461
462 DRIVER_MODULE(fb, simplebus, diu_driver, 0, 0);
463