1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at 9 * http://www.opensource.org/licenses/cddl1.txt. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2004-2011 Emulex. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _EMLXS_DFCLIB_H 28 #define _EMLXS_DFCLIB_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #define MAX_DFC_EVENTS 16 35 #define MAX_EMLXS_BRDS 128 36 #define MAX_CFG_PARAM 64 37 #define MAX_NODES 4096 38 39 #ifndef MAX_VPORTS 40 #define MAX_VPORTS 256 41 #endif /* MAX_VPORTS */ 42 43 #ifdef EMLXS_SPARC 44 #define EMLXS_BIG_ENDIAN 45 #endif /* EMLXS_SPARC */ 46 47 #ifdef EMLXS_I386 48 #define EMLXS_LITTLE_ENDIAN 49 #endif /* EMLXS_I386 */ 50 51 52 typedef struct brdinfo 53 { 54 uint32_t a_mem_hi; /* memory identifier for adapter access */ 55 uint32_t a_mem_low; /* memory identifier for adapter access */ 56 uint32_t a_flash_hi; /* memory identifier for adapter access */ 57 uint32_t a_flash_low; /* memory identifier for adapter access */ 58 uint32_t a_ctlreg_hi; /* memory identifier for adapter access */ 59 uint32_t a_ctlreg_low; /* memory identifier for adapter access */ 60 uint32_t a_intrlvl; /* interrupt level for adapter */ 61 uint32_t a_pci; /* PCI identifier (device / vendor id) */ 62 uint32_t a_busid; /* identifier of PCI bus adapter is on */ 63 uint32_t a_devid; /* identifier of PCI device number */ 64 uint8_t a_rsvd1; /* reserved for future use */ 65 uint8_t a_rsvd2; /* reserved for future use */ 66 uint8_t a_siglvl; /* signal handler used by library */ 67 uint8_t a_ddi; /* identifier device driver instance number */ 68 uint32_t a_onmask; /* mask of ONDI primatives supported */ 69 uint32_t a_offmask; /* mask of OFFDI primatives supported */ 70 uint8_t a_drvrid[16]; /* driver version */ 71 uint8_t a_fwname[32]; /* firmware version */ 72 } brdinfo_t; 73 74 75 typedef struct dfc_brdinfo 76 { 77 uint32_t a_mem_hi; /* memory identifier for adapter access */ 78 uint32_t a_mem_low; /* memory identifier for adapter access */ 79 uint32_t a_flash_hi; /* memory identifier for adapter access */ 80 uint32_t a_flash_low; /* memory identifier for adapter access */ 81 uint32_t a_ctlreg_hi; /* memory identifier for adapter access */ 82 uint32_t a_ctlreg_low; /* memory identifier for adapter access */ 83 uint32_t a_intrlvl; /* interrupt level for adapter */ 84 uint32_t a_pci; /* PCI identifier (device / vendor id) */ 85 uint32_t a_busid; /* identifier of PCI bus adapter is on */ 86 uint32_t a_devid; /* identifier of PCI device number */ 87 uint8_t a_pciFunc; /* identifier of PCI function number */ 88 uint8_t a_siglvl; /* signal handler used by library */ 89 uint16_t a_ddi; /* identifier device driver instance number */ 90 uint32_t a_onmask; /* mask of ONDI primatives supported */ 91 uint32_t a_offmask; /* mask of OFFDI primatives supported */ 92 uint8_t a_drvrid[16]; /* driver version */ 93 uint8_t a_fwname[32]; /* firmware version */ 94 uint8_t a_wwpn[8]; /* worldwide portname */ 95 } dfc_brdinfo_t; 96 97 98 #define PADDR_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xffffffff)) 99 #define PADDR_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32)) 100 #define PADDR(high, low) ((uint64_t)((((uint64_t)(high)) << 32) \ 101 | (((uint64_t)(low)) & 0xffffffff))) 102 103 typedef struct ulp_bde 104 { 105 uint32_t bdeAddress; 106 107 #ifdef EMLXS_BIG_ENDIAN 108 uint32_t bdeReserved:4; 109 uint32_t bdeAddrHigh:4; 110 uint32_t bdeSize:24; 111 #endif 112 #ifdef EMLXS_LITTLE_ENDIAN 113 uint32_t bdeSize:24; 114 uint32_t bdeAddrHigh:4; 115 uint32_t bdeReserved:4; 116 #endif 117 } ulp_bde_t; 118 119 typedef struct ulp_bde64 120 { 121 union 122 { 123 uint32_t w; 124 struct 125 { 126 #ifdef EMLXS_BIG_ENDIAN 127 uint32_t bdeFlags:8; 128 uint32_t bdeSize:24; 129 #endif 130 #ifdef EMLXS_LITTLE_ENDIAN 131 uint32_t bdeSize:24; 132 uint32_t bdeFlags:8; 133 #endif 134 135 #define BUFF_USE_RSVD 0x01 /* bdeFlags */ 136 #define BUFF_USE_INTRPT 0x02 /* Not Implemented with LP6000 */ 137 #define BUFF_USE_CMND 0x04 /* Optional, 1=cmd/rsp 0=data buffer */ 138 #define BUFF_USE_RCV 0x08 /* "" "", 1=rcv buffer, 0=xmit buffer */ 139 #define BUFF_TYPE_32BIT 0x10 /* "" "", 1=32 bit addr 0=64 bit addr */ 140 #define BUFF_TYPE_SPECIAL 0x20 /* Not Implemented with LP6000 */ 141 #define BUFF_TYPE_BDL 0x40 /* Optional, may be set in BDL */ 142 #define BUFF_TYPE_INVALID 0x80 /* "" "" */ 143 } f; 144 } tus; 145 146 uint32_t addrLow; 147 uint32_t addrHigh; 148 } ulp_bde64_t; 149 150 151 /* ==== Mailbox Commands ==== */ 152 #define MBX_SHUTDOWN 0x00 153 #define MBX_LOAD_SM 0x01 154 #define MBX_READ_NV 0x02 155 #define MBX_WRITE_NV 0x03 156 #define MBX_RUN_BIU_DIAG 0x04 157 #define MBX_INIT_LINK 0x05 158 #define MBX_DOWN_LINK 0x06 159 #define MBX_CONFIG_LINK 0x07 160 #define MBX_PART_SLIM 0x08 161 #define MBX_CONFIG_RING 0x09 162 #define MBX_RESET_RING 0x0A 163 #define MBX_READ_CONFIG 0x0B 164 #define MBX_READ_RCONFIG 0x0C 165 #define MBX_READ_SPARM 0x0D 166 #define MBX_READ_STATUS 0x0E 167 #define MBX_READ_RPI 0x0F 168 #define MBX_READ_XRI 0x10 169 #define MBX_READ_REV 0x11 170 #define MBX_READ_LNK_STAT 0x12 171 #define MBX_REG_LOGIN 0x13 172 #define MBX_UNREG_LOGIN 0x14 173 #define MBX_READ_LA 0x15 174 #define MBX_CLEAR_LA 0x16 175 #define MBX_DUMP_MEMORY 0x17 176 #define MBX_DUMP_CONTEXT 0x18 177 #define MBX_RUN_DIAGS 0x19 178 #define MBX_RESTART 0x1A 179 #define MBX_UPDATE_CFG 0x1B 180 #define MBX_DOWN_LOAD 0x1C 181 #define MBX_DEL_LD_ENTRY 0x1D 182 #define MBX_RUN_PROGRAM 0x1E 183 #define MBX_SET_MASK 0x20 184 #define MBX_SET_SLIM 0x21 185 #define MBX_UNREG_D_ID 0x23 186 #define MBX_KILL_BOARD 0x24 187 #define MBX_CONFIG_FARP 0x25 188 #define MBX_WRITE_VPARMS 0x32 189 #define MBX_LOAD_AREA 0x81 190 #define MBX_RUN_BIU_DIAG64 0x84 191 #define MBX_CONFIG_PORT 0x88 192 #define MBX_READ_SPARM64 0x8D 193 #define MBX_READ_RPI64 0x8F 194 #define MBX_CONFIG_MSI 0x90 195 #define MBX_REG_LOGIN64 0x93 196 #define MBX_READ_LA64 0x95 197 #define MBX_FLASH_WR_ULA 0x98 198 #define MBX_SET_DEBUG 0x99 199 #define MBX_SLI_CONFIG 0x9B 200 #define MBX_LOAD_EXP_ROM 0x9C 201 #define MBX_REQUEST_FEATURES 0x9D 202 #define MBX_RESUME_RPI 0x9E 203 #define MBX_REG_VFI 0x9F 204 #define MBX_REG_FCFI 0xA0 205 #define MBX_UNREG_VFI 0xA1 206 #define MBX_UNREG_FCFI 0xA2 207 #define MBX_INIT_VFI 0xA3 208 #define MBX_INIT_VPI 0xA4 209 #define MBX_ACCESS_VDATA 0xA5 210 #define MBX_MAX_CMDS 0xA6 211 #define MBX_SLI2_CMD_MASK 0x80 212 213 214 typedef struct read_sparm_var 215 { 216 uint32_t rsvd1; 217 uint32_t rsvd2; 218 union 219 { 220 ulp_bde_t sp; 221 ulp_bde64_t sp64; 222 } un; 223 } read_sparm_var_t; 224 225 226 typedef struct read_rev_var 227 { 228 #ifdef EMLXS_BIG_ENDIAN 229 uint32_t cv:1; 230 uint32_t rr:1; 231 uint32_t rsvd1:29; 232 uint32_t rv:1; 233 #endif 234 #ifdef EMLXS_LITTLE_ENDIAN 235 uint32_t rv:1; 236 uint32_t rsvd1:29; 237 uint32_t rr:1; 238 uint32_t cv:1; 239 #endif 240 uint32_t biuRev; 241 uint32_t smRev; 242 union 243 { 244 uint32_t smFwRev; 245 struct 246 { 247 #ifdef EMLXS_BIG_ENDIAN 248 uint8_t ProgType; 249 uint8_t ProgId; 250 uint16_t ProgVer:4; 251 uint16_t ProgRev:4; 252 uint16_t ProgFixLvl:2; 253 uint16_t ProgDistType:2; 254 uint16_t DistCnt:4; 255 #endif 256 #ifdef EMLXS_LITTLE_ENDIAN 257 uint16_t DistCnt:4; 258 uint16_t ProgDistType:2; 259 uint16_t ProgFixLvl:2; 260 uint16_t ProgRev:4; 261 uint16_t ProgVer:4; 262 uint8_t ProgId; 263 uint8_t ProgType; 264 #endif 265 } b; 266 } un; 267 uint32_t endecRev; 268 269 #ifdef EMLXS_BIG_ENDIAN 270 uint8_t feaLevelHigh; 271 uint8_t feaLevelLow; 272 uint8_t fcphHigh; 273 uint8_t fcphLow; 274 #endif 275 #ifdef EMLXS_LITTLE_ENDIAN 276 uint8_t fcphLow; 277 uint8_t fcphHigh; 278 uint8_t feaLevelLow; 279 uint8_t feaLevelHigh; 280 #endif 281 uint32_t postKernRev; 282 uint32_t opFwRev; 283 uint8_t opFwName[16]; 284 uint32_t sli1FwRev; 285 uint8_t sli1FwName[16]; 286 uint32_t sli2FwRev; 287 uint8_t sli2FwName[16]; 288 } read_rev_var_t; 289 290 291 typedef struct dump_var 292 { 293 #ifdef EMLXS_BIG_ENDIAN 294 uint32_t rsvd:25; 295 uint32_t ra:1; 296 uint32_t co:1; 297 uint32_t cv:1; 298 uint32_t type:4; 299 300 uint32_t entry_index:16; 301 uint32_t region_id:16; 302 #endif 303 #ifdef EMLXS_LITTLE_ENDIAN 304 uint32_t type:4; 305 uint32_t cv:1; 306 uint32_t co:1; 307 uint32_t ra:1; 308 uint32_t rsvd:25; 309 310 uint32_t region_id:16; 311 uint32_t entry_index:16; 312 #endif 313 uint32_t base_adr; 314 uint32_t word_cnt; 315 uint32_t resp_offset; 316 } dump_var_t; 317 318 319 typedef struct dump4_var 320 { 321 #ifdef EMLXS_BIG_ENDIAN 322 uint32_t link:8; 323 uint32_t rsvd:20; 324 uint32_t type:4; 325 326 uint32_t entry_index:16; 327 uint32_t region_id:16; 328 #endif 329 #ifdef EMLXS_LITTLE_ENDIAN 330 uint32_t type:4; 331 uint32_t rsvd:20; 332 uint32_t link:8; 333 334 uint32_t region_id:16; 335 uint32_t entry_index:16; 336 #endif 337 uint32_t available_cnt; 338 uint32_t addrLow; 339 uint32_t addrHigh; 340 uint32_t rsp_cnt; 341 } dump4_var_t; 342 343 344 typedef struct update_cfg 345 { 346 #ifdef EMLXS_BIG_ENDIAN 347 uint32_t rsvd2:16; 348 uint32_t proc_type:8; 349 uint32_t rsvd1:1; 350 uint32_t Abit:1; 351 uint32_t DIbit:1; 352 uint32_t Vbit:1; 353 uint32_t req_type:4; 354 #define INIT_REGION 1 355 #define UPDATE_DATA 2 356 #define CLEAN_UP_CFG 3 357 uint32_t entry_len:16; 358 uint32_t region_id:16; 359 #endif 360 361 #ifdef EMLXS_LITTLE_ENDIAN 362 uint32_t req_type:4; 363 #define INIT_REGION 1 364 #define UPDATE_DATA 2 365 #define CLEAN_UP_CFG 3 366 uint32_t Vbit:1; 367 uint32_t DIbit:1; 368 uint32_t Abit:1; 369 uint32_t rsvd1:1; 370 uint32_t proc_type:8; 371 uint32_t rsvd2:16; 372 373 uint32_t region_id:16; 374 uint32_t entry_len:16; 375 #endif 376 377 uint32_t rsp_info; 378 uint32_t byte_len; 379 uint32_t cfg_data; 380 } update_cfg_var_t; 381 382 383 384 typedef struct 385 { 386 union { 387 struct { 388 #ifdef EMLXS_BIG_ENDIAN 389 uint8_t domain; 390 uint8_t port_number; 391 uint8_t subsystem; 392 uint8_t opcode; 393 #else 394 uint8_t opcode; 395 uint8_t subsystem; 396 uint8_t port_number; 397 uint8_t domain; 398 #endif 399 uint32_t timeout; 400 uint32_t request_length; 401 uint32_t rsvd0; 402 }req; 403 404 struct { 405 #ifdef EMLXS_BIG_ENDIAN 406 /* dw 0 */ 407 uint8_t domain; 408 uint8_t rsvd0; 409 uint8_t subsystem; 410 uint8_t opcode; 411 412 /* dw 1 */ 413 uint16_t rsvd1; 414 uint8_t additional_status; 415 uint8_t status; 416 #else 417 /* dw 0 */ 418 uint8_t opcode; 419 uint8_t subsystem; 420 uint8_t rsvd0; 421 uint8_t domain; 422 423 /* dw 1 */ 424 uint8_t status; 425 uint8_t additional_status; 426 uint16_t rsvd1; 427 #endif 428 429 uint32_t rsp_length; 430 uint32_t actual_rsp_length; 431 }rsp; 432 uint32_t dw[4]; 433 }u0; 434 } common_hdr_t; 435 436 typedef struct get_oem_attrs 437 { 438 common_hdr_t hdr; 439 union { 440 struct { 441 uint32_t rsvd0; 442 }req; 443 444 struct { 445 uint8_t emulex_serial_number[12]; 446 uint8_t oem_serial_number[24]; 447 uint32_t oem_personality_mgmt_word; 448 #ifdef EMLXS_BIG_ENDIAN 449 uint8_t rsvd[3]; 450 uint8_t oem_current_personality; 451 #else 452 uint8_t oem_current_personality; 453 uint8_t rsvd[3]; 454 #endif 455 456 }rsp; 457 }params; 458 459 } get_oem_attrs_t; 460 461 462 typedef struct read_write_flashrom { 463 common_hdr_t hdr; 464 uint32_t flash_op_code; 465 uint32_t flash_op_type; 466 uint32_t data_buffer_size; 467 uint32_t data_offset; 468 uint8_t data_buffer[4]; 469 } read_write_flashrom_t; 470 471 472 typedef struct 473 { 474 #ifdef EMLXS_BIG_ENDIAN 475 uint32_t special:8; /* word 1 */ 476 uint32_t reserved2:16; /* word 1 */ 477 uint32_t sge_cnt:5; /* word 1 */ 478 uint32_t reserved1:2; /* word 1 */ 479 uint32_t embedded:1; /* word 1 */ 480 #endif 481 #ifdef EMLXS_LITTLE_ENDIAN 482 uint32_t embedded:1; /* word 1 */ 483 uint32_t reserved1:2; /* word 1 */ 484 uint32_t sge_cnt:5; /* word 1 */ 485 uint32_t reserved2:16; /* word 1 */ 486 uint32_t special:8; /* word 1 */ 487 #endif 488 uint32_t payload_length; /* word 2 */ 489 uint32_t tag_low; /* word 3 */ 490 uint32_t tag_hi; /* word 4 */ 491 uint32_t reserved3; /* word 5 */ 492 493 } be_req_header_t; 494 495 typedef struct 496 { 497 be_req_header_t be; 498 499 union 500 { 501 get_oem_attrs_t varOemAttrs; 502 read_write_flashrom_t varFlashRom; 503 } un; 504 505 } sli_config_var_t; 506 507 508 typedef struct read_cfg_var 509 { 510 #ifdef EMLXS_BIG_ENDIAN 511 uint32_t cr:1; 512 uint32_t ci:1; 513 uint32_t cr_delay:6; 514 uint32_t cr_count:8; 515 uint32_t InitBBC:8; 516 uint32_t MaxBBC:8; 517 #endif 518 #ifdef EMLXS_LITTLE_ENDIAN 519 uint32_t MaxBBC:8; 520 uint32_t InitBBC:8; 521 uint32_t cr_count:8; 522 uint32_t cr_delay:6; 523 uint32_t ci:1; 524 uint32_t cr:1; 525 #endif 526 #ifdef EMLXS_BIG_ENDIAN 527 uint32_t topology:8; 528 uint32_t myDid:24; 529 #endif 530 #ifdef EMLXS_LITTLE_ENDIAN 531 uint32_t myDid:24; 532 uint32_t topology:8; 533 #endif 534 /* Defines for topology (defined previously) */ 535 #ifdef EMLXS_BIG_ENDIAN 536 uint32_t AR:1; 537 uint32_t IR:1; 538 uint32_t rsvd1:29; 539 uint32_t ack0:1; 540 #endif 541 #ifdef EMLXS_LITTLE_ENDIAN 542 uint32_t ack0:1; 543 uint32_t rsvd1:29; 544 uint32_t IR:1; 545 uint32_t AR:1; 546 #endif 547 uint32_t edtov; 548 uint32_t arbtov; 549 uint32_t ratov; 550 uint32_t rttov; 551 uint32_t altov; 552 uint32_t lmt; 553 554 #define LMT_1GB_CAPABLE 0x0004 555 #define LMT_2GB_CAPABLE 0x0008 556 #define LMT_4GB_CAPABLE 0x0040 557 #define LMT_8GB_CAPABLE 0x0080 558 #define LMT_10GB_CAPABLE 0x0100 559 560 uint32_t rsvd2; 561 uint32_t rsvd3; 562 uint32_t max_xri; 563 uint32_t max_iocb; 564 uint32_t max_rpi; 565 uint32_t avail_xri; 566 uint32_t avail_iocb; 567 uint32_t avail_rpi; 568 uint32_t default_rpi; 569 } read_cfg_var_t; 570 571 572 typedef struct read_log_var 573 { 574 #ifdef EMLXS_BIG_ENDIAN 575 uint32_t type:8; 576 uint32_t byte_count:8; 577 uint32_t write:1; 578 uint32_t resv:3; 579 uint32_t offset:12; 580 #endif 581 #ifdef EMLXS_LITTLE_ENDIAN 582 uint32_t offset:12; 583 uint32_t resv:3; 584 uint32_t write:1; 585 uint32_t byte_count:8; 586 uint32_t type:8; 587 #endif 588 589 uint32_t data; 590 } read_log_var_t; 591 592 593 typedef struct log_status_var 594 { 595 596 #ifdef EMLXS_BIG_ENDIAN 597 uint16_t split_log_next; 598 uint16_t log_next; 599 600 uint32_t size; 601 602 uint32_t format:8; 603 uint32_t resv2:22; 604 uint32_t log_level:1; 605 uint32_t split_log:1; 606 #endif 607 #ifdef EMLXS_LITTLE_ENDIAN 608 uint16_t log_next; 609 uint16_t split_log_next; 610 611 uint32_t size; 612 613 uint32_t split_log:1; 614 uint32_t log_level:1; 615 uint32_t resv2:22; 616 uint32_t format:8; 617 #endif 618 619 uint32_t offset; 620 } log_status_var_t; 621 622 623 typedef struct read_evt_log_var 624 { 625 #ifdef EMLXS_BIG_ENDIAN 626 uint32_t read_log:1; 627 uint32_t clear_log:1; 628 uint32_t mbox_rsp:1; 629 uint32_t resv:28; 630 #endif 631 #ifdef EMLXS_LITTLE_ENDIAN 632 uint32_t resv:28; 633 uint32_t mbox_rsp:1; 634 uint32_t clear_log:1; 635 uint32_t read_log:1; 636 #endif 637 638 uint32_t offset; 639 640 union 641 { 642 ulp_bde_t sp; 643 ulp_bde64_t sp64; 644 } un; 645 } read_evt_log_var_t; 646 647 648 typedef struct dfc_mailbox 649 { 650 #ifdef EMLXS_BIG_ENDIAN 651 uint16_t mbxStatus; 652 uint8_t mbxCommand; 653 uint8_t mbxReserved:6; 654 uint8_t mbxHc:1; 655 uint8_t mbxOwner:1; /* Low order bit first word */ 656 #endif 657 #ifdef EMLXS_LITTLE_ENDIAN 658 uint8_t mbxOwner:1; /* Low order bit first word */ 659 uint8_t mbxHc:1; 660 uint8_t mbxReserved:6; 661 uint8_t mbxCommand; 662 uint16_t mbxStatus; 663 #endif 664 665 union 666 { 667 uint32_t varWords[31]; 668 read_sparm_var_t varRdSparm; 669 read_rev_var_t varRdRev; 670 read_cfg_var_t varRdCfg; 671 dump_var_t varDmp; 672 read_log_var_t varRdLog; 673 log_status_var_t varLogStat; 674 read_evt_log_var_t varRdEvtLog; 675 676 } un; 677 } dfc_mailbox_t; 678 679 680 typedef struct dfc_mailbox4 681 { 682 #ifdef EMLXS_BIG_ENDIAN 683 uint16_t mbxStatus; 684 uint8_t mbxCommand; 685 uint8_t mbxReserved:6; 686 uint8_t mbxHc:1; 687 uint8_t mbxOwner:1; /* Low order bit first word */ 688 #endif 689 #ifdef EMLXS_LITTLE_ENDIAN 690 uint8_t mbxOwner:1; /* Low order bit first word */ 691 uint8_t mbxHc:1; 692 uint8_t mbxReserved:6; 693 uint8_t mbxCommand; 694 uint16_t mbxStatus; 695 #endif 696 697 union 698 { 699 uint32_t varWords[63]; 700 dump4_var_t varDmp; 701 update_cfg_var_t varUpdateCfg; 702 sli_config_var_t varSLIConfig; 703 } un; 704 } dfc_mailbox4_t; 705 706 707 708 709 /* Config Region 23 Records */ 710 711 typedef struct tlv_fcoe { 712 uint8_t type; 713 uint8_t length; 714 uint8_t version; 715 #define TLV_FCOE_VER 1 716 717 uint8_t fip_flags; 718 #define TLV_FCOE_FIP 0x40 719 #define TLV_FCOE_VLAN 0x01 720 721 uint8_t FCMap[3]; 722 uint8_t reserved; 723 #ifdef EMLXS_BIG_ENDIAN 724 uint32_t rsvd:20; 725 uint32_t VLanId:12; 726 #endif 727 #ifdef EMLXS_LITTLE_ENDIAN 728 uint32_t VLanId:12; 729 uint32_t rsvd:20; 730 #endif 731 } tlv_fcoe_t; 732 733 734 typedef struct tlv_fcfconnectentry { 735 #ifdef EMLXS_BIG_ENDIAN 736 uint32_t rsvd1:4; 737 uint32_t VLanId:12; 738 uint32_t rsvd2:7; 739 uint32_t AddrMode:1; 740 uint32_t AddrModePreferred:1; 741 uint32_t AddrModeValid:1; 742 uint32_t VLanValid:1; 743 uint32_t SwitchNameValid:1; 744 uint32_t FabricNameValid:1; 745 uint32_t Primary:1; 746 uint32_t Boot:1; 747 uint32_t Valid:1; 748 #endif 749 #ifdef EMLXS_LITTLE_ENDIAN 750 uint32_t Valid:1; 751 uint32_t Boot:1; 752 uint32_t Primary:1; 753 uint32_t FabricNameValid:1; 754 uint32_t SwitchNameValid:1; 755 uint32_t VLanValid:1; 756 uint32_t AddrModeValid:1; 757 uint32_t AddrModePreferred:1; 758 uint32_t AddrMode:1; 759 uint32_t rsvd2:7; 760 uint32_t VLanId:12; 761 uint32_t rsvd1:4; 762 #endif 763 uint8_t FabricName[8]; 764 uint8_t SwitchName[8]; 765 } tlv_fcfconnectentry_t; 766 767 768 #define MAX_FCFCONNECTLIST_ENTRIES 16 769 typedef struct tlv_fcfconnectlist { 770 uint8_t type; 771 uint8_t length; 772 uint16_t rsvd; 773 tlv_fcfconnectentry_t entry[MAX_FCFCONNECTLIST_ENTRIES]; 774 } tlv_fcfconnectlist_t; 775 776 777 typedef struct dfc_ioinfo 778 { 779 uint32_t a_mboxCmd; /* mailbox commands issued */ 780 uint32_t a_mboxCmpl; /* mailbox commands completed */ 781 uint32_t a_mboxErr; /* mailbox commands completed, error status */ 782 uint32_t a_iocbCmd; /* iocb command ring issued */ 783 uint32_t a_iocbRsp; /* iocb rsp ring received */ 784 uint32_t a_adapterIntr; /* adapter interrupt events */ 785 uint32_t a_fcpCmd; /* FCP commands issued */ 786 uint32_t a_fcpCmpl; /* FCP command completions received */ 787 uint32_t a_fcpErr; /* FCP command completions errors */ 788 uint32_t a_seqXmit; /* IP xmit sequences sent */ 789 uint32_t a_seqRcv; /* IP sequences received */ 790 uint32_t a_bcastXmit; /* cnt of successful xmit bcast cmds issued */ 791 uint32_t a_bcastRcv; /* cnt of receive bcast cmds received */ 792 uint32_t a_elsXmit; /* cnt of successful ELS req cmds issued */ 793 uint32_t a_elsRcv; /* cnt of ELS request commands received */ 794 uint32_t a_RSCNRcv; /* cnt of RSCN commands received */ 795 uint32_t a_seqXmitErr; /* cnt of unsuccessful xmit bcast cmds issued */ 796 uint32_t a_elsXmitErr; /* cnt of unsuccessful ELS req cmds issued */ 797 uint32_t a_elsBufPost; /* cnt of ELS buffers posted to adapter */ 798 uint32_t a_ipBufPost; /* cnt of IP buffers posted to adapter */ 799 uint32_t a_cnt1; /* generic counter */ 800 uint32_t a_cnt2; /* generic counter */ 801 uint32_t a_cnt3; /* generic counter */ 802 uint32_t a_cnt4; /* generic counter */ 803 804 } dfc_ioinfo_t; 805 806 807 typedef struct dfc_linkinfo 808 { 809 uint32_t a_linkEventTag; 810 uint32_t a_linkUp; 811 uint32_t a_linkDown; 812 uint32_t a_linkMulti; 813 uint32_t a_DID; 814 uint8_t a_topology; 815 uint8_t a_linkState; 816 uint8_t a_alpa; 817 uint8_t a_alpaCnt; 818 uint8_t a_alpaMap[128]; 819 uint8_t a_wwpName[8]; 820 uint8_t a_wwnName[8]; 821 } dfc_linkinfo_t; 822 823 /* values for a_topology */ 824 #define LNK_LOOP 0x1 825 #define LNK_PUBLIC_LOOP 0x2 826 #define LNK_FABRIC 0x3 827 #define LNK_PT2PT 0x4 828 #define LNK_MENLO_MAINTENANCE 0x5 829 830 /* values for a_linkState */ 831 #define LNK_DOWN 0x1 832 #define LNK_UP 0x2 833 #define LNK_FLOGI 0x3 834 #define LNK_DISCOVERY 0x4 835 #define LNK_REDISCOVERY 0x5 836 #define LNK_READY 0x6 837 #define LNK_DOWN_PERSIST 0x7 838 839 840 typedef struct dfc_traceinfo 841 { 842 uint8_t a_event; 843 uint8_t a_cmd; 844 uint16_t a_status; 845 uint32_t a_information; 846 } dfc_traceinfo_t; 847 848 849 typedef struct dfc_cfgparam 850 { 851 char a_string[32]; 852 uint32_t a_low; 853 uint32_t a_hi; 854 uint32_t a_default; 855 uint32_t a_current; 856 uint16_t a_flag; 857 #define CFG_EXPORT 0x1 /* Export this parameter to end user */ 858 #define CFG_IGNORE 0x2 /* Ignore this parameter */ 859 #define CFG_APPLICABLE 0x4 /* Applicable to this HBA */ 860 #define CFG_COMMON 0x8 /* Common to all HBAs */ 861 862 uint16_t a_changestate; 863 #define CFG_REBOOT 0x0 /* Changes effective after system */ 864 /* reboot */ 865 #define CFG_DYMANIC 0x1 /* Changes effective immediately */ 866 #define CFG_RESTART 0x2 /* Changes effective after adapter */ 867 /* restart */ 868 #define CFG_LINKRESET 0x3 /* Changes effective after link reset */ 869 870 char a_help[80]; 871 } dfc_cfgparam_t; 872 873 874 875 typedef struct dfc_nodeinfo 876 { 877 uint16_t a_flag; 878 uint16_t a_state; 879 uint32_t a_did; 880 uint8_t a_wwpn[8]; 881 uint8_t a_wwnn[8]; 882 uint32_t a_targetid; 883 } dfc_nodeinfo_t; 884 885 /* Defines for a_state */ 886 #define NODE_UNUSED 0 /* unused NL_PORT entry */ 887 #define NODE_LIMBO 0x1 /* entry needs to hang around for wwpn / sid */ 888 #define NODE_LOGOUT 0x2 /* NL_PORT is not logged in - entry is cached */ 889 #define NODE_PLOGI 0x3 /* PLOGI was sent to NL_PORT */ 890 #define NODE_LOGIN 0x4 /* NL_PORT is logged in / login REG_LOGINed */ 891 #define NODE_PRLI 0x5 /* PRLI was sent to NL_PORT */ 892 #define NODE_ALLOC 0x6 /* NL_PORT is ready to initiate adapter I/O */ 893 #define NODE_SEED 0x7 /* seed scsi id bind in table */ 894 895 /* Defines for a_flag */ 896 #define NODE_RPI_XRI 0x1 /* creating xri for entry */ 897 #define NODE_REQ_SND 0x2 /* sent ELS request for this entry */ 898 #define NODE_ADDR_AUTH 0x4 /* Authenticating addr for this entry */ 899 #define NODE_RM_ENTRY 0x8 /* Remove this entry */ 900 #define NODE_FARP_SND 0x10 /* sent FARP request for this entry */ 901 #define NODE_FABRIC 0x20 /* this entry represents the Fabric */ 902 #define NODE_FCP_TARGET 0x40 /* this entry is an FCP target */ 903 #define NODE_IP_NODE 0x80 /* this entry is an IP node */ 904 #define NODE_DISC_START 0x100 /* start discovery on this entry */ 905 #define NODE_SEED_WWPN 0x200 /* Entry scsi id is seeded for WWPN */ 906 #define NODE_SEED_WWNN 0x400 /* Entry scsi id is seeded for WWNN */ 907 #define NODE_SEED_DID 0x800 /* Entry scsi id is seeded for DID */ 908 #define NODE_SEED_MASK 0xe00 /* mask for seeded flags */ 909 #define NODE_AUTOMAP 0x1000 /* This entry was automap'ed */ 910 #define NODE_NS_REMOVED 0x2000 /* This entry removed from NameServer */ 911 912 913 typedef struct dfc_vpd 914 { 915 uint32_t version; 916 #define DFC_VPD_VERSION 1 917 918 char ModelDescription[256]; /* VPD field V1 */ 919 char Model[80]; /* VPD field V2 */ 920 char ProgramType[256]; /* VPD field V3 */ 921 char PortNum[20]; /* VPD field V4 */ 922 } dfc_vpd_t; 923 924 typedef struct dfc_destid 925 { 926 uint32_t idType; /* 0 - wwpn, 1 - d_id */ 927 uint32_t d_id; 928 uint8_t wwpn[8]; 929 } dfc_destid_t; 930 931 932 typedef struct dfc_loopback 933 { 934 uint32_t bufSize; 935 uint8_t *XmitBuffer; 936 uint8_t *RcvBuffer; 937 } dfc_loopback_t; 938 939 940 typedef struct dfc_drvinfo 941 { 942 uint8_t drvInfoVer; /* Version of this structure */ 943 #define DFC_DRVINFO_VERSION2 0x02 944 #define DFC_DRVINFO_VERSION3 0x03 /* NPIV */ 945 #define DFC_DRVINFO_VERSION4 0x04 /* DHCHAP */ 946 #define DFC_DRVINFO_VERSION DFC_DRVINFO_VERSION3 947 948 #ifdef DHCHAP_SUPPORT 949 #undef DFC_DRVINFO_VERSION 950 #define DFC_DRVINFO_VERSION DFC_DRVINFO_VERSION4 951 #endif /* DHCHAP_SUPPORT */ 952 953 uint8_t drvType; 954 #define DFC_DRVINFO_SOLARIS 0x11 /* Solaris */ 955 #define DFC_DRVINFO_LEADVILLE 0x14 /* Solaris Leadville ULP */ 956 #define DFC_DRVINFO_COMSTAR 0x16 /* Solaris Comstar ULP */ 957 958 uint16_t reserved; 959 uint8_t rmLevel; /* Remote Management (HBAnyware) */ 960 /* Support Level */ 961 #define DFC_DRVINFO_RMLEVEL 0x02 /* HBAnyware v2.3 */ 962 963 uint8_t mpLevel; /* MultiPulse support Level */ 964 uint8_t hbaapiLevel; /* HBAAPI support level */ 965 #define DFC_DRVINFO_HBAAPI 0x01 /* HBAAPI v1.0 */ 966 967 uint8_t reserved1; 968 char drvVer[16]; /* Driver Version string */ 969 char drvName[8]; /* Driver Name */ 970 char ftrDrvVer[16]; /* Filter/IOCtl Driver Version string */ 971 char ftrDrvName[8]; /* Filter/IOCtl Driver Name */ 972 char ipDrvVer[16]; /* IP Driver/component Version string */ 973 char ipDrvName[8]; /* IP Driver/component Name */ 974 uint32_t d_id; 975 uint8_t wwpn[8]; 976 uint8_t wwnn[8]; 977 uint8_t hostname[32]; /* IP node hostname from uname -n */ 978 979 #if (DFC_DRVINFO_VERSION >= DFC_DRVINFO_VERSION3) 980 uint32_t NPIVsupport; 981 #define DFC_DRVINFO_NPIV_DRV 0x00000001 982 #define DFC_DRVINFO_NPIV_MODS 0x00000002 983 #define DFC_DRVINFO_NPIV_PARMS 0x00000004 984 #define DFC_DRVINFO_NPIV_FW 0x00000008 985 986 #endif /* >= DFC_DRVINFO_VERSION3 */ 987 988 #if (DFC_DRVINFO_VERSION >= DFC_DRVINFO_VERSION4) 989 uint32_t sliMode; 990 uint64_t featureList; 991 #define DFC_DRVINFO_FEATURE_DIAG 0x00000001 992 #define DFC_DRVINFO_FEATURE_MAPPING 0x00000002 993 #define DFC_DRVINFO_FEATURE_DHCHAP 0x00000004 994 #define DFC_DRVINFO_FEATURE_IKE 0x00000008 995 #define DFC_DRVINFO_FEATURE_NPIV 0x00000010 996 #define DFC_DRVINFO_FEATURE_RESET_WWN 0x00000020 997 #define DFC_DRVINFO_FEATURE_VOLATILE_WWN 0x00000040 998 #define DFC_DRVINFO_FEATURE_E2E_AUTH 0x00000080 999 #define DFC_DRVINFO_FEATURE_SAN_DIAG 0x00000100 1000 #define DFC_DRVINFO_FEATURE_FCOE 0x00000200 1001 #define DFC_DRVINFO_FEATURE_PERSISTLINK 0x00000400 1002 #define DFC_DRVINFO_FEATURE_TARGET_MODE 0x00000800 1003 #define DFC_DRVINFO_FEATURE_EXT_MBOX 0x00001000 1004 1005 #endif /* >= DFC_DRVINFO_VERSION4 */ 1006 } dfc_drvinfo_t; 1007 1008 1009 1010 typedef struct dfc_regevent 1011 { 1012 uint32_t ppid; 1013 uint32_t cpid; 1014 1015 uint32_t event; 1016 uint32_t type; 1017 uint32_t outsz; 1018 void *ctx; 1019 void (*func) (); 1020 1021 uint32_t cindex; /* Set only by child */ 1022 uint32_t state; /* Set only by child */ 1023 1024 /* state */ 1025 #define CHILD_UNKNOWN 0 1026 #define CHILD_UNBORN 1 1027 #define CHILD_ALIVE 2 1028 #define CHILD_REGISTERED 3 1029 #define CHILD_ASLEEP 4 1030 #define CHILD_AWAKE 5 1031 #define CHILD_DIED 6 1032 1033 uint32_t pindex; /* Set only by parent */ 1034 uint32_t flags; /* Set only by parent */ 1035 1036 /* flags */ 1037 #define EVENT_REGISTERED 0x01 1038 #define EVENT_SERVICE_ACTIVE 0x02 1039 1040 #ifdef SAN_DIAG_SUPPORT 1041 HBA_WWN portname; 1042 #endif /* SAN_DIAG_SUPPORT */ 1043 1044 pthread_t ptid; 1045 uint32_t board; 1046 1047 } dfc_regevent_t; 1048 1049 1050 /* Defines for RegisterForEvent mask */ 1051 #define FC_REG_LINK_EVENT 0x01 /* Register for link up/down */ 1052 /* events */ 1053 #define FC_REG_RSCN_EVENT 0x02 /* Register for RSCN events */ 1054 #define FC_REG_CT_EVENT 0x04 /* Register for CT request */ 1055 /* events */ 1056 #define FC_REG_MULTIPULSE_EVENT 0x08 /* Register for MultiPulse */ 1057 /* events */ 1058 #define FC_REG_DUMP_EVENT 0x10 /* Register for Diagnostic */ 1059 /* Dump events */ 1060 #define FC_REG_TEMP_EVENT 0x20 /* Register for Temperature */ 1061 /* events */ 1062 #define FC_REG_VPORTRSCN_EVENT 0x40 /* Register for VPort RSCN */ 1063 /* events */ 1064 #ifdef SAN_DIAG_SUPPORT 1065 #define FC_REG_SD_ELS_EVENT 0x1000 /* Register for SANDiag ELS */ 1066 /* events */ 1067 #define FC_REG_SD_FABRIC_EVENT 0x2000 /* Register for SANDiag */ 1068 /* Fabric events */ 1069 #define FC_REG_SD_SCSI_EVENT 0x4000 /* Register for SANDiag SCSI */ 1070 /* events */ 1071 #define FC_REG_SD_BOARD_EVENT 0x8000 /* Register for SANDiag Board */ 1072 /* events */ 1073 #endif /* SAN_DIAG_SUPPORT */ 1074 #define FC_REG_FCOE_EVENT 0x80000000 /* (Unofficial) Register for */ 1075 /* FCOE events */ 1076 1077 #define MAX_RSCN_PAYLOAD 1024 1078 #define MAX_CT_PAYLOAD (1024*320) 1079 1080 /* Temperature event types */ 1081 #define DFC_TEMP_CRITICAL 1 1082 #define DFC_TEMP_WARNING 2 1083 #define DFC_TEMP_SAFE 3 1084 1085 /* bits in a_onmask */ 1086 #define ONDI_MBOX 0x1 /* allows non-destructive mailbox */ 1087 /* commands */ 1088 #define ONDI_IOINFO 0x2 /* supports retrieval of I/O info */ 1089 #define ONDI_LNKINFO 0x4 /* supports retrieval of link info */ 1090 #define ONDI_NODEINFO 0x8 /* supports retrieval of node info */ 1091 #define ONDI_TRACEINFO 0x10 /* supports retrieval of trace info */ 1092 #define ONDI_SETTRACE 0x20 /* supports configuration of trace */ 1093 /* info */ 1094 #define ONDI_SLI1 0x40 /* hardware supports SLI-1 interface */ 1095 #define ONDI_SLI2 0x80 /* hardware supports SLI-2 interface */ 1096 #define ONDI_BIG_ENDIAN 0x100 /* DDI interface is BIG Endian */ 1097 #define ONDI_LTL_ENDIAN 0x200 /* DDI interface is LITTLE Endian */ 1098 #define ONDI_RMEM 0x400 /* allows reading of adapter shared */ 1099 /* memory */ 1100 #define ONDI_RFLASH 0x800 /* allows reading of adapter flash */ 1101 #define ONDI_RPCI 0x1000 /* allows reading of adapter pci */ 1102 /* registers */ 1103 #define ONDI_RCTLREG 0x2000 /* allows reading of adapter cntrol */ 1104 /* registers */ 1105 #define ONDI_CFGPARAM 0x4000 /* supports get/set configuration */ 1106 /* parameters */ 1107 #define ONDI_CT 0x8000 /* supports passthru CT interface */ 1108 #define ONDI_HBAAPI 0x10000 /* supports HBA API interface */ 1109 #define ONDI_SBUS 0x20000 /* supports SBUS adapter interface */ 1110 1111 /* bits in a_offmask */ 1112 #define OFFDI_MBOX 0x1 /* allows all mailbox commands */ 1113 #define OFFDI_RMEM 0x2 /* allows reading of adapter shared */ 1114 /* memory */ 1115 #define OFFDI_WMEM 0x4 /* allows writing of adapter shared */ 1116 /* memory */ 1117 #define OFFDI_RFLASH 0x8 /* allows reading of adapter flash */ 1118 #define OFFDI_WFLASH 0x10 /* allows writing of adapter flash */ 1119 #define OFFDI_RPCI 0x20 /* allows reading of adapter pci */ 1120 /* registers */ 1121 #define OFFDI_WPCI 0x40 /* allows writing of adapter pci */ 1122 /* registers */ 1123 #define OFFDI_RCTLREG 0x80 /* allows reading of adapter cntrol */ 1124 /* registers */ 1125 #define OFFDI_WCTLREG 0x100 /* allows writing of adapter cntrol */ 1126 /* registers */ 1127 #define OFFDI_OFFLINE 0x80000000 /* if set, adapter is in offline */ 1128 /* state */ 1129 1130 1131 #define DDI_SHOW 0x0 1132 #define DDI_ONDI 0x1 1133 #define DDI_OFFDI 0x2 1134 #define DDI_WARMDI 0x3 1135 #define DDI_DIAGDI 0x4 1136 1137 /* mbxStatus */ 1138 #define DFC_MBX_SUCCESS 0x00 1139 #define DFC_MBXERR_NUM_RINGS 0x01 1140 #define DFC_MBXERR_NUM_IOCBS 0x02 1141 #define DFC_MBXERR_IOCBS_EXCEEDED 0x03 1142 #define DFC_MBXERR_BAD_RING_NUMBER 0x04 1143 #define DFC_MBXERR_MASK_ENTRIES_RANGE 0x05 1144 #define DFC_MBXERR_MASKS_EXCEEDED 0x06 1145 #define DFC_MBXERR_BAD_PROFILE 0x07 1146 #define DFC_MBXERR_BAD_DEF_CLASS 0x08 1147 #define DFC_MBXERR_BAD_MAX_RESPONDER 0x09 1148 #define DFC_MBXERR_BAD_MAX_ORIGINATOR 0x0A 1149 #define DFC_MBXERR_RPI_REGISTERED 0x0B 1150 #define DFC_MBXERR_RPI_FULL 0x0C 1151 #define DFC_MBXERR_NO_RESOURCES 0x0D 1152 #define DFC_MBXERR_BAD_RCV_LENGTH 0x0E 1153 #define DFC_MBXERR_DMA_ERROR 0x0F 1154 #define DFC_MBXERR_ERROR 0x10 1155 1156 #define DFC_MBXERR_OVERTEMP_ERROR 0xFA 1157 #define DFC_MBXERR_HARDWARE_ERROR 0xFB 1158 #define DFC_MBXERR_DRVR_ERROR 0xFC 1159 #define DFC_MBXERR_BUSY 0xFD 1160 #define DFC_MBXERR_TIMEOUT 0xFE 1161 #define DFC_MBX_NOT_FINISHED 0xFF 1162 1163 1164 1165 /* Error codes for library calls */ 1166 #define DFC_ERR_GENERAL_ERROR 0x1 1167 1168 #define DFC_ERR_MBOX_ERROR 0x2 1169 #define DFC_ERR_LINK_DOWN 0x2 1170 #define DFC_ERR_INCORRECT_VER 0x2 1171 #define DFC_ERR_INVALID_ID 0x2 1172 #define DFC_ERR_TIMEOUT 0x2 1173 #define DFC_ERR_NOT_SUPPORTED 0x2 1174 #define DFC_ERR_NPIV_ACTIVE 0x2 1175 1176 #define DFC_ERR_NO_RPI 0x3 1177 #define DFC_ERR_BUFFER_OVERFLOW 0x3 1178 #define DFC_ERR_INVALID_LOOPBACK_TYPE 0x3 1179 #define DFC_ERR_OVERTEMP 0x3 1180 1181 #define DFC_ERR_LOOPBACK_BUSY 0x4 1182 #define DFC_ERR_INVALID_RESET_TYPE 0x4 1183 #define DFC_ERR_MENLO_LINKDOWN 0x4 1184 1185 #define DFC_ERR_SEQ_TIMEOUT 0x5 1186 1187 #define DFC_ERR_NO_XMIT 0x6 1188 #define DFC_ERR_INVALID_NUMBER 0x6 1189 1190 #define DFC_ERR_RESET_RECV 0x7 1191 1192 1193 1194 1195 /* type definitions for GetBindList function */ 1196 typedef enum dfc_bindtype 1197 { 1198 BIND_NONE, 1199 BIND_WWNN, 1200 BIND_WWPN, 1201 BIND_DID, 1202 BIND_ALPA 1203 } dfc_bindtype_t; 1204 1205 1206 typedef struct dfc_bind_entry 1207 { 1208 dfc_bindtype_t bind_type; 1209 uint32_t scsi_id; 1210 uint32_t did; 1211 uint8_t wwnn[8]; 1212 uint8_t wwpn[8]; 1213 uint32_t flags; 1214 1215 /* Bind Entry flags */ 1216 #define DFC_BIND_AUTOMAP 0x1 /* Node is automapped */ 1217 #define DFC_BIND_BINDLIST 0x2 /* entry in bind list not mapped */ 1218 #define DFC_BIND_MAPPED 0x4 /* Node is mapped to a scsiid */ 1219 #define DFC_BIND_UNMAPPED 0x8 /* Node is unmapped */ 1220 #define DFC_BIND_NODEVTMO 0x10 /* NODEVTMO flag of the node */ 1221 #define DFC_BIND_NOSCSIID 0x20 /* No scsi id is assigned yet */ 1222 #define DFC_BIND_RPTLUNST 0x40 /* Node is in report lun cmpl st */ 1223 } dfc_bind_entry_t; 1224 1225 typedef struct dfc_bind_list 1226 { 1227 uint32_t NumberOfEntries; 1228 dfc_bind_entry_t entry[1]; /* Variable length array */ 1229 } dfc_bind_list_t; 1230 1231 1232 1233 /* Defines for error codes -OLD- */ 1234 #define FC_ERROR_BUFFER_OVERFLOW 0xff 1235 #define FC_ERROR_RESPONSE_TIMEOUT 0xfe 1236 #define FC_ERROR_LINK_UNAVAILABLE 0xfd 1237 #define FC_ERROR_INSUFFICIENT_RESOURCES 0xfc 1238 #define FC_ERROR_EXISTING_REGISTRATION 0xfb 1239 #define FC_ERROR_INVALID_TAG 0xfa 1240 #define FC_ERROR_INVALID_WWN 0xf9 1241 #define FC_ERROR_CREATEVENT_FAILED 0xf8 1242 1243 1244 1245 typedef union dfc_ct_rev 1246 { 1247 /* Structure is in Big Endian format */ 1248 struct 1249 { 1250 uint32_t Revision:8; 1251 uint32_t InId:24; 1252 } bits; 1253 uint32_t word; 1254 } dfc_ct_rev_t; 1255 1256 typedef union dfc_ct_resp 1257 { 1258 /* Structure is in Big Endian format */ 1259 struct 1260 { 1261 uint32_t CmdRsp:16; 1262 uint32_t Size:16; 1263 } bits; 1264 uint32_t word; 1265 } dfc_ct_resp_t; 1266 1267 typedef struct dfc_ct_request 1268 { 1269 /* Structure is in Big Endian format */ 1270 dfc_ct_rev_t RevisionId; 1271 uint8_t FsType; 1272 uint8_t FsSubType; 1273 uint8_t Options; 1274 uint8_t Rsrvd1; 1275 dfc_ct_resp_t CommandResponse; 1276 uint8_t Rsrvd2; 1277 uint8_t ReasonCode; 1278 uint8_t Explanation; 1279 uint8_t VendorUnique; 1280 } dfc_ct_request_t; 1281 1282 #define SLI_CT_REVISION 1 1283 1284 #define FC_FSTYPE_ALL 0xffff /* match on all fsTypes */ 1285 1286 /* Emulex Vendor-Unique CT Request Command Codes */ 1287 #define CT_OP_GSAT 0x0101 /* Get Server Attributes */ 1288 #define CT_OP_GHAT 0x0102 /* Get HBA Attributes */ 1289 #define CT_OP_GPAT 0x0103 /* Get Port Attributes */ 1290 #define CT_OP_GDAT 0x0104 /* Get Driver Attributes */ 1291 #define CT_OP_GPST 0x0105 /* Get Port Statistics */ 1292 /* 0x0106 is reserved */ 1293 #define CT_OP_GDP 0x0107 /* Get Driver Parameters */ 1294 #define CT_OP_GDPG 0x0108 /* Get Driver Parameters Global */ 1295 #define CT_OP_GEPS 0x0109 /* Get Extended Port Statistics */ 1296 #define CT_OP_GLAT 0x010A /* Get Lun Attributes */ 1297 1298 #define CT_OP_SSAT 0x0111 /* Set Server Attributes */ 1299 #define CT_OP_SHAT 0x0112 /* Set HBA Attributes */ 1300 #define CT_OP_SPAT 0x0113 /* Set Port Attributes */ 1301 #define CT_OP_SDAT 0x0114 /* Set Driver Attributes */ 1302 /* 0x0115 is reserved */ 1303 /* 0x0116 is reserved */ 1304 #define CT_OP_SDP 0x0117 /* Set Driver Parameter */ 1305 #define CT_OP_SBBS 0x0118 /* Set Boot Bios State */ 1306 1307 #define CT_OP_RPST 0x0121 /* Reset Port Statistics */ 1308 #define CT_OP_VFW 0x0122 /* Verify Firmware */ 1309 #define CT_OP_DFW 0x0123 /* Download Firmware */ 1310 #define CT_OP_RES 0x0124 /* Reset HBA */ 1311 #define CT_OP_RHD 0x0125 /* Run HBA Diagnostic */ 1312 #define CT_OP_UFW 0x0126 /* Upgrade Firmware */ 1313 #define CT_OP_RDP 0x0127 /* Reset Driver Parameters */ 1314 #define CT_OP_GHDR 0x0128 /* Get HBA Diagnotic Results */ 1315 #define CT_OP_CHD 0x0129 /* Cancel HBA Diagnostic */ 1316 1317 /* 0x0131 is reserved */ 1318 /* 0x0132 is reserved */ 1319 #define CT_OP_SSR 0x0133 /* Send Software Resource */ 1320 1321 #define CT_OP_RSAT 0x0141 /* Read SA Table */ 1322 #define CT_OP_WSAT 0x0142 /* Write SA Table */ 1323 #define CT_OP_RSAH 0x0143 /* Read SA Table Header */ 1324 #define CT_OP_WSAH 0x0144 /* Write SA Table Header */ 1325 #define CT_OP_RACT 0x0145 /* Read Access Control Table */ 1326 #define CT_OP_WACT 0x0146 /* Write Access Control Table */ 1327 #define CT_OP_RKT 0x0147 /* Read Key Table Table */ 1328 #define CT_OP_WKT 0x0148 /* Write Key Table Table */ 1329 #define CT_OP_SSC 0x0149 /* Cause SA Table re-read;sync */ 1330 1331 #define CT_OP_QHBA 0x0151 /* Query HBA */ 1332 #define CT_OP_GST 0x0152 /* Get Status */ 1333 1334 #define CT_OP_GFTM 0x0161 /* Get FCP Target Mapping */ 1335 #define CT_OP_SRL 0x0162 /* SCSI Report Luns */ 1336 #define CT_OP_SI 0x0163 /* SCSI Inquiry */ 1337 #define CT_OP_SRC 0x0164 /* SCSI Read Capacity */ 1338 1339 #define CT_OP_GPB 0x0171 /* Get FCP Persistent Binding */ 1340 #define CT_OP_SPB 0x0172 /* Set FCP Persistent Binding */ 1341 #define CT_OP_RPB 0x0173 /* Remove FCP Persistent Binding */ 1342 #define CT_OP_RAPB 0x0174 /* Remove All FCP Persistent Bindings */ 1343 #define CT_OP_GBC 0x0175 /* Get Binding Capability */ 1344 #define CT_OP_GBS 0x0176 /* Get Binding Support */ 1345 #define CT_OP_SBS 0x0177 /* Set Binding Support */ 1346 #define CT_OP_GANI 0x0178 /* Get All Nodes Info */ 1347 #define CT_OP_GRV 0x0179 /* Get Range Value for Bus#, Target#, Lun# */ 1348 #define CT_OP_GAPBS 0x017A /* Get AutoPB service state */ 1349 /* (AutoPilotManager) */ 1350 #define CT_OP_APBC 0x017B /* Configure AutoPB service */ 1351 /* (AutoPilotManager) */ 1352 1353 #define CT_OP_GDT 0x0180 /* Get Driver Type */ 1354 #define CT_OP_GDLMI 0x0181 /* Get Drive Letter Mapping */ 1355 /* Information [GDLM] */ 1356 #define CT_OP_GANA 0x0182 /* Get All Node Addresses */ 1357 #define CT_OP_GDLV 0x0183 /* Get Driver Library Version */ 1358 #define CT_OP_GWUP 0x0184 /* Get Adapter Wakeup Parameters */ 1359 #define CT_OP_GLM 0x0185 /* Get Adapter Loopmap */ 1360 #define CT_OP_GABS 0x0186 /* Get Adapter Beacon State */ 1361 #define CT_OP_SABS 0x0187 /* Set Adapter Beacon State */ 1362 #define CT_OP_RPR 0x0188 /* Read Adapter PCI Registers */ 1363 1364 /* NPIV return codes */ 1365 #define DFC_NPIV_SUCCESS 0 1366 #define DFC_NPIV_GENERAL_ERROR 1 1367 #define DFC_NPIV_NOT_SUPPORTED 2 1368 #define DFC_NPIV_NO_RESOURCES 3 1369 #define DFC_NPIV_INVALID_HANDLE 3 1370 #define DFC_NPIV_ILLEGAL_WWPN 4 1371 #define DFC_NPIV_TOO_MANY_VPORTS 4 1372 #define DFC_NPIV_ILLEGAL_WWN 5 1373 #define DFC_NPIV_BUSY 5 1374 #define DFC_NPIV_INVALID_WWN 6 1375 #define DFC_NPIV_LINK_DOWN 7 1376 #define DFC_NPIV_MORE_DATA 7 1377 #define DFC_NPIV_FABRIC_NOT_SUPPORTED 8 1378 #define DFC_NPIV_FABRIC_OUT_OF_RESOURCE 9 1379 #define DFC_NPIV_INVALID_ACCESS_KEY 10 1380 #define DFC_NPIV_INVALID_HANDLE_AT_CREATE 11 1381 #define DFC_NPIV_UNSUPPORTED_OPTION 12 1382 1383 typedef struct dfc_vport_QoS 1384 { 1385 uint32_t resv; 1386 } dfc_vport_QoS_t; 1387 1388 1389 /* VPORT type */ 1390 #define VPORT_TYPE_PHYSICAL 0 1391 #define VPORT_TYPE_VIRTUAL 1 1392 1393 /* VPORT States */ 1394 #define VPORT_STATE_UNKNOWN 0 1395 #define VPORT_STATE_LINKDOWN 1 1396 #define VPORT_STATE_INIT 2 1397 #define VPORT_STATE_NO_FABRIC_SUPPORT 3 1398 #define VPORT_STATE_NO_FABRIC_RESOURCE 4 1399 #define VPORT_STATE_FABRIC_LOGOUT 5 1400 #define VPORT_STATE_FABRIC_REJECT_WWN 6 1401 #define VPORT_STATE_FABRIC_LOGIN_FAIL 7 1402 #define VPORT_STATE_ACTIVE 8 1403 #define VPORT_STATE_AUTH_FAILED 9 1404 1405 /* VPORT Options */ 1406 #define VPORT_OPT_AUTORETRY 0x00000001 1407 #define VPORT_OPT_AUTOWWN 0x00000002 1408 #define VPORT_OPT_ACTIVATE 0x00000004 1409 1410 #define VPORT_OPT_SAVE_CREATE_ONLY 0x00000000 1411 #define VPORT_OPT_SAVE_CREATE_UPDATE 0x00000010 1412 #define VPORT_OPT_SAVE_UPDATE_ONLY 0x00000018 1413 #define VPORT_OPT_SAVE_MASK 0x00000018 1414 1415 #define VPORT_OPT_RESTRICT 0x00000020 1416 #define VPORT_OPT_UNRESTRICT 0x00000040 1417 #define VPORT_OPT_RESTRICT_MASK 0x00000060 1418 1419 #define VPORT_OPT_FAILOVER 0x00000080 1420 1421 /* Check list bit-mapped value */ 1422 #define CL_NPIV_PARM_ENABLE 0x00000001 1423 #define CL_SLI3_ENABLE 0x00000002 1424 #define CL_HBA_SUPPORT_NPIV 0x00000004 1425 #define CL_HBA_HAS_RESOURCES 0x00000008 1426 #define CL_HBA_LINKUP 0x00000010 1427 #define CL_P2P_TOPOLOGY 0x00000020 1428 #define CL_FABRIC_SUPPORTS_NPIV 0x00000040 1429 #define CL_FABRIC_HAS_RESOURCES 0x00000080 1430 #define CL_NPIV_READY 0x000000FF 1431 1432 1433 1434 1435 #define DFC_VPORT_ATTR_VERSION 2 1436 typedef struct dfc_vport_attrs 1437 { 1438 uint8_t version; /* 2 = version of this structure, */ 1439 /* for compatibility check */ 1440 uint8_t reserved1[3]; 1441 1442 uint8_t wwpn[8]; /* virtual port WWPN */ 1443 uint8_t wwnn[8]; /* virtual port WWNN */ 1444 char name[256]; /* name to be register with the */ 1445 /* fabric */ 1446 1447 uint32_t options; 1448 1449 uint32_t portFcId; /* D-ID; set when the N-port is */ 1450 /* created successfully */ 1451 1452 uint8_t state; /* VPORT state */ 1453 uint8_t restrictLogin; 1454 uint8_t flags; 1455 uint8_t reserved2; 1456 uint64_t buf; /* Used for VPI */ 1457 1458 uint8_t fabric_wwn[8]; /* Fabric WWN (WWNN) */ 1459 uint32_t checklist; 1460 uint8_t accessKey[32]; 1461 } dfc_vport_attrs_t; 1462 1463 1464 typedef struct dfc_vport_entry 1465 { 1466 uint8_t wwpn[8]; /* wwpn of the virtual port */ 1467 uint8_t wwnn[8]; /* wwnn of the virtual port */ 1468 uint32_t PortFcId; /* FC port ID assigned to this */ 1469 /* virtual port */ 1470 } dfc_vport_entry_t; 1471 1472 1473 typedef struct dfc_vport_entry_list 1474 { 1475 uint32_t NumberOfEntries; 1476 dfc_vport_entry_t entry[MAX_VPORTS]; 1477 } dfc_vport_entry_list_t; 1478 1479 1480 typedef struct dfc_vport_nodeinfo_entry 1481 { 1482 uint32_t bind_type; 1483 #define VPORT_NODE_BINDDID 0x0000 1484 #define VPORT_NODE_BINDWWNN 0x0001 1485 #define VPORT_NODE_BINDWWPN 0x0002 1486 #define VPORT_NODE_AUTOMAP 0x0004 1487 #define VPORT_NODE_UNMASK_ALL_LUN 0x0008 1488 #define VPORT_NODE_DISABLE_LUN_AUTOMAP 0x0010 1489 #define VPORT_NODE_ALPA 0x0020 1490 1491 HBA_SCSIID scsiId; 1492 HBA_FCPID fcpId; 1493 1494 uint32_t nodeState; 1495 #define VPORT_NODESTATE_EXIST 0x0001 1496 #define VPORT_NODESTATE_READY 0x0002 1497 #define VPORT_NODESTATE_LINKDOWN 0x0004 1498 #define VPORT_NODESTATE_UNMAPPED 0x0008 1499 #define VPORT_NODESTATE_BOUND 0x0010 1500 1501 uint32_t reserved; 1502 } dfc_vport_nodeinfo_entry_t; 1503 1504 typedef struct dfc_vport_get_nodeinfo 1505 { 1506 uint32_t NumberOfEntries; /* number of nodes */ 1507 dfc_vport_nodeinfo_entry_t entry[MAX_NODES]; /* start of array */ 1508 } dfc_vport_get_nodeinfo_t; 1509 1510 1511 typedef struct dfc_vport_resource 1512 { 1513 uint32_t vpi_max; 1514 uint32_t vpi_inuse; 1515 uint32_t rpi_max; 1516 uint32_t rpi_inuse; 1517 } dfc_vport_resource_t; 1518 1519 1520 typedef struct dfc_vlinkinfo 1521 { 1522 uint32_t api_versions; 1523 1524 uint8_t linktype; 1525 uint8_t state; 1526 uint8_t fail_reason; 1527 uint8_t prev_fail_reason; 1528 #define VPORT_FAIL_UNKNOWN 0 1529 #define VPORT_FAIL_LINKDOWN 1 1530 #define VPORT_FAIL_FAB_UNSUPPORTED 2 1531 #define VPORT_FAIL_FAB_NORESOURCES 3 1532 #define VPORT_FAIL_FAB_LOGOUT 4 1533 #define VPORT_FAIL_HBA_NORESOURCES 5 1534 1535 uint8_t wwnn[8]; 1536 uint8_t wwpn[8]; 1537 1538 void *vlink; 1539 1540 uint32_t vpi_max; 1541 uint32_t vpi_inuse; 1542 uint32_t rpi_max; 1543 uint32_t rpi_inuse; 1544 } dfc_vlinkinfo_t; 1545 1546 1547 #ifdef DHCHAP_SUPPORT 1548 1549 /* DHCHAP return code */ 1550 #define DFC_AUTH_STATUS_NOT_CONFIGURED 0x8001 1551 #define DFC_AUTH_STATUS_AUTH_FAILED_NO_SA_FOUND 0x8002 1552 #define DFC_AUTH_STATUS_AUTH_INIT_OK_AUTH_FAILED 0x8003 1553 #define DFC_AUTH_STATUS_COMPARE_FAILED 0x8004 1554 #define DFC_AUTH_STATUS_WWN_NOT_FOUND 0x8005 1555 #define DFC_AUTH_STATUS_PASSWORD_INVALID 0x8006 1556 #define DFC_AUTH_STATUS_INVALID_ENTITY 0x8007 1557 #define DFC_AUTH_STATUS_ENTITY_NOT_ACTIVE 0x8008 1558 #define DFC_AUTH_STATUS_INVALID_OPERATION 0x8009 1559 #define DFC_AUTH_STATUS_OUT_OF_RESOURCES 0x800a 1560 #define DFC_AUTH_STATUS_AUTHENTICATION_GOINGON 0x800b 1561 #define DFC_AUTH_STATUS_INVALID_BOARD_NO 0x800c 1562 #define DFC_AUTH_STATUS_IO_ERROR 0x800d 1563 #define DFC_AUTH_STATUS_CREATE_STORKEY_ERROR 0x800e 1564 #define DFC_AUTH_STATUS_CREATE_PARMKEY_ERROR 0x800f 1565 #define DFC_AUTH_STATUS_CREATE_AUTHKEY_ERROR 0x8010 1566 #define DFC_AUTH_STATUS_LOCAL_REMOTE_PASSWORD_SAME 0x8011 1567 #define DFC_AUTH_STATUS_CREATE_BORDKEY_ERROR 0x8020 1568 #define DFC_AUTH_STATUS_DRVTYPE_NOT_SUPPORTED 0x8030 1569 #define DFC_AUTH_STATUS_AUTHENTICATION_NOT_SUPPORTED 0x8031 1570 #define DFC_AUTH_STATUS_GENERAL_ERROR 0x8032 1571 #define DFC_AUTH_STATUS_CONFIG_NOT_FOUND 0x8034 1572 #define DFC_AUTH_STATUS_NOT_PRIVILEGE_USER 0x8040 1573 1574 1575 typedef struct dfc_fcsp_config 1576 { 1577 HBA_WWN lwwpn; 1578 HBA_WWN rwwpn; 1579 1580 uint16_t auth_tov; /* seconds */ 1581 #define DFC_AUTH_TOV_MIN 20 1582 #define DFC_AUTH_TOV_MAX 1000 1583 #define DFC_AUTH_TOV_DEFAULT 45 1584 1585 uint8_t auth_mode; 1586 #define DFC_AUTH_MODE_DISABLED 1 1587 #define DFC_AUTH_MODE_ACTIVE 2 1588 #define DFC_AUTH_MODE_PASSIVE 3 1589 #define DFC_AUTH_MODE_DEFAULT DFC_AUTH_MODE_DISABLED 1590 1591 uint8_t auth_bidir:1; 1592 #define DFC_AUTH_BIDIR_DISABLED 0 1593 #define DFC_AUTH_BIDIR_ENABLED 1 1594 #define DFC_AUTH_BIDIR_DEFAULT DFC_AUTH_BIDIR_DISABLED 1595 uint8_t reserved:7; 1596 1597 uint8_t type_priority[4]; 1598 #define DFC_AUTH_TYPE_DHCHAP 1 /* Only one currently supported */ 1599 #define DFC_AUTH_TYPE_FCAP 2 1600 #define DFC_AUTH_TYPE_FCPAP 3 1601 #define DFC_AUTH_TYPE_KERBEROS 4 1602 #define DFC_AUTH_TYPE_MAX 4 1603 #define DFC_AUTH_TYPE_DEFAULT0 DFC_AUTH_TYPE_DHCHAP 1604 #define DFC_AUTH_TYPE_DEFAULT1 0 1605 #define DFC_AUTH_TYPE_DEFAULT2 0 1606 #define DFC_AUTH_TYPE_DEFAULT3 0 1607 1608 uint8_t hash_priority[4]; 1609 #define DFC_AUTH_HASH_MD5 1 1610 #define DFC_AUTH_HASH_SHA1 2 1611 #define DFC_AUTH_HASH_MAX 2 1612 #define DFC_AUTH_HASH_DEFAULT0 DFC_AUTH_HASH_MD5 1613 #define DFC_AUTH_HASH_DEFAULT1 DFC_AUTH_HASH_SHA1 1614 #define DFC_AUTH_HASH_DEFAULT2 0 1615 #define DFC_AUTH_HASH_DEFAULT3 0 1616 1617 uint8_t group_priority[8]; 1618 #define DFC_AUTH_GROUP_NULL 1 1619 #define DFC_AUTH_GROUP_1024 2 1620 #define DFC_AUTH_GROUP_1280 3 1621 #define DFC_AUTH_GROUP_1536 4 1622 #define DFC_AUTH_GROUP_2048 5 1623 #define DFC_AUTH_GROUP_MAX 5 1624 1625 #define DFC_AUTH_GROUP_DEFAULT0 DFC_AUTH_GROUP_NULL 1626 #define DFC_AUTH_GROUP_DEFAULT1 DFC_AUTH_GROUP_1024 1627 #define DFC_AUTH_GROUP_DEFAULT2 DFC_AUTH_GROUP_1280 1628 #define DFC_AUTH_GROUP_DEFAULT3 DFC_AUTH_GROUP_1536 1629 #define DFC_AUTH_GROUP_DEFAULT4 DFC_AUTH_GROUP_2048 1630 #define DFC_AUTH_GROUP_DEFAULT5 0 1631 #define DFC_AUTH_GROUP_DEFAULT6 0 1632 #define DFC_AUTH_GROUP_DEFAULT7 0 1633 1634 uint32_t reauth_tov; /* minutes */ 1635 #define DFC_REAUTH_TOV_MIN 0 1636 #define DFC_REAUTH_TOV_MAX 7200 1637 #define DFC_REAUTH_TOV_DEFAULT 1440 1638 } dfc_fcsp_config_t; 1639 1640 1641 typedef struct dfc_password 1642 { 1643 uint16_t length; 1644 #define DFC_PASSWORD_LENGTH_MIN 8 1645 #define DFC_PASSWORD_LENGTH_MAX 128 1646 1647 uint16_t type; 1648 #define DFC_PASSWORD_TYPE_ASCII 1 1649 #define DFC_PASSWORD_TYPE_BINARY 2 1650 #define DFC_PASSWORD_TYPE_IGNORE 3 1651 1652 uint8_t password[DFC_PASSWORD_LENGTH_MAX]; 1653 } dfc_password_t; 1654 1655 typedef struct dfc_auth_password 1656 { 1657 HBA_WWN lwwpn; 1658 HBA_WWN rwwpn; 1659 1660 dfc_password_t lpw; 1661 dfc_password_t rpw; 1662 1663 dfc_password_t lpw_new; 1664 dfc_password_t rpw_new; 1665 } dfc_auth_password_t; 1666 1667 1668 typedef struct dfc_auth_cfglist 1669 { 1670 uint32_t cnt; 1671 HBA_WWN rwwpn[1]; 1672 } dfc_auth_cfglist_t; 1673 1674 1675 typedef struct dfc_auth_status 1676 { 1677 HBA_WWN lwwpn; 1678 HBA_WWN rwwpn; 1679 1680 uint8_t auth_state; 1681 #define DFC_AUTH_STATE_OFF 1 1682 #define DFC_AUTH_STATE_INP 2 1683 #define DFC_AUTH_STATE_ON 3 1684 #define DFC_AUTH_STATE_FAILED 4 1685 1686 uint8_t auth_failReason; 1687 #define DFC_AUTH_FAIL_GENERIC 1 1688 #define DFC_AUTH_FAIL_ELS_TMO 2 1689 #define DFC_AUTH_FAIL_XACT_TMO 3 1690 #define DFC_AUTH_FAIL_LS_RJT 4 1691 #define DFC_AUTH_FAIL_BSY_LS_RJT 5 1692 #define DFC_AUTH_FAIL_REJECTED 6 1693 1694 uint8_t type_priority; 1695 uint8_t group_priority; 1696 1697 uint8_t hash_priority; 1698 uint8_t localAuth :1; 1699 uint8_t remoteAuth :1; 1700 uint8_t pad :6; 1701 uint16_t reserved0; 1702 1703 uint32_t time_from_last_auth; /* seconds */ 1704 uint32_t time_until_next_auth; /* seconds */ 1705 1706 uint32_t reserved1; 1707 uint32_t reserved2; 1708 } dfc_auth_status_t; 1709 1710 #endif /* DHCHAP_SUPPORT */ 1711 1712 /* 1713 * Start of FCP specific structures 1714 */ 1715 1716 #ifndef MAX_FCP_SNS 1717 typedef struct emlxs_fcp_rsp 1718 { 1719 uint32_t rspRsvd1; /* FC Word 0, byte 0:3 */ 1720 uint32_t rspRsvd2; /* FC Word 1, byte 0:3 */ 1721 1722 uint8_t rspStatus0; /* FCP_STATUS byte 0 (reserved) */ 1723 uint8_t rspStatus1; /* FCP_STATUS byte 1 (reserved) */ 1724 uint8_t rspStatus2; /* FCP_STATUS byte 2 field validity */ 1725 #define RSP_LEN_VALID 0x01 /* bit 0 */ 1726 #define SNS_LEN_VALID 0x02 /* bit 1 */ 1727 #define RESID_OVER 0x04 /* bit 2 */ 1728 #define RESID_UNDER 0x08 /* bit 3 */ 1729 uint8_t rspStatus3; /* FCP_STATUS byte 3 SCSI status byte */ 1730 #define SCSI_STAT_GOOD 0x00 1731 #define SCSI_STAT_CHECK_COND 0x02 1732 #define SCSI_STAT_COND_MET 0x04 1733 #define SCSI_STAT_BUSY 0x08 1734 #define SCSI_STAT_INTERMED 0x10 1735 #define SCSI_STAT_INTERMED_CM 0x14 1736 #define SCSI_STAT_RES_CNFLCT 0x18 1737 #define SCSI_STAT_CMD_TERM 0x22 1738 #define SCSI_STAT_QUE_FULL 0x28 1739 #define SCSI_STAT_ACA_ACTIVE 0x30 1740 #define SCSI_STAT_TASK_ABORT 0x40 1741 1742 uint32_t rspResId; /* Residual xfer if RESID_xxxx set in */ 1743 /* fcpStatus2 */ 1744 /* Received in Big Endian format */ 1745 uint32_t rspSnsLen; /* Length of sense data in fcpSnsInfo */ 1746 /* received in Big Endian format */ 1747 uint32_t rspRspLen; /* Length of FCP response data in */ 1748 /* fcpRspInfo */ 1749 /* Received In Big Endian format */ 1750 1751 uint8_t rspInfo0; /* FCP_RSP_INFO byte 0 (reserved) */ 1752 uint8_t rspInfo1; /* FCP_RSP_INFO byte 1 (reserved) */ 1753 uint8_t rspInfo2; /* FCP_RSP_INFO byte 2 (reserved) */ 1754 uint8_t rspInfo3; /* FCP_RSP_INFO RSP_CODE byte 3 */ 1755 1756 #define RSP_NO_FAILURE 0x00 1757 #define RSP_DATA_BURST_ERR 0x01 1758 #define RSP_CMD_FIELD_ERR 0x02 1759 #define RSP_RO_MISMATCH_ERR 0x03 1760 #define RSP_TM_NOT_SUPPORTED 0x04 /* Task mgmt function not supported */ 1761 #define RSP_TM_NOT_COMPLETED 0x05 /* Task mgmt function not performed */ 1762 1763 uint32_t rspInfoRsvd; /* FCP_RSP_INFO bytes 4-7 (reserved) */ 1764 1765 /* 1766 * Define maximum size of SCSI Sense buffer. 1767 * Seagate never issues more than 18 bytes of Sense data. 1768 */ 1769 #define MAX_FCP_SNS 128 1770 uint8_t rspSnsInfo[MAX_FCP_SNS]; 1771 } emlxs_fcp_rsp; 1772 typedef emlxs_fcp_rsp FCP_RSP; 1773 #endif /* MAX_FCP_SNS */ 1774 1775 1776 #ifndef FC_LUN_SHIFT 1777 typedef struct emlxs_fcp_cmd 1778 { 1779 uint32_t fcpLunMsl; /* most significant word (32 bits) */ 1780 uint32_t fcpLunLsl; /* least significant word (32 bits) */ 1781 1782 /* 1783 * # of bits to shift lun id to end up in right payload word, 1784 * little endian = 8, big = 16. 1785 */ 1786 #ifdef EMLXS_LITTLE_ENDIAN 1787 #define FC_LUN_SHIFT 8 1788 #define FC_ADDR_MODE_SHIFT 0 1789 #endif 1790 #ifdef EMLXS_BIG_ENDIAN 1791 #define FC_LUN_SHIFT 16 1792 #define FC_ADDR_MODE_SHIFT 24 1793 #endif 1794 1795 uint8_t fcpCntl0; /* FCP_CNTL byte 0 (reserved) */ 1796 uint8_t fcpCntl1; /* FCP_CNTL byte 1 task codes */ 1797 #define SIMPLE_Q 0x00 1798 #define HEAD_OF_Q 0x01 1799 #define ORDERED_Q 0x02 1800 #define ACA_Q 0x04 1801 #define UNTAGGED 0x05 1802 1803 uint8_t fcpCntl2; /* FCP_CTL byte 2 task management */ 1804 /* codes */ 1805 #define ABORT_TASK_SET 0x02 /* Bit 1 */ 1806 #define CLEAR_TASK_SET 0x04 /* bit 2 */ 1807 #define LUN_RESET 0x10 /* bit 4 */ 1808 #define TARGET_RESET 0x20 /* bit 5 */ 1809 #define CLEAR_ACA 0x40 /* bit 6 */ 1810 #define TERMINATE_TASK 0x80 /* bit 7 */ 1811 1812 uint8_t fcpCntl3; 1813 #define WRITE_DATA 0x01 /* Bit 0 */ 1814 #define READ_DATA 0x02 /* Bit 1 */ 1815 1816 uint8_t fcpCdb[16]; /* SRB cdb field is copied here */ 1817 uint32_t fcpDl; /* Total transfer length */ 1818 } emlxs_fcp_cmd_t; 1819 typedef emlxs_fcp_cmd_t FCP_CMND; 1820 #endif /* FC_LUN_SHIFT */ 1821 1822 1823 /* 1824 * Used by libdfc (SendScsiCmd, SendFcpCmd, DFC_SendScsiCmdV2, DFC_SendFcpCmdV2 1825 * and emlxs_dfc_send_scsi_fcp functions 1826 */ 1827 typedef struct dfc_send_scsi_fcp_cmd_info 1828 { 1829 HBA_WWN src_wwn; 1830 HBA_WWN dst_wwn; 1831 uint32_t cnt1; 1832 uint32_t cnt2; 1833 uint32_t ver; 1834 } dfc_send_scsi_fcp_cmd_info_t; 1835 1836 #define SCSI_RSP_CNT(x) x->cnt1 1837 #define SCSI_SNS_CNT(x) x->cnt2 1838 #define FC_DATA_CNT(x) x->cnt1 1839 #define FC_RSP_CNT(x) x->cnt2 1840 1841 #define DFC_SEND_SCSI_FCP_V1 1 1842 #define DFC_SEND_SCSI_FCP_V2 2 1843 1844 typedef struct DFC_FCoEParam 1845 { 1846 uint8_t version; 1847 #define DFC_FCoE_PARAM_VERSION 1 1848 1849 uint8_t Reserved[3]; 1850 uint8_t FCMap[3]; 1851 uint8_t VLanValid; 1852 #define VLAN_ID_INVALID 0x0 1853 #define VLAN_ID_VALID 0x1 1854 1855 uint16_t VLanId; 1856 } DFC_FCoEParam_t; 1857 1858 typedef struct DFC_FCoEFCFConnectEntry 1859 { 1860 uint16_t flags; 1861 #define FCFCNCT_RSVD 0x00000001 1862 #define FCFCNCT_BOOT 0x00000002 1863 #define FCFCNCT_PRIMARY 0x00000004 1864 #define FCFCNCT_FBNM_VALID 0x00000008 1865 #define FCFCNCT_SWNM_VALID 0x00000010 1866 #define FCFCNCT_VLAN_VALID 0x00000020 1867 #define FCFCNCT_MASK 0xFFFFFF00 1868 1869 uint16_t vlan_id; 1870 uint8_t fabric_name[8]; 1871 uint8_t switch_name[8]; 1872 uint8_t reserved[2]; 1873 } DFC_FCoEFCFConnectEntry_t; 1874 1875 typedef struct DFC_FCoEFCFConnectList 1876 { 1877 uint8_t version; 1878 #define DFC_FCoE_FCFCONNECTLIST_VERSION 1 1879 1880 uint8_t reserved; 1881 uint8_t numberOfEntries; 1882 uint8_t maxNumOfEntries; 1883 DFC_FCoEFCFConnectEntry_t entries[1]; 1884 } DFC_FCoEFCFConnectList_t; 1885 1886 typedef struct DFC_FCoEFCFInfo 1887 { 1888 uint8_t FabricName[8]; 1889 uint8_t SwitchName[8]; 1890 uint8_t Mac[6]; 1891 uint16_t State; 1892 #define FCF_AVAILABLE_STATE 0x1 1893 1894 uint8_t VLanBitMap[512]; 1895 uint8_t FC_Map[3]; 1896 uint8_t reserved1; 1897 uint32_t LKA_Period; 1898 uint32_t reserved2; 1899 uint32_t Priority; 1900 } DFC_FCoEFCFInfo_t; 1901 1902 typedef struct DFC_FCoEFCFList 1903 { 1904 uint8_t version; 1905 #define DFC_FCoE_FCFLIST_VERSION 1 1906 1907 uint8_t reserved[3]; 1908 uint16_t numberOfEntries; 1909 uint16_t nActiveFCFs; 1910 DFC_FCoEFCFInfo_t entries[1]; 1911 } DFC_FCoEFCFList_t; 1912 1913 #ifdef __cplusplus 1914 } 1915 #endif 1916 1917 #endif /* _EMLXS_DFCLIB_H */ 1918