1 /*- 2 * Data structures and definitions for CAM Control Blocks (CCBs). 3 * 4 * SPDX-License-Identifier: BSD-2-Clause 5 * 6 * Copyright (c) 1997, 1998 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #ifndef _CAM_CAM_CCB_H 32 #define _CAM_CAM_CCB_H 1 33 34 #include <sys/queue.h> 35 #include <sys/time.h> 36 #include <sys/limits.h> 37 #ifndef _KERNEL 38 #include <sys/callout.h> 39 #endif 40 #include <cam/cam_debug.h> 41 #include <cam/scsi/scsi_all.h> 42 #include <cam/ata/ata_all.h> 43 #include <cam/nvme/nvme_all.h> 44 #include <cam/mmc/mmc_all.h> 45 46 /* General allocation length definitions for CCB structures */ 47 #define IOCDBLEN CAM_MAX_CDBLEN /* Space for CDB bytes/pointer */ 48 #define VUHBALEN 14 /* Vendor Unique HBA length */ 49 #define SIM_IDLEN 16 /* ASCII string len for SIM ID */ 50 #define HBA_IDLEN 16 /* ASCII string len for HBA ID */ 51 #define DEV_IDLEN 16 /* ASCII string len for device names */ 52 #define CCB_PERIPH_PRIV_SIZE 2 /* size of peripheral private area */ 53 #define CCB_SIM_PRIV_SIZE 2 /* size of sim private area */ 54 55 /* Struct definitions for CAM control blocks */ 56 57 /* Common CCB header */ 58 59 /* CCB memory allocation flags */ 60 typedef enum { 61 CAM_CCB_FROM_UMA = 0x00000001,/* CCB from a periph UMA zone */ 62 } ccb_alloc_flags; 63 64 /* CAM CCB flags */ 65 typedef enum { 66 CAM_CDB_POINTER = 0x00000001,/* The CDB field is a pointer */ 67 CAM_unused1 = 0x00000002, 68 CAM_unused2 = 0x00000004, 69 CAM_NEGOTIATE = 0x00000008,/* 70 * Perform transport negotiation 71 * with this command. 72 */ 73 CAM_DATA_ISPHYS = 0x00000010,/* Data type with physical addrs */ 74 CAM_DIS_AUTOSENSE = 0x00000020,/* Disable autosense feature */ 75 CAM_DIR_BOTH = 0x00000000,/* Data direction (00:IN/OUT) */ 76 CAM_DIR_IN = 0x00000040,/* Data direction (01:DATA IN) */ 77 CAM_DIR_OUT = 0x00000080,/* Data direction (10:DATA OUT) */ 78 CAM_DIR_NONE = 0x000000C0,/* Data direction (11:no data) */ 79 CAM_DIR_MASK = 0x000000C0,/* Data direction Mask */ 80 CAM_DATA_VADDR = 0x00000000,/* Data type (000:Virtual) */ 81 CAM_DATA_PADDR = 0x00000010,/* Data type (001:Physical) */ 82 CAM_DATA_SG = 0x00040000,/* Data type (010:sglist) */ 83 CAM_DATA_SG_PADDR = 0x00040010,/* Data type (011:sglist phys) */ 84 CAM_DATA_BIO = 0x00200000,/* Data type (100:bio) */ 85 CAM_DATA_MASK = 0x00240010,/* Data type mask */ 86 CAM_unused3 = 0x00000100, 87 CAM_unused4 = 0x00000200, 88 CAM_DEV_QFRZDIS = 0x00000400,/* Disable DEV Q freezing */ 89 CAM_DEV_QFREEZE = 0x00000800,/* Freeze DEV Q on execution */ 90 CAM_HIGH_POWER = 0x00001000,/* Command takes a lot of power */ 91 CAM_SENSE_PTR = 0x00002000,/* Sense data is a pointer */ 92 CAM_SENSE_PHYS = 0x00004000,/* Sense pointer is physical addr*/ 93 CAM_TAG_ACTION_VALID = 0x00008000,/* Use the tag action in this ccb*/ 94 CAM_PASS_ERR_RECOVER = 0x00010000,/* Pass driver does err. recovery*/ 95 CAM_DIS_DISCONNECT = 0x00020000,/* Disable disconnect */ 96 CAM_unused5 = 0x00080000, 97 CAM_unused6 = 0x00100000, 98 CAM_CDB_PHYS = 0x00400000,/* CDB poiner is physical */ 99 CAM_unused7 = 0x00800000, 100 101 /* Phase cognizant mode flags */ 102 CAM_unused8 = 0x01000000, 103 CAM_unused9 = 0x02000000, 104 CAM_unused10 = 0x04000000, 105 CAM_unused11 = 0x08000000, 106 CAM_unused12 = 0x10000000, 107 CAM_unused13 = 0x20000000, 108 CAM_unused14 = 0x40000000, 109 110 /* Host target Mode flags */ 111 CAM_SEND_SENSE = 0x08000000,/* Send sense data with status */ 112 CAM_unused15 = 0x10000000, 113 CAM_unused16 = 0x20000000, 114 CAM_SEND_STATUS = 0x40000000,/* Send status after data phase */ 115 116 CAM_UNLOCKED = 0x80000000 /* Call callback without lock. */ 117 } ccb_flags; 118 119 typedef enum { 120 CAM_USER_DATA_ADDR = 0x00000002,/* Userspace data pointers */ 121 CAM_SG_FORMAT_IOVEC = 0x00000004,/* iovec instead of busdma S/G*/ 122 CAM_UNMAPPED_BUF = 0x00000008 /* use unmapped I/O */ 123 } ccb_xflags; 124 125 /* XPT Opcodes for xpt_action */ 126 typedef enum { 127 /* Function code flags are bits greater than 0xff */ 128 XPT_FC_QUEUED = 0x100, 129 /* Non-immediate function code */ 130 XPT_FC_USER_CCB = 0x200, 131 XPT_FC_XPT_ONLY = 0x400, 132 /* Only for the transport layer device */ 133 XPT_FC_DEV_QUEUED = 0x800 | XPT_FC_QUEUED, 134 /* Passes through the device queues */ 135 /* Common function commands: 0x00->0x0F */ 136 XPT_NOOP = 0x00, 137 /* Execute Nothing */ 138 XPT_SCSI_IO = 0x01 | XPT_FC_DEV_QUEUED, 139 /* Execute the requested I/O operation */ 140 XPT_GDEV_TYPE = 0x02, 141 /* Get type information for specified device */ 142 XPT_GDEVLIST = 0x03, 143 /* Get a list of peripheral devices */ 144 XPT_PATH_INQ = 0x04, 145 /* Path routing inquiry */ 146 XPT_REL_SIMQ = 0x05, 147 /* Release a frozen device queue */ 148 XPT_SASYNC_CB = 0x06, 149 /* Set Asynchronous Callback Parameters */ 150 XPT_SDEV_TYPE = 0x07, 151 /* Set device type information */ 152 XPT_SCAN_BUS = 0x08 | XPT_FC_QUEUED | XPT_FC_USER_CCB 153 | XPT_FC_XPT_ONLY, 154 /* (Re)Scan the SCSI Bus */ 155 XPT_DEV_MATCH = 0x09 | XPT_FC_XPT_ONLY, 156 /* Get EDT entries matching the given pattern */ 157 XPT_DEBUG = 0x0a, 158 /* Turn on debugging for a bus, target or lun */ 159 XPT_PATH_STATS = 0x0b, 160 /* Path statistics (error counts, etc.) */ 161 XPT_GDEV_STATS = 0x0c, 162 /* Device statistics (error counts, etc.) */ 163 164 /* 0x0d unused */ 165 XPT_DEV_ADVINFO = 0x0e, 166 /* Get/Set Device advanced information */ 167 XPT_ASYNC = 0x0f | XPT_FC_QUEUED | XPT_FC_USER_CCB 168 | XPT_FC_XPT_ONLY, 169 /* Asynchronous event */ 170 /* SCSI, NVME, and ATA Control Functions: 0x10->0x1F */ 171 XPT_ABORT = 0x10, 172 /* Abort the specified CCB */ 173 XPT_RESET_BUS = 0x11 | XPT_FC_XPT_ONLY, 174 /* Reset the specified SCSI bus */ 175 XPT_RESET_DEV = 0x12 | XPT_FC_DEV_QUEUED, 176 /* Bus Device Reset the specified SCSI device */ 177 XPT_TERM_IO = 0x13, 178 /* Terminate the I/O process */ 179 XPT_SCAN_LUN = 0x14 | XPT_FC_QUEUED | XPT_FC_USER_CCB 180 | XPT_FC_XPT_ONLY, 181 /* Scan Logical Unit */ 182 XPT_GET_TRAN_SETTINGS = 0x15, 183 /* 184 * Get default/user transfer settings 185 * for the target 186 */ 187 XPT_SET_TRAN_SETTINGS = 0x16, 188 /* 189 * Set transfer rate/width 190 * negotiation settings 191 */ 192 XPT_CALC_GEOMETRY = 0x17, 193 /* 194 * Calculate the geometry parameters for 195 * a device give the sector size and 196 * volume size. 197 */ 198 XPT_ATA_IO = 0x18 | XPT_FC_DEV_QUEUED, 199 /* Execute the requested ATA I/O operation */ 200 201 XPT_GET_SIM_KNOB_OLD = 0x18, /* Compat only */ 202 203 XPT_SET_SIM_KNOB = 0x19, 204 /* Set SIM specific knob values. */ 205 206 XPT_GET_SIM_KNOB = 0x1a, 207 /* Get SIM specific knob values. */ 208 209 XPT_SMP_IO = 0x1b | XPT_FC_DEV_QUEUED, 210 /* Serial Management Protocol */ 211 212 XPT_NVME_IO = 0x1c | XPT_FC_DEV_QUEUED, 213 /* Execute the requested NVMe I/O operation */ 214 215 XPT_MMC_IO = 0x1d | XPT_FC_DEV_QUEUED, 216 /* Placeholder for MMC / SD / SDIO I/O stuff */ 217 218 XPT_SCAN_TGT = 0x1e | XPT_FC_QUEUED | XPT_FC_USER_CCB 219 | XPT_FC_XPT_ONLY, 220 /* Scan Target */ 221 222 XPT_NVME_ADMIN = 0x1f | XPT_FC_DEV_QUEUED, 223 /* Execute the requested NVMe Admin operation */ 224 225 /* HBA engine commands 0x20->0x2F */ 226 XPT_ENG_INQ = 0x20 | XPT_FC_XPT_ONLY, 227 /* HBA engine feature inquiry */ 228 XPT_ENG_EXEC = 0x21 | XPT_FC_DEV_QUEUED, 229 /* HBA execute engine request */ 230 231 /* Target mode commands: 0x30->0x3F */ 232 XPT_EN_LUN = 0x30, 233 /* Enable LUN as a target */ 234 XPT_TARGET_IO = 0x31 | XPT_FC_DEV_QUEUED, 235 /* Execute target I/O request */ 236 XPT_ACCEPT_TARGET_IO = 0x32 | XPT_FC_QUEUED | XPT_FC_USER_CCB, 237 /* Accept Host Target Mode CDB */ 238 XPT_CONT_TARGET_IO = 0x33 | XPT_FC_DEV_QUEUED, 239 /* Continue Host Target I/O Connection */ 240 XPT_IMMED_NOTIFY = 0x34 | XPT_FC_QUEUED | XPT_FC_USER_CCB, 241 /* Notify Host Target driver of event (obsolete) */ 242 XPT_NOTIFY_ACK = 0x35, 243 /* Acknowledgement of event (obsolete) */ 244 XPT_IMMEDIATE_NOTIFY = 0x36 | XPT_FC_QUEUED | XPT_FC_USER_CCB, 245 /* Notify Host Target driver of event */ 246 XPT_NOTIFY_ACKNOWLEDGE = 0x37 | XPT_FC_QUEUED | XPT_FC_USER_CCB, 247 /* Acknowledgement of event */ 248 XPT_REPROBE_LUN = 0x38 | XPT_FC_QUEUED | XPT_FC_USER_CCB, 249 /* Query device capacity and notify GEOM */ 250 251 /* More common commands: 0x40-0x7f */ 252 XPT_MMC_SET_TRAN_SETTINGS = 0x40 | XPT_FC_DEV_QUEUED, 253 /* Queued MMC/SD set transmit settings */ 254 XPT_MMC_GET_TRAN_SETTINGS = 0x41 | XPT_FC_DEV_QUEUED, 255 /* Queued MMC/SD get transmit settings */ 256 257 /* Vendor Unique codes: 0x80->0x8F */ 258 XPT_VUNIQUE = 0x80 259 } xpt_opcode; 260 261 #define XPT_FC_GROUP_MASK 0xF0 262 #define XPT_FC_GROUP(op) ((op) & XPT_FC_GROUP_MASK) 263 #define XPT_FC_GROUP_COMMON 0x00 264 #define XPT_FC_GROUP_SCSI_CONTROL 0x10 265 #define XPT_FC_GROUP_HBA_ENGINE 0x20 266 #define XPT_FC_GROUP_TMODE 0x30 267 #define XPT_FC_GROUP_VENDOR_UNIQUE 0x80 268 269 #define XPT_FC_IS_DEV_QUEUED(ccb) \ 270 (((ccb)->ccb_h.func_code & XPT_FC_DEV_QUEUED) == XPT_FC_DEV_QUEUED) 271 #define XPT_FC_IS_QUEUED(ccb) \ 272 (((ccb)->ccb_h.func_code & XPT_FC_QUEUED) != 0) 273 274 typedef enum { 275 PROTO_UNKNOWN, 276 PROTO_UNSPECIFIED, 277 PROTO_SCSI, /* Small Computer System Interface */ 278 PROTO_ATA, /* AT Attachment */ 279 PROTO_ATAPI, /* AT Attachment Packetized Interface */ 280 PROTO_SATAPM, /* SATA Port Multiplier */ 281 PROTO_SEMB, /* SATA Enclosure Management Bridge */ 282 PROTO_NVME, /* NVME */ 283 PROTO_MMCSD, /* MMC, SD, SDIO */ 284 } cam_proto; 285 286 typedef enum { 287 XPORT_UNKNOWN, 288 XPORT_UNSPECIFIED, 289 XPORT_SPI, /* SCSI Parallel Interface */ 290 XPORT_FC, /* Fiber Channel */ 291 XPORT_SSA, /* Serial Storage Architecture */ 292 XPORT_USB, /* Universal Serial Bus */ 293 XPORT_PPB, /* Parallel Port Bus */ 294 XPORT_ATA, /* AT Attachment */ 295 XPORT_SAS, /* Serial Attached SCSI */ 296 XPORT_SATA, /* Serial AT Attachment */ 297 XPORT_ISCSI, /* iSCSI */ 298 XPORT_SRP, /* SCSI RDMA Protocol */ 299 XPORT_NVME, /* NVMe over PCIe */ 300 XPORT_MMCSD, /* MMC, SD, SDIO card */ 301 XPORT_NVMF, /* NVMe over Fabrics */ 302 XPORT_UFSHCI, /* Universal Flash Storage Host Interface */ 303 } cam_xport; 304 305 #define XPORT_IS_NVME(t) ((t) == XPORT_NVME || (t) == XPORT_NVMF) 306 #define XPORT_IS_ATA(t) ((t) == XPORT_ATA || (t) == XPORT_SATA) 307 #define XPORT_IS_SCSI(t) ((t) != XPORT_UNKNOWN && \ 308 (t) != XPORT_UNSPECIFIED && \ 309 !XPORT_IS_ATA(t) && !XPORT_IS_NVME(t)) 310 #define XPORT_DEVSTAT_TYPE(t) (XPORT_IS_ATA(t) ? DEVSTAT_TYPE_IF_IDE : \ 311 XPORT_IS_SCSI(t) ? DEVSTAT_TYPE_IF_SCSI : \ 312 XPORT_IS_NVME(t) ? DEVSTAT_TYPE_IF_NVME : \ 313 DEVSTAT_TYPE_IF_OTHER) 314 315 #define PROTO_VERSION_UNKNOWN (UINT_MAX - 1) 316 #define PROTO_VERSION_UNSPECIFIED UINT_MAX 317 #define XPORT_VERSION_UNKNOWN (UINT_MAX - 1) 318 #define XPORT_VERSION_UNSPECIFIED UINT_MAX 319 320 typedef union { 321 LIST_ENTRY(ccb_hdr) le; 322 SLIST_ENTRY(ccb_hdr) sle; 323 TAILQ_ENTRY(ccb_hdr) tqe; 324 STAILQ_ENTRY(ccb_hdr) stqe; 325 } camq_entry; 326 327 typedef union { 328 void *ptr; 329 u_long field; 330 uint8_t bytes[sizeof(uintptr_t)]; 331 } ccb_priv_entry; 332 333 typedef union { 334 ccb_priv_entry entries[CCB_PERIPH_PRIV_SIZE]; 335 uint8_t bytes[CCB_PERIPH_PRIV_SIZE * sizeof(ccb_priv_entry)]; 336 } ccb_ppriv_area; 337 338 typedef union { 339 ccb_priv_entry entries[CCB_SIM_PRIV_SIZE]; 340 uint8_t bytes[CCB_SIM_PRIV_SIZE * sizeof(ccb_priv_entry)]; 341 } ccb_spriv_area; 342 343 typedef struct { 344 struct timeval *etime; 345 uintptr_t sim_data; 346 uintptr_t periph_data; 347 } ccb_qos_area; 348 349 struct ccb_hdr { 350 cam_pinfo pinfo; /* Info for priority scheduling */ 351 camq_entry xpt_links; /* For chaining in the XPT layer */ 352 camq_entry sim_links; /* For chaining in the SIM layer */ 353 camq_entry periph_links; /* For chaining in the type driver */ 354 #if BYTE_ORDER == LITTLE_ENDIAN 355 uint16_t retry_count; 356 uint16_t alloc_flags; /* ccb_alloc_flags */ 357 #else 358 uint16_t alloc_flags; /* ccb_alloc_flags */ 359 uint16_t retry_count; 360 #endif 361 void (*cbfcnp)(struct cam_periph *, union ccb *); 362 /* Callback on completion function */ 363 xpt_opcode func_code; /* XPT function code */ 364 uint32_t status; /* Status returned by CAM subsystem */ 365 struct cam_path *path; /* Compiled path for this ccb */ 366 path_id_t path_id; /* Path ID for the request */ 367 target_id_t target_id; /* Target device ID */ 368 lun_id_t target_lun; /* Target LUN number */ 369 uint32_t flags; /* ccb_flags */ 370 uint32_t xflags; /* Extended flags */ 371 ccb_ppriv_area periph_priv; 372 ccb_spriv_area sim_priv; 373 ccb_qos_area qos; 374 uint32_t timeout; /* Hard timeout value in mseconds */ 375 struct timeval softtimeout; /* Soft timeout value in sec + usec */ 376 }; 377 378 /* Get Device Information CCB */ 379 struct ccb_getdev { 380 struct ccb_hdr ccb_h; 381 cam_proto protocol; 382 struct scsi_inquiry_data inq_data; 383 struct ata_params ident_data; 384 uint8_t serial_num[252]; 385 uint8_t inq_flags; 386 uint8_t serial_num_len; 387 void *padding[2]; 388 }; 389 390 /* Device Statistics CCB */ 391 struct ccb_getdevstats { 392 struct ccb_hdr ccb_h; 393 int dev_openings; /* Space left for more work on device*/ 394 int dev_active; /* Transactions running on the device */ 395 int allocated; /* CCBs allocated for the device */ 396 int queued; /* CCBs queued to be sent to the device */ 397 int held; /* 398 * CCBs held by peripheral drivers 399 * for this device 400 */ 401 int maxtags; /* 402 * Boundary conditions for number of 403 * tagged operations 404 */ 405 int mintags; 406 struct timeval last_reset; /* Time of last bus reset/loop init */ 407 }; 408 409 typedef enum { 410 CAM_GDEVLIST_LAST_DEVICE, 411 CAM_GDEVLIST_LIST_CHANGED, 412 CAM_GDEVLIST_MORE_DEVS, 413 CAM_GDEVLIST_ERROR 414 } ccb_getdevlist_status_e; 415 416 struct ccb_getdevlist { 417 struct ccb_hdr ccb_h; 418 char periph_name[DEV_IDLEN]; 419 uint32_t unit_number; 420 unsigned int generation; 421 uint32_t index; 422 ccb_getdevlist_status_e status; 423 }; 424 425 typedef enum { 426 PERIPH_MATCH_ANY = 0x000, 427 PERIPH_MATCH_PATH = 0x001, 428 PERIPH_MATCH_TARGET = 0x002, 429 PERIPH_MATCH_LUN = 0x004, 430 PERIPH_MATCH_NAME = 0x008, 431 PERIPH_MATCH_UNIT = 0x010, 432 } periph_pattern_flags; 433 434 struct periph_match_pattern { 435 char periph_name[DEV_IDLEN]; 436 uint32_t unit_number; 437 path_id_t path_id; 438 target_id_t target_id; 439 lun_id_t target_lun; 440 periph_pattern_flags flags; 441 }; 442 443 typedef enum { 444 DEV_MATCH_ANY = 0x000, 445 DEV_MATCH_PATH = 0x001, 446 DEV_MATCH_TARGET = 0x002, 447 DEV_MATCH_LUN = 0x004, 448 DEV_MATCH_INQUIRY = 0x008, 449 DEV_MATCH_DEVID = 0x010, 450 } dev_pattern_flags; 451 452 struct device_id_match_pattern { 453 uint8_t id_len; 454 uint8_t id[256]; 455 }; 456 457 struct device_match_pattern { 458 path_id_t path_id; 459 target_id_t target_id; 460 lun_id_t target_lun; 461 dev_pattern_flags flags; 462 union { 463 struct scsi_static_inquiry_pattern inq_pat; 464 struct device_id_match_pattern devid_pat; 465 } data; 466 }; 467 468 typedef enum { 469 BUS_MATCH_ANY = 0x000, 470 BUS_MATCH_PATH = 0x001, 471 BUS_MATCH_NAME = 0x002, 472 BUS_MATCH_UNIT = 0x004, 473 BUS_MATCH_BUS_ID = 0x008, 474 } bus_pattern_flags; 475 476 struct bus_match_pattern { 477 path_id_t path_id; 478 char dev_name[DEV_IDLEN]; 479 uint32_t unit_number; 480 uint32_t bus_id; 481 bus_pattern_flags flags; 482 }; 483 484 union match_pattern { 485 struct periph_match_pattern periph_pattern; 486 struct device_match_pattern device_pattern; 487 struct bus_match_pattern bus_pattern; 488 }; 489 490 typedef enum { 491 DEV_MATCH_PERIPH, 492 DEV_MATCH_DEVICE, 493 DEV_MATCH_BUS 494 } dev_match_type; 495 496 struct dev_match_pattern { 497 dev_match_type type; 498 union match_pattern pattern; 499 }; 500 501 struct periph_match_result { 502 char periph_name[DEV_IDLEN]; 503 uint32_t unit_number; 504 path_id_t path_id; 505 target_id_t target_id; 506 lun_id_t target_lun; 507 }; 508 509 typedef enum { 510 DEV_RESULT_NOFLAG = 0x00, 511 DEV_RESULT_UNCONFIGURED = 0x01 512 } dev_result_flags; 513 514 struct device_match_result { 515 path_id_t path_id; 516 target_id_t target_id; 517 lun_id_t target_lun; 518 cam_proto protocol; 519 struct scsi_inquiry_data inq_data; 520 struct ata_params ident_data; 521 dev_result_flags flags; 522 }; 523 524 struct bus_match_result { 525 path_id_t path_id; 526 char dev_name[DEV_IDLEN]; 527 uint32_t unit_number; 528 uint32_t bus_id; 529 }; 530 531 union match_result { 532 struct periph_match_result periph_result; 533 struct device_match_result device_result; 534 struct bus_match_result bus_result; 535 }; 536 537 struct dev_match_result { 538 dev_match_type type; 539 union match_result result; 540 }; 541 542 typedef enum { 543 CAM_DEV_MATCH_LAST, 544 CAM_DEV_MATCH_MORE, 545 CAM_DEV_MATCH_LIST_CHANGED, 546 CAM_DEV_MATCH_SIZE_ERROR, 547 CAM_DEV_MATCH_ERROR 548 } ccb_dev_match_status; 549 550 typedef enum { 551 CAM_DEV_POS_NONE = 0x000, 552 CAM_DEV_POS_BUS = 0x001, 553 CAM_DEV_POS_TARGET = 0x002, 554 CAM_DEV_POS_DEVICE = 0x004, 555 CAM_DEV_POS_PERIPH = 0x008, 556 CAM_DEV_POS_PDPTR = 0x010, 557 CAM_DEV_POS_TYPEMASK = 0xf00, 558 CAM_DEV_POS_EDT = 0x100, 559 CAM_DEV_POS_PDRV = 0x200 560 } dev_pos_type; 561 562 struct ccb_dm_cookie { 563 void *bus; 564 void *target; 565 void *device; 566 void *periph; 567 void *pdrv; 568 }; 569 570 struct ccb_dev_position { 571 u_int generations[4]; 572 #define CAM_BUS_GENERATION 0x00 573 #define CAM_TARGET_GENERATION 0x01 574 #define CAM_DEV_GENERATION 0x02 575 #define CAM_PERIPH_GENERATION 0x03 576 dev_pos_type position_type; 577 struct ccb_dm_cookie cookie; 578 }; 579 580 struct ccb_dev_match { 581 struct ccb_hdr ccb_h; 582 ccb_dev_match_status status; 583 uint32_t num_patterns; 584 uint32_t pattern_buf_len; 585 struct dev_match_pattern *patterns; 586 uint32_t num_matches; 587 uint32_t match_buf_len; 588 struct dev_match_result *matches; 589 struct ccb_dev_position pos; 590 }; 591 592 /* 593 * Definitions for the path inquiry CCB fields. 594 */ 595 #define CAM_VERSION 0x1a /* Hex value for current version */ 596 597 typedef enum { 598 PI_MDP_ABLE = 0x80, /* Supports MDP message */ 599 PI_WIDE_32 = 0x40, /* Supports 32 bit wide SCSI */ 600 PI_WIDE_16 = 0x20, /* Supports 16 bit wide SCSI */ 601 PI_SDTR_ABLE = 0x10, /* Supports SDTR message */ 602 PI_LINKED_CDB = 0x08, /* Supports linked CDBs */ 603 PI_SATAPM = 0x04, /* Supports SATA PM */ 604 PI_TAG_ABLE = 0x02, /* Supports tag queue messages */ 605 PI_SOFT_RST = 0x01 /* Supports soft reset alternative */ 606 } pi_inqflag; 607 608 typedef enum { 609 PIT_PROCESSOR = 0x80, /* Target mode processor mode */ 610 PIT_PHASE = 0x40, /* Target mode phase cog. mode */ 611 PIT_DISCONNECT = 0x20, /* Disconnects supported in target mode */ 612 PIT_TERM_IO = 0x10, /* Terminate I/O message supported in TM */ 613 PIT_GRP_6 = 0x08, /* Group 6 commands supported */ 614 PIT_GRP_7 = 0x04 /* Group 7 commands supported */ 615 } pi_tmflag; 616 617 typedef enum { 618 PIM_WLUNS = 0x400,/* Well known LUNs supported */ 619 PIM_ATA_EXT = 0x200,/* ATA requests can understand ata_ext requests */ 620 PIM_EXTLUNS = 0x100,/* 64bit extended LUNs supported */ 621 PIM_SCANHILO = 0x80, /* Bus scans from high ID to low ID */ 622 PIM_NOREMOVE = 0x40, /* Removeable devices not included in scan */ 623 PIM_NOINITIATOR = 0x20, /* Initiator role not supported. */ 624 PIM_NOBUSRESET = 0x10, /* User has disabled initial BUS RESET */ 625 PIM_NO_6_BYTE = 0x08, /* Do not send 6-byte commands */ 626 PIM_SEQSCAN = 0x04, /* Do bus scans sequentially, not in parallel */ 627 PIM_UNMAPPED = 0x02, 628 PIM_NOSCAN = 0x01 /* SIM does its own scanning */ 629 } pi_miscflag; 630 631 /* Path Inquiry CCB */ 632 struct ccb_pathinq_settings_spi { 633 uint8_t ppr_options; 634 }; 635 636 struct ccb_pathinq_settings_fc { 637 uint64_t wwnn; /* world wide node name */ 638 uint64_t wwpn; /* world wide port name */ 639 uint32_t port; /* 24 bit port id, if known */ 640 uint32_t bitrate; /* Mbps */ 641 }; 642 643 struct ccb_pathinq_settings_sas { 644 uint32_t bitrate; /* Mbps */ 645 }; 646 647 #define NVME_DEV_NAME_LEN 52 648 struct ccb_pathinq_settings_nvme { 649 uint32_t nsid; /* Namespace ID for this path */ 650 uint32_t domain; 651 uint8_t bus; 652 uint8_t slot; 653 uint8_t function; 654 uint8_t extra; 655 char dev_name[NVME_DEV_NAME_LEN]; /* nvme controller dev name for this device */ 656 }; 657 _Static_assert(sizeof(struct ccb_pathinq_settings_nvme) == 64, 658 "ccb_pathinq_settings_nvme too big"); 659 660 struct ccb_pathinq_settings_nvmf { 661 uint32_t nsid; /* Namespace ID for this path */ 662 uint8_t trtype; 663 char dev_name[NVME_DEV_NAME_LEN]; /* nvme controller dev name for this device */ 664 }; 665 666 #define PATHINQ_SETTINGS_SIZE 128 667 668 struct ccb_pathinq { 669 struct ccb_hdr ccb_h; 670 uint8_t version_num; /* Version number for the SIM/HBA */ 671 uint8_t hba_inquiry; /* Mimic of INQ byte 7 for the HBA */ 672 uint16_t target_sprt; /* Flags for target mode support */ 673 uint32_t hba_misc; /* Misc HBA features */ 674 uint16_t hba_eng_cnt; /* HBA engine count */ 675 /* Vendor Unique capabilities */ 676 uint8_t vuhba_flags[VUHBALEN]; 677 uint32_t max_target; /* Maximum supported Target */ 678 uint32_t max_lun; /* Maximum supported Lun */ 679 uint32_t async_flags; /* Installed Async handlers */ 680 path_id_t hpath_id; /* Highest Path ID in the subsystem */ 681 target_id_t initiator_id; /* ID of the HBA on the SCSI bus */ 682 char sim_vid[SIM_IDLEN]; /* Vendor ID of the SIM */ 683 char hba_vid[HBA_IDLEN]; /* Vendor ID of the HBA */ 684 char dev_name[DEV_IDLEN];/* Device name for SIM */ 685 uint32_t unit_number; /* Unit number for SIM */ 686 uint32_t bus_id; /* Bus ID for SIM */ 687 uint32_t base_transfer_speed;/* Base bus speed in KB/sec */ 688 cam_proto protocol; 689 u_int protocol_version; 690 cam_xport transport; 691 u_int transport_version; 692 union { 693 struct ccb_pathinq_settings_spi spi; 694 struct ccb_pathinq_settings_fc fc; 695 struct ccb_pathinq_settings_sas sas; 696 struct ccb_pathinq_settings_nvme nvme; 697 struct ccb_pathinq_settings_nvmf nvmf; 698 char ccb_pathinq_settings_opaque[PATHINQ_SETTINGS_SIZE]; 699 } xport_specific; 700 u_int maxio; /* Max supported I/O size, in bytes. */ 701 uint16_t hba_vendor; /* HBA vendor ID */ 702 uint16_t hba_device; /* HBA device ID */ 703 uint16_t hba_subvendor; /* HBA subvendor ID */ 704 uint16_t hba_subdevice; /* HBA subdevice ID */ 705 }; 706 707 /* Path Statistics CCB */ 708 struct ccb_pathstats { 709 struct ccb_hdr ccb_h; 710 struct timeval last_reset; /* Time of last bus reset/loop init */ 711 }; 712 713 typedef enum { 714 SMP_FLAG_NONE = 0x00, 715 SMP_FLAG_REQ_SG = 0x01, 716 SMP_FLAG_RSP_SG = 0x02 717 } ccb_smp_pass_flags; 718 719 /* 720 * Serial Management Protocol CCB 721 * XXX Currently the semantics for this CCB are that it is executed either 722 * by the addressed device, or that device's parent (i.e. an expander for 723 * any device on an expander) if the addressed device doesn't support SMP. 724 * Later, once we have the ability to probe SMP-only devices and put them 725 * in CAM's topology, the CCB will only be executed by the addressed device 726 * if possible. 727 */ 728 struct ccb_smpio { 729 struct ccb_hdr ccb_h; 730 uint8_t *smp_request; 731 int smp_request_len; 732 uint16_t smp_request_sglist_cnt; 733 uint8_t *smp_response; 734 int smp_response_len; 735 uint16_t smp_response_sglist_cnt; 736 ccb_smp_pass_flags flags; 737 }; 738 739 typedef union { 740 uint8_t *sense_ptr; /* 741 * Pointer to storage 742 * for sense information 743 */ 744 /* Storage Area for sense information */ 745 struct scsi_sense_data sense_buf; 746 } sense_t; 747 748 typedef union { 749 uint8_t *cdb_ptr; /* Pointer to the CDB bytes to send */ 750 /* Area for the CDB send */ 751 uint8_t cdb_bytes[IOCDBLEN]; 752 } cdb_t; 753 754 /* 755 * SCSI I/O Request CCB used for the XPT_SCSI_IO and XPT_CONT_TARGET_IO 756 * function codes. 757 */ 758 struct ccb_scsiio { 759 struct ccb_hdr ccb_h; 760 union ccb *next_ccb; /* Ptr for next CCB for action */ 761 uint8_t *req_map; /* Ptr to mapping info */ 762 uint8_t *data_ptr; /* Ptr to the data buf/SG list */ 763 uint32_t dxfer_len; /* Data transfer length */ 764 /* Autosense storage */ 765 struct scsi_sense_data sense_data; 766 uint8_t sense_len; /* Number of bytes to autosense */ 767 uint8_t cdb_len; /* Number of bytes for the CDB */ 768 uint16_t sglist_cnt; /* Number of SG list entries */ 769 uint8_t scsi_status; /* Returned SCSI status */ 770 uint8_t sense_resid; /* Autosense resid length: 2's comp */ 771 uint32_t resid; /* Transfer residual length: 2's comp */ 772 cdb_t cdb_io; /* Union for CDB bytes/pointer */ 773 uint8_t *msg_ptr; /* Pointer to the message buffer */ 774 uint16_t msg_len; /* Number of bytes for the Message */ 775 uint8_t tag_action; /* What to do for tag queueing */ 776 /* 777 * The tag action should be either the define below (to send a 778 * non-tagged transaction) or one of the defined scsi tag messages 779 * from scsi_message.h. 780 */ 781 #define CAM_TAG_ACTION_NONE 0x00 782 uint8_t priority; /* Command priority for SIMPLE tag */ 783 u_int tag_id; /* tag id from initator (target mode) */ 784 u_int init_id; /* initiator id of who selected */ 785 #if defined(BUF_TRACKING) || defined(FULL_BUF_TRACKING) 786 struct bio *bio; /* Associated bio */ 787 #endif 788 }; 789 790 static __inline uint8_t * 791 scsiio_cdb_ptr(struct ccb_scsiio *ccb) 792 { 793 return ((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 794 ccb->cdb_io.cdb_ptr : ccb->cdb_io.cdb_bytes); 795 } 796 797 /* 798 * ATA I/O Request CCB used for the XPT_ATA_IO function code. 799 */ 800 struct ccb_ataio { 801 struct ccb_hdr ccb_h; 802 union ccb *next_ccb; /* Ptr for next CCB for action */ 803 struct ata_cmd cmd; /* ATA command register set */ 804 struct ata_res res; /* ATA result register set */ 805 uint8_t *data_ptr; /* Ptr to the data buf/SG list */ 806 uint32_t dxfer_len; /* Data transfer length */ 807 uint32_t resid; /* Transfer residual length: 2's comp */ 808 uint8_t ata_flags; /* Flags for the rest of the buffer */ 809 #define ATA_FLAG_AUX 0x1 810 #define ATA_FLAG_ICC 0x2 811 uint8_t icc; /* Isochronous Command Completion */ 812 uint32_t aux; 813 uint32_t unused; 814 }; 815 816 /* 817 * MMC I/O Request CCB used for the XPT_MMC_IO function code. 818 */ 819 struct ccb_mmcio { 820 struct ccb_hdr ccb_h; 821 union ccb *next_ccb; /* Ptr for next CCB for action */ 822 struct mmc_command cmd; 823 struct mmc_command stop; 824 }; 825 826 struct ccb_accept_tio { 827 struct ccb_hdr ccb_h; 828 cdb_t cdb_io; /* Union for CDB bytes/pointer */ 829 uint8_t cdb_len; /* Number of bytes for the CDB */ 830 uint8_t tag_action; /* What to do for tag queueing */ 831 uint8_t sense_len; /* Number of bytes of Sense Data */ 832 uint8_t priority; /* Command priority for SIMPLE tag */ 833 u_int tag_id; /* tag id from initator (target mode) */ 834 u_int init_id; /* initiator id of who selected */ 835 struct scsi_sense_data sense_data; 836 }; 837 838 static __inline uint8_t * 839 atio_cdb_ptr(struct ccb_accept_tio *ccb) 840 { 841 return ((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 842 ccb->cdb_io.cdb_ptr : ccb->cdb_io.cdb_bytes); 843 } 844 845 /* Release SIM Queue */ 846 struct ccb_relsim { 847 struct ccb_hdr ccb_h; 848 uint32_t release_flags; 849 #define RELSIM_ADJUST_OPENINGS 0x01 850 #define RELSIM_RELEASE_AFTER_TIMEOUT 0x02 851 #define RELSIM_RELEASE_AFTER_CMDCMPLT 0x04 852 #define RELSIM_RELEASE_AFTER_QEMPTY 0x08 853 uint32_t openings; 854 uint32_t release_timeout; /* Abstract argument. */ 855 uint32_t qfrozen_cnt; 856 }; 857 858 /* 859 * NVMe I/O Request CCB used for the XPT_NVME_IO and XPT_NVME_ADMIN function codes. 860 */ 861 struct ccb_nvmeio { 862 struct ccb_hdr ccb_h; 863 union ccb *next_ccb; /* Ptr for next CCB for action */ 864 struct nvme_command cmd; /* NVME command, per NVME standard */ 865 struct nvme_completion cpl; /* NVME completion, per NVME standard */ 866 uint8_t *data_ptr; /* Ptr to the data buf/SG list */ 867 uint32_t dxfer_len; /* Data transfer length */ 868 uint16_t sglist_cnt; /* Number of SG list entries */ 869 uint16_t unused; /* padding for removed uint32_t */ 870 }; 871 872 /* 873 * Definitions for the asynchronous callback CCB fields. 874 */ 875 typedef enum { 876 AC_UNIT_ATTENTION = 0x4000,/* Device reported UNIT ATTENTION */ 877 AC_ADVINFO_CHANGED = 0x2000,/* Advance info might have changes */ 878 AC_CONTRACT = 0x1000,/* A contractual callback */ 879 AC_GETDEV_CHANGED = 0x800,/* Getdev info might have changed */ 880 AC_INQ_CHANGED = 0x400,/* Inquiry info might have changed */ 881 AC_TRANSFER_NEG = 0x200,/* New transfer settings in effect */ 882 AC_LOST_DEVICE = 0x100,/* A device went away */ 883 AC_FOUND_DEVICE = 0x080,/* A new device was found */ 884 AC_PATH_DEREGISTERED = 0x040,/* A path has de-registered */ 885 AC_PATH_REGISTERED = 0x020,/* A new path has been registered */ 886 AC_SENT_BDR = 0x010,/* A BDR message was sent to target */ 887 AC_SCSI_AEN = 0x008,/* A SCSI AEN has been received */ 888 AC_UNSOL_RESEL = 0x002,/* Unsolicited reselection occurred */ 889 AC_BUS_RESET = 0x001 /* A SCSI bus reset occurred */ 890 } ac_code; 891 892 typedef void ac_callback_t (void *softc, uint32_t code, 893 struct cam_path *path, void *args); 894 895 /* 896 * Generic Asynchronous callbacks. 897 * 898 * Generic arguments passed bac which are then interpreted between a per-system 899 * contract number. 900 */ 901 #define AC_CONTRACT_DATA_MAX (128 - sizeof (uint64_t)) 902 struct ac_contract { 903 uint64_t contract_number; 904 uint8_t contract_data[AC_CONTRACT_DATA_MAX]; 905 }; 906 907 #define AC_CONTRACT_DEV_CHG 1 908 struct ac_device_changed { 909 uint64_t wwpn; 910 uint32_t port; 911 target_id_t target; 912 uint8_t arrived; 913 }; 914 915 /* Set Asynchronous Callback CCB */ 916 struct ccb_setasync { 917 struct ccb_hdr ccb_h; 918 uint32_t event_enable; /* Async Event enables */ 919 ac_callback_t *callback; 920 void *callback_arg; 921 }; 922 923 /* Set Device Type CCB */ 924 struct ccb_setdev { 925 struct ccb_hdr ccb_h; 926 uint8_t dev_type; /* Value for dev type field in EDT */ 927 }; 928 929 /* SCSI Control Functions */ 930 931 /* Abort XPT request CCB */ 932 struct ccb_abort { 933 struct ccb_hdr ccb_h; 934 union ccb *abort_ccb; /* Pointer to CCB to abort */ 935 }; 936 937 /* Reset SCSI Bus CCB */ 938 struct ccb_resetbus { 939 struct ccb_hdr ccb_h; 940 }; 941 942 /* Reset SCSI Device CCB */ 943 struct ccb_resetdev { 944 struct ccb_hdr ccb_h; 945 }; 946 947 /* Terminate I/O Process Request CCB */ 948 struct ccb_termio { 949 struct ccb_hdr ccb_h; 950 union ccb *termio_ccb; /* Pointer to CCB to terminate */ 951 }; 952 953 typedef enum { 954 CTS_TYPE_CURRENT_SETTINGS, 955 CTS_TYPE_USER_SETTINGS 956 } cts_type; 957 958 struct ccb_trans_settings_scsi 959 { 960 u_int valid; /* Which fields to honor */ 961 #define CTS_SCSI_VALID_TQ 0x01 962 u_int flags; 963 #define CTS_SCSI_FLAGS_TAG_ENB 0x01 964 }; 965 966 struct ccb_trans_settings_ata 967 { 968 u_int valid; /* Which fields to honor */ 969 #define CTS_ATA_VALID_TQ 0x01 970 u_int flags; 971 #define CTS_ATA_FLAGS_TAG_ENB 0x01 972 }; 973 974 struct ccb_trans_settings_spi 975 { 976 u_int valid; /* Which fields to honor */ 977 #define CTS_SPI_VALID_SYNC_RATE 0x01 978 #define CTS_SPI_VALID_SYNC_OFFSET 0x02 979 #define CTS_SPI_VALID_BUS_WIDTH 0x04 980 #define CTS_SPI_VALID_DISC 0x08 981 #define CTS_SPI_VALID_PPR_OPTIONS 0x10 982 u_int flags; 983 #define CTS_SPI_FLAGS_DISC_ENB 0x01 984 u_int sync_period; 985 u_int sync_offset; 986 u_int bus_width; 987 u_int ppr_options; 988 }; 989 990 struct ccb_trans_settings_fc { 991 u_int valid; /* Which fields to honor */ 992 #define CTS_FC_VALID_WWNN 0x8000 993 #define CTS_FC_VALID_WWPN 0x4000 994 #define CTS_FC_VALID_PORT 0x2000 995 #define CTS_FC_VALID_SPEED 0x1000 996 uint64_t wwnn; /* world wide node name */ 997 uint64_t wwpn; /* world wide port name */ 998 uint32_t port; /* 24 bit port id, if known */ 999 uint32_t bitrate; /* Mbps */ 1000 }; 1001 1002 struct ccb_trans_settings_sas { 1003 u_int valid; /* Which fields to honor */ 1004 #define CTS_SAS_VALID_SPEED 0x1000 1005 uint32_t bitrate; /* Mbps */ 1006 }; 1007 1008 struct ccb_trans_settings_pata { 1009 u_int valid; /* Which fields to honor */ 1010 #define CTS_ATA_VALID_MODE 0x01 1011 #define CTS_ATA_VALID_BYTECOUNT 0x02 1012 #define CTS_ATA_VALID_ATAPI 0x20 1013 #define CTS_ATA_VALID_CAPS 0x40 1014 int mode; /* Mode */ 1015 u_int bytecount; /* Length of PIO transaction */ 1016 u_int atapi; /* Length of ATAPI CDB */ 1017 u_int caps; /* Device and host SATA caps. */ 1018 #define CTS_ATA_CAPS_H 0x0000ffff 1019 #define CTS_ATA_CAPS_H_DMA48 0x00000001 /* 48-bit DMA */ 1020 #define CTS_ATA_CAPS_D 0xffff0000 1021 }; 1022 1023 struct ccb_trans_settings_sata { 1024 u_int valid; /* Which fields to honor */ 1025 #define CTS_SATA_VALID_MODE 0x01 1026 #define CTS_SATA_VALID_BYTECOUNT 0x02 1027 #define CTS_SATA_VALID_REVISION 0x04 1028 #define CTS_SATA_VALID_PM 0x08 1029 #define CTS_SATA_VALID_TAGS 0x10 1030 #define CTS_SATA_VALID_ATAPI 0x20 1031 #define CTS_SATA_VALID_CAPS 0x40 1032 int mode; /* Legacy PATA mode */ 1033 u_int bytecount; /* Length of PIO transaction */ 1034 int revision; /* SATA revision */ 1035 u_int pm_present; /* PM is present (XPT->SIM) */ 1036 u_int tags; /* Number of allowed tags */ 1037 u_int atapi; /* Length of ATAPI CDB */ 1038 u_int caps; /* Device and host SATA caps. */ 1039 #define CTS_SATA_CAPS_H 0x0000ffff 1040 #define CTS_SATA_CAPS_H_PMREQ 0x00000001 1041 #define CTS_SATA_CAPS_H_APST 0x00000002 1042 #define CTS_SATA_CAPS_H_DMAAA 0x00000010 /* Auto-activation */ 1043 #define CTS_SATA_CAPS_H_AN 0x00000020 /* Async. notification */ 1044 #define CTS_SATA_CAPS_D 0xffff0000 1045 #define CTS_SATA_CAPS_D_PMREQ 0x00010000 1046 #define CTS_SATA_CAPS_D_APST 0x00020000 1047 }; 1048 1049 struct ccb_trans_settings_nvme 1050 { 1051 u_int valid; /* Which fields to honor */ 1052 #define CTS_NVME_VALID_SPEC 0x01 1053 #define CTS_NVME_VALID_CAPS 0x02 1054 #define CTS_NVME_VALID_LINK 0x04 1055 uint32_t spec; /* NVMe spec implemented -- same as vs register */ 1056 uint32_t max_xfer; /* Max transfer size (0 -> unlimited */ 1057 uint32_t caps; 1058 uint8_t lanes; /* Number of PCIe lanes */ 1059 uint8_t speed; /* PCIe generation for each lane */ 1060 uint8_t max_lanes; /* Number of PCIe lanes */ 1061 uint8_t max_speed; /* PCIe generation for each lane */ 1062 }; 1063 1064 struct ccb_trans_settings_nvmf 1065 { 1066 u_int valid; /* Which fields to honor */ 1067 #define CTS_NVMF_VALID_TRTYPE 0x01 1068 uint8_t trtype; 1069 }; 1070 1071 struct ccb_trans_settings_ufshci 1072 { 1073 u_int valid; /* Which fields to honor */ 1074 /* 1075 * Ensure the validity of the information for the Unipro link 1076 * (GEAR, SPEED, LANE) 1077 */ 1078 #define CTS_UFSHCI_VALID_LINK 0x01 1079 uint32_t speed; 1080 uint8_t hs_gear; /* High Speed Gear (G1, G2, G3...) */ 1081 uint8_t tx_lanes; 1082 uint8_t rx_lanes; 1083 uint8_t max_hs_gear; /* Maximum HS Gear */ 1084 uint8_t max_tx_lanes; 1085 uint8_t max_rx_lanes; 1086 }; 1087 1088 1089 #include <cam/mmc/mmc_bus.h> 1090 struct ccb_trans_settings_mmc { 1091 struct mmc_ios ios; 1092 #define MMC_CLK (1 << 1) 1093 #define MMC_VDD (1 << 2) 1094 #define MMC_CS (1 << 3) 1095 #define MMC_BW (1 << 4) 1096 #define MMC_PM (1 << 5) 1097 #define MMC_BT (1 << 6) 1098 #define MMC_BM (1 << 7) 1099 #define MMC_VCCQ (1 << 8) 1100 uint32_t ios_valid; 1101 /* The folowing is used only for GET_TRAN_SETTINGS */ 1102 uint32_t host_ocr; 1103 int host_f_min; 1104 int host_f_max; 1105 /* Copied from sys/dev/mmc/bridge.h */ 1106 #define MMC_CAP_4_BIT_DATA (1 << 0) /* Can do 4-bit data transfers */ 1107 #define MMC_CAP_8_BIT_DATA (1 << 1) /* Can do 8-bit data transfers */ 1108 #define MMC_CAP_HSPEED (1 << 2) /* Can do High Speed transfers */ 1109 #define MMC_CAP_BOOT_NOACC (1 << 4) /* Cannot access boot partitions */ 1110 #define MMC_CAP_WAIT_WHILE_BUSY (1 << 5) /* Host waits for busy responses */ 1111 #define MMC_CAP_UHS_SDR12 (1 << 6) /* Can do UHS SDR12 */ 1112 #define MMC_CAP_UHS_SDR25 (1 << 7) /* Can do UHS SDR25 */ 1113 #define MMC_CAP_UHS_SDR50 (1 << 8) /* Can do UHS SDR50 */ 1114 #define MMC_CAP_UHS_SDR104 (1 << 9) /* Can do UHS SDR104 */ 1115 #define MMC_CAP_UHS_DDR50 (1 << 10) /* Can do UHS DDR50 */ 1116 #define MMC_CAP_MMC_DDR52_120 (1 << 11) /* Can do eMMC DDR52 at 1.2 V */ 1117 #define MMC_CAP_MMC_DDR52_180 (1 << 12) /* Can do eMMC DDR52 at 1.8 V */ 1118 #define MMC_CAP_MMC_DDR52 (MMC_CAP_MMC_DDR52_120 | MMC_CAP_MMC_DDR52_180) 1119 #define MMC_CAP_MMC_HS200_120 (1 << 13) /* Can do eMMC HS200 at 1.2 V */ 1120 #define MMC_CAP_MMC_HS200_180 (1 << 14) /* Can do eMMC HS200 at 1.8 V */ 1121 #define MMC_CAP_MMC_HS200 (MMC_CAP_MMC_HS200_120| MMC_CAP_MMC_HS200_180) 1122 #define MMC_CAP_MMC_HS400_120 (1 << 15) /* Can do eMMC HS400 at 1.2 V */ 1123 #define MMC_CAP_MMC_HS400_180 (1 << 16) /* Can do eMMC HS400 at 1.8 V */ 1124 #define MMC_CAP_MMC_HS400 (MMC_CAP_MMC_HS400_120 | MMC_CAP_MMC_HS400_180) 1125 #define MMC_CAP_MMC_HSX00_120 (MMC_CAP_MMC_HS200_120 | MMC_CAP_MMC_HS400_120) 1126 #define MMC_CAP_MMC_ENH_STROBE (1 << 17) /* Can do eMMC Enhanced Strobe */ 1127 #define MMC_CAP_SIGNALING_120 (1 << 18) /* Can do signaling at 1.2 V */ 1128 #define MMC_CAP_SIGNALING_180 (1 << 19) /* Can do signaling at 1.8 V */ 1129 #define MMC_CAP_SIGNALING_330 (1 << 20) /* Can do signaling at 3.3 V */ 1130 #define MMC_CAP_DRIVER_TYPE_A (1 << 21) /* Can do Driver Type A */ 1131 #define MMC_CAP_DRIVER_TYPE_C (1 << 22) /* Can do Driver Type C */ 1132 #define MMC_CAP_DRIVER_TYPE_D (1 << 23) /* Can do Driver Type D */ 1133 1134 uint32_t host_caps; 1135 uint32_t host_max_data; 1136 }; 1137 1138 /* Get/Set transfer rate/width/disconnection/tag queueing settings */ 1139 struct ccb_trans_settings { 1140 struct ccb_hdr ccb_h; 1141 cts_type type; /* Current or User settings */ 1142 cam_proto protocol; 1143 u_int protocol_version; 1144 cam_xport transport; 1145 u_int transport_version; 1146 union { 1147 u_int valid; /* Which fields to honor */ 1148 struct ccb_trans_settings_ata ata; 1149 struct ccb_trans_settings_scsi scsi; 1150 struct ccb_trans_settings_nvme nvme; 1151 struct ccb_trans_settings_mmc mmc; 1152 } proto_specific; 1153 union { 1154 u_int valid; /* Which fields to honor */ 1155 struct ccb_trans_settings_spi spi; 1156 struct ccb_trans_settings_fc fc; 1157 struct ccb_trans_settings_sas sas; 1158 struct ccb_trans_settings_pata ata; 1159 struct ccb_trans_settings_sata sata; 1160 struct ccb_trans_settings_nvme nvme; 1161 struct ccb_trans_settings_nvmf nvmf; 1162 struct ccb_trans_settings_ufshci ufshci; 1163 } xport_specific; 1164 }; 1165 1166 /* 1167 * Calculate the geometry parameters for a device 1168 * give the block size and volume size in blocks. 1169 */ 1170 struct ccb_calc_geometry { 1171 struct ccb_hdr ccb_h; 1172 uint32_t block_size; 1173 uint64_t volume_size; 1174 uint32_t cylinders; 1175 uint8_t heads; 1176 uint8_t secs_per_track; 1177 }; 1178 1179 /* 1180 * Set or get SIM (and transport) specific knobs 1181 */ 1182 1183 #define KNOB_VALID_ADDRESS 0x1 1184 #define KNOB_VALID_ROLE 0x2 1185 1186 #define KNOB_ROLE_NONE 0x0 1187 #define KNOB_ROLE_INITIATOR 0x1 1188 #define KNOB_ROLE_TARGET 0x2 1189 #define KNOB_ROLE_BOTH 0x3 1190 1191 struct ccb_sim_knob_settings_spi { 1192 u_int valid; 1193 u_int initiator_id; 1194 u_int role; 1195 }; 1196 1197 struct ccb_sim_knob_settings_fc { 1198 u_int valid; 1199 uint64_t wwnn; /* world wide node name */ 1200 uint64_t wwpn; /* world wide port name */ 1201 u_int role; 1202 }; 1203 1204 struct ccb_sim_knob_settings_sas { 1205 u_int valid; 1206 uint64_t wwnn; /* world wide node name */ 1207 u_int role; 1208 }; 1209 #define KNOB_SETTINGS_SIZE 128 1210 1211 struct ccb_sim_knob { 1212 struct ccb_hdr ccb_h; 1213 union { 1214 u_int valid; /* Which fields to honor */ 1215 struct ccb_sim_knob_settings_spi spi; 1216 struct ccb_sim_knob_settings_fc fc; 1217 struct ccb_sim_knob_settings_sas sas; 1218 char pad[KNOB_SETTINGS_SIZE]; 1219 } xport_specific; 1220 }; 1221 1222 /* 1223 * Rescan the given bus, or bus/target/lun 1224 */ 1225 struct ccb_rescan { 1226 struct ccb_hdr ccb_h; 1227 cam_flags flags; 1228 }; 1229 1230 /* 1231 * Turn on debugging for the given bus, bus/target, or bus/target/lun. 1232 */ 1233 struct ccb_debug { 1234 struct ccb_hdr ccb_h; 1235 cam_debug_flags flags; 1236 }; 1237 1238 /* Target mode structures. */ 1239 1240 struct ccb_en_lun { 1241 struct ccb_hdr ccb_h; 1242 uint16_t grp6_len; /* Group 6 VU CDB length */ 1243 uint16_t grp7_len; /* Group 7 VU CDB length */ 1244 uint8_t enable; 1245 }; 1246 1247 /* old, barely used immediate notify, binary compatibility */ 1248 struct ccb_immed_notify { 1249 struct ccb_hdr ccb_h; 1250 struct scsi_sense_data sense_data; 1251 uint8_t sense_len; /* Number of bytes in sense buffer */ 1252 uint8_t initiator_id; /* Id of initiator that selected */ 1253 uint8_t message_args[7]; /* Message Arguments */ 1254 }; 1255 1256 struct ccb_notify_ack { 1257 struct ccb_hdr ccb_h; 1258 uint16_t seq_id; /* Sequence identifier */ 1259 uint8_t event; /* Event flags */ 1260 }; 1261 1262 struct ccb_immediate_notify { 1263 struct ccb_hdr ccb_h; 1264 u_int tag_id; /* Tag for immediate notify */ 1265 u_int seq_id; /* Tag for target of notify */ 1266 u_int initiator_id; /* Initiator Identifier */ 1267 u_int arg; /* Function specific */ 1268 }; 1269 1270 struct ccb_notify_acknowledge { 1271 struct ccb_hdr ccb_h; 1272 u_int tag_id; /* Tag for immediate notify */ 1273 u_int seq_id; /* Tar for target of notify */ 1274 u_int initiator_id; /* Initiator Identifier */ 1275 u_int arg; /* Response information */ 1276 /* 1277 * Lower byte of arg is one of RESPONSE CODE values defined below 1278 * (subset of response codes from SPL-4 and FCP-4 specifications), 1279 * upper 3 bytes is code-specific ADDITIONAL RESPONSE INFORMATION. 1280 */ 1281 #define CAM_RSP_TMF_COMPLETE 0x00 1282 #define CAM_RSP_TMF_REJECTED 0x04 1283 #define CAM_RSP_TMF_FAILED 0x05 1284 #define CAM_RSP_TMF_SUCCEEDED 0x08 1285 #define CAM_RSP_TMF_INCORRECT_LUN 0x09 1286 }; 1287 1288 /* HBA engine structures. */ 1289 1290 typedef enum { 1291 EIT_BUFFER, /* Engine type: buffer memory */ 1292 EIT_LOSSLESS, /* Engine type: lossless compression */ 1293 EIT_LOSSY, /* Engine type: lossy compression */ 1294 EIT_ENCRYPT /* Engine type: encryption */ 1295 } ei_type; 1296 1297 typedef enum { 1298 EAD_VUNIQUE, /* Engine algorithm ID: vendor unique */ 1299 EAD_LZ1V1, /* Engine algorithm ID: LZ1 var.1 */ 1300 EAD_LZ2V1, /* Engine algorithm ID: LZ2 var.1 */ 1301 EAD_LZ2V2 /* Engine algorithm ID: LZ2 var.2 */ 1302 } ei_algo; 1303 1304 struct ccb_eng_inq { 1305 struct ccb_hdr ccb_h; 1306 uint16_t eng_num; /* The engine number for this inquiry */ 1307 ei_type eng_type; /* Returned engine type */ 1308 ei_algo eng_algo; /* Returned engine algorithm type */ 1309 uint32_t eng_memeory; /* Returned engine memory size */ 1310 }; 1311 1312 struct ccb_eng_exec { /* This structure must match SCSIIO size */ 1313 struct ccb_hdr ccb_h; 1314 uint8_t *pdrv_ptr; /* Ptr used by the peripheral driver */ 1315 uint8_t *req_map; /* Ptr for mapping info on the req. */ 1316 uint8_t *data_ptr; /* Pointer to the data buf/SG list */ 1317 uint32_t dxfer_len; /* Data transfer length */ 1318 uint8_t *engdata_ptr; /* Pointer to the engine buffer data */ 1319 uint16_t sglist_cnt; /* Num of scatter gather list entries */ 1320 uint32_t dmax_len; /* Destination data maximum length */ 1321 uint32_t dest_len; /* Destination data length */ 1322 int32_t src_resid; /* Source residual length: 2's comp */ 1323 uint32_t timeout; /* Timeout value */ 1324 uint16_t eng_num; /* Engine number for this request */ 1325 uint16_t vu_flags; /* Vendor Unique flags */ 1326 }; 1327 1328 /* 1329 * Definitions for the timeout field in the SCSI I/O CCB. 1330 */ 1331 #define CAM_TIME_DEFAULT 0x00000000 /* Use SIM default value */ 1332 #define CAM_TIME_INFINITY 0xFFFFFFFF /* Infinite timeout */ 1333 1334 #define CAM_SUCCESS 0 /* For signaling general success */ 1335 1336 #define XPT_CCB_INVALID -1 /* for signaling a bad CCB to free */ 1337 1338 /* 1339 * CCB for working with advanced device information. This operates in a fashion 1340 * similar to XPT_GDEV_TYPE. Specify the target in ccb_h, the buffer 1341 * type requested, and provide a buffer size/buffer to write to. If the 1342 * buffer is too small, provsiz will be larger than bufsiz. 1343 */ 1344 struct ccb_dev_advinfo { 1345 struct ccb_hdr ccb_h; 1346 uint32_t flags; 1347 #define CDAI_FLAG_NONE 0x0 /* No flags set */ 1348 #define CDAI_FLAG_STORE 0x1 /* If set, action becomes store */ 1349 uint32_t buftype; /* IN: Type of data being requested */ 1350 /* NB: buftype is interpreted on a per-transport basis */ 1351 #define CDAI_TYPE_SCSI_DEVID 1 1352 #define CDAI_TYPE_SERIAL_NUM 2 1353 #define CDAI_TYPE_PHYS_PATH 3 1354 #define CDAI_TYPE_RCAPLONG 4 1355 #define CDAI_TYPE_EXT_INQ 5 1356 #define CDAI_TYPE_NVME_CNTRL 6 /* NVMe Identify Controller data */ 1357 #define CDAI_TYPE_NVME_NS 7 /* NVMe Identify Namespace data */ 1358 #define CDAI_TYPE_MMC_PARAMS 8 /* MMC/SD ident */ 1359 off_t bufsiz; /* IN: Size of external buffer */ 1360 #define CAM_SCSI_DEVID_MAXLEN 65536 /* length in buffer is an uint16_t */ 1361 off_t provsiz; /* OUT: Size required/used */ 1362 uint8_t *buf; /* IN/OUT: Buffer for requested data */ 1363 }; 1364 1365 /* 1366 * CCB for sending async events 1367 */ 1368 struct ccb_async { 1369 struct ccb_hdr ccb_h; 1370 uint32_t async_code; 1371 off_t async_arg_size; 1372 void *async_arg_ptr; 1373 }; 1374 1375 /* 1376 * Union of all CCB types for kernel space allocation. This union should 1377 * never be used for manipulating CCBs - its only use is for the allocation 1378 * and deallocation of raw CCB space and is the return type of xpt_ccb_alloc 1379 * and the argument to xpt_ccb_free. 1380 */ 1381 union ccb { 1382 struct ccb_hdr ccb_h; /* For convenience */ 1383 struct ccb_scsiio csio; 1384 struct ccb_getdev cgd; 1385 struct ccb_getdevlist cgdl; 1386 struct ccb_pathinq cpi; 1387 struct ccb_relsim crs; 1388 struct ccb_setasync csa; 1389 struct ccb_setdev csd; 1390 struct ccb_pathstats cpis; 1391 struct ccb_getdevstats cgds; 1392 struct ccb_dev_match cdm; 1393 struct ccb_trans_settings cts; 1394 struct ccb_calc_geometry ccg; 1395 struct ccb_sim_knob knob; 1396 struct ccb_abort cab; 1397 struct ccb_resetbus crb; 1398 struct ccb_resetdev crd; 1399 struct ccb_termio tio; 1400 struct ccb_accept_tio atio; 1401 struct ccb_scsiio ctio; 1402 struct ccb_en_lun cel; 1403 struct ccb_immed_notify cin; 1404 struct ccb_notify_ack cna; 1405 struct ccb_immediate_notify cin1; 1406 struct ccb_notify_acknowledge cna2; 1407 struct ccb_eng_inq cei; 1408 struct ccb_eng_exec cee; 1409 struct ccb_smpio smpio; 1410 struct ccb_rescan crcn; 1411 struct ccb_debug cdbg; 1412 struct ccb_ataio ataio; 1413 struct ccb_dev_advinfo cdai; 1414 struct ccb_async casync; 1415 struct ccb_nvmeio nvmeio; 1416 struct ccb_mmcio mmcio; 1417 }; 1418 1419 #define CCB_CLEAR_ALL_EXCEPT_HDR(ccbp) \ 1420 bzero((char *)(ccbp) + sizeof((ccbp)->ccb_h), \ 1421 sizeof(*(ccbp)) - sizeof((ccbp)->ccb_h)) 1422 1423 __BEGIN_DECLS 1424 static __inline void 1425 cam_fill_csio(struct ccb_scsiio *csio, uint32_t retries, 1426 void (*cbfcnp)(struct cam_periph *, union ccb *), 1427 uint32_t flags, uint8_t tag_action, 1428 uint8_t *data_ptr, uint32_t dxfer_len, 1429 uint8_t sense_len, uint8_t cdb_len, 1430 uint32_t timeout) 1431 { 1432 csio->ccb_h.func_code = XPT_SCSI_IO; 1433 csio->ccb_h.flags = flags; 1434 csio->ccb_h.xflags = 0; 1435 csio->ccb_h.retry_count = retries; 1436 csio->ccb_h.cbfcnp = cbfcnp; 1437 csio->ccb_h.timeout = timeout; 1438 csio->data_ptr = data_ptr; 1439 csio->dxfer_len = dxfer_len; 1440 csio->sense_len = sense_len; 1441 csio->cdb_len = cdb_len; 1442 csio->tag_action = tag_action; 1443 csio->priority = 0; 1444 #if defined(BUF_TRACKING) || defined(FULL_BUF_TRACKING) 1445 csio->bio = NULL; 1446 #endif 1447 } 1448 1449 static __inline void 1450 cam_fill_ctio(struct ccb_scsiio *csio, uint32_t retries, 1451 void (*cbfcnp)(struct cam_periph *, union ccb *), 1452 uint32_t flags, u_int tag_action, u_int tag_id, 1453 u_int init_id, u_int scsi_status, uint8_t *data_ptr, 1454 uint32_t dxfer_len, uint32_t timeout) 1455 { 1456 csio->ccb_h.func_code = XPT_CONT_TARGET_IO; 1457 csio->ccb_h.flags = flags; 1458 csio->ccb_h.xflags = 0; 1459 csio->ccb_h.retry_count = retries; 1460 csio->ccb_h.cbfcnp = cbfcnp; 1461 csio->ccb_h.timeout = timeout; 1462 csio->data_ptr = data_ptr; 1463 csio->dxfer_len = dxfer_len; 1464 csio->scsi_status = scsi_status; 1465 csio->tag_action = tag_action; 1466 csio->priority = 0; 1467 csio->tag_id = tag_id; 1468 csio->init_id = init_id; 1469 } 1470 1471 static __inline void 1472 cam_fill_ataio(struct ccb_ataio *ataio, uint32_t retries, 1473 void (*cbfcnp)(struct cam_periph *, union ccb *), 1474 uint32_t flags, u_int tag_action __unused, 1475 uint8_t *data_ptr, uint32_t dxfer_len, 1476 uint32_t timeout) 1477 { 1478 ataio->ccb_h.func_code = XPT_ATA_IO; 1479 ataio->ccb_h.flags = flags; 1480 ataio->ccb_h.retry_count = retries; 1481 ataio->ccb_h.cbfcnp = cbfcnp; 1482 ataio->ccb_h.timeout = timeout; 1483 ataio->data_ptr = data_ptr; 1484 ataio->dxfer_len = dxfer_len; 1485 ataio->ata_flags = 0; 1486 } 1487 1488 static __inline void 1489 cam_fill_smpio(struct ccb_smpio *smpio, uint32_t retries, 1490 void (*cbfcnp)(struct cam_periph *, union ccb *), uint32_t flags, 1491 uint8_t *smp_request, int smp_request_len, 1492 uint8_t *smp_response, int smp_response_len, 1493 uint32_t timeout) 1494 { 1495 #ifdef _KERNEL 1496 KASSERT((flags & CAM_DIR_MASK) == CAM_DIR_BOTH, 1497 ("direction != CAM_DIR_BOTH")); 1498 KASSERT((smp_request != NULL) && (smp_response != NULL), 1499 ("need valid request and response buffers")); 1500 KASSERT((smp_request_len != 0) && (smp_response_len != 0), 1501 ("need non-zero request and response lengths")); 1502 #endif /*_KERNEL*/ 1503 smpio->ccb_h.func_code = XPT_SMP_IO; 1504 smpio->ccb_h.flags = flags; 1505 smpio->ccb_h.retry_count = retries; 1506 smpio->ccb_h.cbfcnp = cbfcnp; 1507 smpio->ccb_h.timeout = timeout; 1508 smpio->smp_request = smp_request; 1509 smpio->smp_request_len = smp_request_len; 1510 smpio->smp_response = smp_response; 1511 smpio->smp_response_len = smp_response_len; 1512 } 1513 1514 static __inline void 1515 cam_fill_mmcio(struct ccb_mmcio *mmcio, uint32_t retries, 1516 void (*cbfcnp)(struct cam_periph *, union ccb *), uint32_t flags, 1517 uint32_t mmc_opcode, uint32_t mmc_arg, uint32_t mmc_flags, 1518 struct mmc_data *mmc_d, 1519 uint32_t timeout) 1520 { 1521 mmcio->ccb_h.func_code = XPT_MMC_IO; 1522 mmcio->ccb_h.flags = flags; 1523 mmcio->ccb_h.retry_count = retries; 1524 mmcio->ccb_h.cbfcnp = cbfcnp; 1525 mmcio->ccb_h.timeout = timeout; 1526 mmcio->cmd.opcode = mmc_opcode; 1527 mmcio->cmd.arg = mmc_arg; 1528 mmcio->cmd.flags = mmc_flags; 1529 mmcio->cmd.error = 0; 1530 mmcio->stop.opcode = 0; 1531 mmcio->stop.arg = 0; 1532 mmcio->stop.flags = 0; 1533 if (mmc_d != NULL) { 1534 mmcio->cmd.data = mmc_d; 1535 } else 1536 mmcio->cmd.data = NULL; 1537 mmcio->cmd.resp[0] = 0; 1538 mmcio->cmd.resp[1] = 0; 1539 mmcio->cmd.resp[2] = 0; 1540 mmcio->cmd.resp[3] = 0; 1541 } 1542 1543 static __inline void 1544 cam_set_ccbstatus(union ccb *ccb, cam_status status) 1545 { 1546 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1547 ccb->ccb_h.status |= status; 1548 } 1549 1550 static __inline cam_status 1551 cam_ccb_status(union ccb *ccb) 1552 { 1553 return ((cam_status)(ccb->ccb_h.status & CAM_STATUS_MASK)); 1554 } 1555 1556 static inline bool 1557 cam_ccb_success(union ccb *ccb) 1558 { 1559 return (cam_ccb_status(ccb) == CAM_REQ_CMP); 1560 } 1561 1562 void cam_calc_geometry(struct ccb_calc_geometry *ccg, int extended); 1563 1564 static __inline void 1565 cam_fill_nvmeio(struct ccb_nvmeio *nvmeio, uint32_t retries, 1566 void (*cbfcnp)(struct cam_periph *, union ccb *), 1567 uint32_t flags, uint8_t *data_ptr, uint32_t dxfer_len, 1568 uint32_t timeout) 1569 { 1570 nvmeio->ccb_h.func_code = XPT_NVME_IO; 1571 nvmeio->ccb_h.flags = flags; 1572 nvmeio->ccb_h.retry_count = retries; 1573 nvmeio->ccb_h.cbfcnp = cbfcnp; 1574 nvmeio->ccb_h.timeout = timeout; 1575 nvmeio->data_ptr = data_ptr; 1576 nvmeio->dxfer_len = dxfer_len; 1577 } 1578 1579 static __inline void 1580 cam_fill_nvmeadmin(struct ccb_nvmeio *nvmeio, uint32_t retries, 1581 void (*cbfcnp)(struct cam_periph *, union ccb *), 1582 uint32_t flags, uint8_t *data_ptr, uint32_t dxfer_len, 1583 uint32_t timeout) 1584 { 1585 nvmeio->ccb_h.func_code = XPT_NVME_ADMIN; 1586 nvmeio->ccb_h.flags = flags; 1587 nvmeio->ccb_h.retry_count = retries; 1588 nvmeio->ccb_h.cbfcnp = cbfcnp; 1589 nvmeio->ccb_h.timeout = timeout; 1590 nvmeio->data_ptr = data_ptr; 1591 nvmeio->dxfer_len = dxfer_len; 1592 } 1593 __END_DECLS 1594 1595 #endif /* _CAM_CAM_CCB_H */ 1596