1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 /***************************************************************************** 4 * @file icp_accel_devices.h 5 * 6 * @defgroup Acceleration Driver Framework 7 * 8 * @ingroup icp_Adf 9 * 10 * @description 11 * This is the top level header file that contains the layout of the ADF 12 * icp_accel_dev_t structure and related macros/definitions. 13 * It can be used to dereference the icp_accel_dev_t *passed into upper 14 * layers. 15 * 16 *****************************************************************************/ 17 18 #ifndef ICP_ACCEL_DEVICES_H_ 19 #define ICP_ACCEL_DEVICES_H_ 20 21 #include "cpa.h" 22 #include "qat_utils.h" 23 #include "adf_accel_devices.h" 24 25 #define ADF_CFG_NO_INSTANCE 0xFFFFFFFF 26 27 #define ICP_DC_TX_RING_0 6 28 #define ICP_DC_TX_RING_1 7 29 #define ICP_RX_RINGS_OFFSET 8 30 #define ICP_RINGS_PER_BANK 16 31 32 /* Number of worker threads per AE */ 33 #define ICP_ARB_WRK_THREAD_TO_SARB 12 34 #define MAX_ACCEL_NAME_LEN 16 35 #define ADF_DEVICE_NAME_LENGTH 32 36 #define ADF_DEVICE_TYPE_LENGTH 8 37 38 #define ADF_CTL_DEVICE_NAME "/dev/qat_adf_ctl" 39 40 /** 41 ***************************************************************************** 42 * @ingroup icp_AdfAccelHandle 43 * 44 * @description 45 * Accelerator capabilities 46 * 47 *****************************************************************************/ 48 typedef enum { 49 ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = 0x01, 50 ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = 0x02, 51 ICP_ACCEL_CAPABILITIES_CIPHER = 0x04, 52 ICP_ACCEL_CAPABILITIES_AUTHENTICATION = 0x08, 53 ICP_ACCEL_CAPABILITIES_RESERVED_1 = 0x10, 54 ICP_ACCEL_CAPABILITIES_COMPRESSION = 0x20, 55 ICP_ACCEL_CAPABILITIES_DEPRECATED = 0x40, 56 ICP_ACCEL_CAPABILITIES_RANDOM_NUMBER = 0x80, 57 ICP_ACCEL_CAPABILITIES_CRYPTO_ZUC = 0x100, 58 ICP_ACCEL_CAPABILITIES_SHA3 = 0x200, 59 ICP_ACCEL_CAPABILITIES_KPT = 0x400, 60 ICP_ACCEL_CAPABILITIES_RL = 0x800, 61 ICP_ACCEL_CAPABILITIES_HKDF = 0x1000, 62 ICP_ACCEL_CAPABILITIES_ECEDMONT = 0x2000, 63 ICP_ACCEL_CAPABILITIES_EXT_ALGCHAIN = 0x4000, 64 ICP_ACCEL_CAPABILITIES_SHA3_EXT = 0x8000, 65 ICP_ACCEL_CAPABILITIES_AESGCM_SPC = 0x10000, 66 ICP_ACCEL_CAPABILITIES_CHACHA_POLY = 0x20000, 67 ICP_ACCEL_CAPABILITIES_SM2 = 0x40000, 68 ICP_ACCEL_CAPABILITIES_SM3 = 0x80000, 69 ICP_ACCEL_CAPABILITIES_SM4 = 0x100000, 70 ICP_ACCEL_CAPABILITIES_INLINE = 0x200000, 71 ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY = 0x400000, 72 ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64 = 0x800000, 73 ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION = 0x1000000, 74 ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION = 0x2000000, 75 ICP_ACCEL_CAPABILITIES_AES_V2 = 0x4000000, 76 ICP_ACCEL_CAPABILITIES_KPT2 = 0x8000000, 77 } icp_accel_capabilities_t; 78 79 /** 80 ***************************************************************************** 81 * @ingroup icp_AdfAccelHandle 82 * 83 * @description 84 * Device Configuration Data Structure 85 * 86 *****************************************************************************/ 87 88 typedef enum device_type_e { 89 DEVICE_UNKNOWN = 0, 90 DEVICE_DH895XCC, 91 DEVICE_DH895XCCVF, 92 DEVICE_C62X, 93 DEVICE_C62XVF, 94 DEVICE_C3XXX, 95 DEVICE_C3XXXVF, 96 DEVICE_200XX, 97 DEVICE_200XXVF, 98 DEVICE_C4XXX, 99 DEVICE_C4XXXVF, 100 DEVICE_D15XX, 101 DEVICE_D15XXVF, 102 DEVICE_4XXX, 103 DEVICE_4XXXVF 104 } device_type_t; 105 106 /* 107 * Enumeration on Service Type 108 */ 109 typedef enum adf_service_type_s { 110 ADF_SERVICE_CRYPTO, 111 ADF_SERVICE_COMPRESS, 112 ADF_SERVICE_MAX /* this is always the last one */ 113 } adf_service_type_t; 114 115 typedef struct accel_dev_s { 116 /* Some generic information */ 117 Cpa32U accelId; 118 Cpa8U *pAccelName; /* Name given to accelerator */ 119 Cpa32U aeMask; /* Acceleration Engine mask */ 120 device_type_t deviceType; /* Device Type */ 121 /* Device name for SAL */ 122 char deviceName[ADF_DEVICE_NAME_LENGTH + 1]; 123 Cpa32U accelCapabilitiesMask; /* Accelerator's capabilities 124 mask */ 125 Cpa32U dcExtendedFeatures; /* bit field of features */ 126 QatUtilsAtomic usageCounter; /* Usage counter. Prevents 127 shutting down the dev if not 0*/ 128 Cpa32U deviceMemAvail; /* Device memory for intermediate buffers */ 129 /* Component specific fields - cast to relevent layer */ 130 void *pRingInflight; /* For offload optimization */ 131 void *pSalHandle; /* For SAL*/ 132 void *pQatStats; /* For QATAL/SAL stats */ 133 void *ringInfoCallBack; /* Callback for user space 134 ring enabling */ 135 void *pShramConstants; /* Virtual address of Shram constants page */ 136 Cpa64U pShramConstantsDma; /* Bus address of Shram constants page */ 137 138 /* Status of ADF and registered subsystems */ 139 Cpa32U adfSubsystemStatus; 140 /* Physical processor to which the dev is connected */ 141 Cpa8U pkg_id; 142 enum dev_sku_info sku; 143 Cpa32U pciDevId; 144 Cpa8U devFileName[ADF_DEVICE_NAME_LENGTH]; 145 Cpa32S csrFileHdl; 146 Cpa32S ringFileHdl; 147 void *accel; 148 149 Cpa32U maxNumBanks; 150 Cpa32U maxNumRingsPerBank; 151 152 /* pointer to dynamic instance resource manager */ 153 void *pInstMgr; 154 void *banks; /* banks information */ 155 struct adf_accel_dev *accel_dev; 156 struct accel_dev_s *pPrev; 157 struct accel_dev_s *pNext; 158 } icp_accel_dev_t; 159 160 #endif /* ICP_ACCEL_HANDLE_H */ 161