xref: /titanic_41/usr/src/uts/common/io/e1000g/e1000g_sw.h (revision 29fd2c1627adafbe0a83726c224e60b5514c7736)
1 /*
2  * This file is provided under a CDDLv1 license.  When using or
3  * redistributing this file, you may do so under this license.
4  * In redistributing this file this license must be included
5  * and no other modification of this header file is permitted.
6  *
7  * CDDL LICENSE SUMMARY
8  *
9  * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
10  *
11  * The contents of this file are subject to the terms of Version
12  * 1.0 of the Common Development and Distribution License (the "License").
13  *
14  * You should have received a copy of the License with this software.
15  * You can obtain a copy of the License at
16  *	http://www.opensolaris.org/os/licensing.
17  * See the License for the specific language governing permissions
18  * and limitations under the License.
19  */
20 
21 /*
22  * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
23  * Copyright 2012 David Höppner. All rights reserved.
24  */
25 
26 #ifndef _E1000G_SW_H
27 #define	_E1000G_SW_H
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
33 /*
34  * **********************************************************************
35  * Module Name:								*
36  *   e1000g_sw.h							*
37  *									*
38  * Abstract:								*
39  *   This header file contains Software-related data structures		*
40  *   definitions.							*
41  *									*
42  * **********************************************************************
43  */
44 
45 #include <sys/types.h>
46 #include <sys/conf.h>
47 #include <sys/debug.h>
48 #include <sys/stropts.h>
49 #include <sys/stream.h>
50 #include <sys/strsun.h>
51 #include <sys/strlog.h>
52 #include <sys/kmem.h>
53 #include <sys/stat.h>
54 #include <sys/kstat.h>
55 #include <sys/modctl.h>
56 #include <sys/errno.h>
57 #include <sys/mac_provider.h>
58 #include <sys/mac_ether.h>
59 #include <sys/vlan.h>
60 #include <sys/ddi.h>
61 #include <sys/sunddi.h>
62 #include <sys/disp.h>
63 #include <sys/pci.h>
64 #include <sys/sdt.h>
65 #include <sys/ethernet.h>
66 #include <sys/pattr.h>
67 #include <sys/strsubr.h>
68 #include <sys/netlb.h>
69 #include <inet/common.h>
70 #include <inet/ip.h>
71 #include <inet/tcp.h>
72 #include <inet/mi.h>
73 #include <inet/nd.h>
74 #include <sys/ddifm.h>
75 #include <sys/fm/protocol.h>
76 #include <sys/fm/util.h>
77 #include <sys/fm/io/ddi.h>
78 #include "e1000_api.h"
79 
80 /* Driver states */
81 #define	E1000G_UNKNOWN			0x00
82 #define	E1000G_INITIALIZED		0x01
83 #define	E1000G_STARTED			0x02
84 #define	E1000G_SUSPENDED		0x04
85 #define	E1000G_ERROR			0x80
86 
87 #define	JUMBO_FRAG_LENGTH		4096
88 
89 #define	LAST_RAR_ENTRY			(E1000_RAR_ENTRIES - 1)
90 #define	MAX_NUM_UNICAST_ADDRESSES	E1000_RAR_ENTRIES
91 #define	MCAST_ALLOC_SIZE		256
92 
93 /*
94  * MAX_COOKIES = max_LSO_packet_size(65535 + ethernet_header_len)/page_size
95  *	+ one for cross page split
96  * MAX_TX_DESC_PER_PACKET = MAX_COOKIES + one for the context descriptor +
97  *	two for the workaround of the 82546 chip
98  */
99 #define	MAX_COOKIES			18
100 #define	MAX_TX_DESC_PER_PACKET		21
101 
102 /*
103  * constants used in setting flow control thresholds
104  */
105 #define	E1000_PBA_MASK		0xffff
106 #define	E1000_PBA_SHIFT		10
107 #define	E1000_FC_HIGH_DIFF	0x1638 /* High: 5688 bytes below Rx FIFO size */
108 #define	E1000_FC_LOW_DIFF	0x1640 /* Low: 5696 bytes below Rx FIFO size */
109 #define	E1000_FC_PAUSE_TIME	0x0680 /* 858 usec */
110 
111 #define	MAX_NUM_TX_DESCRIPTOR		4096
112 #define	MAX_NUM_RX_DESCRIPTOR		4096
113 #define	MAX_NUM_RX_FREELIST		4096
114 #define	MAX_NUM_TX_FREELIST		4096
115 #define	MAX_RX_LIMIT_ON_INTR		4096
116 #define	MAX_RX_INTR_DELAY		65535
117 #define	MAX_RX_INTR_ABS_DELAY		65535
118 #define	MAX_TX_INTR_DELAY		65535
119 #define	MAX_TX_INTR_ABS_DELAY		65535
120 #define	MAX_INTR_THROTTLING		65535
121 #define	MAX_RX_BCOPY_THRESHOLD		E1000_RX_BUFFER_SIZE_2K
122 #define	MAX_TX_BCOPY_THRESHOLD		E1000_TX_BUFFER_SIZE_2K
123 #define	MAX_MCAST_NUM			8192
124 
125 #define	MIN_NUM_TX_DESCRIPTOR		80
126 #define	MIN_NUM_RX_DESCRIPTOR		80
127 #define	MIN_NUM_RX_FREELIST		64
128 #define	MIN_NUM_TX_FREELIST		80
129 #define	MIN_RX_LIMIT_ON_INTR		16
130 #define	MIN_RX_INTR_DELAY		0
131 #define	MIN_RX_INTR_ABS_DELAY		0
132 #define	MIN_TX_INTR_DELAY		0
133 #define	MIN_TX_INTR_ABS_DELAY		0
134 #define	MIN_INTR_THROTTLING		0
135 #define	MIN_RX_BCOPY_THRESHOLD		0
136 #define	MIN_TX_BCOPY_THRESHOLD		ETHERMIN
137 #define	MIN_MCAST_NUM			8
138 
139 #define	DEFAULT_NUM_RX_DESCRIPTOR	2048
140 #define	DEFAULT_NUM_TX_DESCRIPTOR	2048
141 #define	DEFAULT_NUM_RX_FREELIST		4096
142 #define	DEFAULT_NUM_TX_FREELIST		2304
143 #define	DEFAULT_JUMBO_NUM_RX_DESC	1024
144 #define	DEFAULT_JUMBO_NUM_TX_DESC	1024
145 #define	DEFAULT_JUMBO_NUM_RX_BUF	2048
146 #define	DEFAULT_JUMBO_NUM_TX_BUF	1152
147 #define	DEFAULT_RX_LIMIT_ON_INTR	128
148 #define	RX_FREELIST_INCREASE_SIZE	512
149 
150 #ifdef __sparc
151 #define	MAX_INTR_PER_SEC		7100
152 #define	MIN_INTR_PER_SEC		3000
153 #define	DEFAULT_INTR_PACKET_LOW		5
154 #define	DEFAULT_INTR_PACKET_HIGH	128
155 #else
156 #define	MAX_INTR_PER_SEC		15000
157 #define	MIN_INTR_PER_SEC		4000
158 #define	DEFAULT_INTR_PACKET_LOW		10
159 #define	DEFAULT_INTR_PACKET_HIGH	48
160 #endif
161 
162 #define	DEFAULT_RX_INTR_DELAY		0
163 #define	DEFAULT_RX_INTR_ABS_DELAY	64
164 #define	DEFAULT_TX_INTR_DELAY		64
165 #define	DEFAULT_TX_INTR_ABS_DELAY	64
166 #define	DEFAULT_INTR_THROTTLING_HIGH    1000000000/(MIN_INTR_PER_SEC*256)
167 #define	DEFAULT_INTR_THROTTLING_LOW	1000000000/(MAX_INTR_PER_SEC*256)
168 #define	DEFAULT_INTR_THROTTLING		DEFAULT_INTR_THROTTLING_LOW
169 
170 #define	DEFAULT_RX_BCOPY_THRESHOLD	128
171 #define	DEFAULT_TX_BCOPY_THRESHOLD	512
172 #define	DEFAULT_TX_UPDATE_THRESHOLD	256
173 #define	DEFAULT_TX_NO_RESOURCE		MAX_TX_DESC_PER_PACKET
174 
175 #define	DEFAULT_TX_INTR_ENABLE		1
176 #define	DEFAULT_FLOW_CONTROL		3
177 #define	DEFAULT_MASTER_LATENCY_TIMER	0	/* BIOS should decide */
178 						/* which is normally 0x040 */
179 #define	DEFAULT_TBI_COMPAT_ENABLE	1	/* Enable SBP workaround */
180 #define	DEFAULT_MSI_ENABLE		1	/* MSI Enable */
181 #define	DEFAULT_TX_HCKSUM_ENABLE	1	/* Hardware checksum enable */
182 #define	DEFAULT_LSO_ENABLE		1	/* LSO enable */
183 #define	DEFAULT_MEM_WORKAROUND_82546	1	/* 82546 memory workaround */
184 
185 #define	TX_DRAIN_TIME		(200)	/* # milliseconds xmit drain */
186 #define	RX_DRAIN_TIME		(200)	/* # milliseconds recv drain */
187 
188 #define	TX_STALL_TIME_2S		(200)	/* in unit of tick */
189 #define	TX_STALL_TIME_8S		(800)	/* in unit of tick */
190 
191 /*
192  * The size of the receive/transmite buffers
193  */
194 #define	E1000_RX_BUFFER_SIZE_2K		(2048)
195 #define	E1000_RX_BUFFER_SIZE_4K		(4096)
196 #define	E1000_RX_BUFFER_SIZE_8K		(8192)
197 #define	E1000_RX_BUFFER_SIZE_16K	(16384)
198 
199 #define	E1000_TX_BUFFER_SIZE_2K		(2048)
200 #define	E1000_TX_BUFFER_SIZE_4K		(4096)
201 #define	E1000_TX_BUFFER_SIZE_8K		(8192)
202 #define	E1000_TX_BUFFER_SIZE_16K	(16384)
203 
204 #define	E1000_TX_BUFFER_OEVRRUN_THRESHOLD	(2015)
205 
206 #define	E1000G_RX_NORMAL		0x0
207 #define	E1000G_RX_STOPPED		0x1
208 
209 #define	E1000G_CHAIN_NO_LIMIT		0
210 
211 /*
212  * definitions for smartspeed workaround
213  */
214 #define	  E1000_SMARTSPEED_MAX		30	/* 30 watchdog iterations */
215 						/* or 30 seconds */
216 #define	  E1000_SMARTSPEED_DOWNSHIFT	6	/* 6 watchdog iterations */
217 						/* or 6 seconds */
218 
219 /*
220  * Definitions for module_info.
221  */
222 #define	 WSNAME			"e1000g"	/* module name */
223 
224 /*
225  * Defined for IP header alignment. We also need to preserve space for
226  * VLAN tag (4 bytes)
227  */
228 #define	E1000G_IPALIGNROOM		2
229 
230 /*
231  * bit flags for 'attach_progress' which is a member variable in struct e1000g
232  */
233 #define	ATTACH_PROGRESS_PCI_CONFIG	0x0001	/* PCI config setup */
234 #define	ATTACH_PROGRESS_REGS_MAP	0x0002	/* Registers mapped */
235 #define	ATTACH_PROGRESS_SETUP		0x0004	/* Setup driver parameters */
236 #define	ATTACH_PROGRESS_ADD_INTR	0x0008	/* Interrupt added */
237 #define	ATTACH_PROGRESS_LOCKS		0x0010	/* Locks initialized */
238 #define	ATTACH_PROGRESS_SOFT_INTR	0x0020	/* Soft interrupt added */
239 #define	ATTACH_PROGRESS_KSTATS		0x0040	/* Kstats created */
240 #define	ATTACH_PROGRESS_ALLOC		0x0080	/* DMA resources allocated */
241 #define	ATTACH_PROGRESS_INIT		0x0100	/* Driver initialization */
242 /* 0200 used to be PROGRESS_NDD. Now unused */
243 #define	ATTACH_PROGRESS_MAC		0x0400	/* MAC registered */
244 #define	ATTACH_PROGRESS_ENABLE_INTR	0x0800	/* DDI interrupts enabled */
245 #define	ATTACH_PROGRESS_FMINIT		0x1000	/* FMA initiated */
246 
247 /*
248  * Speed and Duplex Settings
249  */
250 #define	GDIAG_10_HALF		1
251 #define	GDIAG_10_FULL		2
252 #define	GDIAG_100_HALF		3
253 #define	GDIAG_100_FULL		4
254 #define	GDIAG_1000_FULL		6
255 #define	GDIAG_ANY		7
256 
257 /*
258  * Coexist Workaround RP: 07/04/03
259  * 82544 Workaround : Co-existence
260  */
261 #define	MAX_TX_BUF_SIZE		(8 * 1024)
262 
263 /*
264  * Defines for Jumbo Frame
265  */
266 #define	FRAME_SIZE_UPTO_2K	2048
267 #define	FRAME_SIZE_UPTO_4K	4096
268 #define	FRAME_SIZE_UPTO_8K	8192
269 #define	FRAME_SIZE_UPTO_16K	16384
270 #define	FRAME_SIZE_UPTO_9K	9234
271 
272 #define	DEFAULT_MTU		ETHERMTU
273 #define	MAXIMUM_MTU_4K		4096
274 #define	MAXIMUM_MTU_9K		9216
275 
276 #define	DEFAULT_FRAME_SIZE	\
277 	(DEFAULT_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL)
278 #define	MAXIMUM_FRAME_SIZE	\
279 	(MAXIMUM_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL)
280 
281 #define	E1000_LSO_MAXLEN				65535
282 #define	E1000_LSO_FIRST_DESC_ALIGNMENT_BOUNDARY_4K	4096
283 #define	E1000_LSO_FIRST_DESC_ALIGNMENT			128
284 
285 /* Defines for Tx stall check */
286 #define	E1000G_STALL_WATCHDOG_COUNT	8
287 
288 #define	MAX_TX_LINK_DOWN_TIMEOUT	8
289 
290 /* Defines for DVMA */
291 #ifdef __sparc
292 #define	E1000G_DEFAULT_DVMA_PAGE_NUM	2
293 #endif
294 
295 /*
296  * Loopback definitions
297  */
298 #define	E1000G_LB_NONE			0
299 #define	E1000G_LB_EXTERNAL_1000		1
300 #define	E1000G_LB_EXTERNAL_100		2
301 #define	E1000G_LB_EXTERNAL_10		3
302 #define	E1000G_LB_INTERNAL_PHY		4
303 
304 /*
305  * Private dip list definitions
306  */
307 #define	E1000G_PRIV_DEVI_ATTACH	0x0
308 #define	E1000G_PRIV_DEVI_DETACH	0x1
309 
310 /*
311  * Tx descriptor LENGTH field mask
312  */
313 #define	E1000G_TBD_LENGTH_MASK		0x000fffff
314 
315 #define	E1000G_IS_VLAN_PACKET(ptr)				\
316 	((((struct ether_vlan_header *)(uintptr_t)ptr)->ether_tpid) ==	\
317 	htons(ETHERTYPE_VLAN))
318 
319 /*
320  * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL.
321  */
322 #define	QUEUE_INIT_LIST(_LH)	\
323 	(_LH)->Flink = (_LH)->Blink = (PSINGLE_LIST_LINK)0
324 
325 /*
326  * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty.
327  */
328 #define	IS_QUEUE_EMPTY(_LH)	\
329 	((_LH)->Flink == (PSINGLE_LIST_LINK)0)
330 
331 /*
332  * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does
333  * not remove the head from the queue.
334  */
335 #define	QUEUE_GET_HEAD(_LH)	((PSINGLE_LIST_LINK)((_LH)->Flink))
336 
337 /*
338  * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue.
339  */
340 #define	QUEUE_REMOVE_HEAD(_LH)	\
341 { \
342 	PSINGLE_LIST_LINK ListElem; \
343 	if (ListElem = (_LH)->Flink) \
344 	{ \
345 		if (!((_LH)->Flink = ListElem->Flink)) \
346 			(_LH)->Blink = (PSINGLE_LIST_LINK) 0; \
347 	} \
348 }
349 
350 /*
351  * QUEUE_POP_HEAD -- Macro which  will pop the head off of a queue (list),
352  *	and return it (this differs from QUEUE_REMOVE_HEAD only in
353  *	the 1st line).
354  */
355 #define	QUEUE_POP_HEAD(_LH)	\
356 	(PSINGLE_LIST_LINK)(_LH)->Flink; \
357 	{ \
358 		PSINGLE_LIST_LINK ListElem; \
359 		ListElem = (_LH)->Flink; \
360 		if (ListElem) \
361 		{ \
362 			(_LH)->Flink = ListElem->Flink; \
363 			if (!(_LH)->Flink) \
364 				(_LH)->Blink = (PSINGLE_LIST_LINK)0; \
365 		} \
366 	}
367 
368 /*
369  * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not
370  *	remove the tail from the queue.
371  */
372 #define	QUEUE_GET_TAIL(_LH)	((PSINGLE_LIST_LINK)((_LH)->Blink))
373 
374 /*
375  * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue
376  */
377 #define	QUEUE_PUSH_TAIL(_LH, _E)	\
378 	if ((_LH)->Blink) \
379 	{ \
380 		((PSINGLE_LIST_LINK)(_LH)->Blink)->Flink = \
381 			(PSINGLE_LIST_LINK)(_E); \
382 		(_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \
383 	} else { \
384 		(_LH)->Flink = \
385 			(_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \
386 	} \
387 	(_E)->Flink = (PSINGLE_LIST_LINK)0;
388 
389 /*
390  * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue.
391  */
392 #define	QUEUE_PUSH_HEAD(_LH, _E)	\
393 	if (!((_E)->Flink = (_LH)->Flink)) \
394 	{ \
395 		(_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \
396 	} \
397 	(_LH)->Flink = (PSINGLE_LIST_LINK)(_E);
398 
399 /*
400  * QUEUE_GET_NEXT -- Macro which returns the next element linked to the
401  *	current element.
402  */
403 #define	QUEUE_GET_NEXT(_LH, _E)		\
404 	(PSINGLE_LIST_LINK)((((_LH)->Blink) == (_E)) ? \
405 	(0) : ((_E)->Flink))
406 
407 /*
408  * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue
409  */
410 #define	QUEUE_APPEND(_LH1, _LH2)	\
411 	if ((_LH2)->Flink) { \
412 		if ((_LH1)->Flink) { \
413 			((PSINGLE_LIST_LINK)(_LH1)->Blink)->Flink = \
414 				((PSINGLE_LIST_LINK)(_LH2)->Flink); \
415 		} else { \
416 			(_LH1)->Flink = \
417 				((PSINGLE_LIST_LINK)(_LH2)->Flink); \
418 		} \
419 		(_LH1)->Blink = ((PSINGLE_LIST_LINK)(_LH2)->Blink); \
420 	}
421 
422 
423 #define	QUEUE_SWITCH(_LH1, _LH2)					\
424 	if ((_LH2)->Flink) { 						\
425 		(_LH1)->Flink = (_LH2)->Flink;				\
426 		(_LH1)->Blink = (_LH2)->Blink;				\
427 		(_LH2)->Flink = (_LH2)->Blink = (PSINGLE_LIST_LINK)0;	\
428 	}
429 
430 /*
431  * Property lookups
432  */
433 #define	E1000G_PROP_EXISTS(d, n)	ddi_prop_exists(DDI_DEV_T_ANY, (d), \
434 						DDI_PROP_DONTPASS, (n))
435 #define	E1000G_PROP_GET_INT(d, n)	ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
436 						DDI_PROP_DONTPASS, (n), -1)
437 
438 #ifdef E1000G_DEBUG
439 /*
440  * E1000G-specific ioctls ...
441  */
442 #define	E1000G_IOC		((((((('E' << 4) + '1') << 4) \
443 				+ 'K') << 4) + 'G') << 4)
444 
445 /*
446  * These diagnostic IOCTLS are enabled only in DEBUG drivers
447  */
448 #define	E1000G_IOC_REG_PEEK	(E1000G_IOC | 1)
449 #define	E1000G_IOC_REG_POKE	(E1000G_IOC | 2)
450 #define	E1000G_IOC_CHIP_RESET	(E1000G_IOC | 3)
451 
452 #define	E1000G_PP_SPACE_REG	0	/* PCI memory space	*/
453 #define	E1000G_PP_SPACE_E1000G	1	/* driver's soft state	*/
454 
455 typedef struct {
456 	uint64_t pp_acc_size;	/* It's 1, 2, 4 or 8	*/
457 	uint64_t pp_acc_space;	/* See #defines below	*/
458 	uint64_t pp_acc_offset;	/* See regs definition	*/
459 	uint64_t pp_acc_data;	/* output for peek	*/
460 				/* input for poke	*/
461 } e1000g_peekpoke_t;
462 #endif	/* E1000G_DEBUG */
463 
464 /*
465  * (Internal) return values from ioctl subroutines
466  */
467 enum ioc_reply {
468 	IOC_INVAL = -1,		/* bad, NAK with EINVAL	*/
469 	IOC_DONE,		/* OK, reply sent	*/
470 	IOC_ACK,		/* OK, just send ACK	*/
471 	IOC_REPLY		/* OK, just send reply	*/
472 };
473 
474 /*
475  * Named Data (ND) Parameter Management Structure
476  */
477 typedef struct {
478 	uint32_t ndp_info;
479 	uint32_t ndp_min;
480 	uint32_t ndp_max;
481 	uint32_t ndp_val;
482 	struct e1000g *ndp_instance;
483 	char *ndp_name;
484 } nd_param_t;
485 
486 /*
487  * The entry of the private dip list
488  */
489 typedef struct _private_devi_list {
490 	dev_info_t *priv_dip;
491 	uint32_t flag;
492 	uint32_t pending_rx_count;
493 	struct _private_devi_list *prev;
494 	struct _private_devi_list *next;
495 } private_devi_list_t;
496 
497 /*
498  * A structure that points to the next entry in the queue.
499  */
500 typedef struct _SINGLE_LIST_LINK {
501 	struct _SINGLE_LIST_LINK *Flink;
502 } SINGLE_LIST_LINK, *PSINGLE_LIST_LINK;
503 
504 /*
505  * A "ListHead" structure that points to the head and tail of a queue
506  */
507 typedef struct _LIST_DESCRIBER {
508 	struct _SINGLE_LIST_LINK *volatile Flink;
509 	struct _SINGLE_LIST_LINK *volatile Blink;
510 } LIST_DESCRIBER, *PLIST_DESCRIBER;
511 
512 enum e1000g_bar_type {
513 	E1000G_BAR_CONFIG = 0,
514 	E1000G_BAR_IO,
515 	E1000G_BAR_MEM32,
516 	E1000G_BAR_MEM64
517 };
518 
519 typedef struct {
520 	enum e1000g_bar_type type;
521 	int rnumber;
522 } bar_info_t;
523 
524 /*
525  * Address-Length pair structure that stores descriptor info
526  */
527 typedef struct _sw_desc {
528 	uint64_t address;
529 	uint32_t length;
530 } sw_desc_t, *p_sw_desc_t;
531 
532 typedef struct _desc_array {
533 	sw_desc_t descriptor[4];
534 	uint32_t elements;
535 } desc_array_t, *p_desc_array_t;
536 
537 typedef enum {
538 	USE_NONE,
539 	USE_BCOPY,
540 	USE_DVMA,
541 	USE_DMA
542 } dma_type_t;
543 
544 typedef struct _dma_buffer {
545 	caddr_t address;
546 	uint64_t dma_address;
547 	ddi_acc_handle_t acc_handle;
548 	ddi_dma_handle_t dma_handle;
549 	size_t size;
550 	size_t len;
551 } dma_buffer_t, *p_dma_buffer_t;
552 
553 /*
554  * Transmit Control Block (TCB), Ndis equiv of SWPacket This
555  * structure stores the additional information that is
556  * associated with every packet to be transmitted. It stores the
557  * message block pointer and the TBD addresses associated with
558  * the m_blk and also the link to the next tcb in the chain
559  */
560 typedef struct _tx_sw_packet {
561 	/* Link to the next tx_sw_packet in the list */
562 	SINGLE_LIST_LINK Link;
563 	mblk_t *mp;
564 	uint32_t num_desc;
565 	uint32_t num_mblk_frag;
566 	dma_type_t dma_type;
567 	dma_type_t data_transfer_type;
568 	ddi_dma_handle_t tx_dma_handle;
569 	dma_buffer_t tx_buf[1];
570 	sw_desc_t desc[MAX_TX_DESC_PER_PACKET];
571 	int64_t tickstamp;
572 } tx_sw_packet_t, *p_tx_sw_packet_t;
573 
574 /*
575  * This structure is similar to the rx_sw_packet structure used
576  * for Ndis. This structure stores information about the 2k
577  * aligned receive buffer into which the FX1000 DMA's frames.
578  * This structure is maintained as a linked list of many
579  * receiver buffer pointers.
580  */
581 typedef struct _rx_sw_packet {
582 	/* Link to the next rx_sw_packet_t in the list */
583 	SINGLE_LIST_LINK Link;
584 	struct _rx_sw_packet *next;
585 	uint32_t ref_cnt;
586 	mblk_t *mp;
587 	caddr_t rx_data;
588 	dma_type_t dma_type;
589 	frtn_t free_rtn;
590 	dma_buffer_t rx_buf[1];
591 } rx_sw_packet_t, *p_rx_sw_packet_t;
592 
593 typedef struct _mblk_list {
594 	mblk_t *head;
595 	mblk_t *tail;
596 } mblk_list_t, *p_mblk_list_t;
597 
598 typedef struct _context_data {
599 	uint32_t ether_header_size;
600 	uint32_t cksum_flags;
601 	uint32_t cksum_start;
602 	uint32_t cksum_stuff;
603 	uint16_t mss;
604 	uint8_t hdr_len;
605 	uint32_t pay_len;
606 	boolean_t lso_flag;
607 } context_data_t;
608 
609 typedef union _e1000g_ether_addr {
610 	struct {
611 		uint32_t high;
612 		uint32_t low;
613 	} reg;
614 	struct {
615 		uint8_t set;
616 		uint8_t redundant;
617 		uint8_t addr[ETHERADDRL];
618 	} mac;
619 } e1000g_ether_addr_t;
620 
621 typedef struct _e1000g_stat {
622 	kstat_named_t reset_count;	/* Reset Count */
623 
624 	kstat_named_t rx_error;		/* Rx Error in Packet */
625 	kstat_named_t rx_allocb_fail;	/* Rx Allocb Failure */
626 	kstat_named_t rx_size_error;	/* Rx Size Error */
627 
628 	kstat_named_t tx_no_desc;	/* Tx No Desc */
629 	kstat_named_t tx_no_swpkt;	/* Tx No Pkt Buffer */
630 	kstat_named_t tx_send_fail;	/* Tx SendPkt Failure */
631 	kstat_named_t tx_over_size;	/* Tx Pkt Too Long */
632 	kstat_named_t tx_reschedule;	/* Tx Reschedule */
633 
634 #ifdef E1000G_DEBUG
635 	kstat_named_t rx_none;		/* Rx No Incoming Data */
636 	kstat_named_t rx_multi_desc;	/* Rx Multi Spanned Pkt */
637 	kstat_named_t rx_no_freepkt;	/* Rx No Free Pkt */
638 	kstat_named_t rx_avail_freepkt;	/* Rx Freelist Avail Buffers */
639 
640 	kstat_named_t tx_under_size;	/* Tx Packet Under Size */
641 	kstat_named_t tx_empty_frags;	/* Tx Empty Frags */
642 	kstat_named_t tx_exceed_frags;	/* Tx Exceed Max Frags */
643 	kstat_named_t tx_recycle;	/* Tx Recycle */
644 	kstat_named_t tx_recycle_intr;	/* Tx Recycle in Intr */
645 	kstat_named_t tx_recycle_retry;	/* Tx Recycle Retry */
646 	kstat_named_t tx_recycle_none;	/* Tx No Desc Recycled */
647 	kstat_named_t tx_copy;		/* Tx Send Copy */
648 	kstat_named_t tx_bind;		/* Tx Send Bind */
649 	kstat_named_t tx_multi_copy;	/* Tx Copy Multi Fragments */
650 	kstat_named_t tx_multi_cookie;	/* Tx Pkt Span Multi Cookies */
651 	kstat_named_t tx_lack_desc;	/* Tx Lack of Desc */
652 #endif
653 
654 	kstat_named_t Symerrs;	/* Symbol Error Count */
655 	kstat_named_t Mpc;	/* Missed Packet Count */
656 	kstat_named_t Rlec;	/* Receive Length Error Count */
657 	kstat_named_t Xonrxc;	/* XON Received Count */
658 	kstat_named_t Xontxc;	/* XON Xmitted Count */
659 	kstat_named_t Xoffrxc;	/* XOFF Received Count */
660 	kstat_named_t Xofftxc;	/* Xoff Xmitted Count */
661 	kstat_named_t Fcruc;	/* Unknown Flow Conrol Packet Rcvd Count */
662 #ifdef E1000G_DEBUG
663 	kstat_named_t Prc64;	/* Packets Received - 64b */
664 	kstat_named_t Prc127;	/* Packets Received - 65-127b */
665 	kstat_named_t Prc255;	/* Packets Received - 127-255b */
666 	kstat_named_t Prc511;	/* Packets Received - 256-511b */
667 	kstat_named_t Prc1023;	/* Packets Received - 511-1023b */
668 	kstat_named_t Prc1522;	/* Packets Received - 1024-1522b */
669 #endif
670 	kstat_named_t Gprc;	/* Good Packets Received Count */
671 	kstat_named_t Gptc;	/* Good Packets Xmitted Count */
672 	kstat_named_t Gorl;	/* Good Octets Recvd Lo Count */
673 	kstat_named_t Gorh;	/* Good Octets Recvd Hi Count */
674 	kstat_named_t Gotl;	/* Good Octets Xmitd Lo Count */
675 	kstat_named_t Goth;	/* Good Octets Xmitd Hi Count */
676 	kstat_named_t Rfc;	/* Receive Frag Count */
677 #ifdef E1000G_DEBUG
678 	kstat_named_t Ptc64;	/* Packets Xmitted (64b) */
679 	kstat_named_t Ptc127;	/* Packets Xmitted (64-127b) */
680 	kstat_named_t Ptc255;	/* Packets Xmitted (128-255b) */
681 	kstat_named_t Ptc511;	/* Packets Xmitted (255-511b) */
682 	kstat_named_t Ptc1023;	/* Packets Xmitted (512-1023b) */
683 	kstat_named_t Ptc1522;	/* Packets Xmitted (1024-1522b */
684 #endif
685 	kstat_named_t Tncrs;	/* Transmit with no CRS */
686 	kstat_named_t Tsctc;	/* TCP seg contexts xmit count */
687 	kstat_named_t Tsctfc;	/* TCP seg contexts xmit fail count */
688 } e1000g_stat_t, *p_e1000g_stat_t;
689 
690 typedef struct _e1000g_tx_ring {
691 	kmutex_t tx_lock;
692 	kmutex_t freelist_lock;
693 	kmutex_t usedlist_lock;
694 	/*
695 	 * Descriptor queue definitions
696 	 */
697 	ddi_dma_handle_t tbd_dma_handle;
698 	ddi_acc_handle_t tbd_acc_handle;
699 	struct e1000_tx_desc *tbd_area;
700 	uint64_t tbd_dma_addr;
701 	struct e1000_tx_desc *tbd_first;
702 	struct e1000_tx_desc *tbd_last;
703 	struct e1000_tx_desc *tbd_oldest;
704 	struct e1000_tx_desc *tbd_next;
705 	uint32_t tbd_avail;
706 	/*
707 	 * Software packet structures definitions
708 	 */
709 	p_tx_sw_packet_t packet_area;
710 	LIST_DESCRIBER used_list;
711 	LIST_DESCRIBER free_list;
712 	/*
713 	 * TCP/UDP Context Data Information
714 	 */
715 	context_data_t pre_context;
716 	/*
717 	 * Timer definitions for 82547
718 	 */
719 	timeout_id_t timer_id_82547;
720 	boolean_t timer_enable_82547;
721 	/*
722 	 * reschedule when tx resource is available
723 	 */
724 	boolean_t resched_needed;
725 	clock_t resched_timestamp;
726 	mblk_list_t mblks;
727 	/*
728 	 * Statistics
729 	 */
730 	uint32_t stat_no_swpkt;
731 	uint32_t stat_no_desc;
732 	uint32_t stat_send_fail;
733 	uint32_t stat_reschedule;
734 	uint32_t stat_timer_reschedule;
735 	uint32_t stat_over_size;
736 #ifdef E1000G_DEBUG
737 	uint32_t stat_under_size;
738 	uint32_t stat_exceed_frags;
739 	uint32_t stat_empty_frags;
740 	uint32_t stat_recycle;
741 	uint32_t stat_recycle_intr;
742 	uint32_t stat_recycle_retry;
743 	uint32_t stat_recycle_none;
744 	uint32_t stat_copy;
745 	uint32_t stat_bind;
746 	uint32_t stat_multi_copy;
747 	uint32_t stat_multi_cookie;
748 	uint32_t stat_lack_desc;
749 	uint32_t stat_lso_header_fail;
750 #endif
751 	/*
752 	 * Pointer to the adapter
753 	 */
754 	struct e1000g *adapter;
755 } e1000g_tx_ring_t, *pe1000g_tx_ring_t;
756 
757 typedef struct _e1000g_rx_data {
758 	kmutex_t freelist_lock;
759 	kmutex_t recycle_lock;
760 	/*
761 	 * Descriptor queue definitions
762 	 */
763 	ddi_dma_handle_t rbd_dma_handle;
764 	ddi_acc_handle_t rbd_acc_handle;
765 	struct e1000_rx_desc *rbd_area;
766 	uint64_t rbd_dma_addr;
767 	struct e1000_rx_desc *rbd_first;
768 	struct e1000_rx_desc *rbd_last;
769 	struct e1000_rx_desc *rbd_next;
770 	/*
771 	 * Software packet structures definitions
772 	 */
773 	p_rx_sw_packet_t packet_area;
774 	LIST_DESCRIBER recv_list;
775 	LIST_DESCRIBER free_list;
776 	LIST_DESCRIBER recycle_list;
777 	uint32_t flag;
778 
779 	uint32_t pending_count;
780 	uint32_t avail_freepkt;
781 	uint32_t recycle_freepkt;
782 	uint32_t rx_mblk_len;
783 	mblk_t *rx_mblk;
784 	mblk_t *rx_mblk_tail;
785 
786 	private_devi_list_t *priv_devi_node;
787 	struct _e1000g_rx_ring *rx_ring;
788 } e1000g_rx_data_t;
789 
790 typedef struct _e1000g_rx_ring {
791 	e1000g_rx_data_t *rx_data;
792 
793 	kmutex_t rx_lock;
794 
795 	mac_ring_handle_t mrh;
796 	mac_ring_handle_t mrh_init;
797 	uint64_t ring_gen_num;
798 	boolean_t poll_flag;
799 
800 	/*
801 	 * Statistics
802 	 */
803 	uint32_t stat_error;
804 	uint32_t stat_allocb_fail;
805 	uint32_t stat_exceed_pkt;
806 	uint32_t stat_size_error;
807 	uint32_t stat_crc_only_pkt;
808 #ifdef E1000G_DEBUG
809 	uint32_t stat_none;
810 	uint32_t stat_multi_desc;
811 	uint32_t stat_no_freepkt;
812 #endif
813 	/*
814 	 * Pointer to the adapter
815 	 */
816 	struct e1000g *adapter;
817 } e1000g_rx_ring_t, *pe1000g_rx_ring_t;
818 
819 typedef struct e1000g {
820 	int instance;
821 	dev_info_t *dip;
822 	dev_info_t *priv_dip;
823 	private_devi_list_t *priv_devi_node;
824 	mac_handle_t mh;
825 	mac_resource_handle_t mrh;
826 	struct e1000_hw shared;
827 	struct e1000g_osdep osdep;
828 
829 	uint32_t e1000g_state;
830 	boolean_t e1000g_promisc;
831 	boolean_t strip_crc;
832 	boolean_t rx_buffer_setup;
833 	boolean_t esb2_workaround;
834 	link_state_t link_state;
835 	uint64_t link_speed;
836 	uint32_t link_duplex;
837 	uint32_t master_latency_timer;
838 	uint32_t smartspeed;	/* smartspeed w/a counter */
839 	uint32_t init_count;
840 	uint32_t reset_count;
841 	boolean_t reset_flag;
842 	uint32_t stall_threshold;
843 	boolean_t stall_flag;
844 	uint32_t attach_progress;	/* attach tracking */
845 	uint32_t loopback_mode;
846 	uint32_t pending_rx_count;
847 
848 	uint32_t align_errors;
849 	uint32_t brdcstrcv;
850 	uint32_t brdcstxmt;
851 	uint32_t carrier_errors;
852 	uint32_t collisions;
853 	uint32_t defer_xmts;
854 	uint32_t ex_collisions;
855 	uint32_t fcs_errors;
856 	uint32_t first_collisions;
857 	uint32_t ipackets;
858 	uint32_t jabber_errors;
859 	uint32_t macrcv_errors;
860 	uint32_t macxmt_errors;
861 	uint32_t multi_collisions;
862 	uint32_t multircv;
863 	uint32_t multixmt;
864 	uint32_t norcvbuf;
865 	uint32_t oerrors;
866 	uint32_t opackets;
867 	uint32_t sqe_errors;
868 	uint32_t toolong_errors;
869 	uint32_t tooshort_errors;
870 	uint32_t tx_late_collisions;
871 	uint64_t obytes;
872 	uint64_t rbytes;
873 
874 	uint32_t tx_desc_num;
875 	uint32_t tx_freelist_num;
876 	uint32_t rx_desc_num;
877 	uint32_t rx_freelist_num;
878 	uint32_t rx_freelist_limit;
879 	uint32_t tx_buffer_size;
880 	uint32_t rx_buffer_size;
881 
882 	uint32_t tx_link_down_timeout;
883 	uint32_t tx_bcopy_thresh;
884 	uint32_t rx_limit_onintr;
885 	uint32_t rx_bcopy_thresh;
886 	uint32_t rx_buf_align;
887 	uint32_t desc_align;
888 
889 	boolean_t intr_adaptive;
890 	boolean_t tx_intr_enable;
891 	uint32_t tx_intr_delay;
892 	uint32_t tx_intr_abs_delay;
893 	uint32_t rx_intr_delay;
894 	uint32_t rx_intr_abs_delay;
895 	uint32_t intr_throttling_rate;
896 
897 	uint32_t	tx_desc_num_flag:1,
898 			rx_desc_num_flag:1,
899 			tx_buf_num_flag:1,
900 			rx_buf_num_flag:1,
901 			pad_to_32:28;
902 
903 	uint32_t default_mtu;
904 	uint32_t max_mtu;
905 	uint32_t max_frame_size;
906 	uint32_t min_frame_size;
907 
908 	boolean_t watchdog_timer_enabled;
909 	boolean_t watchdog_timer_started;
910 	timeout_id_t watchdog_tid;
911 	boolean_t link_complete;
912 	timeout_id_t link_tid;
913 
914 	e1000g_rx_ring_t rx_ring[1];
915 	e1000g_tx_ring_t tx_ring[1];
916 	mac_group_handle_t rx_group;
917 
918 	/*
919 	 * Rx and Tx packet count for interrupt adaptive setting
920 	 */
921 	uint32_t rx_pkt_cnt;
922 	uint32_t tx_pkt_cnt;
923 
924 	/*
925 	 * The watchdog_lock must be held when updateing the
926 	 * timeout fields in struct e1000g, that is,
927 	 * watchdog_tid, watchdog_timer_started.
928 	 */
929 	kmutex_t watchdog_lock;
930 	/*
931 	 * The link_lock protects the link_complete and link_tid
932 	 * fields in struct e1000g.
933 	 */
934 	kmutex_t link_lock;
935 	/*
936 	 * The chip_lock assures that the Rx/Tx process must be
937 	 * stopped while other functions change the hardware
938 	 * configuration of e1000g card, such as e1000g_reset(),
939 	 * e1000g_reset_hw() etc are executed.
940 	 */
941 	krwlock_t chip_lock;
942 
943 	boolean_t unicst_init;
944 	uint32_t unicst_avail;
945 	uint32_t unicst_total;
946 	e1000g_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES];
947 
948 	uint32_t mcast_count;
949 	uint32_t mcast_max_num;
950 	uint32_t mcast_alloc_count;
951 	struct ether_addr *mcast_table;
952 
953 	ulong_t sys_page_sz;
954 #ifdef __sparc
955 	uint_t dvma_page_num;
956 #endif
957 
958 	boolean_t msi_enable;
959 	boolean_t tx_hcksum_enable;
960 	boolean_t lso_enable;
961 	boolean_t lso_premature_issue;
962 	boolean_t mem_workaround_82546;
963 	int intr_type;
964 	int intr_cnt;
965 	int intr_cap;
966 	size_t intr_size;
967 	uint_t intr_pri;
968 	ddi_intr_handle_t *htable;
969 
970 	int tx_softint_pri;
971 	ddi_softint_handle_t tx_softint_handle;
972 
973 	kstat_t *e1000g_ksp;
974 
975 	boolean_t poll_mode;
976 
977 	uint16_t phy_ctrl;		/* contents of PHY_CTRL */
978 	uint16_t phy_status;		/* contents of PHY_STATUS */
979 	uint16_t phy_an_adv;		/* contents of PHY_AUTONEG_ADV */
980 	uint16_t phy_an_exp;		/* contents of PHY_AUTONEG_EXP */
981 	uint16_t phy_ext_status;	/* contents of PHY_EXT_STATUS */
982 	uint16_t phy_1000t_ctrl;	/* contents of PHY_1000T_CTRL */
983 	uint16_t phy_1000t_status;	/* contents of PHY_1000T_STATUS */
984 	uint16_t phy_lp_able;		/* contents of PHY_LP_ABILITY */
985 
986 	/*
987 	 * FMA capabilities
988 	 */
989 	int fm_capabilities;
990 
991 	uint32_t	param_en_1000fdx:1,
992 			param_en_1000hdx:1,
993 			param_en_100fdx:1,
994 			param_en_100hdx:1,
995 			param_en_10fdx:1,
996 			param_en_10hdx:1,
997 			param_autoneg_cap:1,
998 			param_pause_cap:1,
999 			param_asym_pause_cap:1,
1000 			param_1000fdx_cap:1,
1001 			param_1000hdx_cap:1,
1002 			param_100t4_cap:1,
1003 			param_100fdx_cap:1,
1004 			param_100hdx_cap:1,
1005 			param_10fdx_cap:1,
1006 			param_10hdx_cap:1,
1007 			param_adv_autoneg:1,
1008 			param_adv_pause:1,
1009 			param_adv_asym_pause:1,
1010 			param_adv_1000fdx:1,
1011 			param_adv_1000hdx:1,
1012 			param_adv_100t4:1,
1013 			param_adv_100fdx:1,
1014 			param_adv_100hdx:1,
1015 			param_adv_10fdx:1,
1016 			param_adv_10hdx:1,
1017 			param_lp_autoneg:1,
1018 			param_lp_pause:1,
1019 			param_lp_asym_pause:1,
1020 			param_lp_1000fdx:1,
1021 			param_lp_1000hdx:1,
1022 			param_lp_100t4:1;
1023 
1024 	uint32_t	param_lp_100fdx:1,
1025 			param_lp_100hdx:1,
1026 			param_lp_10fdx:1,
1027 			param_lp_10hdx:1,
1028 			param_pad_to_32:28;
1029 
1030 } e1000g_t;
1031 
1032 
1033 /*
1034  * Function prototypes
1035  */
1036 void e1000g_free_priv_devi_node(private_devi_list_t *devi_node);
1037 void e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data);
1038 void e1000g_free_rx_data(e1000g_rx_data_t *rx_data);
1039 int e1000g_alloc_dma_resources(struct e1000g *Adapter);
1040 void e1000g_release_dma_resources(struct e1000g *Adapter);
1041 void e1000g_free_rx_sw_packet(p_rx_sw_packet_t packet, boolean_t full_release);
1042 void e1000g_tx_setup(struct e1000g *Adapter);
1043 void e1000g_rx_setup(struct e1000g *Adapter);
1044 int e1000g_increase_rx_packets(e1000g_rx_data_t *rx_data);
1045 
1046 int e1000g_recycle(e1000g_tx_ring_t *tx_ring);
1047 void e1000g_free_tx_swpkt(p_tx_sw_packet_t packet);
1048 void e1000g_tx_freemsg(e1000g_tx_ring_t *tx_ring);
1049 uint_t e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2);
1050 mblk_t *e1000g_m_tx(void *arg, mblk_t *mp);
1051 mblk_t *e1000g_receive(e1000g_rx_ring_t *rx_ring, mblk_t **tail, uint_t sz);
1052 void e1000g_rxfree_func(p_rx_sw_packet_t packet);
1053 
1054 int e1000g_m_stat(void *arg, uint_t stat, uint64_t *val);
1055 int e1000g_init_stats(struct e1000g *Adapter);
1056 int e1000g_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
1057 void e1000_tbi_adjust_stats(struct e1000g *Adapter,
1058     uint32_t frame_len, uint8_t *mac_addr);
1059 
1060 void e1000g_clear_interrupt(struct e1000g *Adapter);
1061 void e1000g_mask_interrupt(struct e1000g *Adapter);
1062 void e1000g_clear_all_interrupts(struct e1000g *Adapter);
1063 void e1000g_clear_tx_interrupt(struct e1000g *Adapter);
1064 void e1000g_mask_tx_interrupt(struct e1000g *Adapter);
1065 void phy_spd_state(struct e1000_hw *hw, boolean_t enable);
1066 void e1000_destroy_hw_mutex(struct e1000_hw *hw);
1067 void e1000_enable_pciex_master(struct e1000_hw *hw);
1068 int e1000g_check_acc_handle(ddi_acc_handle_t handle);
1069 int e1000g_check_dma_handle(ddi_dma_handle_t handle);
1070 void e1000g_fm_ereport(struct e1000g *Adapter, char *detail);
1071 void e1000g_set_fma_flags(int dma_flag);
1072 int e1000g_reset_link(struct e1000g *Adapter);
1073 
1074 /*
1075  * Global variables
1076  */
1077 extern boolean_t e1000g_force_detach;
1078 extern uint32_t e1000g_mblks_pending;
1079 extern kmutex_t e1000g_rx_detach_lock;
1080 extern private_devi_list_t *e1000g_private_devi_list;
1081 extern int e1000g_poll_mode;
1082 
1083 #ifdef __cplusplus
1084 }
1085 #endif
1086 
1087 #endif	/* _E1000G_SW_H */
1088