1 /*-
2 * Copyright (c) 2014-2016 Jared D. McNeill <jmcneill@invisible.ca>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 */
27
28 /*
29 * Allwinner A10/A20 DMA controller
30 */
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/rman.h>
36 #include <sys/condvar.h>
37 #include <sys/kernel.h>
38 #include <sys/lock.h>
39 #include <sys/module.h>
40 #include <sys/mutex.h>
41
42 #include <machine/bus.h>
43
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46
47 #include <arm/allwinner/a10_dmac.h>
48 #include <dev/clk/clk.h>
49
50 #include "sunxi_dma_if.h"
51
52 #define NDMA_CHANNELS 8
53 #define DDMA_CHANNELS 8
54
55 enum a10dmac_type {
56 CH_NDMA,
57 CH_DDMA
58 };
59
60 struct a10dmac_softc;
61
62 struct a10dmac_channel {
63 struct a10dmac_softc * ch_sc;
64 uint8_t ch_index;
65 enum a10dmac_type ch_type;
66 void (*ch_callback)(void *);
67 void * ch_callbackarg;
68 uint32_t ch_regoff;
69 };
70
71 struct a10dmac_softc {
72 struct resource * sc_res[2];
73 struct mtx sc_mtx;
74 void * sc_ih;
75
76 struct a10dmac_channel sc_ndma_channels[NDMA_CHANNELS];
77 struct a10dmac_channel sc_ddma_channels[DDMA_CHANNELS];
78 };
79
80 static struct resource_spec a10dmac_spec[] = {
81 { SYS_RES_MEMORY, 0, RF_ACTIVE },
82 { SYS_RES_IRQ, 0, RF_ACTIVE },
83 { -1, 0 }
84 };
85
86 #define DMA_READ(sc, reg) bus_read_4((sc)->sc_res[0], (reg))
87 #define DMA_WRITE(sc, reg, val) bus_write_4((sc)->sc_res[0], (reg), (val))
88 #define DMACH_READ(ch, reg) \
89 DMA_READ((ch)->ch_sc, (reg) + (ch)->ch_regoff)
90 #define DMACH_WRITE(ch, reg, val) \
91 DMA_WRITE((ch)->ch_sc, (reg) + (ch)->ch_regoff, (val))
92
93 static void a10dmac_intr(void *);
94
95 static int
a10dmac_probe(device_t dev)96 a10dmac_probe(device_t dev)
97 {
98 if (!ofw_bus_status_okay(dev))
99 return (ENXIO);
100
101 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-dma"))
102 return (ENXIO);
103
104 device_set_desc(dev, "Allwinner DMA controller");
105 return (BUS_PROBE_DEFAULT);
106 }
107
108 static int
a10dmac_attach(device_t dev)109 a10dmac_attach(device_t dev)
110 {
111 struct a10dmac_softc *sc;
112 unsigned int index;
113 clk_t clk;
114 int error;
115
116 sc = device_get_softc(dev);
117
118 if (bus_alloc_resources(dev, a10dmac_spec, sc->sc_res)) {
119 device_printf(dev, "cannot allocate resources for device\n");
120 return (ENXIO);
121 }
122
123 mtx_init(&sc->sc_mtx, "a10 dmac", NULL, MTX_SPIN);
124
125 /* Activate DMA controller clock */
126 error = clk_get_by_ofw_index(dev, 0, 0, &clk);
127 if (error != 0) {
128 device_printf(dev, "cannot get clock\n");
129 return (error);
130 }
131 error = clk_enable(clk);
132 if (error != 0) {
133 device_printf(dev, "cannot enable clock\n");
134 return (error);
135 }
136
137 /* Disable all interrupts and clear pending status */
138 DMA_WRITE(sc, AWIN_DMA_IRQ_EN_REG, 0);
139 DMA_WRITE(sc, AWIN_DMA_IRQ_PEND_STA_REG, ~0);
140
141 /* Initialize channels */
142 for (index = 0; index < NDMA_CHANNELS; index++) {
143 sc->sc_ndma_channels[index].ch_sc = sc;
144 sc->sc_ndma_channels[index].ch_index = index;
145 sc->sc_ndma_channels[index].ch_type = CH_NDMA;
146 sc->sc_ndma_channels[index].ch_callback = NULL;
147 sc->sc_ndma_channels[index].ch_callbackarg = NULL;
148 sc->sc_ndma_channels[index].ch_regoff = AWIN_NDMA_REG(index);
149 DMACH_WRITE(&sc->sc_ndma_channels[index], AWIN_NDMA_CTL_REG, 0);
150 }
151 for (index = 0; index < DDMA_CHANNELS; index++) {
152 sc->sc_ddma_channels[index].ch_sc = sc;
153 sc->sc_ddma_channels[index].ch_index = index;
154 sc->sc_ddma_channels[index].ch_type = CH_DDMA;
155 sc->sc_ddma_channels[index].ch_callback = NULL;
156 sc->sc_ddma_channels[index].ch_callbackarg = NULL;
157 sc->sc_ddma_channels[index].ch_regoff = AWIN_DDMA_REG(index);
158 DMACH_WRITE(&sc->sc_ddma_channels[index], AWIN_DDMA_CTL_REG, 0);
159 }
160
161 error = bus_setup_intr(dev, sc->sc_res[1], INTR_MPSAFE | INTR_TYPE_MISC,
162 NULL, a10dmac_intr, sc, &sc->sc_ih);
163 if (error != 0) {
164 device_printf(dev, "could not setup interrupt handler\n");
165 bus_release_resources(dev, a10dmac_spec, sc->sc_res);
166 mtx_destroy(&sc->sc_mtx);
167 return (ENXIO);
168 }
169
170 OF_device_register_xref(OF_xref_from_node(ofw_bus_get_node(dev)), dev);
171 return (0);
172 }
173
174 static void
a10dmac_intr(void * priv)175 a10dmac_intr(void *priv)
176 {
177 struct a10dmac_softc *sc = priv;
178 uint32_t sta, bit, mask;
179 uint8_t index;
180
181 sta = DMA_READ(sc, AWIN_DMA_IRQ_PEND_STA_REG);
182 DMA_WRITE(sc, AWIN_DMA_IRQ_PEND_STA_REG, sta);
183
184 while ((bit = ffs(sta & AWIN_DMA_IRQ_END_MASK)) != 0) {
185 mask = (1U << (bit - 1));
186 sta &= ~mask;
187 /*
188 * Map status bit to channel number. The status register is
189 * encoded with two bits of status per channel (lowest bit
190 * is half transfer pending, highest bit is end transfer
191 * pending). The 8 normal DMA channel status are in the lower
192 * 16 bits and the 8 dedicated DMA channel status are in
193 * the upper 16 bits. The output is a channel number from 0-7.
194 */
195 index = ((bit - 1) / 2) & 7;
196 if (mask & AWIN_DMA_IRQ_NDMA) {
197 if (sc->sc_ndma_channels[index].ch_callback == NULL)
198 continue;
199 sc->sc_ndma_channels[index].ch_callback(
200 sc->sc_ndma_channels[index].ch_callbackarg);
201 } else {
202 if (sc->sc_ddma_channels[index].ch_callback == NULL)
203 continue;
204 sc->sc_ddma_channels[index].ch_callback(
205 sc->sc_ddma_channels[index].ch_callbackarg);
206 }
207 }
208 }
209
210 static uint32_t
a10dmac_read_ctl(struct a10dmac_channel * ch)211 a10dmac_read_ctl(struct a10dmac_channel *ch)
212 {
213 if (ch->ch_type == CH_NDMA) {
214 return (DMACH_READ(ch, AWIN_NDMA_CTL_REG));
215 } else {
216 return (DMACH_READ(ch, AWIN_DDMA_CTL_REG));
217 }
218 }
219
220 static void
a10dmac_write_ctl(struct a10dmac_channel * ch,uint32_t val)221 a10dmac_write_ctl(struct a10dmac_channel *ch, uint32_t val)
222 {
223 if (ch->ch_type == CH_NDMA) {
224 DMACH_WRITE(ch, AWIN_NDMA_CTL_REG, val);
225 } else {
226 DMACH_WRITE(ch, AWIN_DDMA_CTL_REG, val);
227 }
228 }
229
230 static int
a10dmac_set_config(device_t dev,void * priv,const struct sunxi_dma_config * cfg)231 a10dmac_set_config(device_t dev, void *priv, const struct sunxi_dma_config *cfg)
232 {
233 struct a10dmac_channel *ch = priv;
234 uint32_t val;
235 unsigned int dst_dw, dst_bl, dst_bs, dst_wc, dst_am;
236 unsigned int src_dw, src_bl, src_bs, src_wc, src_am;
237
238 switch (cfg->dst_width) {
239 case 8:
240 dst_dw = AWIN_DMA_CTL_DATA_WIDTH_8;
241 break;
242 case 16:
243 dst_dw = AWIN_DMA_CTL_DATA_WIDTH_16;
244 break;
245 case 32:
246 dst_dw = AWIN_DMA_CTL_DATA_WIDTH_32;
247 break;
248 default:
249 return (EINVAL);
250 }
251 switch (cfg->dst_burst_len) {
252 case 1:
253 dst_bl = AWIN_DMA_CTL_BURST_LEN_1;
254 break;
255 case 4:
256 dst_bl = AWIN_DMA_CTL_BURST_LEN_4;
257 break;
258 case 8:
259 dst_bl = AWIN_DMA_CTL_BURST_LEN_8;
260 break;
261 default:
262 return (EINVAL);
263 }
264 switch (cfg->src_width) {
265 case 8:
266 src_dw = AWIN_DMA_CTL_DATA_WIDTH_8;
267 break;
268 case 16:
269 src_dw = AWIN_DMA_CTL_DATA_WIDTH_16;
270 break;
271 case 32:
272 src_dw = AWIN_DMA_CTL_DATA_WIDTH_32;
273 break;
274 default:
275 return (EINVAL);
276 }
277 switch (cfg->src_burst_len) {
278 case 1:
279 src_bl = AWIN_DMA_CTL_BURST_LEN_1;
280 break;
281 case 4:
282 src_bl = AWIN_DMA_CTL_BURST_LEN_4;
283 break;
284 case 8:
285 src_bl = AWIN_DMA_CTL_BURST_LEN_8;
286 break;
287 default:
288 return (EINVAL);
289 }
290
291 val = (dst_dw << AWIN_DMA_CTL_DST_DATA_WIDTH_SHIFT) |
292 (dst_bl << AWIN_DMA_CTL_DST_BURST_LEN_SHIFT) |
293 (cfg->dst_drqtype << AWIN_DMA_CTL_DST_DRQ_TYPE_SHIFT) |
294 (src_dw << AWIN_DMA_CTL_SRC_DATA_WIDTH_SHIFT) |
295 (src_bl << AWIN_DMA_CTL_SRC_BURST_LEN_SHIFT) |
296 (cfg->src_drqtype << AWIN_DMA_CTL_SRC_DRQ_TYPE_SHIFT);
297
298 if (ch->ch_type == CH_NDMA) {
299 if (cfg->dst_noincr)
300 val |= AWIN_NDMA_CTL_DST_ADDR_NOINCR;
301 if (cfg->src_noincr)
302 val |= AWIN_NDMA_CTL_SRC_ADDR_NOINCR;
303
304 DMACH_WRITE(ch, AWIN_NDMA_CTL_REG, val);
305 } else {
306 dst_am = cfg->dst_noincr ? AWIN_DDMA_CTL_DMA_ADDR_IO :
307 AWIN_DDMA_CTL_DMA_ADDR_LINEAR;
308 src_am = cfg->src_noincr ? AWIN_DDMA_CTL_DMA_ADDR_IO :
309 AWIN_DDMA_CTL_DMA_ADDR_LINEAR;
310
311 val |= (dst_am << AWIN_DDMA_CTL_DST_ADDR_MODE_SHIFT);
312 val |= (src_am << AWIN_DDMA_CTL_SRC_ADDR_MODE_SHIFT);
313
314 DMACH_WRITE(ch, AWIN_DDMA_CTL_REG, val);
315
316 dst_bs = cfg->dst_blksize - 1;
317 dst_wc = cfg->dst_wait_cyc - 1;
318 src_bs = cfg->src_blksize - 1;
319 src_wc = cfg->src_wait_cyc - 1;
320
321 DMACH_WRITE(ch, AWIN_DDMA_PARA_REG,
322 (dst_bs << AWIN_DDMA_PARA_DST_DATA_BLK_SIZ_SHIFT) |
323 (dst_wc << AWIN_DDMA_PARA_DST_WAIT_CYC_SHIFT) |
324 (src_bs << AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ_SHIFT) |
325 (src_wc << AWIN_DDMA_PARA_SRC_WAIT_CYC_SHIFT));
326 }
327
328 return (0);
329 }
330
331 static void *
a10dmac_alloc(device_t dev,bool dedicated,void (* cb)(void *),void * cbarg)332 a10dmac_alloc(device_t dev, bool dedicated, void (*cb)(void *), void *cbarg)
333 {
334 struct a10dmac_softc *sc = device_get_softc(dev);
335 struct a10dmac_channel *ch_list;
336 struct a10dmac_channel *ch = NULL;
337 uint32_t irqen;
338 uint8_t ch_count, index;
339
340 if (dedicated) {
341 ch_list = sc->sc_ddma_channels;
342 ch_count = DDMA_CHANNELS;
343 } else {
344 ch_list = sc->sc_ndma_channels;
345 ch_count = NDMA_CHANNELS;
346 }
347
348 mtx_lock_spin(&sc->sc_mtx);
349 for (index = 0; index < ch_count; index++) {
350 if (ch_list[index].ch_callback == NULL) {
351 ch = &ch_list[index];
352 ch->ch_callback = cb;
353 ch->ch_callbackarg = cbarg;
354
355 irqen = DMA_READ(sc, AWIN_DMA_IRQ_EN_REG);
356 if (ch->ch_type == CH_NDMA)
357 irqen |= AWIN_DMA_IRQ_NDMA_END(index);
358 else
359 irqen |= AWIN_DMA_IRQ_DDMA_END(index);
360 DMA_WRITE(sc, AWIN_DMA_IRQ_EN_REG, irqen);
361
362 break;
363 }
364 }
365 mtx_unlock_spin(&sc->sc_mtx);
366
367 return (ch);
368 }
369
370 static void
a10dmac_free(device_t dev,void * priv)371 a10dmac_free(device_t dev, void *priv)
372 {
373 struct a10dmac_channel *ch = priv;
374 struct a10dmac_softc *sc = ch->ch_sc;
375 uint32_t irqen, sta, cfg;
376
377 mtx_lock_spin(&sc->sc_mtx);
378
379 irqen = DMA_READ(sc, AWIN_DMA_IRQ_EN_REG);
380 cfg = a10dmac_read_ctl(ch);
381 if (ch->ch_type == CH_NDMA) {
382 sta = AWIN_DMA_IRQ_NDMA_END(ch->ch_index);
383 cfg &= ~AWIN_NDMA_CTL_DMA_LOADING;
384 } else {
385 sta = AWIN_DMA_IRQ_DDMA_END(ch->ch_index);
386 cfg &= ~AWIN_DDMA_CTL_DMA_LOADING;
387 }
388 irqen &= ~sta;
389 a10dmac_write_ctl(ch, cfg);
390 DMA_WRITE(sc, AWIN_DMA_IRQ_EN_REG, irqen);
391 DMA_WRITE(sc, AWIN_DMA_IRQ_PEND_STA_REG, sta);
392
393 ch->ch_callback = NULL;
394 ch->ch_callbackarg = NULL;
395
396 mtx_unlock_spin(&sc->sc_mtx);
397 }
398
399 static int
a10dmac_transfer(device_t dev,void * priv,bus_addr_t src,bus_addr_t dst,size_t nbytes)400 a10dmac_transfer(device_t dev, void *priv, bus_addr_t src, bus_addr_t dst,
401 size_t nbytes)
402 {
403 struct a10dmac_channel *ch = priv;
404 uint32_t cfg;
405
406 cfg = a10dmac_read_ctl(ch);
407 if (ch->ch_type == CH_NDMA) {
408 if (cfg & AWIN_NDMA_CTL_DMA_LOADING)
409 return (EBUSY);
410
411 DMACH_WRITE(ch, AWIN_NDMA_SRC_ADDR_REG, src);
412 DMACH_WRITE(ch, AWIN_NDMA_DEST_ADDR_REG, dst);
413 DMACH_WRITE(ch, AWIN_NDMA_BC_REG, nbytes);
414
415 cfg |= AWIN_NDMA_CTL_DMA_LOADING;
416 a10dmac_write_ctl(ch, cfg);
417 } else {
418 if (cfg & AWIN_DDMA_CTL_DMA_LOADING)
419 return (EBUSY);
420
421 DMACH_WRITE(ch, AWIN_DDMA_SRC_START_ADDR_REG, src);
422 DMACH_WRITE(ch, AWIN_DDMA_DEST_START_ADDR_REG, dst);
423 DMACH_WRITE(ch, AWIN_DDMA_BC_REG, nbytes);
424
425 cfg |= AWIN_DDMA_CTL_DMA_LOADING;
426 a10dmac_write_ctl(ch, cfg);
427 }
428
429 return (0);
430 }
431
432 static void
a10dmac_halt(device_t dev,void * priv)433 a10dmac_halt(device_t dev, void *priv)
434 {
435 struct a10dmac_channel *ch = priv;
436 uint32_t cfg;
437
438 cfg = a10dmac_read_ctl(ch);
439 if (ch->ch_type == CH_NDMA) {
440 cfg &= ~AWIN_NDMA_CTL_DMA_LOADING;
441 } else {
442 cfg &= ~AWIN_DDMA_CTL_DMA_LOADING;
443 }
444 a10dmac_write_ctl(ch, cfg);
445 }
446
447 static device_method_t a10dmac_methods[] = {
448 /* Device interface */
449 DEVMETHOD(device_probe, a10dmac_probe),
450 DEVMETHOD(device_attach, a10dmac_attach),
451
452 /* sunxi DMA interface */
453 DEVMETHOD(sunxi_dma_alloc, a10dmac_alloc),
454 DEVMETHOD(sunxi_dma_free, a10dmac_free),
455 DEVMETHOD(sunxi_dma_set_config, a10dmac_set_config),
456 DEVMETHOD(sunxi_dma_transfer, a10dmac_transfer),
457 DEVMETHOD(sunxi_dma_halt, a10dmac_halt),
458
459 DEVMETHOD_END
460 };
461
462 static driver_t a10dmac_driver = {
463 "a10dmac",
464 a10dmac_methods,
465 sizeof(struct a10dmac_softc)
466 };
467
468 DRIVER_MODULE(a10dmac, simplebus, a10dmac_driver, 0, 0);
469