1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * Vybrid Family Display Control Unit (DCU4)
31 * Chapter 55, Vybrid Reference Manual, Rev. 5, 07/2013
32 */
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/bus.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
39 #include <sys/malloc.h>
40 #include <sys/rman.h>
41 #include <sys/timeet.h>
42 #include <sys/timetc.h>
43 #include <sys/watchdog.h>
44 #include <sys/fbio.h>
45 #include <sys/consio.h>
46 #include <sys/eventhandler.h>
47 #include <sys/gpio.h>
48
49 #include <vm/vm.h>
50 #include <vm/pmap.h>
51
52 #include <dev/ofw/openfirm.h>
53 #include <dev/ofw/ofw_bus.h>
54 #include <dev/ofw/ofw_bus_subr.h>
55
56 #include <dev/vt/vt.h>
57 #include <dev/vt/colors/vt_termcolors.h>
58
59 #include "gpio_if.h"
60
61 #include <machine/bus.h>
62 #include <machine/fdt.h>
63 #include <machine/cpu.h>
64 #include <machine/intr.h>
65
66 #include "fb_if.h"
67
68 #include <arm/freescale/vybrid/vf_common.h>
69
70 #define DCU_CTRLDESCCURSOR1 0x000 /* Control Descriptor Cursor 1 */
71 #define DCU_CTRLDESCCURSOR2 0x004 /* Control Descriptor Cursor 2 */
72 #define DCU_CTRLDESCCURSOR3 0x008 /* Control Descriptor Cursor 3 */
73 #define DCU_CTRLDESCCURSOR4 0x00C /* Control Descriptor Cursor 4 */
74 #define DCU_DCU_MODE 0x010 /* DCU4 Mode */
75 #define DCU_MODE_M 0x3
76 #define DCU_MODE_S 0
77 #define DCU_MODE_NORMAL 0x1
78 #define DCU_MODE_TEST 0x2
79 #define DCU_MODE_COLBAR 0x3
80 #define RASTER_EN (1 << 14) /* Raster scan of pixel data */
81 #define PDI_EN (1 << 13)
82 #define PDI_DE_MODE (1 << 11)
83 #define PDI_MODE_M 2
84 #define DCU_BGND 0x014 /* Background */
85 #define DCU_DISP_SIZE 0x018 /* Display Size */
86 #define DELTA_M 0x7ff
87 #define DELTA_Y_S 16
88 #define DELTA_X_S 0
89 #define DCU_HSYN_PARA 0x01C /* Horizontal Sync Parameter */
90 #define BP_H_SHIFT 22
91 #define PW_H_SHIFT 11
92 #define FP_H_SHIFT 0
93 #define DCU_VSYN_PARA 0x020 /* Vertical Sync Parameter */
94 #define BP_V_SHIFT 22
95 #define PW_V_SHIFT 11
96 #define FP_V_SHIFT 0
97 #define DCU_SYNPOL 0x024 /* Synchronize Polarity */
98 #define INV_HS (1 << 0)
99 #define INV_VS (1 << 1)
100 #define INV_PDI_VS (1 << 8) /* Polarity of PDI input VSYNC. */
101 #define INV_PDI_HS (1 << 9) /* Polarity of PDI input HSYNC. */
102 #define INV_PDI_DE (1 << 10) /* Polarity of PDI input DE. */
103 #define DCU_THRESHOLD 0x028 /* Threshold */
104 #define LS_BF_VS_SHIFT 16
105 #define OUT_BUF_HIGH_SHIFT 8
106 #define OUT_BUF_LOW_SHIFT 0
107 #define DCU_INT_STATUS 0x02C /* Interrupt Status */
108 #define DCU_INT_MASK 0x030 /* Interrupt Mask */
109 #define DCU_COLBAR_1 0x034 /* COLBAR_1 */
110 #define DCU_COLBAR_2 0x038 /* COLBAR_2 */
111 #define DCU_COLBAR_3 0x03C /* COLBAR_3 */
112 #define DCU_COLBAR_4 0x040 /* COLBAR_4 */
113 #define DCU_COLBAR_5 0x044 /* COLBAR_5 */
114 #define DCU_COLBAR_6 0x048 /* COLBAR_6 */
115 #define DCU_COLBAR_7 0x04C /* COLBAR_7 */
116 #define DCU_COLBAR_8 0x050 /* COLBAR_8 */
117 #define DCU_DIV_RATIO 0x054 /* Divide Ratio */
118 #define DCU_SIGN_CALC_1 0x058 /* Sign Calculation 1 */
119 #define DCU_SIGN_CALC_2 0x05C /* Sign Calculation 2 */
120 #define DCU_CRC_VAL 0x060 /* CRC Value */
121 #define DCU_PDI_STATUS 0x064 /* PDI Status */
122 #define DCU_PDI_STA_MSK 0x068 /* PDI Status Mask */
123 #define DCU_PARR_ERR_STATUS1 0x06C /* Parameter Error Status 1 */
124 #define DCU_PARR_ERR_STATUS2 0x070 /* Parameter Error Status 2 */
125 #define DCU_PARR_ERR_STATUS3 0x07C /* Parameter Error Status 3 */
126 #define DCU_MASK_PARR_ERR_ST1 0x080 /* Mask Parameter Error Status 1 */
127 #define DCU_MASK_PARR_ERR_ST2 0x084 /* Mask Parameter Error Status 2 */
128 #define DCU_MASK_PARR_ERR_ST3 0x090 /* Mask Parameter Error Status 3 */
129 #define DCU_THRESHOLD_INP_BUF_1 0x094 /* Threshold Input 1 */
130 #define DCU_THRESHOLD_INP_BUF_2 0x098 /* Threshold Input 2 */
131 #define DCU_THRESHOLD_INP_BUF_3 0x09C /* Threshold Input 3 */
132 #define DCU_LUMA_COMP 0x0A0 /* LUMA Component */
133 #define DCU_CHROMA_RED 0x0A4 /* Red Chroma Components */
134 #define DCU_CHROMA_GREEN 0x0A8 /* Green Chroma Components */
135 #define DCU_CHROMA_BLUE 0x0AC /* Blue Chroma Components */
136 #define DCU_CRC_POS 0x0B0 /* CRC Position */
137 #define DCU_LYR_INTPOL_EN 0x0B4 /* Layer Interpolation Enable */
138 #define DCU_LYR_LUMA_COMP 0x0B8 /* Layer Luminance Component */
139 #define DCU_LYR_CHRM_RED 0x0BC /* Layer Chroma Red */
140 #define DCU_LYR_CHRM_GRN 0x0C0 /* Layer Chroma Green */
141 #define DCU_LYR_CHRM_BLUE 0x0C4 /* Layer Chroma Blue */
142 #define DCU_COMP_IMSIZE 0x0C8 /* Compression Image Size */
143 #define DCU_UPDATE_MODE 0x0CC /* Update Mode */
144 #define READREG (1 << 30)
145 #define MODE (1 << 31)
146 #define DCU_UNDERRUN 0x0D0 /* Underrun */
147 #define DCU_GLBL_PROTECT 0x100 /* Global Protection */
148 #define DCU_SFT_LCK_BIT_L0 0x104 /* Soft Lock Bit Layer 0 */
149 #define DCU_SFT_LCK_BIT_L1 0x108 /* Soft Lock Bit Layer 1 */
150 #define DCU_SFT_LCK_DISP_SIZE 0x10C /* Soft Lock Display Size */
151 #define DCU_SFT_LCK_HS_VS_PARA 0x110 /* Soft Lock Hsync/Vsync Parameter */
152 #define DCU_SFT_LCK_POL 0x114 /* Soft Lock POL */
153 #define DCU_SFT_LCK_L0_TRANSP 0x118 /* Soft Lock L0 Transparency */
154 #define DCU_SFT_LCK_L1_TRANSP 0x11C /* Soft Lock L1 Transparency */
155
156 /* Control Descriptor */
157 #define DCU_CTRLDESCL(n, m) 0x200 + (0x40 * n) + 0x4 * (m - 1)
158 #define DCU_CTRLDESCLn_1(n) DCU_CTRLDESCL(n, 1)
159 #define DCU_CTRLDESCLn_2(n) DCU_CTRLDESCL(n, 2)
160 #define DCU_CTRLDESCLn_3(n) DCU_CTRLDESCL(n, 3)
161 #define TRANS_SHIFT 20
162 #define DCU_CTRLDESCLn_4(n) DCU_CTRLDESCL(n, 4)
163 #define BPP_MASK 0xf /* Bit per pixel Mask */
164 #define BPP_SHIFT 16 /* Bit per pixel Shift */
165 #define BPP24 0x5
166 #define EN_LAYER (1 << 31) /* Enable the layer */
167 #define DCU_CTRLDESCLn_5(n) DCU_CTRLDESCL(n, 5)
168 #define DCU_CTRLDESCLn_6(n) DCU_CTRLDESCL(n, 6)
169 #define DCU_CTRLDESCLn_7(n) DCU_CTRLDESCL(n, 7)
170 #define DCU_CTRLDESCLn_8(n) DCU_CTRLDESCL(n, 8)
171 #define DCU_CTRLDESCLn_9(n) DCU_CTRLDESCL(n, 9)
172
173 #define NUM_LAYERS 64
174
175 struct panel_info {
176 uint32_t width;
177 uint32_t height;
178 uint32_t h_back_porch;
179 uint32_t h_pulse_width;
180 uint32_t h_front_porch;
181 uint32_t v_back_porch;
182 uint32_t v_pulse_width;
183 uint32_t v_front_porch;
184 uint32_t clk_div;
185 uint32_t backlight_pin;
186 };
187
188 struct dcu_softc {
189 struct resource *res[2];
190 bus_space_tag_t bst;
191 bus_space_handle_t bsh;
192 void *ih;
193 device_t dev;
194 device_t sc_fbd; /* fbd child */
195 struct fb_info sc_info;
196 struct panel_info *panel;
197 };
198
199 static struct resource_spec dcu_spec[] = {
200 { SYS_RES_MEMORY, 0, RF_ACTIVE },
201 { SYS_RES_IRQ, 0, RF_ACTIVE },
202 { -1, 0 }
203 };
204
205 static int
dcu_probe(device_t dev)206 dcu_probe(device_t dev)
207 {
208
209 if (!ofw_bus_status_okay(dev))
210 return (ENXIO);
211
212 if (!ofw_bus_is_compatible(dev, "fsl,mvf600-dcu4"))
213 return (ENXIO);
214
215 device_set_desc(dev, "Vybrid Family Display Control Unit (DCU4)");
216 return (BUS_PROBE_DEFAULT);
217 }
218
219 static void
dcu_intr(void * arg)220 dcu_intr(void *arg)
221 {
222 struct dcu_softc *sc;
223 int reg;
224
225 sc = arg;
226
227 /* Ack interrupts */
228 reg = READ4(sc, DCU_INT_STATUS);
229 WRITE4(sc, DCU_INT_STATUS, reg);
230
231 /* TODO interrupt handler */
232 }
233
234 static int
get_panel_info(struct dcu_softc * sc,struct panel_info * panel)235 get_panel_info(struct dcu_softc *sc, struct panel_info *panel)
236 {
237 phandle_t node;
238 pcell_t dts_value[3];
239 int len;
240
241 if ((node = ofw_bus_get_node(sc->dev)) == -1)
242 return (ENXIO);
243
244 /* panel size */
245 if ((len = OF_getproplen(node, "panel-size")) <= 0)
246 return (ENXIO);
247 OF_getencprop(node, "panel-size", dts_value, len);
248 panel->width = dts_value[0];
249 panel->height = dts_value[1];
250
251 /* hsync */
252 if ((len = OF_getproplen(node, "panel-hsync")) <= 0)
253 return (ENXIO);
254 OF_getencprop(node, "panel-hsync", dts_value, len);
255 panel->h_back_porch = dts_value[0];
256 panel->h_pulse_width = dts_value[1];
257 panel->h_front_porch = dts_value[2];
258
259 /* vsync */
260 if ((len = OF_getproplen(node, "panel-vsync")) <= 0)
261 return (ENXIO);
262 OF_getencprop(node, "panel-vsync", dts_value, len);
263 panel->v_back_porch = dts_value[0];
264 panel->v_pulse_width = dts_value[1];
265 panel->v_front_porch = dts_value[2];
266
267 /* clk divider */
268 if ((len = OF_getproplen(node, "panel-clk-div")) <= 0)
269 return (ENXIO);
270 OF_getencprop(node, "panel-clk-div", dts_value, len);
271 panel->clk_div = dts_value[0];
272
273 /* backlight pin */
274 if ((len = OF_getproplen(node, "panel-backlight-pin")) <= 0)
275 return (ENXIO);
276 OF_getencprop(node, "panel-backlight-pin", dts_value, len);
277 panel->backlight_pin = dts_value[0];
278
279 return (0);
280 }
281
282 static int
dcu_init(struct dcu_softc * sc)283 dcu_init(struct dcu_softc *sc)
284 {
285 struct panel_info *panel;
286 int reg;
287 int i;
288
289 panel = sc->panel;
290
291 /* Configure DCU */
292 reg = ((sc->sc_info.fb_height) << DELTA_Y_S);
293 reg |= (sc->sc_info.fb_width / 16);
294 WRITE4(sc, DCU_DISP_SIZE, reg);
295
296 reg = (panel->h_back_porch << BP_H_SHIFT);
297 reg |= (panel->h_pulse_width << PW_H_SHIFT);
298 reg |= (panel->h_front_porch << FP_H_SHIFT);
299 WRITE4(sc, DCU_HSYN_PARA, reg);
300
301 reg = (panel->v_back_porch << BP_V_SHIFT);
302 reg |= (panel->v_pulse_width << PW_V_SHIFT);
303 reg |= (panel->v_front_porch << FP_V_SHIFT);
304 WRITE4(sc, DCU_VSYN_PARA, reg);
305
306 WRITE4(sc, DCU_BGND, 0);
307 WRITE4(sc, DCU_DIV_RATIO, panel->clk_div);
308
309 reg = (INV_VS | INV_HS);
310 WRITE4(sc, DCU_SYNPOL, reg);
311
312 /* TODO: export to panel info */
313 reg = (0x3 << LS_BF_VS_SHIFT);
314 reg |= (0x78 << OUT_BUF_HIGH_SHIFT);
315 reg |= (0 << OUT_BUF_LOW_SHIFT);
316 WRITE4(sc, DCU_THRESHOLD, reg);
317
318 /* Mask all the interrupts */
319 WRITE4(sc, DCU_INT_MASK, 0xffffffff);
320
321 /* Reset all layers */
322 for (i = 0; i < NUM_LAYERS; i++) {
323 WRITE4(sc, DCU_CTRLDESCLn_1(i), 0x0);
324 WRITE4(sc, DCU_CTRLDESCLn_2(i), 0x0);
325 WRITE4(sc, DCU_CTRLDESCLn_3(i), 0x0);
326 WRITE4(sc, DCU_CTRLDESCLn_4(i), 0x0);
327 WRITE4(sc, DCU_CTRLDESCLn_5(i), 0x0);
328 WRITE4(sc, DCU_CTRLDESCLn_6(i), 0x0);
329 WRITE4(sc, DCU_CTRLDESCLn_7(i), 0x0);
330 WRITE4(sc, DCU_CTRLDESCLn_8(i), 0x0);
331 WRITE4(sc, DCU_CTRLDESCLn_9(i), 0x0);
332 }
333
334 /* Setup first layer */
335 reg = (sc->sc_info.fb_width | (sc->sc_info.fb_height << 16));
336 WRITE4(sc, DCU_CTRLDESCLn_1(0), reg);
337 WRITE4(sc, DCU_CTRLDESCLn_2(0), 0x0);
338 WRITE4(sc, DCU_CTRLDESCLn_3(0), sc->sc_info.fb_pbase);
339 reg = (BPP24 << BPP_SHIFT);
340 reg |= EN_LAYER;
341 reg |= (0xFF << TRANS_SHIFT); /* completely opaque */
342 WRITE4(sc, DCU_CTRLDESCLn_4(0), reg);
343 WRITE4(sc, DCU_CTRLDESCLn_5(0), 0xffffff);
344 WRITE4(sc, DCU_CTRLDESCLn_6(0), 0x0);
345 WRITE4(sc, DCU_CTRLDESCLn_7(0), 0x0);
346 WRITE4(sc, DCU_CTRLDESCLn_8(0), 0x0);
347 WRITE4(sc, DCU_CTRLDESCLn_9(0), 0x0);
348
349 /* Enable DCU in normal mode */
350 reg = READ4(sc, DCU_DCU_MODE);
351 reg &= ~(DCU_MODE_M << DCU_MODE_S);
352 reg |= (DCU_MODE_NORMAL << DCU_MODE_S);
353 reg |= (RASTER_EN);
354 WRITE4(sc, DCU_DCU_MODE, reg);
355 WRITE4(sc, DCU_UPDATE_MODE, READREG);
356
357 return (0);
358 }
359
360 static int
dcu_attach(device_t dev)361 dcu_attach(device_t dev)
362 {
363 struct panel_info panel;
364 struct dcu_softc *sc;
365 device_t gpio_dev;
366 int err;
367
368 sc = device_get_softc(dev);
369 sc->dev = dev;
370
371 if (bus_alloc_resources(dev, dcu_spec, sc->res)) {
372 device_printf(dev, "could not allocate resources\n");
373 return (ENXIO);
374 }
375
376 /* Memory interface */
377 sc->bst = rman_get_bustag(sc->res[0]);
378 sc->bsh = rman_get_bushandle(sc->res[0]);
379
380 /* Setup interrupt handler */
381 err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_BIO | INTR_MPSAFE,
382 NULL, dcu_intr, sc, &sc->ih);
383 if (err) {
384 device_printf(dev, "Unable to alloc interrupt resource.\n");
385 return (ENXIO);
386 }
387
388 if (get_panel_info(sc, &panel)) {
389 device_printf(dev, "Can't get panel info\n");
390 return (ENXIO);
391 }
392
393 sc->panel = &panel;
394
395 /* Bypass timing control (used for raw lcd panels) */
396 tcon_bypass();
397
398 /* Get the GPIO device, we need this to give power to USB */
399 gpio_dev = devclass_get_device(devclass_find("gpio"), 0);
400 if (gpio_dev == NULL) {
401 device_printf(sc->dev, "Error: failed to get the GPIO dev\n");
402 return (1);
403 }
404
405 /* Turn on backlight */
406 /* TODO: Use FlexTimer/PWM */
407 GPIO_PIN_SETFLAGS(gpio_dev, panel.backlight_pin, GPIO_PIN_OUTPUT);
408 GPIO_PIN_SET(gpio_dev, panel.backlight_pin, GPIO_PIN_HIGH);
409
410 sc->sc_info.fb_width = panel.width;
411 sc->sc_info.fb_height = panel.height;
412 sc->sc_info.fb_stride = sc->sc_info.fb_width * 3;
413 sc->sc_info.fb_bpp = sc->sc_info.fb_depth = 24;
414 sc->sc_info.fb_size = sc->sc_info.fb_height * sc->sc_info.fb_stride;
415 sc->sc_info.fb_vbase = (intptr_t)contigmalloc(sc->sc_info.fb_size,
416 M_DEVBUF, M_ZERO, 0, ~0, PAGE_SIZE, 0);
417 sc->sc_info.fb_pbase = (intptr_t)vtophys(sc->sc_info.fb_vbase);
418
419 #if 0
420 printf("%dx%d [%d]\n", sc->sc_info.fb_width, sc->sc_info.fb_height,
421 sc->sc_info.fb_stride);
422 printf("pbase == 0x%08x\n", sc->sc_info.fb_pbase);
423 #endif
424
425 memset((int8_t *)sc->sc_info.fb_vbase, 0x0, sc->sc_info.fb_size);
426
427 dcu_init(sc);
428
429 sc->sc_info.fb_name = device_get_nameunit(dev);
430
431 /* Ask newbus to attach framebuffer device to me. */
432 sc->sc_fbd = device_add_child(dev, "fbd", device_get_unit(dev));
433 if (sc->sc_fbd == NULL)
434 device_printf(dev, "Can't attach fbd device\n");
435
436 if (device_probe_and_attach(sc->sc_fbd) != 0) {
437 device_printf(sc->dev, "Failed to attach fbd device\n");
438 }
439
440 return (0);
441 }
442
443 static struct fb_info *
dcu4_fb_getinfo(device_t dev)444 dcu4_fb_getinfo(device_t dev)
445 {
446 struct dcu_softc *sc = device_get_softc(dev);
447
448 return (&sc->sc_info);
449 }
450
451 static device_method_t dcu_methods[] = {
452 DEVMETHOD(device_probe, dcu_probe),
453 DEVMETHOD(device_attach, dcu_attach),
454
455 /* Framebuffer service methods */
456 DEVMETHOD(fb_getinfo, dcu4_fb_getinfo),
457 { 0, 0 }
458 };
459
460 static driver_t dcu_driver = {
461 "fb",
462 dcu_methods,
463 sizeof(struct dcu_softc),
464 };
465
466 DRIVER_MODULE(fb, simplebus, dcu_driver, 0, 0);
467