1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __SKL_WATERMARK_REGS_H__ 7 #define __SKL_WATERMARK_REGS_H__ 8 9 #include "intel_display_reg_defs.h" 10 11 #define _PIPEA_MBUS_DBOX_CTL 0x7003C 12 #define _PIPEB_MBUS_DBOX_CTL 0x7103C 13 #define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \ 14 _PIPEB_MBUS_DBOX_CTL) 15 #define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK REG_GENMASK(24, 20) /* tgl+ */ 16 #define MBUS_DBOX_B2B_TRANSACTIONS_MAX(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK, x) 17 #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK REG_GENMASK(19, 17) /* tgl+ */ 18 #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK, x) 19 #define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */ 20 #define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14) 21 #define MBUS_DBOX_BW_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x) 22 #define MBUS_DBOX_BW_4CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x2) 23 #define MBUS_DBOX_BW_8CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x3) 24 #define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8) 25 #define MBUS_DBOX_B_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x) 26 #define MBUS_DBOX_I_CREDIT_MASK REG_GENMASK(7, 5) 27 #define MBUS_DBOX_I_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_I_CREDIT_MASK, x) 28 #define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0) 29 #define MBUS_DBOX_A_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x) 30 31 #define MBUS_UBOX_CTL _MMIO(0x4503C) 32 #define MBUS_BBOX_CTL_S1 _MMIO(0x45040) 33 #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) 34 35 #define MBUS_CTL _MMIO(0x4438C) 36 #define MBUS_JOIN REG_BIT(31) 37 #define MBUS_HASHING_MODE_MASK REG_BIT(30) 38 #define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0) 39 #define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1) 40 #define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26) 41 #define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe) 42 #define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7) 43 #define XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK REG_GENMASK(16, 13) 44 #define XE3P_MBUS_TRANSLATION_THROTTLE_MIN(val) REG_FIELD_PREP(XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK, val) 45 #define MBUS_TRANSLATION_THROTTLE_MIN_MASK REG_GENMASK(15, 13) 46 #define MBUS_TRANSLATION_THROTTLE_MIN(val) REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val) 47 48 /* 49 * The below are numbered starting from "S1" on gen11/gen12, but starting 50 * with display 13, the bspec switches to a 0-based numbering scheme 51 * (although the addresses stay the same so new S0 = old S1, new S1 = old S2). 52 * We'll just use the 0-based numbering here for all platforms since it's the 53 * way things will be named by the hardware team going forward, plus it's more 54 * consistent with how most of the rest of our registers are named. 55 */ 56 #define _DBUF_CTL_S0 0x45008 57 #define _DBUF_CTL_S1 0x44FE8 58 #define _DBUF_CTL_S2 0x44300 59 #define _DBUF_CTL_S3 0x44304 60 #define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \ 61 _DBUF_CTL_S0, \ 62 _DBUF_CTL_S1, \ 63 _DBUF_CTL_S2, \ 64 _DBUF_CTL_S3)) 65 #define DBUF_POWER_REQUEST REG_BIT(31) 66 #define DBUF_POWER_STATE REG_BIT(30) 67 #define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19) 68 #define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x) 69 #define XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(20, 16) 70 #define XE3P_DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) 71 #define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16) /* ADL-P+ */ 72 #define DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */ 73 74 #define MTL_LATENCY_LP0_LP1 _MMIO(0x45780) 75 #define MTL_LATENCY_LP2_LP3 _MMIO(0x45784) 76 #define MTL_LATENCY_LP4_LP5 _MMIO(0x45788) 77 #define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0) 78 #define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16) 79 80 #define MTL_LATENCY_SAGV _MMIO(0x4578c) 81 #define MTL_LATENCY_QCLK_SAGV REG_GENMASK(12, 0) 82 83 #define LNL_PKG_C_LATENCY _MMIO(0x46460) 84 #define LNL_ADDED_WAKE_TIME_MASK REG_GENMASK(28, 16) 85 #define LNL_PKG_C_LATENCY_MASK REG_GENMASK(12, 0) 86 87 #endif /* __SKL_WATERMARK_REGS_H__ */ 88