xref: /titanic_41/usr/src/uts/sun4u/montecarlo/sys/acebus.h (revision 03831d35f7499c87d51205817c93e9a8d42c4bae)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef _SYS_ACEBUS_H
28 #define	_SYS_ACEBUS_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 #ifdef	__cplusplus
33 extern "C" {
34 #endif
35 
36 /*
37  * driver state type:
38  */
39 typedef enum { NEW = 0, ATTACHED, RESUMED, DETACHED,
40 		SUSPENDED, PM_SUSPENDED } driver_state_t;
41 
42 /*
43  * The i86pc specific code fragments are to support the debug of "honeynut"
44  * and "multigrain" prototypes on i86pc platform.  Most of the fragments
45  * deal with differences in the interrupt dispatching between the prototypes
46  * and the cheerio ebus.  On the prototype boards, all interrupt lines are
47  * tied together.  For this case, the nexus driver uses a common interrupt
48  * handler to poll all of its children.
49  */
50 #if defined(i86pc)
51 #define	MAX_EBUS_DEVS	6
52 
53 /*
54  * ebus device interrupt info;
55  */
56 typedef struct {
57 	char *name;
58 	uint_t inuse;
59 	uint_t (*handler)();
60 	caddr_t arg;
61 } ebus_intr_slot_t;
62 #endif
63 
64 struct ebus_intr_map {
65 	uint32_t ebus_phys_hi;
66 	uint32_t ebus_phys_low;
67 	uint32_t ebus_intr;
68 	uint32_t intr_ctlr_nodeid;
69 	uint32_t ino;
70 };
71 
72 struct ebus_intr_map_mask {
73 	uint32_t ebus_phys_hi;
74 	uint32_t ebus_phys_low;
75 	uint32_t ebus_intr;
76 };
77 
78 /*
79  * driver soft state structure:
80  */
81 typedef struct {
82 	dev_info_t *dip;
83 	driver_state_t state;
84 	pci_regspec_t *reg;
85 	int nreg;
86 	struct ebus_pci_rangespec *rangep;
87 	int range_cnt;
88 
89 #if defined(i86pc)
90 	ddi_iblock_cookie_t iblock;
91 	ddi_idevice_cookie_t idevice;
92 	ebus_intr_slot_t intr_slot[MAX_EBUS_DEVS];
93 #endif
94 #if defined(__sparc)
95 	/* Interrupt support */
96 	int intr_map_size;
97 	struct ebus_intr_map *intr_map;
98 	struct ebus_intr_map_mask *intr_map_mask;
99 #endif
100 } ebus_devstate_t;
101 
102 /*
103  * definition of ebus reg spec entry:
104  */
105 typedef struct {
106 	uint32_t addr_hi;
107 	uint32_t addr_low;
108 	uint32_t size;
109 } ebus_regspec_t;
110 
111 /* EBUS range entry */
112 struct ebus_pci_rangespec {
113 	uint32_t ebus_phys_hi;			/* Child hi range address */
114 	uint32_t ebus_phys_low;			/* Child low range address */
115 	uint32_t pci_phys_hi;			/* Parent hi rng addr */
116 	uint32_t pci_phys_mid;			/* Parent mid rng addr */
117 	uint32_t pci_phys_low;			/* Parent low rng addr */
118 	uint32_t rng_size;			/* Range size */
119 };
120 
121 /*
122  * use macros for soft state and driver properties:
123  */
124 #define	get_acebus_soft_state(i)	\
125 	((ebus_devstate_t *)ddi_get_soft_state(per_acebus_state, (i)))
126 
127 #define	alloc_acebus_soft_state(i)	\
128 	ddi_soft_state_zalloc(per_acebus_state, (i))
129 
130 #define	free_acebus_soft_state(i)	\
131 	ddi_soft_state_free(per_acebus_state, (i))
132 
133 
134 #define	getprop(dip, name, addr, intp)		\
135 		ddi_getlongprop(DDI_DEV_T_ANY, (dip), DDI_PROP_DONTPASS, \
136 				(name), (caddr_t)(addr), (intp))
137 
138 /*
139  * register offsets and lengths:
140  */
141 #define	TCR_OFFSET	0x710000
142 #define	TCR_LENGTH	12
143 
144 #define	CSR_IO_RINDEX		2
145 #define	CSR_SIZE		0x00800000
146 #define	TCR1_OFF		0x00710000
147 #define	TCR2_OFF		0x00710004
148 #define	TCR3_OFF		0x00710008
149 #define	PMD_AUX_OFF		0x00728000
150 #define	FREQ_AUX_OFF		0x0072a000
151 #define	DCSR1_OFF		0x00700000
152 #define	DACR1_OFF		0x00700004
153 #define	DBCR1_OFF		0x00700008
154 #define	DCSR2_OFF		0x00702000
155 #define	DACR2_OFF		0x00702004
156 #define	DBCR2_OFF		0x00702008
157 #define	DCSR3_OFF		0x00704000
158 #define	DACR3_OFF		0x00704004
159 #define	DBCR3_OFF		0x00704008
160 #define	DCSR4_OFF		0x00706000
161 #define	DACR4_OFF		0x00706004
162 #define	DBCR4_OFF		0x00706008
163 
164 /*
165  * timing control register settings:
166  */
167 #define	TCR1		0x08101008
168 #define	TCR2		0x08100020
169 #define	TCR3		0x00000020
170 #define	TCR1_REGVAL	0xe3080808
171 #define	TCR2_REGVAL	0x0808ff20
172 #define	TCR3_REGVAL	0x91f3c420
173 
174 
175 
176 #if defined(DEBUG)
177 #define	D_IDENTIFY	0x00000001
178 #define	D_ATTACH	0x00000002
179 #define	D_DETACH	0x00000004
180 #define	D_MAP		0x00000008
181 #define	D_CTLOPS	0x00000010
182 #define	D_INTR		0x00000100
183 
184 #define	DBG(flag, psp, fmt)	\
185 	acebus_debug(flag, psp, fmt, 0, 0, 0, 0, 0);
186 #define	DBG1(flag, psp, fmt, a1)	\
187 	acebus_debug(flag, psp, fmt, (uintptr_t)(a1), 0, 0, 0, 0);
188 #define	DBG2(flag, psp, fmt, a1, a2)	\
189 	acebus_debug(flag, psp, fmt, (uintptr_t)(a1), (uintptr_t)(a2), 0, 0, 0);
190 #define	DBG3(flag, psp, fmt, a1, a2, a3)	\
191 	acebus_debug(flag, psp, fmt, (uintptr_t)(a1), (uintptr_t)(a2), \
192 	    (uintptr_t)(a3), 0, 0);
193 #define	DBG4(flag, psp, fmt, a1, a2, a3, a4)	\
194 	acebus_debug(flag, psp, fmt, (uintptr_t)(a1), (uintptr_t)(a2), \
195 	    (uintptr_t)(a3), \
196 		(uintptr_t)(a4), 0);
197 #define	DBG5(flag, psp, fmt, a1, a2, a3, a4, a5)	\
198 	acebus_debug(flag, psp, fmt, (uintptr_t)(a1), (uintptr_t)(a2), \
199 	    (uintptr_t)(a3), \
200 		(uintptr_t)(a4), (uintptr_t)(a5));
201 static void
202 acebus_debug(uint_t, ebus_devstate_t *, char *, uintptr_t, uintptr_t, uintptr_t,
203     uintptr_t, uintptr_t);
204 #else
205 #define	DBG(flag, psp, fmt)
206 #define	DBG1(flag, psp, fmt, a1)
207 #define	DBG2(flag, psp, fmt, a1, a2)
208 #define	DBG3(flag, psp, fmt, a1, a2, a3)
209 #define	DBG4(flag, psp, fmt, a1, a2, a3, a4)
210 #define	DBG5(flag, psp, fmt, a1, a2, a3, a4, a5)
211 #endif
212 
213 #ifdef	__cplusplus
214 }
215 #endif
216 
217 #endif	/* _SYS_ACEBUS_H */
218