1 /**************************************************************************
2 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
3 * Written 2003 by Timothy Legge <tlegge@rogers.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * Portions of this code based on:
20 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
21 * for Linux kernel 2.4.x.
22 *
23 * Written 2002 ShuChen <shuchen@realtek.com.tw>
24 * See Linux Driver for full information
25 *
26 * Linux Driver Version 1.27a, 10.02.2002
27 *
28 * Thanks to:
29 * Jean Chen of RealTek Semiconductor Corp. for
30 * providing the evaluation NIC used to develop
31 * this driver. RealTek's support for Etherboot
32 * is appreciated.
33 *
34 * REVISION HISTORY:
35 * ================
36 *
37 * v1.0 11-26-2003 timlegge Initial port of Linux driver
38 * v1.5 01-17-2004 timlegge Initial driver output cleanup
39 * v1.6 03-27-2004 timlegge Additional Cleanup
40 *
41 * Indent Options: indent -kr -i8
42 ***************************************************************************/
43
44 /* to get some global routines like printf */
45 #include "etherboot.h"
46 /* to get the interface to the body of the program */
47 #include "nic.h"
48 /* to get the PCI support functions, if this is a PCI NIC */
49 #include "pci.h"
50 #include "timer.h"
51
52 #define drv_version "v1.6"
53 #define drv_date "03-27-2004"
54
55 typedef unsigned char u8;
56 typedef signed char s8;
57 typedef unsigned short u16;
58 typedef signed short s16;
59 typedef unsigned int u32;
60 typedef signed int s32;
61
62 #define HZ 1000
63
64 static u32 ioaddr;
65
66 #ifdef EDEBUG
67 #define dprintf(x) printf x
68 #else
69 #define dprintf(x)
70 #endif
71
72 /* Condensed operations for readability. */
73 #define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
74 #define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
75
76 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
77
78 /* media options
79 _10_Half = 0x01,
80 _10_Full = 0x02,
81 _100_Half = 0x04,
82 _100_Full = 0x08,
83 _1000_Full = 0x10,
84 */
85 static int media = -1;
86
87 #if 0
88 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
89 static int max_interrupt_work = 20;
90 #endif
91
92 #if 0
93 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
94 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
95 static int multicast_filter_limit = 32;
96 #endif
97
98 /* MAC address length*/
99 #define MAC_ADDR_LEN 6
100
101 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
102 #define MAX_ETH_FRAME_SIZE 1536
103
104 #define TX_FIFO_THRESH 256 /* In bytes */
105
106 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
107 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
108 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
109 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
110 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
111 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
112
113 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */
114 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */
115 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
116
117 #define RTL_MIN_IO_SIZE 0x80
118 #define TX_TIMEOUT (6*HZ)
119
120 /* write/read MMIO register */
121 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
122 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
123 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
124 #define RTL_R8(reg) readb (ioaddr + (reg))
125 #define RTL_R16(reg) readw (ioaddr + (reg))
126 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
127
128 enum RTL8169_registers {
129 MAC0 = 0, /* Ethernet hardware address. */
130 MAR0 = 8, /* Multicast filter. */
131 TxDescStartAddr = 0x20,
132 TxHDescStartAddr = 0x28,
133 FLASH = 0x30,
134 ERSR = 0x36,
135 ChipCmd = 0x37,
136 TxPoll = 0x38,
137 IntrMask = 0x3C,
138 IntrStatus = 0x3E,
139 TxConfig = 0x40,
140 RxConfig = 0x44,
141 RxMissed = 0x4C,
142 Cfg9346 = 0x50,
143 Config0 = 0x51,
144 Config1 = 0x52,
145 Config2 = 0x53,
146 Config3 = 0x54,
147 Config4 = 0x55,
148 Config5 = 0x56,
149 MultiIntr = 0x5C,
150 PHYAR = 0x60,
151 TBICSR = 0x64,
152 TBI_ANAR = 0x68,
153 TBI_LPAR = 0x6A,
154 PHYstatus = 0x6C,
155 RxMaxSize = 0xDA,
156 CPlusCmd = 0xE0,
157 RxDescStartAddr = 0xE4,
158 EarlyTxThres = 0xEC,
159 FuncEvent = 0xF0,
160 FuncEventMask = 0xF4,
161 FuncPresetState = 0xF8,
162 FuncForceEvent = 0xFC,
163 };
164
165 enum RTL8169_register_content {
166 /*InterruptStatusBits */
167 SYSErr = 0x8000,
168 PCSTimeout = 0x4000,
169 SWInt = 0x0100,
170 TxDescUnavail = 0x80,
171 RxFIFOOver = 0x40,
172 RxUnderrun = 0x20,
173 RxOverflow = 0x10,
174 TxErr = 0x08,
175 TxOK = 0x04,
176 RxErr = 0x02,
177 RxOK = 0x01,
178
179 /*RxStatusDesc */
180 RxRES = 0x00200000,
181 RxCRC = 0x00080000,
182 RxRUNT = 0x00100000,
183 RxRWT = 0x00400000,
184
185 /*ChipCmdBits */
186 CmdReset = 0x10,
187 CmdRxEnb = 0x08,
188 CmdTxEnb = 0x04,
189 RxBufEmpty = 0x01,
190
191 /*Cfg9346Bits */
192 Cfg9346_Lock = 0x00,
193 Cfg9346_Unlock = 0xC0,
194
195 /*rx_mode_bits */
196 AcceptErr = 0x20,
197 AcceptRunt = 0x10,
198 AcceptBroadcast = 0x08,
199 AcceptMulticast = 0x04,
200 AcceptMyPhys = 0x02,
201 AcceptAllPhys = 0x01,
202
203 /*RxConfigBits */
204 RxCfgFIFOShift = 13,
205 RxCfgDMAShift = 8,
206
207 /*TxConfigBits */
208 TxInterFrameGapShift = 24,
209 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
210
211 /*rtl8169_PHYstatus */
212 TBI_Enable = 0x80,
213 TxFlowCtrl = 0x40,
214 RxFlowCtrl = 0x20,
215 _1000bpsF = 0x10,
216 _100bps = 0x08,
217 _10bps = 0x04,
218 LinkStatus = 0x02,
219 FullDup = 0x01,
220
221 /*GIGABIT_PHY_registers */
222 PHY_CTRL_REG = 0,
223 PHY_STAT_REG = 1,
224 PHY_AUTO_NEGO_REG = 4,
225 PHY_1000_CTRL_REG = 9,
226
227 /*GIGABIT_PHY_REG_BIT */
228 PHY_Restart_Auto_Nego = 0x0200,
229 PHY_Enable_Auto_Nego = 0x1000,
230
231 /* PHY_STAT_REG = 1; */
232 PHY_Auto_Neco_Comp = 0x0020,
233
234 /* PHY_AUTO_NEGO_REG = 4; */
235 PHY_Cap_10_Half = 0x0020,
236 PHY_Cap_10_Full = 0x0040,
237 PHY_Cap_100_Half = 0x0080,
238 PHY_Cap_100_Full = 0x0100,
239
240 /* PHY_1000_CTRL_REG = 9; */
241 PHY_Cap_1000_Full = 0x0200,
242
243 PHY_Cap_Null = 0x0,
244
245 /*_MediaType*/
246 _10_Half = 0x01,
247 _10_Full = 0x02,
248 _100_Half = 0x04,
249 _100_Full = 0x08,
250 _1000_Full = 0x10,
251
252 /*_TBICSRBit*/
253 TBILinkOK = 0x02000000,
254 };
255
256 static struct {
257 const char *name;
258 u8 version; /* depend on RTL8169 docs */
259 u32 RxConfigMask; /* should clear the bits supported by this chip */
260 } rtl_chip_info[] = {
261 {
262 "RTL-8169", 0x00, 0xff7e1880,},};
263
264 enum _DescStatusBit {
265 OWNbit = 0x80000000,
266 EORbit = 0x40000000,
267 FSbit = 0x20000000,
268 LSbit = 0x10000000,
269 };
270
271 struct TxDesc {
272 u32 status;
273 u32 vlan_tag;
274 u32 buf_addr;
275 u32 buf_Haddr;
276 };
277
278 struct RxDesc {
279 u32 status;
280 u32 vlan_tag;
281 u32 buf_addr;
282 u32 buf_Haddr;
283 };
284
285 /* The descriptors for this card are required to be aligned on
286 256 byte boundaries. As the align attribute does not do more than
287 16 bytes of alignment it requires some extra steps. Add 256 to the
288 size of the array and the init_ring adjusts the alignment */
289
290 /* Define the TX Descriptor */
291 static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256];
292
293 /* Create a static buffer of size RX_BUF_SZ for each
294 TX Descriptor. All descriptors point to a
295 part of this buffer */
296 static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE];
297
298 /* Define the RX Descriptor */
299 static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256];
300
301 /* Create a static buffer of size RX_BUF_SZ for each
302 RX Descriptor All descriptors point to a
303 part of this buffer */
304 static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE];
305
306 struct rtl8169_private {
307 void *mmio_addr; /* memory map physical address */
308 int chipset;
309 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
310 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
311 unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */
312 unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */
313 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */
314 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */
315 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */
316 unsigned char *Tx_skbuff[NUM_TX_DESC];
317 } tpx;
318
319 static struct rtl8169_private *tpc;
320
321 static const u16 rtl8169_intr_mask =
322 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr |
323 TxOK | RxErr | RxOK;
324 static const unsigned int rtl8169_rx_config =
325 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
326
mdio_write(int RegAddr,int value)327 void mdio_write(int RegAddr, int value)
328 {
329 int i;
330
331 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
332 udelay(1000);
333
334 for (i = 2000; i > 0; i--) {
335 /* Check if the RTL8169 has completed writing to the specified MII register */
336 if (!(RTL_R32(PHYAR) & 0x80000000)) {
337 break;
338 } else {
339 udelay(100);
340 }
341 }
342 }
343
mdio_read(int RegAddr)344 int mdio_read(int RegAddr)
345 {
346 int i, value = -1;
347
348 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
349 udelay(1000);
350
351 for (i = 2000; i > 0; i--) {
352 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
353 if (RTL_R32(PHYAR) & 0x80000000) {
354 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
355 break;
356 } else {
357 udelay(100);
358 }
359 }
360 return value;
361 }
362
rtl8169_init_board(struct pci_device * pdev)363 static int rtl8169_init_board(struct pci_device *pdev)
364 {
365 int i;
366 unsigned long rtreg_base, rtreg_len;
367 u32 tmp;
368
369 rtreg_base = pci_bar_start(pdev, PCI_BASE_ADDRESS_1);
370 rtreg_len = pci_bar_size(pdev, PCI_BASE_ADDRESS_1);
371
372 /* check for weird/broken PCI region reporting */
373 if (rtreg_len < RTL_MIN_IO_SIZE) {
374 printf("Invalid PCI region size(s), aborting\n");
375 }
376
377 adjust_pci_device(pdev);
378 /* pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); */
379
380 /* ioremap MMIO region */
381 ioaddr = (unsigned long) ioremap(rtreg_base, rtreg_len);
382 if (ioaddr == 0)
383 return 0;
384
385 tpc->mmio_addr = &ioaddr;
386 /* Soft reset the chip. */
387 RTL_W8(ChipCmd, CmdReset);
388
389 /* Check that the chip has finished the reset. */
390 for (i = 1000; i > 0; i--)
391 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
392 break;
393 else
394 udelay(10);
395
396 /* identify chip attached to board */
397 tmp = RTL_R32(TxConfig);
398 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
399
400 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--)
401 if (tmp == rtl_chip_info[i].version) {
402 tpc->chipset = i;
403 goto match;
404 }
405 /* if unknown chip, assume array element #0, original RTL-8169 in this case */
406 dprintf(("PCI device: unknown chip version, assuming RTL-8169\n"));
407 dprintf(("PCI device: TxConfig = 0x%hX\n",
408 (unsigned long) RTL_R32(TxConfig)));
409 tpc->chipset = 0;
410 return 1;
411 match:
412 return 0;
413
414 }
415
416 /**************************************************************************
417 IRQ - Wait for a frame
418 ***************************************************************************/
r8169_irq(struct nic * nic __unused,irq_action_t action)419 void r8169_irq ( struct nic *nic __unused, irq_action_t action ) {
420 int intr_status = 0;
421 int interested = RxUnderrun | RxOverflow | RxFIFOOver | RxErr | RxOK;
422
423 switch ( action ) {
424 case DISABLE:
425 case ENABLE:
426 intr_status = RTL_R16(IntrStatus);
427 /* h/w no longer present (hotplug?) or major error,
428 bail */
429 if (intr_status == 0xFFFF)
430 break;
431
432 intr_status = intr_status & ~interested;
433 if ( action == ENABLE )
434 intr_status = intr_status | interested;
435 RTL_W16(IntrMask, intr_status);
436 break;
437 case FORCE :
438 RTL_W8(TxPoll, (RTL_R8(TxPoll) | 0x01));
439 break;
440 }
441 }
442
443 /**************************************************************************
444 POLL - Wait for a frame
445 ***************************************************************************/
r8169_poll(struct nic * nic,int retreive)446 static int r8169_poll(struct nic *nic, int retreive)
447 {
448 /* return true if there's an ethernet packet ready to read */
449 /* nic->packet should contain data on return */
450 /* nic->packetlen should contain length of data */
451 int cur_rx;
452 unsigned int intr_status = 0;
453 cur_rx = tpc->cur_rx;
454 if ((tpc->RxDescArray[cur_rx].status & OWNbit) == 0) {
455 /* There is a packet ready */
456 if(!retreive)
457 return 1;
458 intr_status = RTL_R16(IntrStatus);
459 /* h/w no longer present (hotplug?) or major error,
460 bail */
461 if (intr_status == 0xFFFF)
462 return 0;
463 RTL_W16(IntrStatus, intr_status &
464 ~(RxFIFOOver | RxOverflow | RxOK));
465
466 if (!(tpc->RxDescArray[cur_rx].status & RxRES)) {
467 nic->packetlen = (int) (tpc->RxDescArray[cur_rx].
468 status & 0x00001FFF) - 4;
469 memcpy(nic->packet, tpc->RxBufferRing[cur_rx],
470 nic->packetlen);
471 if (cur_rx == NUM_RX_DESC - 1)
472 tpc->RxDescArray[cur_rx].status =
473 (OWNbit | EORbit) + RX_BUF_SIZE;
474 else
475 tpc->RxDescArray[cur_rx].status =
476 OWNbit + RX_BUF_SIZE;
477 tpc->RxDescArray[cur_rx].buf_addr =
478 virt_to_bus(tpc->RxBufferRing[cur_rx]);
479 } else
480 printf("Error Rx");
481 /* FIXME: shouldn't I reset the status on an error */
482 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
483 tpc->cur_rx = cur_rx;
484 RTL_W16(IntrStatus, intr_status &
485 (RxFIFOOver | RxOverflow | RxOK));
486
487 return 1;
488
489 }
490 tpc->cur_rx = cur_rx;
491 /* FIXME: There is no reason to do this as cur_rx did not change */
492
493 return (0); /* initially as this is called to flush the input */
494
495 }
496
497 /**************************************************************************
498 TRANSMIT - Transmit a frame
499 ***************************************************************************/
r8169_transmit(struct nic * nic,const char * d,unsigned int t,unsigned int s,const char * p)500 static void r8169_transmit(struct nic *nic, const char *d, /* Destination */
501 unsigned int t, /* Type */
502 unsigned int s, /* size */
503 const char *p)
504 { /* Packet */
505 /* send the packet to destination */
506
507 u16 nstype;
508 u32 to;
509 u8 *ptxb;
510 int entry = tpc->cur_tx % NUM_TX_DESC;
511
512 /* point to the current txb incase multiple tx_rings are used */
513 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
514 memcpy(ptxb, d, ETH_ALEN);
515 memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN);
516 nstype = htons((u16) t);
517 memcpy(ptxb + 2 * ETH_ALEN, (u8 *) & nstype, 2);
518 memcpy(ptxb + ETH_HLEN, p, s);
519 s += ETH_HLEN;
520 s &= 0x0FFF;
521 while (s < ETH_ZLEN)
522 ptxb[s++] = '\0';
523
524 tpc->TxDescArray[entry].buf_addr = virt_to_bus(ptxb);
525 if (entry != (NUM_TX_DESC - 1))
526 tpc->TxDescArray[entry].status =
527 (OWNbit | FSbit | LSbit) | ((s > ETH_ZLEN) ? s :
528 ETH_ZLEN);
529 else
530 tpc->TxDescArray[entry].status =
531 (OWNbit | EORbit | FSbit | LSbit) | ((s > ETH_ZLEN) ? s
532 : ETH_ZLEN);
533 RTL_W8(TxPoll, 0x40); /* set polling bit */
534
535 tpc->cur_tx++;
536 to = currticks() + TX_TIMEOUT;
537 while ((tpc->TxDescArray[entry].status & OWNbit) && (currticks() < to)); /* wait */
538
539 if (currticks() >= to) {
540 printf("TX Time Out");
541 }
542 }
543
rtl8169_set_rx_mode(struct nic * nic __unused)544 static void rtl8169_set_rx_mode(struct nic *nic __unused)
545 {
546 u32 mc_filter[2]; /* Multicast hash filter */
547 int rx_mode;
548 u32 tmp = 0;
549
550 /* IFF_ALLMULTI */
551 /* Too many to filter perfectly -- accept all multicasts. */
552 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
553 mc_filter[1] = mc_filter[0] = 0xffffffff;
554
555 tmp =
556 rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
557 rtl_chip_info[tpc->chipset].
558 RxConfigMask);
559
560 RTL_W32(RxConfig, tmp);
561 RTL_W32(MAR0 + 0, mc_filter[0]);
562 RTL_W32(MAR0 + 4, mc_filter[1]);
563 }
rtl8169_hw_start(struct nic * nic)564 static void rtl8169_hw_start(struct nic *nic)
565 {
566 u32 i;
567
568 /* Soft reset the chip. */
569 RTL_W8(ChipCmd, CmdReset);
570
571 /* Check that the chip has finished the reset. */
572 for (i = 1000; i > 0; i--) {
573 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
574 break;
575 else
576 udelay(10);
577 }
578
579 RTL_W8(Cfg9346, Cfg9346_Unlock);
580 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
581 RTL_W8(EarlyTxThres, EarlyTxThld);
582
583 /* For gigabit rtl8169 */
584 RTL_W16(RxMaxSize, RxPacketMaxSize);
585
586 /* Set Rx Config register */
587 i = rtl8169_rx_config | (RTL_R32(RxConfig) &
588 rtl_chip_info[tpc->chipset].RxConfigMask);
589 RTL_W32(RxConfig, i);
590
591 /* Set DMA burst size and Interframe Gap Time */
592 RTL_W32(TxConfig,
593 (TX_DMA_BURST << TxDMAShift) | (InterFrameGap <<
594 TxInterFrameGapShift));
595
596
597 tpc->cur_rx = 0;
598
599 RTL_W32(TxDescStartAddr, virt_to_le32desc(tpc->TxDescArray));
600 RTL_W32(RxDescStartAddr, virt_to_le32desc(tpc->RxDescArray));
601 RTL_W8(Cfg9346, Cfg9346_Lock);
602 udelay(10);
603
604 RTL_W32(RxMissed, 0);
605
606 rtl8169_set_rx_mode(nic);
607
608 /* no early-rx interrupts */
609 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
610 }
611
rtl8169_init_ring(struct nic * nic __unused)612 static void rtl8169_init_ring(struct nic *nic __unused)
613 {
614 int i;
615
616 tpc->cur_rx = 0;
617 tpc->cur_tx = 0;
618 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
619 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
620
621 for (i = 0; i < NUM_TX_DESC; i++) {
622 tpc->Tx_skbuff[i] = &txb[i];
623 }
624
625 for (i = 0; i < NUM_RX_DESC; i++) {
626 if (i == (NUM_RX_DESC - 1))
627 tpc->RxDescArray[i].status =
628 (OWNbit | EORbit) + RX_BUF_SIZE;
629 else
630 tpc->RxDescArray[i].status = OWNbit + RX_BUF_SIZE;
631
632 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
633 tpc->RxDescArray[i].buf_addr =
634 virt_to_bus(tpc->RxBufferRing[i]);
635 }
636 }
637
638 /**************************************************************************
639 RESET - Finish setting up the ethernet interface
640 ***************************************************************************/
r8169_reset(struct nic * nic)641 static void r8169_reset(struct nic *nic)
642 {
643 int i;
644 u8 diff;
645 u32 TxPhyAddr, RxPhyAddr;
646
647 tpc->TxDescArrays = tx_ring;
648 if (tpc->TxDescArrays == 0)
649 printf("Allot Error");
650 /* Tx Desscriptor needs 256 bytes alignment; */
651 TxPhyAddr = virt_to_bus(tpc->TxDescArrays);
652 diff = 256 - (TxPhyAddr - ((TxPhyAddr >> 8) << 8));
653 TxPhyAddr += diff;
654 tpc->TxDescArray = (struct TxDesc *) (tpc->TxDescArrays + diff);
655
656 tpc->RxDescArrays = rx_ring;
657 /* Rx Desscriptor needs 256 bytes alignment; */
658 RxPhyAddr = virt_to_bus(tpc->RxDescArrays);
659 diff = 256 - (RxPhyAddr - ((RxPhyAddr >> 8) << 8));
660 RxPhyAddr += diff;
661 tpc->RxDescArray = (struct RxDesc *) (tpc->RxDescArrays + diff);
662
663 if (tpc->TxDescArrays == NULL || tpc->RxDescArrays == NULL) {
664 printf("Allocate RxDescArray or TxDescArray failed\n");
665 return;
666 }
667
668 rtl8169_init_ring(nic);
669 rtl8169_hw_start(nic);
670 /* Construct a perfect filter frame with the mac address as first match
671 * and broadcast for all others */
672 for (i = 0; i < 192; i++)
673 txb[i] = 0xFF;
674
675 txb[0] = nic->node_addr[0];
676 txb[1] = nic->node_addr[1];
677 txb[2] = nic->node_addr[2];
678 txb[3] = nic->node_addr[3];
679 txb[4] = nic->node_addr[4];
680 txb[5] = nic->node_addr[5];
681 }
682
683 /**************************************************************************
684 DISABLE - Turn off ethernet interface
685 ***************************************************************************/
r8169_disable(struct dev * dev __unused)686 static void r8169_disable(struct dev *dev __unused)
687 {
688 int i;
689 /* Stop the chip's Tx and Rx DMA processes. */
690 RTL_W8(ChipCmd, 0x00);
691
692 /* Disable interrupts by clearing the interrupt mask. */
693 RTL_W16(IntrMask, 0x0000);
694
695 RTL_W32(RxMissed, 0);
696
697 tpc->TxDescArrays = NULL;
698 tpc->RxDescArrays = NULL;
699 tpc->TxDescArray = NULL;
700 tpc->RxDescArray = NULL;
701 for (i = 0; i < NUM_RX_DESC; i++) {
702 tpc->RxBufferRing[i] = NULL;
703 }
704 }
705
706 /**************************************************************************
707 PROBE - Look for an adapter, this routine's visible to the outside
708 ***************************************************************************/
709
710 #define board_found 1
711 #define valid_link 0
r8169_probe(struct dev * dev,struct pci_device * pci)712 static int r8169_probe(struct dev *dev, struct pci_device *pci)
713 {
714 struct nic *nic = (struct nic *) dev;
715 static int board_idx = -1;
716 static int printed_version = 0;
717 int i, rc;
718 int option = -1, Cap10_100 = 0, Cap1000 = 0;
719
720 printf("r8169.c: Found %s, Vendor=%hX Device=%hX\n",
721 pci->name, pci->vendor, pci->dev_id);
722
723 board_idx++;
724
725 printed_version = 1;
726
727 /* point to private storage */
728 tpc = &tpx;
729
730 rc = rtl8169_init_board(pci); /* Return code is meaningless */
731
732 /* Get MAC address. FIXME: read EEPROM */
733 for (i = 0; i < MAC_ADDR_LEN; i++)
734 nic->node_addr[i] = RTL_R8(MAC0 + i);
735
736 dprintf(("%s: Identified chip type is '%s'.\n", pci->name,
737 rtl_chip_info[tpc->chipset].name));
738 /* Print out some hardware info */
739 printf("%s: %! at ioaddr %hX, ", pci->name, nic->node_addr,
740 ioaddr);
741
742 /* if TBI is not endbled */
743 if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
744 int val = mdio_read(PHY_AUTO_NEGO_REG);
745
746 option = media;
747 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
748 if (option > 0) {
749 printf(" Force-mode Enabled.\n");
750 Cap10_100 = 0, Cap1000 = 0;
751 switch (option) {
752 case _10_Half:
753 Cap10_100 = PHY_Cap_10_Half;
754 Cap1000 = PHY_Cap_Null;
755 break;
756 case _10_Full:
757 Cap10_100 = PHY_Cap_10_Full;
758 Cap1000 = PHY_Cap_Null;
759 break;
760 case _100_Half:
761 Cap10_100 = PHY_Cap_100_Half;
762 Cap1000 = PHY_Cap_Null;
763 break;
764 case _100_Full:
765 Cap10_100 = PHY_Cap_100_Full;
766 Cap1000 = PHY_Cap_Null;
767 break;
768 case _1000_Full:
769 Cap10_100 = PHY_Cap_Null;
770 Cap1000 = PHY_Cap_1000_Full;
771 break;
772 default:
773 break;
774 }
775 /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
776 mdio_write(PHY_AUTO_NEGO_REG,
777 Cap10_100 | (val & 0x1F));
778 mdio_write(PHY_1000_CTRL_REG, Cap1000);
779 } else {
780 dprintf(("Auto-negotiation Enabled.\n",
781 pci->name));
782
783 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
784 mdio_write(PHY_AUTO_NEGO_REG,
785 PHY_Cap_10_Half | PHY_Cap_10_Full |
786 PHY_Cap_100_Half | PHY_Cap_100_Full |
787 (val & 0x1F));
788
789 /* enable 1000 Full Mode */
790 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
791
792 }
793
794 /* Enable auto-negotiation and restart auto-nigotiation */
795 mdio_write(PHY_CTRL_REG,
796 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
797 udelay(100);
798
799 /* wait for auto-negotiation process */
800 for (i = 10000; i > 0; i--) {
801 /* Check if auto-negotiation complete */
802 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Neco_Comp) {
803 udelay(100);
804 option = RTL_R8(PHYstatus);
805 if (option & _1000bpsF) {
806 printf
807 ("1000Mbps Full-duplex operation.\n");
808 } else {
809 printf
810 ("%sMbps %s-duplex operation.\n",
811 (option & _100bps) ? "100" :
812 "10",
813 (option & FullDup) ? "Full" :
814 "Half");
815 }
816 break;
817 } else {
818 udelay(100);
819 }
820 } /* end for-loop to wait for auto-negotiation process */
821
822 } else {
823 udelay(100);
824 printf
825 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
826 pci->name,
827 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
828
829 }
830
831 r8169_reset(nic);
832 /* point to NIC specific routines */
833 dev->disable = r8169_disable;
834 nic->poll = r8169_poll;
835 nic->transmit = r8169_transmit;
836 nic->irqno = pci->irq;
837 nic->irq = r8169_irq;
838 nic->ioaddr = ioaddr;
839 return 1;
840
841 }
842
843 static struct pci_id r8169_nics[] = {
844 PCI_ROM(0x10ec, 0x8169, "r8169", "RealTek RTL8169 Gigabit Ethernet"),
845 };
846
847 struct pci_driver r8169_driver = {
848 .type = NIC_DRIVER,
849 .name = "r8169/PCI",
850 .probe = r8169_probe,
851 .ids = r8169_nics,
852 .id_count = sizeof(r8169_nics) / sizeof(r8169_nics[0]),
853 .class = 0,
854 };
855