1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2004-2005 HighPoint Technologies, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/kernel.h>
32 #include <sys/bus.h>
33 #include <sys/malloc.h>
34 #include <sys/resource.h>
35 #include <sys/time.h>
36 #include <sys/callout.h>
37 #include <sys/signalvar.h>
38 #include <sys/eventhandler.h>
39 #include <sys/proc.h>
40 #include <sys/kthread.h>
41
42 #include <sys/mutex.h>
43 #include <sys/module.h>
44 #include <sys/sx.h>
45
46 #include <dev/pci/pcireg.h>
47 #include <dev/pci/pcivar.h>
48
49 #ifndef __KERNEL__
50 #define __KERNEL__
51 #endif
52
53 #include <dev/hptmv/global.h>
54 #include <dev/hptmv/hptintf.h>
55 #include <dev/hptmv/osbsd.h>
56 #include <dev/hptmv/access601.h>
57
58
59 #ifdef DEBUG
60 #ifdef DEBUG_LEVEL
61 int hpt_dbg_level = DEBUG_LEVEL;
62 #else
63 int hpt_dbg_level = 0;
64 #endif
65 #endif
66
67 #define MV_ERROR printf
68
69 /*
70 * CAM SIM entry points
71 */
72 static int hpt_probe (device_t dev);
73 static void launch_worker_thread(void);
74 static int hpt_attach(device_t dev);
75 static int hpt_detach(device_t dev);
76 static int hpt_shutdown(device_t dev);
77 static void hpt_poll(struct cam_sim *sim);
78 static void hpt_intr(void *arg);
79 static void hpt_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg);
80 static void hpt_action(struct cam_sim *sim, union ccb *ccb);
81
82 static device_method_t driver_methods[] = {
83 /* Device interface */
84 DEVMETHOD(device_probe, hpt_probe),
85 DEVMETHOD(device_attach, hpt_attach),
86 DEVMETHOD(device_detach, hpt_detach),
87
88 DEVMETHOD(device_shutdown, hpt_shutdown),
89 DEVMETHOD_END
90 };
91
92 static driver_t hpt_pci_driver = {
93 __str(PROC_DIR_NAME),
94 driver_methods,
95 sizeof(IAL_ADAPTER_T)
96 };
97
98 DRIVER_MODULE(PROC_DIR_NAME, pci, hpt_pci_driver, NULL, NULL);
99 MODULE_DEPEND(PROC_DIR_NAME, cam, 1, 1, 1);
100
101 #define ccb_ccb_ptr spriv_ptr0
102 #define ccb_adapter ccb_h.spriv_ptr1
103
104 static void SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev);
105 static void HPTLIBAPI OsSendCommand (_VBUS_ARG union ccb * ccb);
106 static void HPTLIBAPI fOsCommandDone(_VBUS_ARG PCommand pCmd);
107 static void ccb_done(union ccb *ccb);
108 static void hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb);
109 static void hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb);
110 static void hpt_intr_locked(IAL_ADAPTER_T *pAdapter);
111 static void hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter);
112 static void hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum);
113 static void handleEdmaError(_VBUS_ARG PCommand pCmd);
114 static int hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum);
115 static int fResetActiveCommands(PVBus _vbus_p);
116 static void fRegisterVdevice(IAL_ADAPTER_T *pAdapter);
117 static int hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter);
118 static void hptmv_handle_event_disconnect(void *data);
119 static void hptmv_handle_event_connect(void *data);
120 static int start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum);
121 static void init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel);
122 static int hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel);
123 static int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg,
124 int logical);
125 static MV_BOOLEAN CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter,
126 MV_U8 channelNum, MV_COMPLETION_TYPE comp_type, MV_VOID_PTR commandId,
127 MV_U16 responseFlags, MV_U32 timeStamp,
128 MV_STORAGE_DEVICE_REGISTERS *registerStruct);
129 static MV_BOOLEAN hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter,
130 MV_EVENT_TYPE eventType, MV_U32 param1, MV_U32 param2);
131
132 #define ccb_ccb_ptr spriv_ptr0
133 #define ccb_adapter ccb_h.spriv_ptr1
134
135 static struct sx hptmv_list_lock;
136 SX_SYSINIT(hptmv_list_lock, &hptmv_list_lock, "hptmv list");
137 IAL_ADAPTER_T *gIal_Adapter = NULL;
138 IAL_ADAPTER_T *pCurAdapter = NULL;
139 static MV_SATA_CHANNEL gMvSataChannels[MAX_VBUS][MV_SATA_CHANNELS_NUM];
140
141 typedef struct st_HPT_DPC {
142 IAL_ADAPTER_T *pAdapter;
143 void (*dpc)(IAL_ADAPTER_T *, void *, UCHAR);
144 void *arg;
145 UCHAR flags;
146 } ST_HPT_DPC;
147
148 #define MAX_DPC 16
149 UCHAR DPC_Request_Nums = 0;
150 static ST_HPT_DPC DpcQueue[MAX_DPC];
151 static int DpcQueue_First=0;
152 static int DpcQueue_Last = 0;
153 static struct mtx DpcQueue_Lock;
154 MTX_SYSINIT(hpmtv_dpc_lock, &DpcQueue_Lock, "hptmv dpc", MTX_DEF);
155
156 char DRIVER_VERSION[] = "v1.16";
157
158 /*******************************************************************************
159 * Name: hptmv_free_channel
160 *
161 * Description: free allocated queues for the given channel
162 *
163 * Parameters: pMvSataAdapter - pointer to the RR18xx controller this
164 * channel connected to.
165 * channelNum - channel number.
166 *
167 ******************************************************************************/
168 static void
hptmv_free_channel(IAL_ADAPTER_T * pAdapter,MV_U8 channelNum)169 hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum)
170 {
171 HPT_ASSERT(channelNum < MV_SATA_CHANNELS_NUM);
172 pAdapter->mvSataAdapter.sataChannel[channelNum] = NULL;
173 }
174
failDevice(PVDevice pVDev)175 static void failDevice(PVDevice pVDev)
176 {
177 PVBus _vbus_p = pVDev->pVBus;
178 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)_vbus_p->OsExt;
179
180 pVDev->u.disk.df_on_line = 0;
181 pVDev->vf_online = 0;
182 if (pVDev->pfnDeviceFailed)
183 CallWhenIdle(_VBUS_P (DPC_PROC)pVDev->pfnDeviceFailed, pVDev);
184
185 fNotifyGUI(ET_DEVICE_REMOVED, pVDev);
186
187 #ifndef FOR_DEMO
188 if (pAdapter->ver_601==2 && !pAdapter->beeping) {
189 pAdapter->beeping = 1;
190 BeepOn(pAdapter->mvSataAdapter.adapterIoBaseAddress);
191 set_fail_led(&pAdapter->mvSataAdapter, pVDev->u.disk.mv->channelNumber, 1);
192 }
193 #endif
194 }
195
196 int MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel);
197
198 static void
handleEdmaError(_VBUS_ARG PCommand pCmd)199 handleEdmaError(_VBUS_ARG PCommand pCmd)
200 {
201 PDevice pDevice = &pCmd->pVDevice->u.disk;
202 MV_SATA_ADAPTER * pSataAdapter = pDevice->mv->mvSataAdapter;
203
204 if (!pDevice->df_on_line) {
205 KdPrint(("Device is offline"));
206 pCmd->Result = RETURN_BAD_DEVICE;
207 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
208 return;
209 }
210
211 if (pCmd->RetryCount++>5) {
212 hpt_printk(("too many retries on channel(%d)\n", pDevice->mv->channelNumber));
213 failed:
214 failDevice(pCmd->pVDevice);
215 pCmd->Result = RETURN_IDE_ERROR;
216 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
217 return;
218 }
219
220 /* reset the channel and retry the command */
221 if (MvSataResetChannel(pSataAdapter, pDevice->mv->channelNumber))
222 goto failed;
223
224 fNotifyGUI(ET_DEVICE_ERROR, Map2pVDevice(pDevice));
225
226 hpt_printk(("Retry on channel(%d)\n", pDevice->mv->channelNumber));
227 fDeviceSendCommand(_VBUS_P pCmd);
228 }
229
230 /****************************************************************
231 * Name: hptmv_init_channel
232 *
233 * Description: allocate request and response queues for the EDMA of the
234 * given channel and sets other fields.
235 *
236 * Parameters:
237 * pAdapter - pointer to the emulated adapter data structure
238 * channelNum - channel number.
239 * Return: 0 on success, otherwise on failure
240 ****************************************************************/
241 static int
hptmv_init_channel(IAL_ADAPTER_T * pAdapter,MV_U8 channelNum)242 hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum)
243 {
244 MV_SATA_CHANNEL *pMvSataChannel;
245 dma_addr_t req_dma_addr;
246 dma_addr_t rsp_dma_addr;
247
248 if (channelNum >= MV_SATA_CHANNELS_NUM)
249 {
250 MV_ERROR("RR18xx[%d]: Bad channelNum=%d",
251 pAdapter->mvSataAdapter.adapterId, channelNum);
252 return -1;
253 }
254
255 pMvSataChannel = &gMvSataChannels[pAdapter->mvSataAdapter.adapterId][channelNum];
256 pAdapter->mvSataAdapter.sataChannel[channelNum] = pMvSataChannel;
257 pMvSataChannel->channelNumber = channelNum;
258 pMvSataChannel->lba48Address = MV_FALSE;
259 pMvSataChannel->maxReadTransfer = MV_FALSE;
260
261 pMvSataChannel->requestQueue = (struct mvDmaRequestQueueEntry *)
262 (pAdapter->requestsArrayBaseAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE));
263 req_dma_addr = pAdapter->requestsArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE);
264
265
266 KdPrint(("requestQueue addr is 0x%llX", (HPT_U64)(ULONG_PTR)req_dma_addr));
267
268 /* check the 1K alignment of the request queue*/
269 if (req_dma_addr & 0x3ff)
270 {
271 MV_ERROR("RR18xx[%d]: request queue allocated isn't 1 K aligned,"
272 " dma_addr=%llx channel=%d\n", pAdapter->mvSataAdapter.adapterId,
273 (HPT_U64)(ULONG_PTR)req_dma_addr, channelNum);
274 return -1;
275 }
276 pMvSataChannel->requestQueuePciLowAddress = req_dma_addr;
277 pMvSataChannel->requestQueuePciHiAddress = 0;
278 KdPrint(("RR18xx[%d,%d]: request queue allocated: 0x%p",
279 pAdapter->mvSataAdapter.adapterId, channelNum,
280 pMvSataChannel->requestQueue));
281 pMvSataChannel->responseQueue = (struct mvDmaResponseQueueEntry *)
282 (pAdapter->responsesArrayBaseAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE));
283 rsp_dma_addr = pAdapter->responsesArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE);
284
285 /* check the 256 alignment of the response queue*/
286 if (rsp_dma_addr & 0xff)
287 {
288 MV_ERROR("RR18xx[%d,%d]: response queue allocated isn't 256 byte "
289 "aligned, dma_addr=%llx\n",
290 pAdapter->mvSataAdapter.adapterId, channelNum, (HPT_U64)(ULONG_PTR)rsp_dma_addr);
291 return -1;
292 }
293 pMvSataChannel->responseQueuePciLowAddress = rsp_dma_addr;
294 pMvSataChannel->responseQueuePciHiAddress = 0;
295 KdPrint(("RR18xx[%d,%d]: response queue allocated: 0x%p",
296 pAdapter->mvSataAdapter.adapterId, channelNum,
297 pMvSataChannel->responseQueue));
298
299 pAdapter->mvChannel[channelNum].online = MV_TRUE;
300 return 0;
301 }
302
303 /******************************************************************************
304 * Name: hptmv_parse_identify_results
305 *
306 * Description: this functions parses the identify command results, checks
307 * that the connected deives can be accesed by RR18xx EDMA,
308 * and updates the channel structure accordingly.
309 *
310 * Parameters: pMvSataChannel, pointer to the channel data structure.
311 *
312 * Returns: =0 ->success, < 0 ->failure.
313 *
314 ******************************************************************************/
315 static int
hptmv_parse_identify_results(MV_SATA_CHANNEL * pMvSataChannel)316 hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel)
317 {
318 MV_U16 *iden = pMvSataChannel->identifyDevice;
319
320 /*LBA addressing*/
321 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x200))
322 {
323 KdPrint(("IAL Error in IDENTIFY info: LBA not supported\n"));
324 return -1;
325 }
326 else
327 {
328 KdPrint(("%25s - %s\n", "Capabilities", "LBA supported"));
329 }
330 /*DMA support*/
331 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x100))
332 {
333 KdPrint(("IAL Error in IDENTIFY info: DMA not supported\n"));
334 return -1;
335 }
336 else
337 {
338 KdPrint(("%25s - %s\n", "Capabilities", "DMA supported"));
339 }
340 /* PIO */
341 if ((iden[IDEN_VALID] & 2) == 0)
342 {
343 KdPrint(("IAL Error in IDENTIFY info: not able to find PIO mode\n"));
344 return -1;
345 }
346 KdPrint(("%25s - 0x%02x\n", "PIO modes supported",
347 iden[IDEN_PIO_MODE_SPPORTED] & 0xff));
348
349 /*UDMA*/
350 if ((iden[IDEN_VALID] & 4) == 0)
351 {
352 KdPrint(("IAL Error in IDENTIFY info: not able to find UDMA mode\n"));
353 return -1;
354 }
355
356 /* 48 bit address */
357 if ((iden[IDEN_SUPPORTED_COMMANDS2] & 0x400))
358 {
359 KdPrint(("%25s - %s\n", "LBA48 addressing", "supported"));
360 pMvSataChannel->lba48Address = MV_TRUE;
361 }
362 else
363 {
364 KdPrint(("%25s - %s\n", "LBA48 addressing", "Not supported"));
365 pMvSataChannel->lba48Address = MV_FALSE;
366 }
367 return 0;
368 }
369
370 static void
init_vdev_params(IAL_ADAPTER_T * pAdapter,MV_U8 channel)371 init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel)
372 {
373 PVDevice pVDev = &pAdapter->VDevices[channel];
374 MV_SATA_CHANNEL *pMvSataChannel = pAdapter->mvSataAdapter.sataChannel[channel];
375 MV_U16_PTR IdentifyData = pMvSataChannel->identifyDevice;
376
377 pMvSataChannel->outstandingCommands = 0;
378
379 pVDev->u.disk.mv = pMvSataChannel;
380 pVDev->u.disk.df_on_line = 1;
381 pVDev->u.disk.pVBus = &pAdapter->VBus;
382 pVDev->pVBus = &pAdapter->VBus;
383
384 #ifdef SUPPORT_48BIT_LBA
385 if (pMvSataChannel->lba48Address == MV_TRUE)
386 pVDev->u.disk.dDeRealCapacity = ((IdentifyData[101]<<16) | IdentifyData[100]) - 1;
387 else
388 #endif
389 if(IdentifyData[53] & 1) {
390 pVDev->u.disk.dDeRealCapacity =
391 (((IdentifyData[58]<<16 | IdentifyData[57]) < (IdentifyData[61]<<16 | IdentifyData[60])) ?
392 (IdentifyData[61]<<16 | IdentifyData[60]) :
393 (IdentifyData[58]<<16 | IdentifyData[57])) - 1;
394 } else
395 pVDev->u.disk.dDeRealCapacity =
396 (IdentifyData[61]<<16 | IdentifyData[60]) - 1;
397
398 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting =
399 pAdapter->mvChannel[channel].maxPioModeSupported - MV_ATA_TRANSFER_PIO_0;
400
401 if (pAdapter->mvChannel[channel].maxUltraDmaModeSupported!=0xFF) {
402 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting =
403 pAdapter->mvChannel[channel].maxUltraDmaModeSupported - MV_ATA_TRANSFER_UDMA_0 + 8;
404 }
405 }
406
device_change(IAL_ADAPTER_T * pAdapter,MV_U8 channelIndex,int plugged)407 static void device_change(IAL_ADAPTER_T *pAdapter , MV_U8 channelIndex, int plugged)
408 {
409 PVDevice pVDev;
410 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter;
411 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelIndex];
412
413 if (!pMvSataChannel) return;
414
415 if (plugged)
416 {
417 pVDev = &(pAdapter->VDevices[channelIndex]);
418 init_vdev_params(pAdapter, channelIndex);
419
420 pVDev->VDeviceType = pVDev->u.disk.df_atapi? VD_ATAPI :
421 pVDev->u.disk.df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK;
422
423 pVDev->VDeviceCapacity = pVDev->u.disk.dDeRealCapacity-SAVE_FOR_RAID_INFO;
424 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType];
425 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType];
426 pVDev->vf_online = 1;
427
428 #ifdef SUPPORT_ARRAY
429 if(pVDev->pParent)
430 {
431 int iMember;
432 for (iMember = 0; iMember < pVDev->pParent->u.array.bArnMember; iMember++)
433 if((PVDevice)pVDev->pParent->u.array.pMember[iMember] == pVDev)
434 pVDev->pParent->u.array.pMember[iMember] = NULL;
435 pVDev->pParent = NULL;
436 }
437 #endif
438 fNotifyGUI(ET_DEVICE_PLUGGED,pVDev);
439 fCheckBootable(pVDev);
440 RegisterVDevice(pVDev);
441
442 #ifndef FOR_DEMO
443 if (pAdapter->beeping) {
444 pAdapter->beeping = 0;
445 BeepOff(pAdapter->mvSataAdapter.adapterIoBaseAddress);
446 }
447 #endif
448
449 }
450 else
451 {
452 pVDev = &(pAdapter->VDevices[channelIndex]);
453 failDevice(pVDev);
454 }
455 }
456
457 static int
start_channel(IAL_ADAPTER_T * pAdapter,MV_U8 channelNum)458 start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum)
459 {
460 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter;
461 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelNum];
462 MV_CHANNEL *pChannelInfo = &(pAdapter->mvChannel[channelNum]);
463 MV_U32 udmaMode,pioMode;
464
465 KdPrint(("RR18xx [%d]: start channel (%d)", pMvSataAdapter->adapterId,
466 channelNum));
467
468
469 /* Software reset channel */
470 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE)
471 {
472 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n",
473 pMvSataAdapter->adapterId, channelNum);
474 return -1;
475 }
476
477 /* Hardware reset channel */
478 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE)
479 {
480 /* If failed, try again - this is when trying to hardreset a channel */
481 /* when drive is just spinning up */
482 StallExec(5000000); /* wait 5 sec before trying again */
483 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE)
484 {
485 MV_ERROR("RR18xx [%d,%d]: failed to perform Hard reset\n",
486 pMvSataAdapter->adapterId, channelNum);
487 return -1;
488 }
489 }
490
491 /* identify device*/
492 if (mvStorageDevATAIdentifyDevice(pMvSataAdapter, channelNum) == MV_FALSE)
493 {
494 MV_ERROR("RR18xx [%d,%d]: failed to perform ATA Identify command\n"
495 , pMvSataAdapter->adapterId, channelNum);
496 return -1;
497 }
498 if (hptmv_parse_identify_results(pMvSataChannel))
499 {
500 MV_ERROR("RR18xx [%d,%d]: Error in parsing ATA Identify message\n"
501 , pMvSataAdapter->adapterId, channelNum);
502 return -1;
503 }
504
505 /* mvStorageDevATASetFeatures */
506 /* Disable 8 bit PIO in case CFA enabled */
507 if (pMvSataChannel->identifyDevice[86] & 4)
508 {
509 KdPrint(("RR18xx [%d]: Disable 8 bit PIO (CFA enabled) \n",
510 pMvSataAdapter->adapterId));
511 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
512 MV_ATA_SET_FEATURES_DISABLE_8_BIT_PIO, 0,
513 0, 0, 0) == MV_FALSE)
514 {
515 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures"
516 " failed\n", pMvSataAdapter->adapterId, channelNum);
517 return -1;
518 }
519 }
520 /* Write cache */
521 #ifdef ENABLE_WRITE_CACHE
522 if (pMvSataChannel->identifyDevice[82] & 0x20)
523 {
524 if (!(pMvSataChannel->identifyDevice[85] & 0x20)) /* if not enabled by default */
525 {
526 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
527 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0,
528 0, 0, 0) == MV_FALSE)
529 {
530 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n",
531 pMvSataAdapter->adapterId, channelNum);
532 return -1;
533 }
534 }
535 KdPrint(("RR18xx [%d]: channel %d, write cache enabled\n",
536 pMvSataAdapter->adapterId, channelNum));
537 }
538 else
539 {
540 KdPrint(("RR18xx [%d]: channel %d, write cache not supported\n",
541 pMvSataAdapter->adapterId, channelNum));
542 }
543 #else /* disable write cache */
544 {
545 if (pMvSataChannel->identifyDevice[85] & 0x20)
546 {
547 KdPrint(("RR18xx [%d]: channel =%d, disable write cache\n",
548 pMvSataAdapter->adapterId, channelNum));
549 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
550 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0,
551 0, 0, 0) == MV_FALSE)
552 {
553 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n",
554 pMvSataAdapter->adapterId, channelNum);
555 return -1;
556 }
557 }
558 KdPrint(("RR18xx [%d]: channel=%d, write cache disabled\n",
559 pMvSataAdapter->adapterId, channelNum));
560 }
561 #endif
562
563 /* Set transfer mode */
564 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_SLOW\n",
565 pMvSataAdapter->adapterId));
566 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
567 MV_ATA_SET_FEATURES_TRANSFER,
568 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) ==
569 MV_FALSE)
570 {
571 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n",
572 pMvSataAdapter->adapterId, channelNum);
573 return -1;
574 }
575
576 if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 1)
577 {
578 pioMode = MV_ATA_TRANSFER_PIO_4;
579 }
580 else if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 2)
581 {
582 pioMode = MV_ATA_TRANSFER_PIO_3;
583 }
584 else
585 {
586 MV_ERROR("IAL Error in IDENTIFY info: PIO modes 3 and 4 not supported\n");
587 pioMode = MV_ATA_TRANSFER_PIO_SLOW;
588 }
589
590 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_4\n",
591 pMvSataAdapter->adapterId));
592 pAdapter->mvChannel[channelNum].maxPioModeSupported = pioMode;
593 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
594 MV_ATA_SET_FEATURES_TRANSFER,
595 pioMode, 0, 0, 0) == MV_FALSE)
596 {
597 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n",
598 pMvSataAdapter->adapterId, channelNum);
599 return -1;
600 }
601
602 udmaMode = MV_ATA_TRANSFER_UDMA_0;
603 if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x40)
604 {
605 udmaMode = MV_ATA_TRANSFER_UDMA_6;
606 }
607 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x20)
608 {
609 udmaMode = MV_ATA_TRANSFER_UDMA_5;
610 }
611 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x10)
612 {
613 udmaMode = MV_ATA_TRANSFER_UDMA_4;
614 }
615 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 8)
616 {
617 udmaMode = MV_ATA_TRANSFER_UDMA_3;
618 }
619 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 4)
620 {
621 udmaMode = MV_ATA_TRANSFER_UDMA_2;
622 }
623
624 KdPrint(("RR18xx [%d] Set transfer mode XFER_UDMA_%d\n",
625 pMvSataAdapter->adapterId, udmaMode & 0xf));
626 pChannelInfo->maxUltraDmaModeSupported = udmaMode;
627
628 /*if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
629 MV_ATA_SET_FEATURES_TRANSFER, udmaMode,
630 0, 0, 0) == MV_FALSE)
631 {
632 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n",
633 pMvSataAdapter->adapterId, channelNum);
634 return -1;
635 }*/
636 if (pChannelInfo->maxUltraDmaModeSupported == 0xFF)
637 return TRUE;
638 else
639 do
640 {
641 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
642 MV_ATA_SET_FEATURES_TRANSFER,
643 pChannelInfo->maxUltraDmaModeSupported,
644 0, 0, 0) == MV_FALSE)
645 {
646 if (pChannelInfo->maxUltraDmaModeSupported > MV_ATA_TRANSFER_UDMA_0)
647 {
648 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE)
649 {
650 MV_REG_WRITE_BYTE(pMvSataAdapter->adapterIoBaseAddress,
651 pMvSataChannel->eDmaRegsOffset +
652 0x11c, /* command reg */
653 MV_ATA_COMMAND_IDLE_IMMEDIATE);
654 mvMicroSecondsDelay(10000);
655 mvSataChannelHardReset(pMvSataAdapter, channelNum);
656 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE)
657 return FALSE;
658 }
659 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE)
660 return FALSE;
661 pChannelInfo->maxUltraDmaModeSupported--;
662 continue;
663 }
664 else return FALSE;
665 }
666 break;
667 }while (1);
668
669 /* Read look ahead */
670 #ifdef ENABLE_READ_AHEAD
671 if (pMvSataChannel->identifyDevice[82] & 0x40)
672 {
673 if (!(pMvSataChannel->identifyDevice[85] & 0x40)) /* if not enabled by default */
674 {
675 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
676 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0,
677 0, 0) == MV_FALSE)
678 {
679 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n",
680 pMvSataAdapter->adapterId, channelNum);
681 return -1;
682 }
683 }
684 KdPrint(("RR18xx [%d]: channel=%d, read look ahead enabled\n",
685 pMvSataAdapter->adapterId, channelNum));
686 }
687 else
688 {
689 KdPrint(("RR18xx [%d]: channel %d, Read Look Ahead not supported\n",
690 pMvSataAdapter->adapterId, channelNum));
691 }
692 #else
693 {
694 if (pMvSataChannel->identifyDevice[86] & 0x20)
695 {
696 KdPrint(("RR18xx [%d]:channel %d, disable read look ahead\n",
697 pMvSataAdapter->adapterId, channelNum));
698 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
699 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0,
700 0, 0) == MV_FALSE)
701 {
702 MV_ERROR("RR18xx [%d]:channel %d: ATA Set Features failed\n",
703 pMvSataAdapter->adapterId, channelNum);
704 return -1;
705 }
706 }
707 KdPrint(("RR18xx [%d]:channel %d, read look ahead disabled\n",
708 pMvSataAdapter->adapterId, channelNum));
709 }
710 #endif
711
712
713 {
714 KdPrint(("RR18xx [%d]: channel %d config EDMA, Non Queued Mode\n",
715 pMvSataAdapter->adapterId,
716 channelNum));
717 if (mvSataConfigEdmaMode(pMvSataAdapter, channelNum,
718 MV_EDMA_MODE_NOT_QUEUED, 0) == MV_FALSE)
719 {
720 MV_ERROR("RR18xx [%d] channel %d Error: mvSataConfigEdmaMode failed\n",
721 pMvSataAdapter->adapterId, channelNum);
722 return -1;
723 }
724 }
725 /* Enable EDMA */
726 if (mvSataEnableChannelDma(pMvSataAdapter, channelNum) == MV_FALSE)
727 {
728 MV_ERROR("RR18xx [%d] Failed to enable DMA, channel=%d\n",
729 pMvSataAdapter->adapterId, channelNum);
730 return -1;
731 }
732 MV_ERROR("RR18xx [%d,%d]: channel started successfully\n",
733 pMvSataAdapter->adapterId, channelNum);
734
735 #ifndef FOR_DEMO
736 set_fail_led(pMvSataAdapter, channelNum, 0);
737 #endif
738 return 0;
739 }
740
741 static void
hptmv_handle_event(void * data,int flag)742 hptmv_handle_event(void * data, int flag)
743 {
744 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)data;
745 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter;
746 MV_U8 channelIndex;
747
748 mtx_assert(&pAdapter->lock, MA_OWNED);
749 /* mvOsSemTake(&pMvSataAdapter->semaphore); */
750 for (channelIndex = 0; channelIndex < MV_SATA_CHANNELS_NUM; channelIndex++)
751 {
752 switch(pAdapter->sataEvents[channelIndex])
753 {
754 case SATA_EVENT_CHANNEL_CONNECTED:
755 /* Handle only connects */
756 if (flag == 1)
757 break;
758 KdPrint(("RR18xx [%d,%d]: new device connected\n",
759 pMvSataAdapter->adapterId, channelIndex));
760 hptmv_init_channel(pAdapter, channelIndex);
761 if (mvSataConfigureChannel( pMvSataAdapter, channelIndex) == MV_FALSE)
762 {
763 MV_ERROR("RR18xx [%d,%d] Failed to configure\n",
764 pMvSataAdapter->adapterId, channelIndex);
765 hptmv_free_channel(pAdapter, channelIndex);
766 }
767 else
768 {
769 /*mvSataChannelHardReset(pMvSataAdapter, channel);*/
770 if (start_channel( pAdapter, channelIndex))
771 {
772 MV_ERROR("RR18xx [%d,%d]Failed to start channel\n",
773 pMvSataAdapter->adapterId, channelIndex);
774 hptmv_free_channel(pAdapter, channelIndex);
775 }
776 else
777 {
778 device_change(pAdapter, channelIndex, TRUE);
779 }
780 }
781 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE;
782 break;
783
784 case SATA_EVENT_CHANNEL_DISCONNECTED:
785 /* Handle only disconnects */
786 if (flag == 0)
787 break;
788 KdPrint(("RR18xx [%d,%d]: device disconnected\n",
789 pMvSataAdapter->adapterId, channelIndex));
790 /* Flush pending commands */
791 if(pMvSataAdapter->sataChannel[channelIndex])
792 {
793 _VBUS_INST(&pAdapter->VBus)
794 mvSataFlushDmaQueue (pMvSataAdapter, channelIndex,
795 MV_FLUSH_TYPE_CALLBACK);
796 CheckPendingCall(_VBUS_P0);
797 mvSataRemoveChannel(pMvSataAdapter,channelIndex);
798 hptmv_free_channel(pAdapter, channelIndex);
799 pMvSataAdapter->sataChannel[channelIndex] = NULL;
800 KdPrint(("RR18xx [%d,%d]: channel removed\n",
801 pMvSataAdapter->adapterId, channelIndex));
802 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0)
803 Check_Idle_Call(pAdapter);
804 }
805 else
806 {
807 KdPrint(("RR18xx [%d,%d]: channel already removed!!\n",
808 pMvSataAdapter->adapterId, channelIndex));
809 }
810 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE;
811 break;
812
813 case SATA_EVENT_NO_CHANGE:
814 break;
815
816 default:
817 break;
818 }
819 }
820 /* mvOsSemRelease(&pMvSataAdapter->semaphore); */
821 }
822
823 #define EVENT_CONNECT 1
824 #define EVENT_DISCONNECT 0
825
826 static void
hptmv_handle_event_connect(void * data)827 hptmv_handle_event_connect(void *data)
828 {
829 hptmv_handle_event (data, 0);
830 }
831
832 static void
hptmv_handle_event_disconnect(void * data)833 hptmv_handle_event_disconnect(void *data)
834 {
835 hptmv_handle_event (data, 1);
836 }
837
838 static MV_BOOLEAN
hptmv_event_notify(MV_SATA_ADAPTER * pMvSataAdapter,MV_EVENT_TYPE eventType,MV_U32 param1,MV_U32 param2)839 hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, MV_EVENT_TYPE eventType,
840 MV_U32 param1, MV_U32 param2)
841 {
842 IAL_ADAPTER_T *pAdapter = pMvSataAdapter->IALData;
843
844 switch (eventType)
845 {
846 case MV_EVENT_TYPE_SATA_CABLE:
847 {
848 MV_U8 channel = param2;
849
850 if (param1 == EVENT_CONNECT)
851 {
852 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_CONNECTED;
853 KdPrint(("RR18xx [%d,%d]: device connected event received\n",
854 pMvSataAdapter->adapterId, channel));
855 /* Delete previous timers (if multiple drives connected in the same time */
856 callout_reset(&pAdapter->event_timer_connect, 10 * hz, hptmv_handle_event_connect, pAdapter);
857 }
858 else if (param1 == EVENT_DISCONNECT)
859 {
860 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_DISCONNECTED;
861 KdPrint(("RR18xx [%d,%d]: device disconnected event received \n",
862 pMvSataAdapter->adapterId, channel));
863 device_change(pAdapter, channel, FALSE);
864 /* Delete previous timers (if multiple drives disconnected in the same time */
865 /*callout_reset(&pAdapter->event_timer_disconnect, 10 * hz, hptmv_handle_event_disconnect, pAdapter); */
866 /*It is not necessary to wait, handle it directly*/
867 hptmv_handle_event_disconnect(pAdapter);
868 }
869 else
870 {
871
872 MV_ERROR("RR18xx: illegal value for param1(%d) at "
873 "connect/disconnect event, host=%d\n", param1,
874 pMvSataAdapter->adapterId );
875
876 }
877 }
878 break;
879 case MV_EVENT_TYPE_ADAPTER_ERROR:
880 KdPrint(("RR18xx: DEVICE error event received, pci cause "
881 "reg=%x, don't how to handle this\n", param1));
882 return MV_TRUE;
883 default:
884 MV_ERROR("RR18xx[%d]: unknown event type (%d)\n",
885 pMvSataAdapter->adapterId, eventType);
886 return MV_FALSE;
887 }
888 return MV_TRUE;
889 }
890
891 static int
hptmv_allocate_edma_queues(IAL_ADAPTER_T * pAdapter)892 hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter)
893 {
894 pAdapter->requestsArrayBaseAddr = (MV_U8 *)contigmalloc(REQUESTS_ARRAY_SIZE,
895 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul);
896 if (pAdapter->requestsArrayBaseAddr == NULL)
897 {
898 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA request"
899 " queues\n", pAdapter->mvSataAdapter.adapterId);
900 return -1;
901 }
902 pAdapter->requestsArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->requestsArrayBaseAddr);
903 pAdapter->requestsArrayBaseAlignedAddr = pAdapter->requestsArrayBaseAddr;
904 pAdapter->requestsArrayBaseAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE;
905 pAdapter->requestsArrayBaseAlignedAddr = (MV_U8 *)
906 (((ULONG_PTR)pAdapter->requestsArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1));
907 pAdapter->requestsArrayBaseDmaAlignedAddr = pAdapter->requestsArrayBaseDmaAddr;
908 pAdapter->requestsArrayBaseDmaAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE;
909 pAdapter->requestsArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1);
910
911 if ((pAdapter->requestsArrayBaseDmaAlignedAddr - pAdapter->requestsArrayBaseDmaAddr) !=
912 (pAdapter->requestsArrayBaseAlignedAddr - pAdapter->requestsArrayBaseAddr))
913 {
914 MV_ERROR("RR18xx[%d]: Error in Request Quueues Alignment\n",
915 pAdapter->mvSataAdapter.adapterId);
916 free(pAdapter->requestsArrayBaseAddr, M_DEVBUF);
917 return -1;
918 }
919 /* response queues */
920 pAdapter->responsesArrayBaseAddr = (MV_U8 *)contigmalloc(RESPONSES_ARRAY_SIZE,
921 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul);
922 if (pAdapter->responsesArrayBaseAddr == NULL)
923 {
924 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA response"
925 " queues\n", pAdapter->mvSataAdapter.adapterId);
926 free(pAdapter->requestsArrayBaseAddr, M_DEVBUF);
927 return -1;
928 }
929 pAdapter->responsesArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->responsesArrayBaseAddr);
930 pAdapter->responsesArrayBaseAlignedAddr = pAdapter->responsesArrayBaseAddr;
931 pAdapter->responsesArrayBaseAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE;
932 pAdapter->responsesArrayBaseAlignedAddr = (MV_U8 *)
933 (((ULONG_PTR)pAdapter->responsesArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1));
934 pAdapter->responsesArrayBaseDmaAlignedAddr = pAdapter->responsesArrayBaseDmaAddr;
935 pAdapter->responsesArrayBaseDmaAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE;
936 pAdapter->responsesArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1);
937
938 if ((pAdapter->responsesArrayBaseDmaAlignedAddr - pAdapter->responsesArrayBaseDmaAddr) !=
939 (pAdapter->responsesArrayBaseAlignedAddr - pAdapter->responsesArrayBaseAddr))
940 {
941 MV_ERROR("RR18xx[%d]: Error in Response Queues Alignment\n",
942 pAdapter->mvSataAdapter.adapterId);
943 free(pAdapter->requestsArrayBaseAddr, M_DEVBUF);
944 free(pAdapter->responsesArrayBaseAddr, M_DEVBUF);
945 return -1;
946 }
947 return 0;
948 }
949
950 static void
hptmv_free_edma_queues(IAL_ADAPTER_T * pAdapter)951 hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter)
952 {
953 free(pAdapter->requestsArrayBaseAddr, M_DEVBUF);
954 free(pAdapter->responsesArrayBaseAddr, M_DEVBUF);
955 }
956
957 static PVOID
AllocatePRDTable(IAL_ADAPTER_T * pAdapter)958 AllocatePRDTable(IAL_ADAPTER_T *pAdapter)
959 {
960 PVOID ret;
961 if (pAdapter->pFreePRDLink) {
962 KdPrint(("pAdapter->pFreePRDLink:%p\n",pAdapter->pFreePRDLink));
963 ret = pAdapter->pFreePRDLink;
964 pAdapter->pFreePRDLink = *(void**)ret;
965 return ret;
966 }
967 return NULL;
968 }
969
970 static void
FreePRDTable(IAL_ADAPTER_T * pAdapter,PVOID PRDTable)971 FreePRDTable(IAL_ADAPTER_T *pAdapter, PVOID PRDTable)
972 {
973 *(void**)PRDTable = pAdapter->pFreePRDLink;
974 pAdapter->pFreePRDLink = PRDTable;
975 }
976
977 extern PVDevice fGetFirstChild(PVDevice pLogical);
978 extern void fResetBootMark(PVDevice pLogical);
979 static void
fRegisterVdevice(IAL_ADAPTER_T * pAdapter)980 fRegisterVdevice(IAL_ADAPTER_T *pAdapter)
981 {
982 PVDevice pPhysical, pLogical;
983 PVBus pVBus;
984 int i,j;
985
986 for (i = 0; i < MV_SATA_CHANNELS_NUM; i++) {
987 pPhysical = &(pAdapter->VDevices[i]);
988 pLogical = pPhysical;
989 while (pLogical->pParent) pLogical = pLogical->pParent;
990 if (pLogical->vf_online==0) {
991 pPhysical->vf_bootmark = pLogical->vf_bootmark = 0;
992 continue;
993 }
994 if (pLogical->VDeviceType==VD_SPARE || pPhysical!=fGetFirstChild(pLogical))
995 continue;
996
997 pVBus = &pAdapter->VBus;
998 if(pVBus)
999 {
1000 j=0;
1001 while(j<MAX_VDEVICE_PER_VBUS && pVBus->pVDevice[j]) j++;
1002 if(j<MAX_VDEVICE_PER_VBUS){
1003 pVBus->pVDevice[j] = pLogical;
1004 pLogical->pVBus = pVBus;
1005
1006 if (j>0 && pLogical->vf_bootmark) {
1007 if (pVBus->pVDevice[0]->vf_bootmark) {
1008 fResetBootMark(pLogical);
1009 }
1010 else {
1011 do { pVBus->pVDevice[j] = pVBus->pVDevice[j-1]; } while (--j);
1012 pVBus->pVDevice[0] = pLogical;
1013 }
1014 }
1015 }
1016 }
1017 }
1018 }
1019
1020 PVDevice
GetSpareDisk(_VBUS_ARG PVDevice pArray)1021 GetSpareDisk(_VBUS_ARG PVDevice pArray)
1022 {
1023 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pArray->pVBus->OsExt;
1024 LBA_T capacity = LongDiv(pArray->VDeviceCapacity, pArray->u.array.bArnMember-1);
1025 LBA_T thiscap, maxcap = MAX_LBA_T;
1026 PVDevice pVDevice, pFind = NULL;
1027 int i;
1028
1029 for (i=0; i < MV_SATA_CHANNELS_NUM; i++) {
1030 pVDevice = &pAdapter->VDevices[i];
1031 if(!pVDevice)
1032 continue;
1033 thiscap = pArray->vf_format_v2? pVDevice->u.disk.dDeRealCapacity : pVDevice->VDeviceCapacity;
1034 /* find the smallest usable spare disk */
1035 if (pVDevice->VDeviceType==VD_SPARE &&
1036 pVDevice->u.disk.df_on_line &&
1037 thiscap < maxcap &&
1038 thiscap >= capacity)
1039 {
1040 maxcap = pVDevice->VDeviceCapacity;
1041 pFind = pVDevice;
1042 }
1043 }
1044 return pFind;
1045 }
1046
1047 /******************************************************************
1048 * IO ATA Command
1049 *******************************************************************/
1050 int HPTLIBAPI
fDeReadWrite(PDevice pDev,ULONG Lba,UCHAR Cmd,void * tmpBuffer)1051 fDeReadWrite(PDevice pDev, ULONG Lba, UCHAR Cmd, void *tmpBuffer)
1052 {
1053 return mvReadWrite(pDev->mv, Lba, Cmd, tmpBuffer);
1054 }
1055
fDeSelectMode(PDevice pDev,UCHAR NewMode)1056 void HPTLIBAPI fDeSelectMode(PDevice pDev, UCHAR NewMode)
1057 {
1058 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1059 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1060 MV_U8 channelIndex = pSataChannel->channelNumber;
1061 UCHAR mvMode;
1062 /* 508x don't use MW-DMA? */
1063 if (NewMode>4 && NewMode<8) NewMode = 4;
1064 pDev->bDeModeSetting = NewMode;
1065 if (NewMode<=4)
1066 mvMode = MV_ATA_TRANSFER_PIO_0 + NewMode;
1067 else
1068 mvMode = MV_ATA_TRANSFER_UDMA_0 + (NewMode-8);
1069
1070 /*To fix 88i8030 bug*/
1071 if (mvMode > MV_ATA_TRANSFER_UDMA_0 && mvMode < MV_ATA_TRANSFER_UDMA_4)
1072 mvMode = MV_ATA_TRANSFER_UDMA_0;
1073
1074 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1075 /* Flush pending commands */
1076 mvSataFlushDmaQueue (pSataAdapter, channelIndex, MV_FLUSH_TYPE_NONE);
1077
1078 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1079 MV_ATA_SET_FEATURES_TRANSFER,
1080 mvMode, 0, 0, 0) == MV_FALSE)
1081 {
1082 KdPrint(("channel %d: Set Features failed\n", channelIndex));
1083 }
1084 /* Enable EDMA */
1085 if (mvSataEnableChannelDma(pSataAdapter, channelIndex) == MV_FALSE)
1086 KdPrint(("Failed to enable DMA, channel=%d", channelIndex));
1087 }
1088
fDeSetTCQ(PDevice pDev,int enable,int depth)1089 int HPTLIBAPI fDeSetTCQ(PDevice pDev, int enable, int depth)
1090 {
1091 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1092 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1093 MV_U8 channelIndex = pSataChannel->channelNumber;
1094 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData;
1095 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]);
1096 int dmaActive = pSataChannel->queueCommandsEnabled;
1097 int ret = 0;
1098
1099 if (dmaActive) {
1100 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1101 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK);
1102 }
1103
1104 if (enable) {
1105 if (pSataChannel->queuedDMA == MV_EDMA_MODE_NOT_QUEUED &&
1106 (pSataChannel->identifyDevice[IDEN_SUPPORTED_COMMANDS2] & (0x2))) {
1107 UCHAR depth = ((pSataChannel->identifyDevice[IDEN_QUEUE_DEPTH]) & 0x1f) + 1;
1108 channelInfo->queueDepth = (depth==32)? 31 : depth;
1109 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_QUEUED, depth);
1110 ret = 1;
1111 }
1112 }
1113 else
1114 {
1115 if (pSataChannel->queuedDMA != MV_EDMA_MODE_NOT_QUEUED) {
1116 channelInfo->queueDepth = 2;
1117 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_NOT_QUEUED, 0);
1118 ret = 1;
1119 }
1120 }
1121
1122 if (dmaActive)
1123 mvSataEnableChannelDma(pSataAdapter,channelIndex);
1124 return ret;
1125 }
1126
fDeSetNCQ(PDevice pDev,int enable,int depth)1127 int HPTLIBAPI fDeSetNCQ(PDevice pDev, int enable, int depth)
1128 {
1129 return 0;
1130 }
1131
fDeSetWriteCache(PDevice pDev,int enable)1132 int HPTLIBAPI fDeSetWriteCache(PDevice pDev, int enable)
1133 {
1134 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1135 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1136 MV_U8 channelIndex = pSataChannel->channelNumber;
1137 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData;
1138 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]);
1139 int dmaActive = pSataChannel->queueCommandsEnabled;
1140 int ret = 0;
1141
1142 if (dmaActive) {
1143 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1144 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK);
1145 }
1146
1147 if ((pSataChannel->identifyDevice[82] & (0x20))) {
1148 if (enable) {
1149 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1150 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 0, 0, 0))
1151 {
1152 channelInfo->writeCacheEnabled = MV_TRUE;
1153 ret = 1;
1154 }
1155 }
1156 else {
1157 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1158 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 0, 0, 0))
1159 {
1160 channelInfo->writeCacheEnabled = MV_FALSE;
1161 ret = 1;
1162 }
1163 }
1164 }
1165
1166 if (dmaActive)
1167 mvSataEnableChannelDma(pSataAdapter,channelIndex);
1168 return ret;
1169 }
1170
fDeSetReadAhead(PDevice pDev,int enable)1171 int HPTLIBAPI fDeSetReadAhead(PDevice pDev, int enable)
1172 {
1173 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1174 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1175 MV_U8 channelIndex = pSataChannel->channelNumber;
1176 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData;
1177 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]);
1178 int dmaActive = pSataChannel->queueCommandsEnabled;
1179 int ret = 0;
1180
1181 if (dmaActive) {
1182 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1183 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK);
1184 }
1185
1186 if ((pSataChannel->identifyDevice[82] & (0x40))) {
1187 if (enable) {
1188 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1189 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 0, 0))
1190 {
1191 channelInfo->readAheadEnabled = MV_TRUE;
1192 ret = 1;
1193 }
1194 }
1195 else {
1196 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1197 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 0, 0))
1198 {
1199 channelInfo->readAheadEnabled = MV_FALSE;
1200 ret = 1;
1201 }
1202 }
1203 }
1204
1205 if (dmaActive)
1206 mvSataEnableChannelDma(pSataAdapter,channelIndex);
1207 return ret;
1208 }
1209
1210 #ifdef SUPPORT_ARRAY
1211 #define IdeRegisterVDevice fCheckArray
1212 #else
1213 void
IdeRegisterVDevice(PDevice pDev)1214 IdeRegisterVDevice(PDevice pDev)
1215 {
1216 PVDevice pVDev = Map2pVDevice(pDev);
1217
1218 pVDev->VDeviceType = pDev->df_atapi? VD_ATAPI :
1219 pDev->df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK;
1220 pVDev->vf_online = 1;
1221 pVDev->VDeviceCapacity = pDev->dDeRealCapacity;
1222 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType];
1223 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType];
1224 }
1225 #endif
1226
1227 static __inline PBUS_DMAMAP
dmamap_get(struct IALAdapter * pAdapter)1228 dmamap_get(struct IALAdapter * pAdapter)
1229 {
1230 PBUS_DMAMAP p = pAdapter->pbus_dmamap_list;
1231 if (p)
1232 pAdapter->pbus_dmamap_list = p-> next;
1233 return p;
1234 }
1235
1236 static __inline void
dmamap_put(PBUS_DMAMAP p)1237 dmamap_put(PBUS_DMAMAP p)
1238 {
1239 p->next = p->pAdapter->pbus_dmamap_list;
1240 p->pAdapter->pbus_dmamap_list = p;
1241 }
1242
1243 static int num_adapters = 0;
1244 static int
init_adapter(IAL_ADAPTER_T * pAdapter)1245 init_adapter(IAL_ADAPTER_T *pAdapter)
1246 {
1247 PVBus _vbus_p = &pAdapter->VBus;
1248 MV_SATA_ADAPTER *pMvSataAdapter;
1249 int i, channel, rid;
1250
1251 PVDevice pVDev;
1252
1253 mtx_init(&pAdapter->lock, "hptsleeplock", NULL, MTX_DEF);
1254 callout_init_mtx(&pAdapter->event_timer_connect, &pAdapter->lock, 0);
1255 callout_init_mtx(&pAdapter->event_timer_disconnect, &pAdapter->lock, 0);
1256
1257 sx_xlock(&hptmv_list_lock);
1258 pAdapter->next = 0;
1259
1260 if(gIal_Adapter == NULL){
1261 gIal_Adapter = pAdapter;
1262 pCurAdapter = gIal_Adapter;
1263 }
1264 else {
1265 pCurAdapter->next = pAdapter;
1266 pCurAdapter = pAdapter;
1267 }
1268 sx_xunlock(&hptmv_list_lock);
1269
1270 pAdapter->outstandingCommands = 0;
1271
1272 pMvSataAdapter = &(pAdapter->mvSataAdapter);
1273 _vbus_p->OsExt = (void *)pAdapter;
1274 pMvSataAdapter->IALData = pAdapter;
1275
1276 if (bus_dma_tag_create(bus_get_dma_tag(pAdapter->hpt_dev),/* parent */
1277 4, /* alignment */
1278 BUS_SPACE_MAXADDR_32BIT+1, /* boundary */
1279 BUS_SPACE_MAXADDR, /* lowaddr */
1280 BUS_SPACE_MAXADDR, /* highaddr */
1281 NULL, NULL, /* filter, filterarg */
1282 PAGE_SIZE * (MAX_SG_DESCRIPTORS-1), /* maxsize */
1283 MAX_SG_DESCRIPTORS, /* nsegments */
1284 0x10000, /* maxsegsize */
1285 BUS_DMA_WAITOK, /* flags */
1286 busdma_lock_mutex, /* lockfunc */
1287 &pAdapter->lock, /* lockfuncarg */
1288 &pAdapter->io_dma_parent /* tag */))
1289 {
1290 return ENXIO;
1291 }
1292
1293
1294 if (hptmv_allocate_edma_queues(pAdapter))
1295 {
1296 MV_ERROR("RR18xx: Failed to allocate memory for EDMA queues\n");
1297 return ENOMEM;
1298 }
1299
1300 /* also map EPROM address */
1301 rid = 0x10;
1302 if (!(pAdapter->mem_res = bus_alloc_resource_any(pAdapter->hpt_dev,
1303 SYS_RES_MEMORY, &rid, RF_ACTIVE))
1304 ||
1305 !(pMvSataAdapter->adapterIoBaseAddress = rman_get_virtual(pAdapter->mem_res)))
1306 {
1307 MV_ERROR("RR18xx: Failed to remap memory space\n");
1308 hptmv_free_edma_queues(pAdapter);
1309 return ENXIO;
1310 }
1311 else
1312 {
1313 KdPrint(("RR18xx: io base address 0x%p\n", pMvSataAdapter->adapterIoBaseAddress));
1314 }
1315
1316 pMvSataAdapter->adapterId = num_adapters++;
1317 /* get the revision ID */
1318 pMvSataAdapter->pciConfigRevisionId = pci_read_config(pAdapter->hpt_dev, PCIR_REVID, 1);
1319 pMvSataAdapter->pciConfigDeviceId = pci_get_device(pAdapter->hpt_dev);
1320
1321 /* init RR18xx */
1322 pMvSataAdapter->intCoalThre[0]= 1;
1323 pMvSataAdapter->intCoalThre[1]= 1;
1324 pMvSataAdapter->intTimeThre[0] = 1;
1325 pMvSataAdapter->intTimeThre[1] = 1;
1326 pMvSataAdapter->pciCommand = 0x0107E371;
1327 pMvSataAdapter->pciSerrMask = 0xd77fe6ul;
1328 pMvSataAdapter->pciInterruptMask = 0xd77fe6ul;
1329 pMvSataAdapter->mvSataEventNotify = hptmv_event_notify;
1330
1331 if (mvSataInitAdapter(pMvSataAdapter) == MV_FALSE)
1332 {
1333 MV_ERROR("RR18xx[%d]: core failed to initialize the adapter\n",
1334 pMvSataAdapter->adapterId);
1335 unregister:
1336 bus_release_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, rid, pAdapter->mem_res);
1337 hptmv_free_edma_queues(pAdapter);
1338 return ENXIO;
1339 }
1340 pAdapter->ver_601 = pMvSataAdapter->pcbVersion;
1341
1342 #ifndef FOR_DEMO
1343 set_fail_leds(pMvSataAdapter, 0);
1344 #endif
1345
1346 /* setup command blocks */
1347 KdPrint(("Allocate command blocks\n"));
1348 _vbus_(pFreeCommands) = 0;
1349 pAdapter->pCommandBlocks =
1350 malloc(sizeof(struct _Command) * MAX_COMMAND_BLOCKS_FOR_EACH_VBUS, M_DEVBUF, M_NOWAIT);
1351 KdPrint(("pCommandBlocks:%p\n",pAdapter->pCommandBlocks));
1352 if (!pAdapter->pCommandBlocks) {
1353 MV_ERROR("insufficient memory\n");
1354 goto unregister;
1355 }
1356
1357 for (i = 0; i < MAX_COMMAND_BLOCKS_FOR_EACH_VBUS; i++) {
1358 FreeCommand(_VBUS_P &(pAdapter->pCommandBlocks[i]));
1359 }
1360
1361 /*Set up the bus_dmamap*/
1362 pAdapter->pbus_dmamap = (PBUS_DMAMAP)malloc (sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM, M_DEVBUF, M_NOWAIT);
1363 if(!pAdapter->pbus_dmamap) {
1364 MV_ERROR("insufficient memory\n");
1365 free(pAdapter->pCommandBlocks, M_DEVBUF);
1366 goto unregister;
1367 }
1368
1369 memset((void *)pAdapter->pbus_dmamap, 0, sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM);
1370 pAdapter->pbus_dmamap_list = 0;
1371 for (i = 0; i < MAX_QUEUE_COMM; i++) {
1372 PBUS_DMAMAP pmap = &(pAdapter->pbus_dmamap[i]);
1373 pmap->pAdapter = pAdapter;
1374 dmamap_put(pmap);
1375
1376 if(bus_dmamap_create(pAdapter->io_dma_parent, 0, &pmap->dma_map)) {
1377 MV_ERROR("Can not allocate dma map\n");
1378 free(pAdapter->pCommandBlocks, M_DEVBUF);
1379 free(pAdapter->pbus_dmamap, M_DEVBUF);
1380 goto unregister;
1381 }
1382 callout_init_mtx(&pmap->timeout, &pAdapter->lock, 0);
1383 }
1384 /* setup PRD Tables */
1385 KdPrint(("Allocate PRD Tables\n"));
1386 pAdapter->pFreePRDLink = 0;
1387
1388 pAdapter->prdTableAddr = (PUCHAR)contigmalloc(
1389 (PRD_ENTRIES_SIZE*PRD_TABLES_FOR_VBUS + 32), M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul);
1390
1391 KdPrint(("prdTableAddr:%p\n",pAdapter->prdTableAddr));
1392 if (!pAdapter->prdTableAddr) {
1393 MV_ERROR("insufficient PRD Tables\n");
1394 goto unregister;
1395 }
1396 pAdapter->prdTableAlignedAddr = (PUCHAR)(((ULONG_PTR)pAdapter->prdTableAddr + 0x1f) & ~(ULONG_PTR)0x1fL);
1397 {
1398 PUCHAR PRDTable = pAdapter->prdTableAlignedAddr;
1399 for (i = 0; i < PRD_TABLES_FOR_VBUS; i++)
1400 {
1401 /* KdPrint(("i=%d,pAdapter->pFreePRDLink=%p\n",i,pAdapter->pFreePRDLink)); */
1402 FreePRDTable(pAdapter, PRDTable);
1403 PRDTable += PRD_ENTRIES_SIZE;
1404 }
1405 }
1406
1407 /* enable the adapter interrupts */
1408
1409 /* configure and start the connected channels*/
1410 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++)
1411 {
1412 pAdapter->mvChannel[channel].online = MV_FALSE;
1413 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel)
1414 == MV_TRUE)
1415 {
1416 KdPrint(("RR18xx[%d]: channel %d is connected\n",
1417 pMvSataAdapter->adapterId, channel));
1418
1419 if (hptmv_init_channel(pAdapter, channel) == 0)
1420 {
1421 if (mvSataConfigureChannel(pMvSataAdapter, channel) == MV_FALSE)
1422 {
1423 MV_ERROR("RR18xx[%d]: Failed to configure channel"
1424 " %d\n",pMvSataAdapter->adapterId, channel);
1425 hptmv_free_channel(pAdapter, channel);
1426 }
1427 else
1428 {
1429 if (start_channel(pAdapter, channel))
1430 {
1431 MV_ERROR("RR18xx[%d]: Failed to start channel,"
1432 " channel=%d\n",pMvSataAdapter->adapterId,
1433 channel);
1434 hptmv_free_channel(pAdapter, channel);
1435 }
1436 pAdapter->mvChannel[channel].online = MV_TRUE;
1437 /* mvSataChannelSetEdmaLoopBackMode(pMvSataAdapter,
1438 channel,
1439 MV_TRUE);*/
1440 }
1441 }
1442 }
1443 KdPrint(("pAdapter->mvChannel[channel].online:%x, channel:%d\n",
1444 pAdapter->mvChannel[channel].online, channel));
1445 }
1446
1447 #ifdef SUPPORT_ARRAY
1448 for (i = MAX_ARRAY_DEVICE - 1; i >= 0; i--) {
1449 pVDev = ArrayTables(i);
1450 mArFreeArrayTable(pVDev);
1451 }
1452 #endif
1453
1454 KdPrint(("Initialize Devices\n"));
1455 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) {
1456 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channel];
1457 if (pMvSataChannel) {
1458 init_vdev_params(pAdapter, channel);
1459 IdeRegisterVDevice(&pAdapter->VDevices[channel].u.disk);
1460 }
1461 }
1462 #ifdef SUPPORT_ARRAY
1463 CheckArrayCritical(_VBUS_P0);
1464 #endif
1465 _vbus_p->nInstances = 1;
1466 fRegisterVdevice(pAdapter);
1467
1468 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) {
1469 pVDev = _vbus_p->pVDevice[channel];
1470 if (pVDev && pVDev->vf_online)
1471 fCheckBootable(pVDev);
1472 }
1473
1474 #if defined(SUPPORT_ARRAY) && defined(_RAID5N_)
1475 init_raid5_memory(_VBUS_P0);
1476 _vbus_(r5).enable_write_back = 1;
1477 printf("RR18xx: RAID5 write-back %s\n", _vbus_(r5).enable_write_back? "enabled" : "disabled");
1478 #endif
1479
1480 mvSataUnmaskAdapterInterrupt(pMvSataAdapter);
1481 return 0;
1482 }
1483
1484 int
MvSataResetChannel(MV_SATA_ADAPTER * pMvSataAdapter,MV_U8 channel)1485 MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel)
1486 {
1487 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pMvSataAdapter->IALData;
1488
1489 mvSataDisableChannelDma(pMvSataAdapter, channel);
1490 /* Flush pending commands */
1491 mvSataFlushDmaQueue (pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK);
1492
1493 /* Software reset channel */
1494 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channel) == MV_FALSE)
1495 {
1496 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n",
1497 pMvSataAdapter->adapterId, channel);
1498 hptmv_free_channel(pAdapter, channel);
1499 return -1;
1500 }
1501
1502 /* Hardware reset channel */
1503 if (mvSataChannelHardReset(pMvSataAdapter, channel)== MV_FALSE)
1504 {
1505 MV_ERROR("RR18xx [%d,%d] Failed to Hard reser the SATA channel\n",
1506 pMvSataAdapter->adapterId, channel);
1507 hptmv_free_channel(pAdapter, channel);
1508 return -1;
1509 }
1510
1511 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) == MV_FALSE)
1512 {
1513 MV_ERROR("RR18xx [%d,%d] Failed to Connect Device\n",
1514 pMvSataAdapter->adapterId, channel);
1515 hptmv_free_channel(pAdapter, channel);
1516 return -1;
1517 }else
1518 {
1519 MV_ERROR("channel %d: perform recalibrate command", channel);
1520 if (!mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel,
1521 MV_NON_UDMA_PROTOCOL_NON_DATA,
1522 MV_FALSE,
1523 NULL, /* pBuffer*/
1524 0, /* count */
1525 0, /*features*/
1526 /* sectorCount */
1527 0,
1528 0, /* lbaLow */
1529 0, /* lbaMid */
1530 /* lbaHigh */
1531 0,
1532 0, /* device */
1533 /* command */
1534 0x10))
1535 MV_ERROR("channel %d: recalibrate failed", channel);
1536
1537 /* Set transfer mode */
1538 if((mvStorageDevATASetFeatures(pMvSataAdapter, channel,
1539 MV_ATA_SET_FEATURES_TRANSFER,
1540 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == MV_FALSE) ||
1541 (mvStorageDevATASetFeatures(pMvSataAdapter, channel,
1542 MV_ATA_SET_FEATURES_TRANSFER,
1543 pAdapter->mvChannel[channel].maxPioModeSupported, 0, 0, 0) == MV_FALSE) ||
1544 (mvStorageDevATASetFeatures(pMvSataAdapter, channel,
1545 MV_ATA_SET_FEATURES_TRANSFER,
1546 pAdapter->mvChannel[channel].maxUltraDmaModeSupported, 0, 0, 0) == MV_FALSE) )
1547 {
1548 MV_ERROR("channel %d: Set Features failed", channel);
1549 hptmv_free_channel(pAdapter, channel);
1550 return -1;
1551 }
1552 /* Enable EDMA */
1553 if (mvSataEnableChannelDma(pMvSataAdapter, channel) == MV_FALSE)
1554 {
1555 MV_ERROR("Failed to enable DMA, channel=%d", channel);
1556 hptmv_free_channel(pAdapter, channel);
1557 return -1;
1558 }
1559 }
1560 return 0;
1561 }
1562
1563 static int
fResetActiveCommands(PVBus _vbus_p)1564 fResetActiveCommands(PVBus _vbus_p)
1565 {
1566 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter;
1567 MV_U8 channel;
1568 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) {
1569 if (pMvSataAdapter->sataChannel[channel] && pMvSataAdapter->sataChannel[channel]->outstandingCommands)
1570 MvSataResetChannel(pMvSataAdapter,channel);
1571 }
1572 return 0;
1573 }
1574
fCompleteAllCommandsSynchronously(PVBus _vbus_p)1575 void fCompleteAllCommandsSynchronously(PVBus _vbus_p)
1576 {
1577 UINT cont;
1578 ULONG ticks = 0;
1579 MV_U8 channel;
1580 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter;
1581 MV_SATA_CHANNEL *pMvSataChannel;
1582
1583 do {
1584 check_cmds:
1585 cont = 0;
1586 CheckPendingCall(_VBUS_P0);
1587 #ifdef _RAID5N_
1588 dataxfer_poll();
1589 xor_poll();
1590 #endif
1591 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) {
1592 pMvSataChannel = pMvSataAdapter->sataChannel[channel];
1593 if (pMvSataChannel && pMvSataChannel->outstandingCommands)
1594 {
1595 while (pMvSataChannel->outstandingCommands) {
1596 if (!mvSataInterruptServiceRoutine(pMvSataAdapter)) {
1597 StallExec(1000);
1598 if (ticks++ > 3000) {
1599 MvSataResetChannel(pMvSataAdapter,channel);
1600 goto check_cmds;
1601 }
1602 }
1603 else
1604 ticks = 0;
1605 }
1606 cont = 1;
1607 }
1608 }
1609 } while (cont);
1610 }
1611
1612 void
fResetVBus(_VBUS_ARG0)1613 fResetVBus(_VBUS_ARG0)
1614 {
1615 KdPrint(("fMvResetBus(%p)", _vbus_p));
1616
1617 /* some commands may already finished. */
1618 CheckPendingCall(_VBUS_P0);
1619
1620 fResetActiveCommands(_vbus_p);
1621 /*
1622 * the other pending commands may still be finished successfully.
1623 */
1624 fCompleteAllCommandsSynchronously(_vbus_p);
1625
1626 /* Now there should be no pending commands. No more action needed. */
1627 CheckIdleCall(_VBUS_P0);
1628
1629 KdPrint(("fMvResetBus() done"));
1630 }
1631
1632 /*No rescan function*/
1633 void
fRescanAllDevice(_VBUS_ARG0)1634 fRescanAllDevice(_VBUS_ARG0)
1635 {
1636 }
1637
1638 static MV_BOOLEAN
CommandCompletionCB(MV_SATA_ADAPTER * pMvSataAdapter,MV_U8 channelNum,MV_COMPLETION_TYPE comp_type,MV_VOID_PTR commandId,MV_U16 responseFlags,MV_U32 timeStamp,MV_STORAGE_DEVICE_REGISTERS * registerStruct)1639 CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter,
1640 MV_U8 channelNum,
1641 MV_COMPLETION_TYPE comp_type,
1642 MV_VOID_PTR commandId,
1643 MV_U16 responseFlags,
1644 MV_U32 timeStamp,
1645 MV_STORAGE_DEVICE_REGISTERS *registerStruct)
1646 {
1647 PCommand pCmd = (PCommand) commandId;
1648 _VBUS_INST(pCmd->pVDevice->pVBus)
1649
1650 if (pCmd->uScratch.sata_param.prdAddr)
1651 FreePRDTable(pMvSataAdapter->IALData,pCmd->uScratch.sata_param.prdAddr);
1652
1653 switch (comp_type)
1654 {
1655 case MV_COMPLETION_TYPE_NORMAL:
1656 pCmd->Result = RETURN_SUCCESS;
1657 break;
1658 case MV_COMPLETION_TYPE_ABORT:
1659 pCmd->Result = RETURN_BUS_RESET;
1660 break;
1661 case MV_COMPLETION_TYPE_ERROR:
1662 MV_ERROR("IAL: COMPLETION ERROR, adapter %d, channel %d, flags=%x\n",
1663 pMvSataAdapter->adapterId, channelNum, responseFlags);
1664
1665 if (responseFlags & 4) {
1666 MV_ERROR("ATA regs: error %x, sector count %x, LBA low %x, LBA mid %x,"
1667 " LBA high %x, device %x, status %x\n",
1668 registerStruct->errorRegister,
1669 registerStruct->sectorCountRegister,
1670 registerStruct->lbaLowRegister,
1671 registerStruct->lbaMidRegister,
1672 registerStruct->lbaHighRegister,
1673 registerStruct->deviceRegister,
1674 registerStruct->statusRegister);
1675 }
1676 /*We can't do handleEdmaError directly here, because CommandCompletionCB is called by
1677 * mv's ISR, if we retry the command, than the internel data structure may be destroyed*/
1678 pCmd->uScratch.sata_param.responseFlags = responseFlags;
1679 pCmd->uScratch.sata_param.bIdeStatus = registerStruct->statusRegister;
1680 pCmd->uScratch.sata_param.errorRegister = registerStruct->errorRegister;
1681 pCmd->pVDevice->u.disk.QueueLength--;
1682 CallAfterReturn(_VBUS_P (DPC_PROC)handleEdmaError,pCmd);
1683 return TRUE;
1684
1685 default:
1686 MV_ERROR(" Unknown completion type (%d)\n", comp_type);
1687 return MV_FALSE;
1688 }
1689
1690 if (pCmd->uCmd.Ide.Command == IDE_COMMAND_VERIFY && pCmd->uScratch.sata_param.cmd_priv > 1) {
1691 pCmd->uScratch.sata_param.cmd_priv --;
1692 return TRUE;
1693 }
1694 pCmd->pVDevice->u.disk.QueueLength--;
1695 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1696 return TRUE;
1697 }
1698
1699 void
fDeviceSendCommand(_VBUS_ARG PCommand pCmd)1700 fDeviceSendCommand(_VBUS_ARG PCommand pCmd)
1701 {
1702 MV_SATA_EDMA_PRD_ENTRY *pPRDTable = 0;
1703 MV_SATA_ADAPTER *pMvSataAdapter;
1704 MV_SATA_CHANNEL *pMvSataChannel;
1705 PVDevice pVDevice = pCmd->pVDevice;
1706 PDevice pDevice = &pVDevice->u.disk;
1707 LBA_T Lba = pCmd->uCmd.Ide.Lba;
1708 USHORT nSector = pCmd->uCmd.Ide.nSectors;
1709
1710 MV_QUEUE_COMMAND_RESULT result;
1711 MV_QUEUE_COMMAND_INFO commandInfo;
1712 MV_UDMA_COMMAND_PARAMS *pUdmaParams = &commandInfo.commandParams.udmaCommand;
1713 MV_NONE_UDMA_COMMAND_PARAMS *pNoUdmaParams = &commandInfo.commandParams.NoneUdmaCommand;
1714
1715 MV_BOOLEAN is48bit;
1716 MV_U8 channel;
1717 int i = 0;
1718
1719 DECLARE_BUFFER(FPSCAT_GATH, tmpSg);
1720
1721 if (!pDevice->df_on_line) {
1722 MV_ERROR("Device is offline");
1723 pCmd->Result = RETURN_BAD_DEVICE;
1724 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1725 return;
1726 }
1727
1728 pDevice->HeadPosition = pCmd->uCmd.Ide.Lba + pCmd->uCmd.Ide.nSectors;
1729 pMvSataChannel = pDevice->mv;
1730 pMvSataAdapter = pMvSataChannel->mvSataAdapter;
1731 channel = pMvSataChannel->channelNumber;
1732
1733 /* old RAID0 has hidden lba. Remember to clear dDeHiddenLba when delete array! */
1734 Lba += pDevice->dDeHiddenLba;
1735 /* check LBA */
1736 if (Lba+nSector-1 > pDevice->dDeRealCapacity) {
1737 pCmd->Result = RETURN_INVALID_REQUEST;
1738 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1739 return;
1740 }
1741
1742 /*
1743 * always use 48bit LBA if drive supports it.
1744 * Some Seagate drives report error if you use a 28-bit command
1745 * to access sector 0xfffffff.
1746 */
1747 is48bit = pMvSataChannel->lba48Address;
1748
1749 switch (pCmd->uCmd.Ide.Command)
1750 {
1751 case IDE_COMMAND_READ:
1752 case IDE_COMMAND_WRITE:
1753 if (pDevice->bDeModeSetting<8) goto pio;
1754
1755 commandInfo.type = MV_QUEUED_COMMAND_TYPE_UDMA;
1756 pUdmaParams->isEXT = is48bit;
1757 pUdmaParams->numOfSectors = nSector;
1758 pUdmaParams->lowLBAAddress = Lba;
1759 pUdmaParams->highLBAAddress = 0;
1760 pUdmaParams->prdHighAddr = 0;
1761 pUdmaParams->callBack = CommandCompletionCB;
1762 pUdmaParams->commandId = (MV_VOID_PTR )pCmd;
1763 if(pCmd->uCmd.Ide.Command == IDE_COMMAND_READ)
1764 pUdmaParams->readWrite = MV_UDMA_TYPE_READ;
1765 else
1766 pUdmaParams->readWrite = MV_UDMA_TYPE_WRITE;
1767
1768 if (pCmd->pSgTable && pCmd->cf_physical_sg) {
1769 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable;
1770 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0);
1771 }
1772 else {
1773 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 0)) {
1774 pio:
1775 mvSataDisableChannelDma(pMvSataAdapter, channel);
1776 mvSataFlushDmaQueue(pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK);
1777
1778 if (pCmd->pSgTable && pCmd->cf_physical_sg==0) {
1779 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable;
1780 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0);
1781 }
1782 else {
1783 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 1)) {
1784 pCmd->Result = RETURN_NEED_LOGICAL_SG;
1785 goto finish_cmd;
1786 }
1787 }
1788
1789 do {
1790 ULONG size = tmpSg->wSgSize? tmpSg->wSgSize : 0x10000;
1791 ULONG_PTR addr = tmpSg->dSgAddress;
1792 if (size & 0x1ff) {
1793 pCmd->Result = RETURN_INVALID_REQUEST;
1794 goto finish_cmd;
1795 }
1796 if (mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel,
1797 (pCmd->cf_data_out)?MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT:MV_NON_UDMA_PROTOCOL_PIO_DATA_IN,
1798 is48bit,
1799 (MV_U16_PTR)addr,
1800 size >> 1, /* count */
1801 0, /* features N/A */
1802 (MV_U16)(size>>9), /*sector count*/
1803 (MV_U16)( (is48bit? (MV_U16)((Lba >> 16) & 0xFF00) : 0 ) | (UCHAR)(Lba & 0xFF) ), /*lbalow*/
1804 (MV_U16)((Lba >> 8) & 0xFF), /* lbaMid */
1805 (MV_U16)((Lba >> 16) & 0xFF),/* lbaHigh */
1806 (MV_U8)(0x40 | (is48bit ? 0 : (UCHAR)(Lba >> 24) & 0xFF )),/* device */
1807 (MV_U8)(is48bit ? (pCmd->cf_data_in?IDE_COMMAND_READ_EXT:IDE_COMMAND_WRITE_EXT):pCmd->uCmd.Ide.Command)
1808 )==MV_FALSE)
1809 {
1810 pCmd->Result = RETURN_IDE_ERROR;
1811 goto finish_cmd;
1812 }
1813 Lba += size>>9;
1814 if(Lba & 0xF0000000) is48bit = MV_TRUE;
1815 }
1816 while ((tmpSg++->wSgFlag & SG_FLAG_EOT)==0);
1817 pCmd->Result = RETURN_SUCCESS;
1818 finish_cmd:
1819 mvSataEnableChannelDma(pMvSataAdapter,channel);
1820 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1821 return;
1822 }
1823 }
1824
1825 pPRDTable = (MV_SATA_EDMA_PRD_ENTRY *) AllocatePRDTable(pMvSataAdapter->IALData);
1826 KdPrint(("pPRDTable:%p\n",pPRDTable));
1827 if (!pPRDTable) {
1828 pCmd->Result = RETURN_DEVICE_BUSY;
1829 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1830 HPT_ASSERT(0);
1831 return;
1832 }
1833
1834 do{
1835 pPRDTable[i].highBaseAddr = (sizeof(tmpSg->dSgAddress)>4 ? (MV_U32)(tmpSg->dSgAddress>>32) : 0);
1836 pPRDTable[i].flags = (MV_U16)tmpSg->wSgFlag;
1837 pPRDTable[i].byteCount = (MV_U16)tmpSg->wSgSize;
1838 pPRDTable[i].lowBaseAddr = (MV_U32)tmpSg->dSgAddress;
1839 pPRDTable[i].reserved = 0;
1840 i++;
1841 }while((tmpSg++->wSgFlag & SG_FLAG_EOT)==0);
1842
1843 pUdmaParams->prdLowAddr = (ULONG)fOsPhysicalAddress(pPRDTable);
1844 if ((pUdmaParams->numOfSectors == 256) && (pMvSataChannel->lba48Address == MV_FALSE)) {
1845 pUdmaParams->numOfSectors = 0;
1846 }
1847
1848 pCmd->uScratch.sata_param.prdAddr = (PVOID)pPRDTable;
1849
1850 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo);
1851
1852 if (result != MV_QUEUE_COMMAND_RESULT_OK)
1853 {
1854 queue_failed:
1855 switch (result)
1856 {
1857 case MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS:
1858 MV_ERROR("IAL Error: Edma Queue command failed. Bad LBA "
1859 "LBA[31:0](0x%08x)\n", pUdmaParams->lowLBAAddress);
1860 pCmd->Result = RETURN_IDE_ERROR;
1861 break;
1862 case MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED:
1863 MV_ERROR("IAL Error: Edma Queue command failed. EDMA"
1864 " disabled adapter %d channel %d\n",
1865 pMvSataAdapter->adapterId, channel);
1866 mvSataEnableChannelDma(pMvSataAdapter,channel);
1867 pCmd->Result = RETURN_IDE_ERROR;
1868 break;
1869 case MV_QUEUE_COMMAND_RESULT_FULL:
1870 MV_ERROR("IAL Error: Edma Queue command failed. Queue is"
1871 " Full adapter %d channel %d\n",
1872 pMvSataAdapter->adapterId, channel);
1873 pCmd->Result = RETURN_DEVICE_BUSY;
1874 break;
1875 case MV_QUEUE_COMMAND_RESULT_BAD_PARAMS:
1876 MV_ERROR("IAL Error: Edma Queue command failed. (Bad "
1877 "Params), pMvSataAdapter: %p, pSataChannel: %p.\n",
1878 pMvSataAdapter, pMvSataAdapter->sataChannel[channel]);
1879 pCmd->Result = RETURN_IDE_ERROR;
1880 break;
1881 default:
1882 MV_ERROR("IAL Error: Bad result value (%d) from queue"
1883 " command\n", result);
1884 pCmd->Result = RETURN_IDE_ERROR;
1885 }
1886 if(pPRDTable)
1887 FreePRDTable(pMvSataAdapter->IALData,pPRDTable);
1888 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1889 }
1890 pDevice->QueueLength++;
1891 return;
1892
1893 case IDE_COMMAND_VERIFY:
1894 commandInfo.type = MV_QUEUED_COMMAND_TYPE_NONE_UDMA;
1895 pNoUdmaParams->bufPtr = NULL;
1896 pNoUdmaParams->callBack = CommandCompletionCB;
1897 pNoUdmaParams->commandId = (MV_VOID_PTR)pCmd;
1898 pNoUdmaParams->count = 0;
1899 pNoUdmaParams->features = 0;
1900 pNoUdmaParams->protocolType = MV_NON_UDMA_PROTOCOL_NON_DATA;
1901
1902 pCmd->uScratch.sata_param.cmd_priv = 1;
1903 if (pMvSataChannel->lba48Address == MV_TRUE){
1904 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS_EXT;
1905 pNoUdmaParams->isEXT = MV_TRUE;
1906 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16);
1907 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8);
1908 pNoUdmaParams->lbaLow =
1909 (MV_U16)(((Lba & 0xff000000) >> 16)| (Lba & 0xff));
1910 pNoUdmaParams->sectorCount = nSector;
1911 pNoUdmaParams->device = 0x40;
1912 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo);
1913 if (result != MV_QUEUE_COMMAND_RESULT_OK){
1914 goto queue_failed;
1915 }
1916 return;
1917 }
1918 else{
1919 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS;
1920 pNoUdmaParams->isEXT = MV_FALSE;
1921 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16);
1922 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8);
1923 pNoUdmaParams->lbaLow = (MV_U16)(Lba & 0xff);
1924 pNoUdmaParams->sectorCount = 0xff & nSector;
1925 pNoUdmaParams->device = (MV_U8)(0x40 |
1926 ((Lba & 0xf000000) >> 24));
1927 pNoUdmaParams->callBack = CommandCompletionCB;
1928 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo);
1929 /*FIXME: how about the commands already queued? but marvel also forgets to consider this*/
1930 if (result != MV_QUEUE_COMMAND_RESULT_OK){
1931 goto queue_failed;
1932 }
1933 }
1934 break;
1935 default:
1936 pCmd->Result = RETURN_INVALID_REQUEST;
1937 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1938 break;
1939 }
1940 }
1941
1942 /**********************************************************
1943 *
1944 * Probe the hostadapter.
1945 *
1946 **********************************************************/
1947 static int
hpt_probe(device_t dev)1948 hpt_probe(device_t dev)
1949 {
1950 if ((pci_get_vendor(dev) == MV_SATA_VENDOR_ID) &&
1951 (pci_get_device(dev) == MV_SATA_DEVICE_ID_5081
1952 #ifdef FOR_DEMO
1953 || pci_get_device(dev) == MV_SATA_DEVICE_ID_5080
1954 #endif
1955 ))
1956 {
1957 KdPrintI((CONTROLLER_NAME " found\n"));
1958 device_set_desc(dev, CONTROLLER_NAME);
1959 return (BUS_PROBE_DEFAULT);
1960 }
1961 else
1962 return(ENXIO);
1963 }
1964
1965 /***********************************************************
1966 *
1967 * Auto configuration: attach and init a host adapter.
1968 *
1969 ***********************************************************/
1970 static int
hpt_attach(device_t dev)1971 hpt_attach(device_t dev)
1972 {
1973 IAL_ADAPTER_T * pAdapter = device_get_softc(dev);
1974 int rid;
1975 union ccb *ccb;
1976 struct cam_devq *devq;
1977 struct cam_sim *hpt_vsim;
1978
1979 device_printf(dev, "%s Version %s \n", DRIVER_NAME, DRIVER_VERSION);
1980
1981 pAdapter->hpt_dev = dev;
1982
1983 rid = init_adapter(pAdapter);
1984 if (rid)
1985 return rid;
1986
1987 rid = 0;
1988 if ((pAdapter->hpt_irq = bus_alloc_resource_any(pAdapter->hpt_dev, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE)) == NULL)
1989 {
1990 hpt_printk(("can't allocate interrupt\n"));
1991 return(ENXIO);
1992 }
1993
1994 if (bus_setup_intr(pAdapter->hpt_dev, pAdapter->hpt_irq,
1995 INTR_TYPE_CAM | INTR_MPSAFE,
1996 NULL, hpt_intr, pAdapter, &pAdapter->hpt_intr))
1997 {
1998 hpt_printk(("can't set up interrupt\n"));
1999 free(pAdapter, M_DEVBUF);
2000 return(ENXIO);
2001 }
2002
2003
2004 ccb = xpt_alloc_ccb();
2005 ccb->ccb_h.pinfo.priority = 1;
2006 ccb->ccb_h.pinfo.index = CAM_UNQUEUED_INDEX;
2007
2008 /*
2009 * Create the device queue for our SIM(s).
2010 */
2011 if((devq = cam_simq_alloc(8/*MAX_QUEUE_COMM*/)) == NULL)
2012 {
2013 KdPrint(("ENXIO\n"));
2014 return ENOMEM;
2015 }
2016
2017 /*
2018 * Construct our SIM entry
2019 */
2020 hpt_vsim = cam_sim_alloc(hpt_action, hpt_poll, __str(PROC_DIR_NAME),
2021 pAdapter, device_get_unit(pAdapter->hpt_dev),
2022 &pAdapter->lock, 1, 8, devq);
2023 if (hpt_vsim == NULL) {
2024 cam_simq_free(devq);
2025 return ENOMEM;
2026 }
2027
2028 mtx_lock(&pAdapter->lock);
2029 if (xpt_bus_register(hpt_vsim, dev, 0) != CAM_SUCCESS)
2030 {
2031 cam_sim_free(hpt_vsim, /*free devq*/ TRUE);
2032 mtx_unlock(&pAdapter->lock);
2033 hpt_vsim = NULL;
2034 return ENXIO;
2035 }
2036
2037 if(xpt_create_path(&pAdapter->path, /*periph */ NULL,
2038 cam_sim_path(hpt_vsim), CAM_TARGET_WILDCARD,
2039 CAM_LUN_WILDCARD) != CAM_REQ_CMP)
2040 {
2041 xpt_bus_deregister(cam_sim_path(hpt_vsim));
2042 cam_sim_free(hpt_vsim, /*free_devq*/TRUE);
2043 mtx_unlock(&pAdapter->lock);
2044 hpt_vsim = NULL;
2045 return ENXIO;
2046 }
2047 mtx_unlock(&pAdapter->lock);
2048
2049 xpt_setup_ccb(&(ccb->ccb_h), pAdapter->path, /*priority*/5);
2050 ccb->ccb_h.func_code = XPT_SASYNC_CB;
2051 ccb->csa.event_enable = AC_LOST_DEVICE;
2052 ccb->csa.callback = hpt_async;
2053 ccb->csa.callback_arg = hpt_vsim;
2054 xpt_action((union ccb *)ccb);
2055 xpt_free_ccb(ccb);
2056
2057 if (device_get_unit(dev) == 0) {
2058 /* Start the work thread. XXX */
2059 launch_worker_thread();
2060 }
2061
2062 return 0;
2063 }
2064
2065 static int
hpt_detach(device_t dev)2066 hpt_detach(device_t dev)
2067 {
2068 return (EBUSY);
2069 }
2070
2071
2072 /***************************************************************
2073 * The poll function is used to simulate the interrupt when
2074 * the interrupt subsystem is not functioning.
2075 *
2076 ***************************************************************/
2077 static void
hpt_poll(struct cam_sim * sim)2078 hpt_poll(struct cam_sim *sim)
2079 {
2080
2081 hpt_intr_locked((void *)cam_sim_softc(sim));
2082 }
2083
2084 /****************************************************************
2085 * Name: hpt_intr
2086 * Description: Interrupt handler.
2087 ****************************************************************/
2088 static void
hpt_intr(void * arg)2089 hpt_intr(void *arg)
2090 {
2091 IAL_ADAPTER_T *pAdapter;
2092
2093 pAdapter = arg;
2094 mtx_lock(&pAdapter->lock);
2095 hpt_intr_locked(pAdapter);
2096 mtx_unlock(&pAdapter->lock);
2097 }
2098
2099 static void
hpt_intr_locked(IAL_ADAPTER_T * pAdapter)2100 hpt_intr_locked(IAL_ADAPTER_T *pAdapter)
2101 {
2102
2103 mtx_assert(&pAdapter->lock, MA_OWNED);
2104 /* KdPrintI(("----- Entering Isr() -----\n")); */
2105 if (mvSataInterruptServiceRoutine(&pAdapter->mvSataAdapter) == MV_TRUE)
2106 {
2107 _VBUS_INST(&pAdapter->VBus)
2108 CheckPendingCall(_VBUS_P0);
2109 }
2110
2111 /* KdPrintI(("----- Leaving Isr() -----\n")); */
2112 }
2113
2114 /**********************************************************
2115 * Asynchronous Events
2116 *********************************************************/
2117 #if (!defined(UNREFERENCED_PARAMETER))
2118 #define UNREFERENCED_PARAMETER(x) (void)(x)
2119 #endif
2120
2121 static void
hpt_async(void * callback_arg,u_int32_t code,struct cam_path * path,void * arg)2122 hpt_async(void * callback_arg, u_int32_t code, struct cam_path * path,
2123 void * arg)
2124 {
2125 /* debug XXXX */
2126 panic("Here");
2127 UNREFERENCED_PARAMETER(callback_arg);
2128 UNREFERENCED_PARAMETER(code);
2129 UNREFERENCED_PARAMETER(path);
2130 UNREFERENCED_PARAMETER(arg);
2131
2132 }
2133
2134 static void
FlushAdapter(IAL_ADAPTER_T * pAdapter)2135 FlushAdapter(IAL_ADAPTER_T *pAdapter)
2136 {
2137 int i;
2138
2139 hpt_printk(("flush all devices\n"));
2140
2141 /* flush all devices */
2142 for (i = 0; i < MAX_VDEVICE_PER_VBUS; i++) {
2143 PVDevice pVDev = pAdapter->VBus.pVDevice[i];
2144 if(pVDev) fFlushVDev(pVDev);
2145 }
2146 }
2147
2148 static int
hpt_shutdown(device_t dev)2149 hpt_shutdown(device_t dev)
2150 {
2151 IAL_ADAPTER_T *pAdapter;
2152
2153 pAdapter = device_get_softc(dev);
2154
2155 mtx_lock(&pAdapter->lock);
2156 FlushAdapter(pAdapter);
2157 mtx_unlock(&pAdapter->lock);
2158 /* give the flush some time to happen,
2159 *otherwise "shutdown -p now" will make file system corrupted */
2160 DELAY(1000 * 1000 * 5);
2161 return 0;
2162 }
2163
2164 void
Check_Idle_Call(IAL_ADAPTER_T * pAdapter)2165 Check_Idle_Call(IAL_ADAPTER_T *pAdapter)
2166 {
2167 _VBUS_INST(&pAdapter->VBus)
2168
2169 if (mWaitingForIdle(_VBUS_P0)) {
2170 CheckIdleCall(_VBUS_P0);
2171 #ifdef SUPPORT_ARRAY
2172 {
2173 int i;
2174 PVDevice pArray;
2175 for (i = 0; i < MAX_ARRAY_PER_VBUS; i++) {
2176 if ((pArray=ArrayTables(i))->u.array.dArStamp==0)
2177 continue;
2178 else if (pArray->u.array.rf_auto_rebuild) {
2179 KdPrint(("auto rebuild.\n"));
2180 pArray->u.array.rf_auto_rebuild = 0;
2181 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapter, pArray, DUPLICATE);
2182 }
2183 }
2184 }
2185 #endif
2186 }
2187 /* launch the awaiting commands blocked by mWaitingForIdle */
2188 while(pAdapter->pending_Q!= NULL)
2189 {
2190 _VBUS_INST(&pAdapter->VBus)
2191 union ccb *ccb = (union ccb *)pAdapter->pending_Q->ccb_h.ccb_ccb_ptr;
2192 hpt_free_ccb(&pAdapter->pending_Q, ccb);
2193 CallAfterReturn(_VBUS_P (DPC_PROC)OsSendCommand, ccb);
2194 }
2195 }
2196
2197 static void
ccb_done(union ccb * ccb)2198 ccb_done(union ccb *ccb)
2199 {
2200 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter;
2201 IAL_ADAPTER_T * pAdapter = pmap->pAdapter;
2202 KdPrintI(("ccb_done: ccb %p status %x\n", ccb, ccb->ccb_h.status));
2203
2204 dmamap_put(pmap);
2205 xpt_done(ccb);
2206
2207 pAdapter->outstandingCommands--;
2208
2209 if (pAdapter->outstandingCommands == 0)
2210 {
2211 if(DPC_Request_Nums == 0)
2212 Check_Idle_Call(pAdapter);
2213 wakeup(pAdapter);
2214 }
2215 }
2216
2217 /****************************************************************
2218 * Name: hpt_action
2219 * Description: Process a queued command from the CAM layer.
2220 * Parameters: sim - Pointer to SIM object
2221 * ccb - Pointer to SCSI command structure.
2222 ****************************************************************/
2223
2224 void
hpt_action(struct cam_sim * sim,union ccb * ccb)2225 hpt_action(struct cam_sim *sim, union ccb *ccb)
2226 {
2227 IAL_ADAPTER_T * pAdapter = (IAL_ADAPTER_T *) cam_sim_softc(sim);
2228 PBUS_DMAMAP pmap;
2229 _VBUS_INST(&pAdapter->VBus)
2230
2231 mtx_assert(&pAdapter->lock, MA_OWNED);
2232 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("hpt_action\n"));
2233 KdPrint(("hpt_action(%lx,%lx{%x})\n", (u_long)sim, (u_long)ccb, ccb->ccb_h.func_code));
2234
2235 switch (ccb->ccb_h.func_code)
2236 {
2237 case XPT_SCSI_IO: /* Execute the requested I/O operation */
2238 {
2239 /* ccb->ccb_h.path_id is not our bus id - don't check it */
2240
2241 if (ccb->ccb_h.target_lun) {
2242 ccb->ccb_h.status = CAM_LUN_INVALID;
2243 xpt_done(ccb);
2244 return;
2245 }
2246 if (ccb->ccb_h.target_id >= MAX_VDEVICE_PER_VBUS ||
2247 pAdapter->VBus.pVDevice[ccb->ccb_h.target_id]==0) {
2248 ccb->ccb_h.status = CAM_TID_INVALID;
2249 xpt_done(ccb);
2250 return;
2251 }
2252
2253 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0)
2254 Check_Idle_Call(pAdapter);
2255
2256 pmap = dmamap_get(pAdapter);
2257 HPT_ASSERT(pmap);
2258 ccb->ccb_adapter = pmap;
2259 memset((void *)pmap->psg, 0, sizeof(pmap->psg));
2260
2261 if (mWaitingForIdle(_VBUS_P0))
2262 hpt_queue_ccb(&pAdapter->pending_Q, ccb);
2263 else
2264 OsSendCommand(_VBUS_P ccb);
2265
2266 /* KdPrint(("leave scsiio\n")); */
2267 break;
2268 }
2269
2270 case XPT_RESET_BUS:
2271 KdPrint(("reset bus\n"));
2272 fResetVBus(_VBUS_P0);
2273 xpt_done(ccb);
2274 break;
2275
2276 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
2277 case XPT_ABORT: /* Abort the specified CCB */
2278 case XPT_TERM_IO: /* Terminate the I/O process */
2279 /* XXX Implement */
2280 ccb->ccb_h.status = CAM_REQ_INVALID;
2281 xpt_done(ccb);
2282 break;
2283
2284 case XPT_GET_TRAN_SETTINGS:
2285 case XPT_SET_TRAN_SETTINGS:
2286 /* XXX Implement */
2287 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
2288 xpt_done(ccb);
2289 break;
2290
2291 case XPT_CALC_GEOMETRY:
2292 cam_calc_geometry(&ccb->ccg, 1);
2293 xpt_done(ccb);
2294 break;
2295
2296 case XPT_PATH_INQ: /* Path routing inquiry */
2297 {
2298 struct ccb_pathinq *cpi = &ccb->cpi;
2299
2300 cpi->version_num = 1; /* XXX??? */
2301 cpi->hba_inquiry = PI_SDTR_ABLE;
2302 cpi->target_sprt = 0;
2303 /* Not necessary to reset bus */
2304 cpi->hba_misc = PIM_NOBUSRESET;
2305 cpi->hba_eng_cnt = 0;
2306
2307 cpi->max_target = MAX_VDEVICE_PER_VBUS;
2308 cpi->max_lun = 0;
2309 cpi->initiator_id = MAX_VDEVICE_PER_VBUS;
2310
2311 cpi->bus_id = cam_sim_bus(sim);
2312 cpi->base_transfer_speed = 3300;
2313 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2314 strlcpy(cpi->hba_vid, "HPT ", HBA_IDLEN);
2315 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2316 cpi->unit_number = cam_sim_unit(sim);
2317 cpi->transport = XPORT_SPI;
2318 cpi->transport_version = 2;
2319 cpi->protocol = PROTO_SCSI;
2320 cpi->protocol_version = SCSI_REV_2;
2321 cpi->ccb_h.status = CAM_REQ_CMP;
2322 xpt_done(ccb);
2323 break;
2324 }
2325
2326 default:
2327 KdPrint(("invalid cmd\n"));
2328 ccb->ccb_h.status = CAM_REQ_INVALID;
2329 xpt_done(ccb);
2330 break;
2331 }
2332 /* KdPrint(("leave hpt_action..............\n")); */
2333 }
2334
2335 /* shall be called at lock_driver() */
2336 static void
hpt_queue_ccb(union ccb ** ccb_Q,union ccb * ccb)2337 hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb)
2338 {
2339 if(*ccb_Q == NULL)
2340 ccb->ccb_h.ccb_ccb_ptr = ccb;
2341 else {
2342 ccb->ccb_h.ccb_ccb_ptr = (*ccb_Q)->ccb_h.ccb_ccb_ptr;
2343 (*ccb_Q)->ccb_h.ccb_ccb_ptr = (char *)ccb;
2344 }
2345
2346 *ccb_Q = ccb;
2347 }
2348
2349 /* shall be called at lock_driver() */
2350 static void
hpt_free_ccb(union ccb ** ccb_Q,union ccb * ccb)2351 hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb)
2352 {
2353 union ccb *TempCCB;
2354
2355 TempCCB = *ccb_Q;
2356
2357 if(ccb->ccb_h.ccb_ccb_ptr == ccb) /*it means SCpnt is the last one in CURRCMDs*/
2358 *ccb_Q = NULL;
2359 else {
2360 while(TempCCB->ccb_h.ccb_ccb_ptr != (char *)ccb)
2361 TempCCB = (union ccb *)TempCCB->ccb_h.ccb_ccb_ptr;
2362
2363 TempCCB->ccb_h.ccb_ccb_ptr = ccb->ccb_h.ccb_ccb_ptr;
2364
2365 if(*ccb_Q == ccb)
2366 *ccb_Q = TempCCB;
2367 }
2368 }
2369
2370 #ifdef SUPPORT_ARRAY
2371 /***************************************************************************
2372 * Function: hpt_worker_thread
2373 * Description: Do background rebuilding. Execute in kernel thread context.
2374 * Returns: None
2375 ***************************************************************************/
hpt_worker_thread(void)2376 static void hpt_worker_thread(void)
2377 {
2378
2379 for (;;) {
2380 mtx_lock(&DpcQueue_Lock);
2381 while (DpcQueue_First!=DpcQueue_Last) {
2382 ST_HPT_DPC p;
2383 p = DpcQueue[DpcQueue_First];
2384 DpcQueue_First++;
2385 DpcQueue_First %= MAX_DPC;
2386 DPC_Request_Nums++;
2387 mtx_unlock(&DpcQueue_Lock);
2388 p.dpc(p.pAdapter, p.arg, p.flags);
2389
2390 mtx_lock(&p.pAdapter->lock);
2391 mtx_lock(&DpcQueue_Lock);
2392 DPC_Request_Nums--;
2393 /* since we may have prevented Check_Idle_Call, do it here */
2394 if (DPC_Request_Nums==0) {
2395 if (p.pAdapter->outstandingCommands == 0) {
2396 _VBUS_INST(&p.pAdapter->VBus);
2397 Check_Idle_Call(p.pAdapter);
2398 CheckPendingCall(_VBUS_P0);
2399 }
2400 }
2401 mtx_unlock(&p.pAdapter->lock);
2402 mtx_unlock(&DpcQueue_Lock);
2403
2404 /*Schedule out*/
2405 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) {
2406 /* abort rebuilding process. */
2407 IAL_ADAPTER_T *pAdapter;
2408 PVDevice pArray;
2409 PVBus _vbus_p;
2410 int i;
2411
2412 sx_slock(&hptmv_list_lock);
2413 pAdapter = gIal_Adapter;
2414
2415 while(pAdapter != NULL){
2416 mtx_lock(&pAdapter->lock);
2417 _vbus_p = &pAdapter->VBus;
2418
2419 for (i = 0; i < MAX_ARRAY_PER_VBUS; i++)
2420 {
2421 if ((pArray=ArrayTables(i))->u.array.dArStamp==0)
2422 continue;
2423 else if (pArray->u.array.rf_rebuilding ||
2424 pArray->u.array.rf_verifying ||
2425 pArray->u.array.rf_initializing)
2426 {
2427 pArray->u.array.rf_abort_rebuild = 1;
2428 }
2429 }
2430 mtx_unlock(&pAdapter->lock);
2431 pAdapter = pAdapter->next;
2432 }
2433 sx_sunlock(&hptmv_list_lock);
2434 }
2435 mtx_lock(&DpcQueue_Lock);
2436 }
2437 mtx_unlock(&DpcQueue_Lock);
2438
2439 /*Remove this debug option*/
2440 /*
2441 #ifdef DEBUG
2442 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP))
2443 pause("hptrdy", 2*hz);
2444 #endif
2445 */
2446 kproc_suspend_check(curproc);
2447 pause("-", 2*hz); /* wait for something to do */
2448 }
2449 }
2450
2451 static struct proc *hptdaemonproc;
2452 static struct kproc_desc hpt_kp = {
2453 "hpt_wt",
2454 hpt_worker_thread,
2455 &hptdaemonproc
2456 };
2457
2458 /*Start this thread in the hpt_attach, to prevent kernel from loading it without our controller.*/
2459 static void
launch_worker_thread(void)2460 launch_worker_thread(void)
2461 {
2462 IAL_ADAPTER_T *pAdapTemp;
2463
2464 kproc_start(&hpt_kp);
2465
2466 sx_slock(&hptmv_list_lock);
2467 for (pAdapTemp = gIal_Adapter; pAdapTemp; pAdapTemp = pAdapTemp->next) {
2468
2469 _VBUS_INST(&pAdapTemp->VBus)
2470 int i;
2471 PVDevice pVDev;
2472
2473 for (i = 0; i < MAX_ARRAY_PER_VBUS; i++)
2474 if ((pVDev=ArrayTables(i))->u.array.dArStamp==0)
2475 continue;
2476 else{
2477 if (pVDev->u.array.rf_need_rebuild && !pVDev->u.array.rf_rebuilding)
2478 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapTemp, pVDev,
2479 (UCHAR)((pVDev->u.array.CriticalMembers || pVDev->VDeviceType == VD_RAID_1)? DUPLICATE : REBUILD_PARITY));
2480 }
2481 }
2482 sx_sunlock(&hptmv_list_lock);
2483
2484 /*
2485 * hpt_worker_thread needs to be suspended after shutdown sync, when fs sync finished.
2486 */
2487 EVENTHANDLER_REGISTER(shutdown_post_sync, kproc_shutdown, hptdaemonproc,
2488 SHUTDOWN_PRI_LAST);
2489 }
2490 /*
2491 *SYSINIT(hptwt, SI_SUB_KTHREAD_IDLE, SI_ORDER_FIRST, launch_worker_thread, NULL);
2492 */
2493
2494 #endif
2495
2496 /********************************************************************************/
2497
fOsBuildSgl(_VBUS_ARG PCommand pCmd,FPSCAT_GATH pSg,int logical)2498 int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, int logical)
2499 {
2500 union ccb *ccb = (union ccb *)pCmd->pOrgCommand;
2501
2502 if (logical) {
2503 pSg->dSgAddress = (ULONG_PTR)(UCHAR *)ccb->csio.data_ptr;
2504 pSg->wSgSize = ccb->csio.dxfer_len;
2505 pSg->wSgFlag = SG_FLAG_EOT;
2506 return TRUE;
2507 }
2508 /* since we have provided physical sg, nobody will ask us to build physical sg */
2509 HPT_ASSERT(0);
2510 return FALSE;
2511 }
2512
2513 /*******************************************************************************/
2514 ULONG HPTLIBAPI
GetStamp(void)2515 GetStamp(void)
2516 {
2517 /*
2518 * the system variable, ticks, can't be used since it hasn't yet been active
2519 * when our driver starts (ticks==0, it's a invalid stamp value)
2520 */
2521 ULONG stamp;
2522 do { stamp = random(); } while (stamp==0);
2523 return stamp;
2524 }
2525
2526
2527 static void
SetInquiryData(PINQUIRYDATA inquiryData,PVDevice pVDev)2528 SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev)
2529 {
2530 int i;
2531 IDENTIFY_DATA2 *pIdentify = (IDENTIFY_DATA2*)pVDev->u.disk.mv->identifyDevice;
2532
2533 inquiryData->DeviceType = T_DIRECT; /*DIRECT_ACCESS_DEVICE*/
2534 inquiryData->AdditionalLength = (UCHAR)(sizeof(INQUIRYDATA) - 5);
2535 #ifndef SERIAL_CMDS
2536 inquiryData->CommandQueue = 1;
2537 #endif
2538
2539 switch(pVDev->VDeviceType) {
2540 case VD_SINGLE_DISK:
2541 case VD_ATAPI:
2542 case VD_REMOVABLE:
2543 /* Set the removable bit, if applicable. */
2544 if ((pVDev->u.disk.df_removable_drive) || (pIdentify->GeneralConfiguration & 0x80))
2545 inquiryData->RemovableMedia = 1;
2546
2547 /* Fill in vendor identification fields. */
2548 for (i = 0; i < 20; i += 2) {
2549 inquiryData->VendorId[i] = ((PUCHAR)pIdentify->ModelNumber)[i + 1];
2550 inquiryData->VendorId[i+1] = ((PUCHAR)pIdentify->ModelNumber)[i];
2551
2552 }
2553
2554 /* Initialize unused portion of product id. */
2555 for (i = 0; i < 4; i++) inquiryData->ProductId[12+i] = ' ';
2556
2557 /* firmware revision */
2558 for (i = 0; i < 4; i += 2)
2559 {
2560 inquiryData->ProductRevisionLevel[i] = ((PUCHAR)pIdentify->FirmwareRevision)[i+1];
2561 inquiryData->ProductRevisionLevel[i+1] = ((PUCHAR)pIdentify->FirmwareRevision)[i];
2562 }
2563 break;
2564 default:
2565 memcpy(&inquiryData->VendorId, "RR18xx ", 8);
2566 #ifdef SUPPORT_ARRAY
2567 switch(pVDev->VDeviceType){
2568 case VD_RAID_0:
2569 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) ||
2570 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1])))
2571 memcpy(&inquiryData->ProductId, "RAID 1/0 Array ", 16);
2572 else
2573 memcpy(&inquiryData->ProductId, "RAID 0 Array ", 16);
2574 break;
2575 case VD_RAID_1:
2576 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) ||
2577 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1])))
2578 memcpy(&inquiryData->ProductId, "RAID 0/1 Array ", 16);
2579 else
2580 memcpy(&inquiryData->ProductId, "RAID 1 Array ", 16);
2581 break;
2582 case VD_RAID_5:
2583 memcpy(&inquiryData->ProductId, "RAID 5 Array ", 16);
2584 break;
2585 case VD_JBOD:
2586 memcpy(&inquiryData->ProductId, "JBOD Array ", 16);
2587 break;
2588 }
2589 #endif
2590 memcpy(&inquiryData->ProductRevisionLevel, "3.00", 4);
2591 break;
2592 }
2593 }
2594
2595 static void
hpt_timeout(void * arg)2596 hpt_timeout(void *arg)
2597 {
2598 PBUS_DMAMAP pmap = (PBUS_DMAMAP)((union ccb *)arg)->ccb_adapter;
2599 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2600 _VBUS_INST(&pAdapter->VBus)
2601
2602 mtx_assert(&pAdapter->lock, MA_OWNED);
2603 fResetVBus(_VBUS_P0);
2604 }
2605
2606 static void
hpt_io_dmamap_callback(void * arg,bus_dma_segment_t * segs,int nsegs,int error)2607 hpt_io_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
2608 {
2609 PCommand pCmd = (PCommand)arg;
2610 union ccb *ccb = pCmd->pOrgCommand;
2611 struct ccb_hdr *ccb_h = &ccb->ccb_h;
2612 PBUS_DMAMAP pmap = (PBUS_DMAMAP) ccb->ccb_adapter;
2613 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2614 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id];
2615 FPSCAT_GATH psg = pCmd->pSgTable;
2616 int idx;
2617 _VBUS_INST(pVDev->pVBus)
2618
2619 HPT_ASSERT(pCmd->cf_physical_sg);
2620
2621 if (error)
2622 panic("busdma error");
2623
2624 HPT_ASSERT(nsegs<= MAX_SG_DESCRIPTORS);
2625
2626 if (nsegs != 0) {
2627 for (idx = 0; idx < nsegs; idx++, psg++) {
2628 psg->dSgAddress = (ULONG_PTR)(UCHAR *)segs[idx].ds_addr;
2629 psg->wSgSize = segs[idx].ds_len;
2630 psg->wSgFlag = (idx == nsegs-1)? SG_FLAG_EOT: 0;
2631 /* KdPrint(("psg[%d]:add=%p,size=%x,flag=%x\n", idx, psg->dSgAddress,psg->wSgSize,psg->wSgFlag)); */
2632 }
2633 /* psg[-1].wSgFlag = SG_FLAG_EOT; */
2634
2635 if (pCmd->cf_data_in) {
2636 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map,
2637 BUS_DMASYNC_PREREAD);
2638 }
2639 else if (pCmd->cf_data_out) {
2640 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map,
2641 BUS_DMASYNC_PREWRITE);
2642 }
2643 }
2644
2645 callout_reset(&pmap->timeout, 20 * hz, hpt_timeout, ccb);
2646 pVDev->pfnSendCommand(_VBUS_P pCmd);
2647 CheckPendingCall(_VBUS_P0);
2648 }
2649
2650
2651
2652 static void HPTLIBAPI
OsSendCommand(_VBUS_ARG union ccb * ccb)2653 OsSendCommand(_VBUS_ARG union ccb *ccb)
2654 {
2655 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter;
2656 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2657 struct ccb_hdr *ccb_h = &ccb->ccb_h;
2658 struct ccb_scsiio *csio = &ccb->csio;
2659 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id];
2660
2661 KdPrintI(("OsSendCommand: ccb %p cdb %x-%x-%x\n",
2662 ccb,
2663 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[0],
2664 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[4],
2665 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[8]
2666 ));
2667
2668 pAdapter->outstandingCommands++;
2669
2670 if (pVDev == NULL || pVDev->vf_online == 0) {
2671 ccb->ccb_h.status = CAM_REQ_INVALID;
2672 ccb_done(ccb);
2673 goto Command_Complished;
2674 }
2675
2676 switch(ccb->csio.cdb_io.cdb_bytes[0])
2677 {
2678 case TEST_UNIT_READY:
2679 case START_STOP_UNIT:
2680 case SYNCHRONIZE_CACHE:
2681 /* FALLTHROUGH */
2682 ccb->ccb_h.status = CAM_REQ_CMP;
2683 break;
2684
2685 case INQUIRY:
2686 ZeroMemory(ccb->csio.data_ptr, ccb->csio.dxfer_len);
2687 SetInquiryData((PINQUIRYDATA)ccb->csio.data_ptr, pVDev);
2688 ccb_h->status = CAM_REQ_CMP;
2689 break;
2690
2691 case READ_CAPACITY:
2692 {
2693 UCHAR *rbuf=csio->data_ptr;
2694 unsigned int cap;
2695
2696 if (pVDev->VDeviceCapacity > 0xfffffffful) {
2697 cap = 0xfffffffful;
2698 } else {
2699 cap = pVDev->VDeviceCapacity - 1;
2700 }
2701
2702 rbuf[0] = (UCHAR)(cap>>24);
2703 rbuf[1] = (UCHAR)(cap>>16);
2704 rbuf[2] = (UCHAR)(cap>>8);
2705 rbuf[3] = (UCHAR)cap;
2706 /* Claim 512 byte blocks (big-endian). */
2707 rbuf[4] = 0;
2708 rbuf[5] = 0;
2709 rbuf[6] = 2;
2710 rbuf[7] = 0;
2711
2712 ccb_h->status = CAM_REQ_CMP;
2713 break;
2714 }
2715
2716 case 0x9e: /*SERVICE_ACTION_IN*/
2717 {
2718 UCHAR *rbuf = csio->data_ptr;
2719 LBA_T cap = pVDev->VDeviceCapacity - 1;
2720
2721 rbuf[0] = (UCHAR)(cap>>56);
2722 rbuf[1] = (UCHAR)(cap>>48);
2723 rbuf[2] = (UCHAR)(cap>>40);
2724 rbuf[3] = (UCHAR)(cap>>32);
2725 rbuf[4] = (UCHAR)(cap>>24);
2726 rbuf[5] = (UCHAR)(cap>>16);
2727 rbuf[6] = (UCHAR)(cap>>8);
2728 rbuf[7] = (UCHAR)cap;
2729 rbuf[8] = 0;
2730 rbuf[9] = 0;
2731 rbuf[10] = 2;
2732 rbuf[11] = 0;
2733
2734 ccb_h->status = CAM_REQ_CMP;
2735 break;
2736 }
2737
2738 case READ_6:
2739 case WRITE_6:
2740 case READ_10:
2741 case WRITE_10:
2742 case 0x88: /* READ_16 */
2743 case 0x8a: /* WRITE_16 */
2744 case 0x13:
2745 case 0x2f:
2746 {
2747 UCHAR Cdb[16];
2748 UCHAR CdbLength;
2749 _VBUS_INST(pVDev->pVBus)
2750 PCommand pCmd = AllocateCommand(_VBUS_P0);
2751 int error;
2752 HPT_ASSERT(pCmd);
2753
2754 CdbLength = csio->cdb_len;
2755 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0)
2756 {
2757 if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0)
2758 {
2759 bcopy(csio->cdb_io.cdb_ptr, Cdb, CdbLength);
2760 }
2761 else
2762 {
2763 KdPrintE(("ERROR!!!\n"));
2764 ccb->ccb_h.status = CAM_REQ_INVALID;
2765 break;
2766 }
2767 }
2768 else
2769 {
2770 bcopy(csio->cdb_io.cdb_bytes, Cdb, CdbLength);
2771 }
2772
2773 pCmd->pOrgCommand = ccb;
2774 pCmd->pVDevice = pVDev;
2775 pCmd->pfnCompletion = fOsCommandDone;
2776 pCmd->pfnBuildSgl = fOsBuildSgl;
2777 pCmd->pSgTable = pmap->psg;
2778
2779 switch (Cdb[0])
2780 {
2781 case READ_6:
2782 case WRITE_6:
2783 case 0x13:
2784 pCmd->uCmd.Ide.Lba = ((ULONG)Cdb[1] << 16) | ((ULONG)Cdb[2] << 8) | (ULONG)Cdb[3];
2785 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[4];
2786 break;
2787
2788 case 0x88: /* READ_16 */
2789 case 0x8a: /* WRITE_16 */
2790 pCmd->uCmd.Ide.Lba =
2791 (HPT_U64)Cdb[2] << 56 |
2792 (HPT_U64)Cdb[3] << 48 |
2793 (HPT_U64)Cdb[4] << 40 |
2794 (HPT_U64)Cdb[5] << 32 |
2795 (HPT_U64)Cdb[6] << 24 |
2796 (HPT_U64)Cdb[7] << 16 |
2797 (HPT_U64)Cdb[8] << 8 |
2798 (HPT_U64)Cdb[9];
2799 pCmd->uCmd.Ide.nSectors = (USHORT)Cdb[12] << 8 | (USHORT)Cdb[13];
2800 break;
2801
2802 default:
2803 pCmd->uCmd.Ide.Lba = (ULONG)Cdb[5] | ((ULONG)Cdb[4] << 8) | ((ULONG)Cdb[3] << 16) | ((ULONG)Cdb[2] << 24);
2804 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[8] | ((USHORT)Cdb[7]<<8);
2805 break;
2806 }
2807
2808 switch (Cdb[0])
2809 {
2810 case READ_6:
2811 case READ_10:
2812 case 0x88: /* READ_16 */
2813 pCmd->uCmd.Ide.Command = IDE_COMMAND_READ;
2814 pCmd->cf_data_in = 1;
2815 break;
2816
2817 case WRITE_6:
2818 case WRITE_10:
2819 case 0x8a: /* WRITE_16 */
2820 pCmd->uCmd.Ide.Command = IDE_COMMAND_WRITE;
2821 pCmd->cf_data_out = 1;
2822 break;
2823 case 0x13:
2824 case 0x2f:
2825 pCmd->uCmd.Ide.Command = IDE_COMMAND_VERIFY;
2826 break;
2827 }
2828 /*///////////////////////// */
2829 pCmd->cf_physical_sg = 1;
2830 error = bus_dmamap_load_ccb(pAdapter->io_dma_parent,
2831 pmap->dma_map,
2832 ccb,
2833 hpt_io_dmamap_callback,
2834 pCmd, BUS_DMA_WAITOK
2835 );
2836 KdPrint(("bus_dmamap_load return %d\n", error));
2837 if (error && error!=EINPROGRESS) {
2838 hpt_printk(("bus_dmamap_load error %d\n", error));
2839 FreeCommand(_VBUS_P pCmd);
2840 ccb->ccb_h.status = CAM_REQ_CMP_ERR;
2841 dmamap_put(pmap);
2842 pAdapter->outstandingCommands--;
2843 if (pAdapter->outstandingCommands == 0)
2844 wakeup(pAdapter);
2845 xpt_done(ccb);
2846 }
2847 goto Command_Complished;
2848 }
2849
2850 default:
2851 ccb->ccb_h.status = CAM_REQ_INVALID;
2852 break;
2853 }
2854 ccb_done(ccb);
2855 Command_Complished:
2856 CheckPendingCall(_VBUS_P0);
2857 return;
2858 }
2859
2860 static void HPTLIBAPI
fOsCommandDone(_VBUS_ARG PCommand pCmd)2861 fOsCommandDone(_VBUS_ARG PCommand pCmd)
2862 {
2863 union ccb *ccb = pCmd->pOrgCommand;
2864 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter;
2865 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2866
2867 KdPrint(("fOsCommandDone(pcmd=%p, result=%d)\n", pCmd, pCmd->Result));
2868
2869 callout_stop(&pmap->timeout);
2870
2871 switch(pCmd->Result) {
2872 case RETURN_SUCCESS:
2873 ccb->ccb_h.status = CAM_REQ_CMP;
2874 break;
2875 case RETURN_BAD_DEVICE:
2876 ccb->ccb_h.status = CAM_DEV_NOT_THERE;
2877 break;
2878 case RETURN_DEVICE_BUSY:
2879 ccb->ccb_h.status = CAM_BUSY;
2880 break;
2881 case RETURN_INVALID_REQUEST:
2882 ccb->ccb_h.status = CAM_REQ_INVALID;
2883 break;
2884 case RETURN_SELECTION_TIMEOUT:
2885 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2886 break;
2887 case RETURN_RETRY:
2888 ccb->ccb_h.status = CAM_BUSY;
2889 break;
2890 default:
2891 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
2892 break;
2893 }
2894
2895 if (pCmd->cf_data_in) {
2896 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTREAD);
2897 }
2898 else if (pCmd->cf_data_out) {
2899 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTWRITE);
2900 }
2901
2902 bus_dmamap_unload(pAdapter->io_dma_parent, pmap->dma_map);
2903
2904 FreeCommand(_VBUS_P pCmd);
2905 ccb_done(ccb);
2906 }
2907
2908 int
hpt_queue_dpc(HPT_DPC dpc,IAL_ADAPTER_T * pAdapter,void * arg,UCHAR flags)2909 hpt_queue_dpc(HPT_DPC dpc, IAL_ADAPTER_T * pAdapter, void *arg, UCHAR flags)
2910 {
2911 int p;
2912
2913 mtx_lock(&DpcQueue_Lock);
2914 p = (DpcQueue_Last + 1) % MAX_DPC;
2915 if (p==DpcQueue_First) {
2916 KdPrint(("DPC Queue full!\n"));
2917 mtx_unlock(&DpcQueue_Lock);
2918 return -1;
2919 }
2920
2921 DpcQueue[DpcQueue_Last].dpc = dpc;
2922 DpcQueue[DpcQueue_Last].pAdapter = pAdapter;
2923 DpcQueue[DpcQueue_Last].arg = arg;
2924 DpcQueue[DpcQueue_Last].flags = flags;
2925 DpcQueue_Last = p;
2926 mtx_unlock(&DpcQueue_Lock);
2927
2928 return 0;
2929 }
2930
2931 #ifdef _RAID5N_
2932 /*
2933 * Allocate memory above 16M, otherwise we may eat all low memory for ISA devices.
2934 * How about the memory for 5081 request/response array and PRD table?
2935 */
2936 void
os_alloc_page(_VBUS_ARG0)2937 *os_alloc_page(_VBUS_ARG0)
2938 {
2939 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul);
2940 }
2941
2942 void
os_alloc_dma_page(_VBUS_ARG0)2943 *os_alloc_dma_page(_VBUS_ARG0)
2944 {
2945 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul);
2946 }
2947
2948 void
os_free_page(_VBUS_ARG void * p)2949 os_free_page(_VBUS_ARG void *p)
2950 {
2951 free(p, M_DEVBUF);
2952 }
2953
2954 void
os_free_dma_page(_VBUS_ARG void * p)2955 os_free_dma_page(_VBUS_ARG void *p)
2956 {
2957 free(p, M_DEVBUF);
2958 }
2959
2960 void
DoXor1(ULONG * p0,ULONG * p1,ULONG * p2,UINT nBytes)2961 DoXor1(ULONG *p0, ULONG *p1, ULONG *p2, UINT nBytes)
2962 {
2963 UINT i;
2964 for (i = 0; i < nBytes / 4; i++) *p0++ = *p1++ ^ *p2++;
2965 }
2966
2967 void
DoXor2(ULONG * p0,ULONG * p2,UINT nBytes)2968 DoXor2(ULONG *p0, ULONG *p2, UINT nBytes)
2969 {
2970 UINT i;
2971 for (i = 0; i < nBytes / 4; i++) *p0++ ^= *p2++;
2972 }
2973 #endif
2974