1 //===-- riscv.h - Generic JITLink riscv edge kinds, utilities -*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // Generic utilities for graphs representing riscv objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_EXECUTIONENGINE_JITLINK_RISCV_H 14 #define LLVM_EXECUTIONENGINE_JITLINK_RISCV_H 15 16 #include "llvm/ExecutionEngine/JITLink/JITLink.h" 17 #include "llvm/Support/Compiler.h" 18 19 namespace llvm { 20 namespace jitlink { 21 namespace riscv { 22 23 /// Represents riscv fixups. Ordered in the same way as the relocations in 24 /// include/llvm/BinaryFormat/ELFRelocs/RISCV.def. 25 enum EdgeKind_riscv : Edge::Kind { 26 27 // TODO: Capture and replace to generic fixups 28 /// A plain 32-bit pointer value relocation 29 /// 30 /// Fixup expression: 31 /// Fixup <= Target + Addend : uint32 32 /// 33 R_RISCV_32 = Edge::FirstRelocation, 34 35 /// A plain 64-bit pointer value relocation 36 /// 37 /// Fixup expression: 38 /// Fixup <- Target + Addend : uint32 39 /// 40 R_RISCV_64, 41 42 /// PC-relative branch pointer value relocation 43 /// 44 /// Fixup expression: 45 /// Fixup <- (Target - Fixup + Addend) 46 /// 47 R_RISCV_BRANCH, 48 49 /// High 20 bits of PC-relative jump pointer value relocation 50 /// 51 /// Fixup expression: 52 /// Fixup <- Target - Fixup + Addend 53 /// 54 R_RISCV_JAL, 55 56 /// PC relative call 57 /// 58 /// Fixup expression: 59 /// Fixup <- (Target - Fixup + Addend) 60 R_RISCV_CALL, 61 62 /// PC relative call by PLT 63 /// 64 /// Fixup expression: 65 /// Fixup <- (Target - Fixup + Addend) 66 R_RISCV_CALL_PLT, 67 68 /// PC relative GOT offset 69 /// 70 /// Fixup expression: 71 /// Fixup <- (GOT - Fixup + Addend) >> 12 72 R_RISCV_GOT_HI20, 73 74 /// High 20 bits of PC relative relocation 75 /// 76 /// Fixup expression: 77 /// Fixup <- (Target - Fixup + Addend + 0x800) >> 12 78 R_RISCV_PCREL_HI20, 79 80 /// Low 12 bits of PC relative relocation, used by I type instruction format 81 /// 82 /// Fixup expression: 83 /// Fixup <- (Target - Fixup + Addend) & 0xFFF 84 R_RISCV_PCREL_LO12_I, 85 86 /// Low 12 bits of PC relative relocation, used by S type instruction format 87 /// 88 /// Fixup expression: 89 /// Fixup <- (Target - Fixup + Addend) & 0xFFF 90 R_RISCV_PCREL_LO12_S, 91 92 /// High 20 bits of 32-bit pointer value relocation 93 /// 94 /// Fixup expression 95 /// Fixup <- (Target + Addend + 0x800) >> 12 96 R_RISCV_HI20, 97 98 /// Low 12 bits of 32-bit pointer value relocation 99 /// 100 /// Fixup expression 101 /// Fixup <- (Target + Addend) & 0xFFF 102 R_RISCV_LO12_I, 103 104 /// Low 12 bits of 32-bit pointer value relocation, used by S type instruction 105 /// format 106 /// 107 /// Fixup expression 108 /// Fixup <- (Target + Addend) & 0xFFF 109 R_RISCV_LO12_S, 110 111 /// 8 bits label addition 112 /// 113 /// Fixup expression 114 /// Fixup <- (Target + *{1}Fixup + Addend) 115 R_RISCV_ADD8, 116 117 /// 16 bits label addition 118 /// 119 /// Fixup expression 120 /// Fixup <- (Target + *{2}Fixup + Addend) 121 R_RISCV_ADD16, 122 123 /// 32 bits label addition 124 /// 125 /// Fixup expression: 126 /// Fixup <- (Target + *{4}Fixup + Addend) 127 R_RISCV_ADD32, 128 129 /// 64 bits label addition 130 /// 131 /// Fixup expression: 132 /// Fixup <- (Target + *{8}Fixup + Addend) 133 R_RISCV_ADD64, 134 135 /// 8 bits label subtraction 136 /// 137 /// Fixup expression 138 /// Fixup <- (Target - *{1}Fixup - Addend) 139 R_RISCV_SUB8, 140 141 /// 16 bits label subtraction 142 /// 143 /// Fixup expression 144 /// Fixup <- (Target - *{2}Fixup - Addend) 145 R_RISCV_SUB16, 146 147 /// 32 bits label subtraction 148 /// 149 /// Fixup expression 150 /// Fixup <- (Target - *{4}Fixup - Addend) 151 R_RISCV_SUB32, 152 153 /// 64 bits label subtraction 154 /// 155 /// Fixup expression 156 /// Fixup <- (Target - *{8}Fixup - Addend) 157 R_RISCV_SUB64, 158 159 /// 8-bit PC-relative branch offset 160 /// 161 /// Fixup expression: 162 /// Fixup <- (Target - Fixup + Addend) 163 R_RISCV_RVC_BRANCH, 164 165 /// 11-bit PC-relative jump offset 166 /// 167 /// Fixup expression: 168 /// Fixup <- (Target - Fixup + Addend) 169 R_RISCV_RVC_JUMP, 170 171 /// 6 bits label subtraction 172 /// 173 /// Fixup expression 174 /// Fixup <- (Target - *{1}Fixup - Addend) 175 R_RISCV_SUB6, 176 177 /// Local label assignment 178 /// 179 /// Fixup expression: 180 /// Fixup <- (Target + Addend) 181 R_RISCV_SET6, 182 183 /// Local label assignment 184 /// 185 /// Fixup expression: 186 /// Fixup <- (Target + Addend) 187 R_RISCV_SET8, 188 189 /// Local label assignment 190 /// 191 /// Fixup expression: 192 /// Fixup <- (Target + Addend) 193 R_RISCV_SET16, 194 195 /// Local label assignment 196 /// 197 /// Fixup expression: 198 /// Fixup <- (Target + Addend) 199 R_RISCV_SET32, 200 201 /// 32 bits PC relative relocation 202 /// 203 /// Fixup expression: 204 /// Fixup <- (Target - Fixup + Addend) 205 R_RISCV_32_PCREL, 206 207 /// An auipc/jalr pair eligible for linker relaxation. 208 /// 209 /// Linker relaxation will replace this with R_RISCV_RVC_JUMP or R_RISCV_JAL 210 /// if it succeeds, or with R_RISCV_CALL_PLT if it fails. 211 CallRelaxable, 212 213 /// Alignment requirement used by linker relaxation. 214 /// 215 /// Linker relaxation will use this to ensure all code sequences are properly 216 /// aligned and then remove these edges from the graph. 217 AlignRelaxable, 218 219 /// 32-bit negative delta. 220 /// 221 /// Fixup expression: 222 /// Fixup <- Fixup - Target + Addend 223 NegDelta32, 224 }; 225 226 /// Returns a string name for the given riscv edge. For debugging purposes 227 /// only 228 LLVM_ABI const char *getEdgeKindName(Edge::Kind K); 229 } // namespace riscv 230 } // namespace jitlink 231 } // namespace llvm 232 233 #endif 234