1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright(c) 2020 Intel Corporation. */
3
4 #ifndef __CXL_CORE_H__
5 #define __CXL_CORE_H__
6
7 extern const struct device_type cxl_nvdimm_bridge_type;
8 extern const struct device_type cxl_nvdimm_type;
9 extern const struct device_type cxl_pmu_type;
10
11 extern struct attribute_group cxl_base_attribute_group;
12
13 #ifdef CONFIG_CXL_REGION
14 extern struct device_attribute dev_attr_create_pmem_region;
15 extern struct device_attribute dev_attr_create_ram_region;
16 extern struct device_attribute dev_attr_delete_region;
17 extern struct device_attribute dev_attr_region;
18 extern const struct device_type cxl_pmem_region_type;
19 extern const struct device_type cxl_dax_region_type;
20 extern const struct device_type cxl_region_type;
21 void cxl_decoder_kill_region(struct cxl_endpoint_decoder *cxled);
22 #define CXL_REGION_ATTR(x) (&dev_attr_##x.attr)
23 #define CXL_REGION_TYPE(x) (&cxl_region_type)
24 #define SET_CXL_REGION_ATTR(x) (&dev_attr_##x.attr),
25 #define CXL_PMEM_REGION_TYPE(x) (&cxl_pmem_region_type)
26 #define CXL_DAX_REGION_TYPE(x) (&cxl_dax_region_type)
27 int cxl_region_init(void);
28 void cxl_region_exit(void);
29 int cxl_get_poison_by_endpoint(struct cxl_port *port);
30 struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa);
31 u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd,
32 u64 dpa);
33
34 #else
cxl_dpa_to_hpa(struct cxl_region * cxlr,const struct cxl_memdev * cxlmd,u64 dpa)35 static inline u64 cxl_dpa_to_hpa(struct cxl_region *cxlr,
36 const struct cxl_memdev *cxlmd, u64 dpa)
37 {
38 return ULLONG_MAX;
39 }
40 static inline
cxl_dpa_to_region(const struct cxl_memdev * cxlmd,u64 dpa)41 struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa)
42 {
43 return NULL;
44 }
cxl_get_poison_by_endpoint(struct cxl_port * port)45 static inline int cxl_get_poison_by_endpoint(struct cxl_port *port)
46 {
47 return 0;
48 }
cxl_decoder_kill_region(struct cxl_endpoint_decoder * cxled)49 static inline void cxl_decoder_kill_region(struct cxl_endpoint_decoder *cxled)
50 {
51 }
cxl_region_init(void)52 static inline int cxl_region_init(void)
53 {
54 return 0;
55 }
cxl_region_exit(void)56 static inline void cxl_region_exit(void)
57 {
58 }
59 #define CXL_REGION_ATTR(x) NULL
60 #define CXL_REGION_TYPE(x) NULL
61 #define SET_CXL_REGION_ATTR(x)
62 #define CXL_PMEM_REGION_TYPE(x) NULL
63 #define CXL_DAX_REGION_TYPE(x) NULL
64 #endif
65
66 struct cxl_send_command;
67 struct cxl_mem_query_commands;
68 int cxl_query_cmd(struct cxl_memdev *cxlmd,
69 struct cxl_mem_query_commands __user *q);
70 int cxl_send_cmd(struct cxl_memdev *cxlmd, struct cxl_send_command __user *s);
71 void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
72 resource_size_t length);
73
74 struct dentry *cxl_debugfs_create_dir(const char *dir);
75 int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled,
76 enum cxl_decoder_mode mode);
77 int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size);
78 int cxl_dpa_free(struct cxl_endpoint_decoder *cxled);
79 resource_size_t cxl_dpa_size(struct cxl_endpoint_decoder *cxled);
80 resource_size_t cxl_dpa_resource_start(struct cxl_endpoint_decoder *cxled);
81
82 enum cxl_rcrb {
83 CXL_RCRB_DOWNSTREAM,
84 CXL_RCRB_UPSTREAM,
85 };
86 struct cxl_rcrb_info;
87 resource_size_t __rcrb_to_component(struct device *dev,
88 struct cxl_rcrb_info *ri,
89 enum cxl_rcrb which);
90 u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb);
91
92 extern struct rw_semaphore cxl_dpa_rwsem;
93 extern struct rw_semaphore cxl_region_rwsem;
94
95 int cxl_memdev_init(void);
96 void cxl_memdev_exit(void);
97 void cxl_mbox_init(void);
98
99 enum cxl_poison_trace_type {
100 CXL_POISON_TRACE_LIST,
101 CXL_POISON_TRACE_INJECT,
102 CXL_POISON_TRACE_CLEAR,
103 };
104
105 long cxl_pci_get_latency(struct pci_dev *pdev);
106
107 int cxl_update_hmat_access_coordinates(int nid, struct cxl_region *cxlr,
108 enum access_coordinate_class access);
109 bool cxl_need_node_perf_attrs_update(int nid);
110
111 #endif /* __CXL_CORE_H__ */
112