1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011, 2016, 2025 Chelsio Communications. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef __T4_HW_H 30 #define __T4_HW_H 31 32 #include "osdep.h" 33 34 enum { 35 NCHAN = 4, /* # of HW channels */ 36 T6_NCHAN = 2, 37 MAX_NCHAN = 4, 38 MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */ 39 EEPROMSIZE = 17408, /* Serial EEPROM physical size */ 40 EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */ 41 EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */ 42 RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */ 43 T6_RSS_NENTRIES = 4096, 44 T7_RSS_NENTRIES = 16384, 45 TCB_SIZE = 128, /* TCB size */ 46 NMTUS = 16, /* size of MTU table */ 47 NCCTRL_WIN = 32, /* # of congestion control windows */ 48 NTX_SCHED = 8, /* # of HW Tx scheduling queues */ 49 PM_NSTATS = 5, /* # of PM stats */ 50 T6_PM_NSTATS = 7, /* # of PM stats in T6 */ 51 MAX_PM_NSTATS = 7, 52 T7_PM_RX_CACHE_NSTATS = 27, /* # of PM Rx Cache stats in T7 */ 53 MBOX_LEN = 64, /* mailbox size in bytes */ 54 NTRACE = 4, /* # of tracing filters */ 55 TRACE_LEN = 112, /* length of trace data and mask */ 56 FILTER_OPT_LEN = 36, /* filter tuple width of optional components */ 57 T5_FILTER_OPT_LEN = 40, 58 T7_FILTER_OPT_LEN = 63, 59 NWOL_PAT = 8, /* # of WoL patterns */ 60 WOL_PAT_LEN = 128, /* length of WoL patterns */ 61 UDBS_SEG_SIZE = 128, /* Segment size of BAR2 doorbells */ 62 UDBS_SEG_SHIFT = 7, /* log2(UDBS_SEG_SIZE) */ 63 UDBS_DB_OFFSET = 8, /* offset of the 4B doorbell in a segment */ 64 UDBS_WR_OFFSET = 64, /* offset of the work request in a segment */ 65 MAX_UP_CORES = 8, /* Max # of uP cores that can be enabled */ 66 }; 67 68 enum { 69 CIM_NUM_IBQ = 6, /* # of CIM IBQs */ 70 CIM_NUM_IBQ_T7 = 16, /* # of CIM IBQs for T7 */ 71 CIM_NUM_OBQ = 6, /* # of CIM OBQs */ 72 CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */ 73 CIM_NUM_OBQ_T7 = 16, /* # of CIM OBQs for T7 adapter */ 74 CIMLA_SIZE = 256 * 8, /* 256 rows * ceil(235/32) 32-bit words */ 75 CIMLA_SIZE_T6 = 256 * 10, /* 256 rows * ceil(311/32) 32-bit words */ 76 CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */ 77 CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */ 78 CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */ 79 CIM_OBQ_SIZE = 128, /* # of 128-bit words in a CIM OBQ */ 80 TPLA_SIZE = 128, /* # of 64-bit words in TP LA */ 81 ULPRX_LA_SIZE = 512, /* # of 256-bit words in ULP_RX LA */ 82 }; 83 84 enum { 85 SF_PAGE_SIZE = 256, /* serial flash page size */ 86 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */ 87 }; 88 89 /* SGE context types */ 90 enum ctxt_type { CTXT_EGRESS, CTXT_INGRESS, CTXT_FLM, CTXT_CNM }; 91 92 enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */ 93 94 enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */ 95 96 enum { 97 SGE_MAX_WR_LEN = 512, /* max WR size in bytes */ 98 SGE_CTXT_SIZE = 24, /* size of SGE context */ 99 SGE_CTXT_SIZE_T7 = 28, /* size of SGE context for T7 */ 100 SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */ 101 SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */ 102 SGE_NDBQTIMERS = 8, /* # of Doorbell Queue Timer values */ 103 SGE_MAX_IQ_SIZE = 65520, 104 SGE_FLBUF_SIZES = 16, 105 }; 106 107 struct sge_qstat { /* data written to SGE queue status entries */ 108 volatile __be32 qid; 109 volatile __be16 cidx; 110 volatile __be16 pidx; 111 }; 112 113 #define S_QSTAT_PIDX 0 114 #define M_QSTAT_PIDX 0xffff 115 #define G_QSTAT_PIDX(x) (((x) >> S_QSTAT_PIDX) & M_QSTAT_PIDX) 116 117 #define S_QSTAT_CIDX 16 118 #define M_QSTAT_CIDX 0xffff 119 #define G_QSTAT_CIDX(x) (((x) >> S_QSTAT_CIDX) & M_QSTAT_CIDX) 120 121 /* 122 * Structure for last 128 bits of response descriptors 123 */ 124 struct rsp_ctrl { 125 __be32 hdrbuflen_pidx; 126 __be32 pldbuflen_qid; 127 union { 128 u8 type_gen; 129 __be64 last_flit; 130 } u; 131 }; 132 133 #define S_RSPD_NEWBUF 31 134 #define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF) 135 #define F_RSPD_NEWBUF V_RSPD_NEWBUF(1U) 136 137 #define S_RSPD_LEN 0 138 #define M_RSPD_LEN 0x7fffffff 139 #define V_RSPD_LEN(x) ((x) << S_RSPD_LEN) 140 #define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN) 141 142 #define S_RSPD_QID S_RSPD_LEN 143 #define M_RSPD_QID M_RSPD_LEN 144 #define V_RSPD_QID(x) V_RSPD_LEN(x) 145 #define G_RSPD_QID(x) G_RSPD_LEN(x) 146 147 #define S_RSPD_GEN 7 148 #define V_RSPD_GEN(x) ((x) << S_RSPD_GEN) 149 #define F_RSPD_GEN V_RSPD_GEN(1U) 150 151 #define S_RSPD_QOVFL 6 152 #define V_RSPD_QOVFL(x) ((x) << S_RSPD_QOVFL) 153 #define F_RSPD_QOVFL V_RSPD_QOVFL(1U) 154 155 #define S_RSPD_TYPE 4 156 #define M_RSPD_TYPE 0x3 157 #define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE) 158 #define G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE) 159 160 /* Rx queue interrupt deferral fields: counter enable and timer index */ 161 #define S_QINTR_CNT_EN 0 162 #define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN) 163 #define F_QINTR_CNT_EN V_QINTR_CNT_EN(1U) 164 165 #define S_QINTR_TIMER_IDX 1 166 #define M_QINTR_TIMER_IDX 0x7 167 #define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX) 168 #define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX) 169 170 #define S_ARM_QTYPE 11 171 #define M_ARM_QTYPE 1 172 #define V_ARM_QTYPE(x) ((x) << S_ARM_QTYPE) 173 174 #define S_ARM_PIDX 0 175 #define M_ARM_PIDX 0x7ffU 176 #define V_ARM_PIDX(x) ((x) << S_ARM_PIDX) 177 178 #define S_ARM_CIDXINC 0 179 #define M_ARM_CIDXINC 0x7ffU 180 #define V_ARM_CIDXINC(x) ((x) << S_ARM_CIDXINC) 181 182 /* # of pages a pagepod can hold without needing another pagepod */ 183 #define PPOD_PAGES 4U 184 185 struct pagepod { 186 __be64 vld_tid_pgsz_tag_color; 187 __be64 len_offset; 188 __be64 rsvd; 189 __be64 addr[PPOD_PAGES + 1]; 190 }; 191 192 #define S_PPOD_COLOR 0 193 #define M_PPOD_COLOR 0x3F 194 #define V_PPOD_COLOR(x) ((x) << S_PPOD_COLOR) 195 196 #define S_PPOD_TAG 6 197 #define M_PPOD_TAG 0xFFFFFF 198 #define V_PPOD_TAG(x) ((x) << S_PPOD_TAG) 199 #define G_PPOD_TAG(x) (((x) >> S_PPOD_TAG) & M_PPOD_TAG) 200 201 #define S_PPOD_PGSZ 30 202 #define M_PPOD_PGSZ 0x3 203 #define V_PPOD_PGSZ(x) ((x) << S_PPOD_PGSZ) 204 #define G_PPOD_PGSZ(x) (((x) >> S_PPOD_PGSZ) & M_PPOD_PGSZ) 205 206 #define S_PPOD_TID 32 207 #define M_PPOD_TID 0xFFFFFF 208 #define V_PPOD_TID(x) ((__u64)(x) << S_PPOD_TID) 209 210 #define S_PPOD_VALID 56 211 #define V_PPOD_VALID(x) ((__u64)(x) << S_PPOD_VALID) 212 #define F_PPOD_VALID V_PPOD_VALID(1ULL) 213 214 #define S_PPOD_LEN 32 215 #define M_PPOD_LEN 0xFFFFFFFF 216 #define V_PPOD_LEN(x) ((__u64)(x) << S_PPOD_LEN) 217 218 #define S_PPOD_OFST 0 219 #define M_PPOD_OFST 0xFFFFFFFF 220 #define V_PPOD_OFST(x) ((x) << S_PPOD_OFST) 221 222 /* 223 * Flash layout. 224 */ 225 #define FLASH_START(start) ((start) * SF_SEC_SIZE) 226 #define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE) 227 #define FLASH_MIN_SIZE FLASH_START(32) 228 229 enum t4_flash_loc { 230 /* 231 * Various Expansion-ROM boot images, etc. 232 */ 233 FLASH_LOC_EXP_ROM = 0, 234 235 /* 236 * iSCSI Boot Firmware Table (iBFT) and other driver-related 237 * parameters ... 238 */ 239 FLASH_LOC_IBFT, 240 241 /* 242 * Boot configuration data. 243 */ 244 FLASH_LOC_BOOTCFG, 245 246 /* 247 * Location of firmware image in FLASH. 248 */ 249 FLASH_LOC_FW, 250 251 /* 252 * Location of bootstrap firmware image in FLASH. 253 */ 254 FLASH_LOC_FWBOOTSTRAP, 255 256 /* 257 * iSCSI persistent/crash information. 258 */ 259 FLASH_LOC_ISCSI_CRASH, 260 261 /* 262 * FCoE persistent/crash information. 263 */ 264 FLASH_LOC_FCOE_CRASH, 265 266 /* 267 * Location of Firmware Configuration File in FLASH. 268 */ 269 FLASH_LOC_CFG, 270 271 /* 272 * CUDBG chip dump. 273 */ 274 FLASH_LOC_CUDBG, 275 276 /* 277 * FW chip dump. 278 */ 279 FLASH_LOC_CHIP_DUMP, 280 281 /* 282 * DPU boot information store. 283 */ 284 FLASH_LOC_DPU_BOOT, 285 286 /* 287 * DPU peristent information store. 288 */ 289 FLASH_LOC_DPU_AREA, 290 291 /* 292 * VPD location. 293 */ 294 FLASH_LOC_VPD, 295 296 /* 297 * Backup init/vpd. 298 */ 299 FLASH_LOC_VPD_BACKUP, 300 301 /* 302 * Backup firmware image. 303 */ 304 FLASH_LOC_FW_BACKUP, 305 306 /* 307 * Backup bootstrap firmware image. 308 */ 309 FLASH_LOC_FWBOOTSTRAP_BACKUP, 310 311 /* 312 * Backup Location of Firmware Configuration File in FLASH. 313 */ 314 FLASH_LOC_CFG_BACK, 315 316 /* 317 * Helper to retrieve info that spans the entire Boot related area. 318 */ 319 FLASH_LOC_BOOT_AREA, 320 321 /* 322 * Helper to determine minimum standard set of sections needed for 323 * normal operations. 324 */ 325 FLASH_LOC_MIN_SIZE, 326 327 /* 328 * End of FLASH regions. 329 */ 330 FLASH_LOC_END 331 }; 332 333 struct t4_flash_loc_entry { 334 u16 start_sec; 335 u16 nsecs; 336 }; 337 338 #define S_SGE_TIMESTAMP 0 339 #define M_SGE_TIMESTAMP 0xfffffffffffffffULL 340 #define V_SGE_TIMESTAMP(x) ((__u64)(x) << S_SGE_TIMESTAMP) 341 #define G_SGE_TIMESTAMP(x) (((__u64)(x) >> S_SGE_TIMESTAMP) & M_SGE_TIMESTAMP) 342 343 #define I2C_DEV_ADDR_A0 0xa0 344 #define I2C_DEV_ADDR_A2 0xa2 345 #define I2C_PAGE_SIZE 0x100 346 #define SFP_DIAG_TYPE_ADDR 0x5c 347 #define SFP_DIAG_TYPE_LEN 0x1 348 #define SFF_8472_COMP_ADDR 0x5e 349 #define SFF_8472_COMP_LEN 0x1 350 #define SFF_REV_ADDR 0x1 351 #define SFF_REV_LEN 0x1 352 353 #endif /* __T4_HW_H */ 354