1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2015 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_CSR_H 7 #define _ASM_RISCV_CSR_H 8 9 #include <asm/asm.h> 10 #include <linux/bits.h> 11 12 /* Status register flags */ 13 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ 14 #define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */ 15 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ 16 #define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */ 17 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ 18 #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ 19 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ 20 21 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ 22 #define SR_FS_OFF _AC(0x00000000, UL) 23 #define SR_FS_INITIAL _AC(0x00002000, UL) 24 #define SR_FS_CLEAN _AC(0x00004000, UL) 25 #define SR_FS_DIRTY _AC(0x00006000, UL) 26 27 #define SR_VS _AC(0x00000600, UL) /* Vector Status */ 28 #define SR_VS_OFF _AC(0x00000000, UL) 29 #define SR_VS_INITIAL _AC(0x00000200, UL) 30 #define SR_VS_CLEAN _AC(0x00000400, UL) 31 #define SR_VS_DIRTY _AC(0x00000600, UL) 32 33 #define SR_VS_THEAD _AC(0x01800000, UL) /* xtheadvector Status */ 34 #define SR_VS_OFF_THEAD _AC(0x00000000, UL) 35 #define SR_VS_INITIAL_THEAD _AC(0x00800000, UL) 36 #define SR_VS_CLEAN_THEAD _AC(0x01000000, UL) 37 #define SR_VS_DIRTY_THEAD _AC(0x01800000, UL) 38 39 #define SR_XS _AC(0x00018000, UL) /* Extension Status */ 40 #define SR_XS_OFF _AC(0x00000000, UL) 41 #define SR_XS_INITIAL _AC(0x00008000, UL) 42 #define SR_XS_CLEAN _AC(0x00010000, UL) 43 #define SR_XS_DIRTY _AC(0x00018000, UL) 44 45 #define SR_FS_VS (SR_FS | SR_VS) /* Vector and Floating-Point Unit */ 46 47 #ifndef CONFIG_64BIT 48 #define SR_SD _AC(0x80000000, UL) /* FS/VS/XS dirty */ 49 #else 50 #define SR_SD _AC(0x8000000000000000, UL) /* FS/VS/XS dirty */ 51 #endif 52 53 #ifdef CONFIG_64BIT 54 #define SR_UXL _AC(0x300000000, UL) /* XLEN mask for U-mode */ 55 #define SR_UXL_32 _AC(0x100000000, UL) /* XLEN = 32 for U-mode */ 56 #define SR_UXL_64 _AC(0x200000000, UL) /* XLEN = 64 for U-mode */ 57 #endif 58 59 /* SATP flags */ 60 #ifndef CONFIG_64BIT 61 #define SATP_PPN _AC(0x003FFFFF, UL) 62 #define SATP_MODE_32 _AC(0x80000000, UL) 63 #define SATP_MODE_SHIFT 31 64 #define SATP_ASID_BITS 9 65 #define SATP_ASID_SHIFT 22 66 #define SATP_ASID_MASK _AC(0x1FF, UL) 67 #else 68 #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) 69 #define SATP_MODE_39 _AC(0x8000000000000000, UL) 70 #define SATP_MODE_48 _AC(0x9000000000000000, UL) 71 #define SATP_MODE_57 _AC(0xa000000000000000, UL) 72 #define SATP_MODE_SHIFT 60 73 #define SATP_ASID_BITS 16 74 #define SATP_ASID_SHIFT 44 75 #define SATP_ASID_MASK _AC(0xFFFF, UL) 76 #endif 77 78 /* Exception cause high bit - is an interrupt if set */ 79 #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) 80 81 /* Interrupt causes (minus the high bit) */ 82 #define IRQ_S_SOFT 1 83 #define IRQ_VS_SOFT 2 84 #define IRQ_M_SOFT 3 85 #define IRQ_S_TIMER 5 86 #define IRQ_VS_TIMER 6 87 #define IRQ_M_TIMER 7 88 #define IRQ_S_EXT 9 89 #define IRQ_VS_EXT 10 90 #define IRQ_M_EXT 11 91 #define IRQ_S_GEXT 12 92 #define IRQ_PMU_OVF 13 93 #define IRQ_LOCAL_MAX (IRQ_PMU_OVF + 1) 94 #define IRQ_LOCAL_MASK GENMASK((IRQ_LOCAL_MAX - 1), 0) 95 96 /* Exception causes */ 97 #define EXC_INST_MISALIGNED 0 98 #define EXC_INST_ACCESS 1 99 #define EXC_INST_ILLEGAL 2 100 #define EXC_BREAKPOINT 3 101 #define EXC_LOAD_MISALIGNED 4 102 #define EXC_LOAD_ACCESS 5 103 #define EXC_STORE_MISALIGNED 6 104 #define EXC_STORE_ACCESS 7 105 #define EXC_SYSCALL 8 106 #define EXC_HYPERVISOR_SYSCALL 9 107 #define EXC_SUPERVISOR_SYSCALL 10 108 #define EXC_INST_PAGE_FAULT 12 109 #define EXC_LOAD_PAGE_FAULT 13 110 #define EXC_STORE_PAGE_FAULT 15 111 #define EXC_INST_GUEST_PAGE_FAULT 20 112 #define EXC_LOAD_GUEST_PAGE_FAULT 21 113 #define EXC_VIRTUAL_INST_FAULT 22 114 #define EXC_STORE_GUEST_PAGE_FAULT 23 115 116 /* PMP configuration */ 117 #define PMP_R 0x01 118 #define PMP_W 0x02 119 #define PMP_X 0x04 120 #define PMP_A 0x18 121 #define PMP_A_TOR 0x08 122 #define PMP_A_NA4 0x10 123 #define PMP_A_NAPOT 0x18 124 #define PMP_L 0x80 125 126 /* HSTATUS flags */ 127 #ifdef CONFIG_64BIT 128 #define HSTATUS_HUPMM _AC(0x3000000000000, UL) 129 #define HSTATUS_HUPMM_PMLEN_0 _AC(0x0000000000000, UL) 130 #define HSTATUS_HUPMM_PMLEN_7 _AC(0x2000000000000, UL) 131 #define HSTATUS_HUPMM_PMLEN_16 _AC(0x3000000000000, UL) 132 #define HSTATUS_VSXL _AC(0x300000000, UL) 133 #define HSTATUS_VSXL_SHIFT 32 134 #endif 135 #define HSTATUS_VTSR _AC(0x00400000, UL) 136 #define HSTATUS_VTW _AC(0x00200000, UL) 137 #define HSTATUS_VTVM _AC(0x00100000, UL) 138 #define HSTATUS_VGEIN _AC(0x0003f000, UL) 139 #define HSTATUS_VGEIN_SHIFT 12 140 #define HSTATUS_HU _AC(0x00000200, UL) 141 #define HSTATUS_SPVP _AC(0x00000100, UL) 142 #define HSTATUS_SPV _AC(0x00000080, UL) 143 #define HSTATUS_GVA _AC(0x00000040, UL) 144 #define HSTATUS_VSBE _AC(0x00000020, UL) 145 146 /* HGATP flags */ 147 #define HGATP_MODE_OFF _AC(0, UL) 148 #define HGATP_MODE_SV32X4 _AC(1, UL) 149 #define HGATP_MODE_SV39X4 _AC(8, UL) 150 #define HGATP_MODE_SV48X4 _AC(9, UL) 151 #define HGATP_MODE_SV57X4 _AC(10, UL) 152 153 #define HGATP32_MODE_SHIFT 31 154 #define HGATP32_VMID_SHIFT 22 155 #define HGATP32_VMID GENMASK(28, 22) 156 #define HGATP32_PPN GENMASK(21, 0) 157 158 #define HGATP64_MODE_SHIFT 60 159 #define HGATP64_VMID_SHIFT 44 160 #define HGATP64_VMID GENMASK(57, 44) 161 #define HGATP64_PPN GENMASK(43, 0) 162 163 #define HGATP_PAGE_SHIFT 12 164 165 #ifdef CONFIG_64BIT 166 #define HGATP_PPN HGATP64_PPN 167 #define HGATP_VMID_SHIFT HGATP64_VMID_SHIFT 168 #define HGATP_VMID HGATP64_VMID 169 #define HGATP_MODE_SHIFT HGATP64_MODE_SHIFT 170 #else 171 #define HGATP_PPN HGATP32_PPN 172 #define HGATP_VMID_SHIFT HGATP32_VMID_SHIFT 173 #define HGATP_VMID HGATP32_VMID 174 #define HGATP_MODE_SHIFT HGATP32_MODE_SHIFT 175 #endif 176 177 /* VSIP & HVIP relation */ 178 #define VSIP_TO_HVIP_SHIFT (IRQ_VS_SOFT - IRQ_S_SOFT) 179 #define VSIP_VALID_MASK ((_AC(1, UL) << IRQ_S_SOFT) | \ 180 (_AC(1, UL) << IRQ_S_TIMER) | \ 181 (_AC(1, UL) << IRQ_S_EXT) | \ 182 (_AC(1, UL) << IRQ_PMU_OVF)) 183 184 /* AIA CSR bits */ 185 #define TOPI_IID_SHIFT 16 186 #define TOPI_IID_MASK GENMASK(11, 0) 187 #define TOPI_IPRIO_MASK GENMASK(7, 0) 188 #define TOPI_IPRIO_BITS 8 189 190 #define TOPEI_ID_SHIFT 16 191 #define TOPEI_ID_MASK GENMASK(10, 0) 192 #define TOPEI_PRIO_MASK GENMASK(10, 0) 193 194 #define ISELECT_IPRIO0 0x30 195 #define ISELECT_IPRIO15 0x3f 196 #define ISELECT_MASK GENMASK(8, 0) 197 198 #define HVICTL_VTI BIT(30) 199 #define HVICTL_IID GENMASK(27, 16) 200 #define HVICTL_IID_SHIFT 16 201 #define HVICTL_DPR BIT(9) 202 #define HVICTL_IPRIOM BIT(8) 203 #define HVICTL_IPRIO GENMASK(7, 0) 204 205 /* xENVCFG flags */ 206 #define ENVCFG_STCE (_AC(1, ULL) << 63) 207 #define ENVCFG_PBMTE (_AC(1, ULL) << 62) 208 #define ENVCFG_ADUE (_AC(1, ULL) << 61) 209 #define ENVCFG_PMM (_AC(0x3, ULL) << 32) 210 #define ENVCFG_PMM_PMLEN_0 (_AC(0x0, ULL) << 32) 211 #define ENVCFG_PMM_PMLEN_7 (_AC(0x2, ULL) << 32) 212 #define ENVCFG_PMM_PMLEN_16 (_AC(0x3, ULL) << 32) 213 #define ENVCFG_CBZE (_AC(1, UL) << 7) 214 #define ENVCFG_CBCFE (_AC(1, UL) << 6) 215 #define ENVCFG_CBIE_SHIFT 4 216 #define ENVCFG_CBIE (_AC(0x3, UL) << ENVCFG_CBIE_SHIFT) 217 #define ENVCFG_CBIE_ILL _AC(0x0, UL) 218 #define ENVCFG_CBIE_FLUSH _AC(0x1, UL) 219 #define ENVCFG_CBIE_INV _AC(0x3, UL) 220 #define ENVCFG_FIOM _AC(0x1, UL) 221 222 /* Smstateen bits */ 223 #define SMSTATEEN0_AIA_IMSIC_SHIFT 58 224 #define SMSTATEEN0_AIA_IMSIC (_ULL(1) << SMSTATEEN0_AIA_IMSIC_SHIFT) 225 #define SMSTATEEN0_AIA_SHIFT 59 226 #define SMSTATEEN0_AIA (_ULL(1) << SMSTATEEN0_AIA_SHIFT) 227 #define SMSTATEEN0_AIA_ISEL_SHIFT 60 228 #define SMSTATEEN0_AIA_ISEL (_ULL(1) << SMSTATEEN0_AIA_ISEL_SHIFT) 229 #define SMSTATEEN0_HSENVCFG_SHIFT 62 230 #define SMSTATEEN0_HSENVCFG (_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT) 231 #define SMSTATEEN0_SSTATEEN0_SHIFT 63 232 #define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT) 233 234 /* mseccfg bits */ 235 #define MSECCFG_PMM ENVCFG_PMM 236 #define MSECCFG_PMM_PMLEN_0 ENVCFG_PMM_PMLEN_0 237 #define MSECCFG_PMM_PMLEN_7 ENVCFG_PMM_PMLEN_7 238 #define MSECCFG_PMM_PMLEN_16 ENVCFG_PMM_PMLEN_16 239 240 /* symbolic CSR names: */ 241 #define CSR_CYCLE 0xc00 242 #define CSR_TIME 0xc01 243 #define CSR_INSTRET 0xc02 244 #define CSR_HPMCOUNTER3 0xc03 245 #define CSR_HPMCOUNTER4 0xc04 246 #define CSR_HPMCOUNTER5 0xc05 247 #define CSR_HPMCOUNTER6 0xc06 248 #define CSR_HPMCOUNTER7 0xc07 249 #define CSR_HPMCOUNTER8 0xc08 250 #define CSR_HPMCOUNTER9 0xc09 251 #define CSR_HPMCOUNTER10 0xc0a 252 #define CSR_HPMCOUNTER11 0xc0b 253 #define CSR_HPMCOUNTER12 0xc0c 254 #define CSR_HPMCOUNTER13 0xc0d 255 #define CSR_HPMCOUNTER14 0xc0e 256 #define CSR_HPMCOUNTER15 0xc0f 257 #define CSR_HPMCOUNTER16 0xc10 258 #define CSR_HPMCOUNTER17 0xc11 259 #define CSR_HPMCOUNTER18 0xc12 260 #define CSR_HPMCOUNTER19 0xc13 261 #define CSR_HPMCOUNTER20 0xc14 262 #define CSR_HPMCOUNTER21 0xc15 263 #define CSR_HPMCOUNTER22 0xc16 264 #define CSR_HPMCOUNTER23 0xc17 265 #define CSR_HPMCOUNTER24 0xc18 266 #define CSR_HPMCOUNTER25 0xc19 267 #define CSR_HPMCOUNTER26 0xc1a 268 #define CSR_HPMCOUNTER27 0xc1b 269 #define CSR_HPMCOUNTER28 0xc1c 270 #define CSR_HPMCOUNTER29 0xc1d 271 #define CSR_HPMCOUNTER30 0xc1e 272 #define CSR_HPMCOUNTER31 0xc1f 273 #define CSR_CYCLEH 0xc80 274 #define CSR_TIMEH 0xc81 275 #define CSR_INSTRETH 0xc82 276 #define CSR_HPMCOUNTER3H 0xc83 277 #define CSR_HPMCOUNTER4H 0xc84 278 #define CSR_HPMCOUNTER5H 0xc85 279 #define CSR_HPMCOUNTER6H 0xc86 280 #define CSR_HPMCOUNTER7H 0xc87 281 #define CSR_HPMCOUNTER8H 0xc88 282 #define CSR_HPMCOUNTER9H 0xc89 283 #define CSR_HPMCOUNTER10H 0xc8a 284 #define CSR_HPMCOUNTER11H 0xc8b 285 #define CSR_HPMCOUNTER12H 0xc8c 286 #define CSR_HPMCOUNTER13H 0xc8d 287 #define CSR_HPMCOUNTER14H 0xc8e 288 #define CSR_HPMCOUNTER15H 0xc8f 289 #define CSR_HPMCOUNTER16H 0xc90 290 #define CSR_HPMCOUNTER17H 0xc91 291 #define CSR_HPMCOUNTER18H 0xc92 292 #define CSR_HPMCOUNTER19H 0xc93 293 #define CSR_HPMCOUNTER20H 0xc94 294 #define CSR_HPMCOUNTER21H 0xc95 295 #define CSR_HPMCOUNTER22H 0xc96 296 #define CSR_HPMCOUNTER23H 0xc97 297 #define CSR_HPMCOUNTER24H 0xc98 298 #define CSR_HPMCOUNTER25H 0xc99 299 #define CSR_HPMCOUNTER26H 0xc9a 300 #define CSR_HPMCOUNTER27H 0xc9b 301 #define CSR_HPMCOUNTER28H 0xc9c 302 #define CSR_HPMCOUNTER29H 0xc9d 303 #define CSR_HPMCOUNTER30H 0xc9e 304 #define CSR_HPMCOUNTER31H 0xc9f 305 306 #define CSR_SCOUNTOVF 0xda0 307 308 #define CSR_SSTATUS 0x100 309 #define CSR_SIE 0x104 310 #define CSR_STVEC 0x105 311 #define CSR_SCOUNTEREN 0x106 312 #define CSR_SENVCFG 0x10a 313 #define CSR_SSTATEEN0 0x10c 314 #define CSR_SSCRATCH 0x140 315 #define CSR_SEPC 0x141 316 #define CSR_SCAUSE 0x142 317 #define CSR_STVAL 0x143 318 #define CSR_SIP 0x144 319 #define CSR_SATP 0x180 320 321 #define CSR_STIMECMP 0x14D 322 #define CSR_STIMECMPH 0x15D 323 324 /* xtheadvector symbolic CSR names */ 325 #define CSR_VXSAT 0x9 326 #define CSR_VXRM 0xa 327 328 /* xtheadvector CSR masks */ 329 #define CSR_VXRM_MASK 3 330 #define CSR_VXRM_SHIFT 1 331 #define CSR_VXSAT_MASK 1 332 333 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ 334 #define CSR_SISELECT 0x150 335 #define CSR_SIREG 0x151 336 337 /* Supervisor-Level Interrupts (AIA) */ 338 #define CSR_STOPEI 0x15c 339 #define CSR_STOPI 0xdb0 340 341 /* Supervisor-Level High-Half CSRs (AIA) */ 342 #define CSR_SIEH 0x114 343 #define CSR_SIPH 0x154 344 345 #define CSR_VSSTATUS 0x200 346 #define CSR_VSIE 0x204 347 #define CSR_VSTVEC 0x205 348 #define CSR_VSSCRATCH 0x240 349 #define CSR_VSEPC 0x241 350 #define CSR_VSCAUSE 0x242 351 #define CSR_VSTVAL 0x243 352 #define CSR_VSIP 0x244 353 #define CSR_VSATP 0x280 354 #define CSR_VSTIMECMP 0x24D 355 #define CSR_VSTIMECMPH 0x25D 356 357 #define CSR_HSTATUS 0x600 358 #define CSR_HEDELEG 0x602 359 #define CSR_HIDELEG 0x603 360 #define CSR_HIE 0x604 361 #define CSR_HTIMEDELTA 0x605 362 #define CSR_HCOUNTEREN 0x606 363 #define CSR_HGEIE 0x607 364 #define CSR_HENVCFG 0x60a 365 #define CSR_HTIMEDELTAH 0x615 366 #define CSR_HENVCFGH 0x61a 367 #define CSR_HTVAL 0x643 368 #define CSR_HIP 0x644 369 #define CSR_HVIP 0x645 370 #define CSR_HTINST 0x64a 371 #define CSR_HGATP 0x680 372 #define CSR_HGEIP 0xe12 373 374 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ 375 #define CSR_HVIEN 0x608 376 #define CSR_HVICTL 0x609 377 #define CSR_HVIPRIO1 0x646 378 #define CSR_HVIPRIO2 0x647 379 380 /* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */ 381 #define CSR_VSISELECT 0x250 382 #define CSR_VSIREG 0x251 383 384 /* VS-Level Interrupts (H-extension with AIA) */ 385 #define CSR_VSTOPEI 0x25c 386 #define CSR_VSTOPI 0xeb0 387 388 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ 389 #define CSR_HIDELEGH 0x613 390 #define CSR_HVIENH 0x618 391 #define CSR_HVIPH 0x655 392 #define CSR_HVIPRIO1H 0x656 393 #define CSR_HVIPRIO2H 0x657 394 #define CSR_VSIEH 0x214 395 #define CSR_VSIPH 0x254 396 397 /* Hypervisor stateen CSRs */ 398 #define CSR_HSTATEEN0 0x60c 399 #define CSR_HSTATEEN0H 0x61c 400 401 #define CSR_MSTATUS 0x300 402 #define CSR_MISA 0x301 403 #define CSR_MIDELEG 0x303 404 #define CSR_MIE 0x304 405 #define CSR_MTVEC 0x305 406 #define CSR_MENVCFG 0x30a 407 #define CSR_MENVCFGH 0x31a 408 #define CSR_MSCRATCH 0x340 409 #define CSR_MEPC 0x341 410 #define CSR_MCAUSE 0x342 411 #define CSR_MTVAL 0x343 412 #define CSR_MIP 0x344 413 #define CSR_PMPCFG0 0x3a0 414 #define CSR_PMPADDR0 0x3b0 415 #define CSR_MSECCFG 0x747 416 #define CSR_MSECCFGH 0x757 417 #define CSR_MVENDORID 0xf11 418 #define CSR_MARCHID 0xf12 419 #define CSR_MIMPID 0xf13 420 #define CSR_MHARTID 0xf14 421 422 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ 423 #define CSR_MISELECT 0x350 424 #define CSR_MIREG 0x351 425 426 /* Machine-Level Interrupts (AIA) */ 427 #define CSR_MTOPEI 0x35c 428 #define CSR_MTOPI 0xfb0 429 430 /* Virtual Interrupts for Supervisor Level (AIA) */ 431 #define CSR_MVIEN 0x308 432 #define CSR_MVIP 0x309 433 434 /* Machine-Level High-Half CSRs (AIA) */ 435 #define CSR_MIDELEGH 0x313 436 #define CSR_MIEH 0x314 437 #define CSR_MVIENH 0x318 438 #define CSR_MVIPH 0x319 439 #define CSR_MIPH 0x354 440 441 #define CSR_VSTART 0x8 442 #define CSR_VCSR 0xf 443 #define CSR_VL 0xc20 444 #define CSR_VTYPE 0xc21 445 #define CSR_VLENB 0xc22 446 447 /* Scalar Crypto Extension - Entropy */ 448 #define CSR_SEED 0x015 449 #define SEED_OPST_MASK _AC(0xC0000000, UL) 450 #define SEED_OPST_BIST _AC(0x00000000, UL) 451 #define SEED_OPST_WAIT _AC(0x40000000, UL) 452 #define SEED_OPST_ES16 _AC(0x80000000, UL) 453 #define SEED_OPST_DEAD _AC(0xC0000000, UL) 454 #define SEED_ENTROPY_MASK _AC(0xFFFF, UL) 455 456 #ifdef CONFIG_RISCV_M_MODE 457 # define CSR_STATUS CSR_MSTATUS 458 # define CSR_IE CSR_MIE 459 # define CSR_TVEC CSR_MTVEC 460 # define CSR_ENVCFG CSR_MENVCFG 461 # define CSR_SCRATCH CSR_MSCRATCH 462 # define CSR_EPC CSR_MEPC 463 # define CSR_CAUSE CSR_MCAUSE 464 # define CSR_TVAL CSR_MTVAL 465 # define CSR_IP CSR_MIP 466 467 # define CSR_IEH CSR_MIEH 468 # define CSR_ISELECT CSR_MISELECT 469 # define CSR_IREG CSR_MIREG 470 # define CSR_IPH CSR_MIPH 471 # define CSR_TOPEI CSR_MTOPEI 472 # define CSR_TOPI CSR_MTOPI 473 474 # define SR_IE SR_MIE 475 # define SR_PIE SR_MPIE 476 # define SR_PP SR_MPP 477 478 # define RV_IRQ_SOFT IRQ_M_SOFT 479 # define RV_IRQ_TIMER IRQ_M_TIMER 480 # define RV_IRQ_EXT IRQ_M_EXT 481 #else /* CONFIG_RISCV_M_MODE */ 482 # define CSR_STATUS CSR_SSTATUS 483 # define CSR_IE CSR_SIE 484 # define CSR_TVEC CSR_STVEC 485 # define CSR_ENVCFG CSR_SENVCFG 486 # define CSR_SCRATCH CSR_SSCRATCH 487 # define CSR_EPC CSR_SEPC 488 # define CSR_CAUSE CSR_SCAUSE 489 # define CSR_TVAL CSR_STVAL 490 # define CSR_IP CSR_SIP 491 492 # define CSR_IEH CSR_SIEH 493 # define CSR_ISELECT CSR_SISELECT 494 # define CSR_IREG CSR_SIREG 495 # define CSR_IPH CSR_SIPH 496 # define CSR_TOPEI CSR_STOPEI 497 # define CSR_TOPI CSR_STOPI 498 499 # define SR_IE SR_SIE 500 # define SR_PIE SR_SPIE 501 # define SR_PP SR_SPP 502 503 # define RV_IRQ_SOFT IRQ_S_SOFT 504 # define RV_IRQ_TIMER IRQ_S_TIMER 505 # define RV_IRQ_EXT IRQ_S_EXT 506 # define RV_IRQ_PMU IRQ_PMU_OVF 507 # define SIP_LCOFIP (_AC(0x1, UL) << IRQ_PMU_OVF) 508 509 #endif /* !CONFIG_RISCV_M_MODE */ 510 511 /* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */ 512 #define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT) 513 #define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER) 514 #define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT) 515 516 #ifndef __ASSEMBLY__ 517 518 #define csr_swap(csr, val) \ 519 ({ \ 520 unsigned long __v = (unsigned long)(val); \ 521 __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ 522 : "=r" (__v) : "rK" (__v) \ 523 : "memory"); \ 524 __v; \ 525 }) 526 527 #define csr_read(csr) \ 528 ({ \ 529 register unsigned long __v; \ 530 __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ 531 : "=r" (__v) : \ 532 : "memory"); \ 533 __v; \ 534 }) 535 536 #define csr_write(csr, val) \ 537 ({ \ 538 unsigned long __v = (unsigned long)(val); \ 539 __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ 540 : : "rK" (__v) \ 541 : "memory"); \ 542 }) 543 544 #define csr_read_set(csr, val) \ 545 ({ \ 546 unsigned long __v = (unsigned long)(val); \ 547 __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ 548 : "=r" (__v) : "rK" (__v) \ 549 : "memory"); \ 550 __v; \ 551 }) 552 553 #define csr_set(csr, val) \ 554 ({ \ 555 unsigned long __v = (unsigned long)(val); \ 556 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ 557 : : "rK" (__v) \ 558 : "memory"); \ 559 }) 560 561 #define csr_read_clear(csr, val) \ 562 ({ \ 563 unsigned long __v = (unsigned long)(val); \ 564 __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ 565 : "=r" (__v) : "rK" (__v) \ 566 : "memory"); \ 567 __v; \ 568 }) 569 570 #define csr_clear(csr, val) \ 571 ({ \ 572 unsigned long __v = (unsigned long)(val); \ 573 __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ 574 : : "rK" (__v) \ 575 : "memory"); \ 576 }) 577 578 #endif /* __ASSEMBLY__ */ 579 580 #endif /* _ASM_RISCV_CSR_H */ 581