xref: /linux/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h (revision 2c1ed907520c50326b8f604907a8478b27881a2e)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) Rockchip Electronics Co., Ltd.
4  * Author:Mark Yao <mark.yao@rock-chips.com>
5  */
6 
7 #ifndef _ROCKCHIP_DRM_VOP2_H
8 #define _ROCKCHIP_DRM_VOP2_H
9 
10 #include <linux/regmap.h>
11 #include <drm/drm_modes.h>
12 #include "rockchip_drm_drv.h"
13 #include "rockchip_drm_vop.h"
14 
15 #define VOP2_VP_FEATURE_OUTPUT_10BIT        BIT(0)
16 
17 #define VOP2_FEATURE_HAS_SYS_GRF	BIT(0)
18 #define VOP2_FEATURE_HAS_VO0_GRF	BIT(1)
19 #define VOP2_FEATURE_HAS_VO1_GRF	BIT(2)
20 #define VOP2_FEATURE_HAS_VOP_GRF	BIT(3)
21 #define VOP2_FEATURE_HAS_SYS_PMU	BIT(4)
22 
23 #define WIN_FEATURE_AFBDC		BIT(0)
24 #define WIN_FEATURE_CLUSTER		BIT(1)
25 
26 #define HIWORD_UPDATE(v, h, l)  ((GENMASK(h, l) << 16) | ((v) << (l)))
27 /*
28  *  the delay number of a window in different mode.
29  */
30 enum win_dly_mode {
31 	VOP2_DLY_MODE_DEFAULT,   /**< default mode */
32 	VOP2_DLY_MODE_HISO_S,    /** HDR in SDR out mode, as a SDR window */
33 	VOP2_DLY_MODE_HIHO_H,    /** HDR in HDR out mode, as a HDR window */
34 	VOP2_DLY_MODE_MAX,
35 };
36 
37 enum vop2_scale_up_mode {
38 	VOP2_SCALE_UP_NRST_NBOR,
39 	VOP2_SCALE_UP_BIL,
40 	VOP2_SCALE_UP_BIC,
41 };
42 
43 enum vop2_scale_down_mode {
44 	VOP2_SCALE_DOWN_NRST_NBOR,
45 	VOP2_SCALE_DOWN_BIL,
46 	VOP2_SCALE_DOWN_AVG,
47 };
48 
49 /*
50  * vop2 internal power domain id,
51  * should be all none zero, 0 will be treat as invalid;
52  */
53 #define VOP2_PD_CLUSTER0	BIT(0)
54 #define VOP2_PD_CLUSTER1	BIT(1)
55 #define VOP2_PD_CLUSTER2	BIT(2)
56 #define VOP2_PD_CLUSTER3	BIT(3)
57 #define VOP2_PD_DSC_8K		BIT(5)
58 #define VOP2_PD_DSC_4K		BIT(6)
59 #define VOP2_PD_ESMART		BIT(7)
60 
61 enum vop2_win_regs {
62 	VOP2_WIN_ENABLE,
63 	VOP2_WIN_FORMAT,
64 	VOP2_WIN_CSC_MODE,
65 	VOP2_WIN_XMIRROR,
66 	VOP2_WIN_YMIRROR,
67 	VOP2_WIN_RB_SWAP,
68 	VOP2_WIN_UV_SWAP,
69 	VOP2_WIN_ACT_INFO,
70 	VOP2_WIN_DSP_INFO,
71 	VOP2_WIN_DSP_ST,
72 	VOP2_WIN_YRGB_MST,
73 	VOP2_WIN_UV_MST,
74 	VOP2_WIN_YRGB_VIR,
75 	VOP2_WIN_UV_VIR,
76 	VOP2_WIN_YUV_CLIP,
77 	VOP2_WIN_Y2R_EN,
78 	VOP2_WIN_R2Y_EN,
79 	VOP2_WIN_COLOR_KEY,
80 	VOP2_WIN_COLOR_KEY_EN,
81 	VOP2_WIN_DITHER_UP,
82 	VOP2_WIN_AXI_BUS_ID,
83 	VOP2_WIN_AXI_YRGB_R_ID,
84 	VOP2_WIN_AXI_UV_R_ID,
85 
86 	/* scale regs */
87 	VOP2_WIN_SCALE_YRGB_X,
88 	VOP2_WIN_SCALE_YRGB_Y,
89 	VOP2_WIN_SCALE_CBCR_X,
90 	VOP2_WIN_SCALE_CBCR_Y,
91 	VOP2_WIN_YRGB_HOR_SCL_MODE,
92 	VOP2_WIN_YRGB_HSCL_FILTER_MODE,
93 	VOP2_WIN_YRGB_VER_SCL_MODE,
94 	VOP2_WIN_YRGB_VSCL_FILTER_MODE,
95 	VOP2_WIN_CBCR_VER_SCL_MODE,
96 	VOP2_WIN_CBCR_HSCL_FILTER_MODE,
97 	VOP2_WIN_CBCR_HOR_SCL_MODE,
98 	VOP2_WIN_CBCR_VSCL_FILTER_MODE,
99 	VOP2_WIN_VSD_CBCR_GT2,
100 	VOP2_WIN_VSD_CBCR_GT4,
101 	VOP2_WIN_VSD_YRGB_GT2,
102 	VOP2_WIN_VSD_YRGB_GT4,
103 	VOP2_WIN_BIC_COE_SEL,
104 
105 	/* cluster regs */
106 	VOP2_WIN_CLUSTER_ENABLE,
107 	VOP2_WIN_AFBC_ENABLE,
108 	VOP2_WIN_CLUSTER_LB_MODE,
109 
110 	/* afbc regs */
111 	VOP2_WIN_AFBC_FORMAT,
112 	VOP2_WIN_AFBC_RB_SWAP,
113 	VOP2_WIN_AFBC_UV_SWAP,
114 	VOP2_WIN_AFBC_AUTO_GATING_EN,
115 	VOP2_WIN_AFBC_BLOCK_SPLIT_EN,
116 	VOP2_WIN_AFBC_PIC_VIR_WIDTH,
117 	VOP2_WIN_AFBC_TILE_NUM,
118 	VOP2_WIN_AFBC_PIC_OFFSET,
119 	VOP2_WIN_AFBC_PIC_SIZE,
120 	VOP2_WIN_AFBC_DSP_OFFSET,
121 	VOP2_WIN_AFBC_TRANSFORM_OFFSET,
122 	VOP2_WIN_AFBC_HDR_PTR,
123 	VOP2_WIN_AFBC_HALF_BLOCK_EN,
124 	VOP2_WIN_AFBC_ROTATE_270,
125 	VOP2_WIN_AFBC_ROTATE_90,
126 	VOP2_WIN_MAX_REG,
127 };
128 
129 struct vop2_regs_dump {
130 	const char *name;
131 	u32 base;
132 	u32 size;
133 	u32 en_reg;
134 	u32 en_val;
135 	u32 en_mask;
136 };
137 
138 struct vop2_win_data {
139 	const char *name;
140 	unsigned int phys_id;
141 
142 	u32 base;
143 	enum drm_plane_type type;
144 
145 	u32 nformats;
146 	const u32 *formats;
147 	const uint64_t *format_modifiers;
148 	const unsigned int supported_rotations;
149 
150 	/**
151 	 * @layer_sel_id: defined by register OVERLAY_LAYER_SEL of VOP2
152 	 */
153 	unsigned int layer_sel_id;
154 	uint64_t feature;
155 
156 	uint8_t axi_bus_id;
157 	uint8_t axi_yrgb_r_id;
158 	uint8_t axi_uv_r_id;
159 
160 	unsigned int max_upscale_factor;
161 	unsigned int max_downscale_factor;
162 	const u8 dly[VOP2_DLY_MODE_MAX];
163 };
164 
165 struct vop2_video_port_data {
166 	unsigned int id;
167 	u32 feature;
168 	u16 gamma_lut_len;
169 	u16 cubic_lut_len;
170 	struct vop_rect max_output;
171 	const u8 pre_scan_max_dly[4];
172 	unsigned int offset;
173 };
174 
175 struct vop2_data {
176 	u8 nr_vps;
177 	u64 feature;
178 	const struct vop2_win_data *win;
179 	const struct vop2_video_port_data *vp;
180 	const struct vop2_regs_dump *regs_dump;
181 	struct vop_rect max_input;
182 	struct vop_rect max_output;
183 
184 	unsigned int win_size;
185 	unsigned int regs_dump_size;
186 	unsigned int soc_id;
187 };
188 
189 /* interrupt define */
190 #define FS_NEW_INTR			BIT(4)
191 #define ADDR_SAME_INTR			BIT(5)
192 #define LINE_FLAG1_INTR			BIT(6)
193 #define WIN0_EMPTY_INTR			BIT(7)
194 #define WIN1_EMPTY_INTR			BIT(8)
195 #define WIN2_EMPTY_INTR			BIT(9)
196 #define WIN3_EMPTY_INTR			BIT(10)
197 #define HWC_EMPTY_INTR			BIT(11)
198 #define POST_BUF_EMPTY_INTR		BIT(12)
199 #define PWM_GEN_INTR			BIT(13)
200 #define DMA_FINISH_INTR			BIT(14)
201 #define FS_FIELD_INTR			BIT(15)
202 #define FE_INTR				BIT(16)
203 #define WB_UV_FIFO_FULL_INTR		BIT(17)
204 #define WB_YRGB_FIFO_FULL_INTR		BIT(18)
205 #define WB_COMPLETE_INTR		BIT(19)
206 
207 
208 enum vop_csc_format {
209 	CSC_BT601L,
210 	CSC_BT709L,
211 	CSC_BT601F,
212 	CSC_BT2020,
213 };
214 
215 enum src_factor_mode {
216 	SRC_FAC_ALPHA_ZERO,
217 	SRC_FAC_ALPHA_ONE,
218 	SRC_FAC_ALPHA_DST,
219 	SRC_FAC_ALPHA_DST_INVERSE,
220 	SRC_FAC_ALPHA_SRC,
221 	SRC_FAC_ALPHA_SRC_GLOBAL,
222 };
223 
224 enum dst_factor_mode {
225 	DST_FAC_ALPHA_ZERO,
226 	DST_FAC_ALPHA_ONE,
227 	DST_FAC_ALPHA_SRC,
228 	DST_FAC_ALPHA_SRC_INVERSE,
229 	DST_FAC_ALPHA_DST,
230 	DST_FAC_ALPHA_DST_GLOBAL,
231 };
232 
233 #define RK3568_GRF_VO_CON1			0x0364
234 
235 #define RK3588_GRF_SOC_CON1			0x0304
236 #define RK3588_GRF_VOP_CON2			0x08
237 #define RK3588_GRF_VO1_CON0			0x00
238 
239 /* System registers definition */
240 #define RK3568_REG_CFG_DONE			0x000
241 #define RK3568_VERSION_INFO			0x004
242 #define RK3568_SYS_AUTO_GATING_CTRL		0x008
243 #define RK3568_SYS_AXI_LUT_CTRL			0x024
244 #define RK3568_DSP_IF_EN			0x028
245 #define RK3568_DSP_IF_CTRL			0x02c
246 #define RK3568_DSP_IF_POL			0x030
247 #define RK3588_SYS_PD_CTRL			0x034
248 #define RK3568_WB_CTRL				0x40
249 #define RK3568_WB_XSCAL_FACTOR			0x44
250 #define RK3568_WB_YRGB_MST			0x48
251 #define RK3568_WB_CBR_MST			0x4C
252 #define RK3568_OTP_WIN_EN			0x050
253 #define RK3568_LUT_PORT_SEL			0x058
254 #define RK3568_SYS_STATUS0			0x060
255 #define RK3568_VP_LINE_FLAG(vp)			(0x70 + (vp) * 0x4)
256 #define RK3568_SYS0_INT_EN			0x80
257 #define RK3568_SYS0_INT_CLR			0x84
258 #define RK3568_SYS0_INT_STATUS			0x88
259 #define RK3568_SYS1_INT_EN			0x90
260 #define RK3568_SYS1_INT_CLR			0x94
261 #define RK3568_SYS1_INT_STATUS			0x98
262 #define RK3568_VP_INT_EN(vp)			(0xA0 + (vp) * 0x10)
263 #define RK3568_VP_INT_CLR(vp)			(0xA4 + (vp) * 0x10)
264 #define RK3568_VP_INT_STATUS(vp)		(0xA8 + (vp) * 0x10)
265 #define RK3568_VP_INT_RAW_STATUS(vp)		(0xAC + (vp) * 0x10)
266 
267 /* Video Port registers definition */
268 #define RK3568_VP0_CTRL_BASE			0x0C00
269 #define RK3568_VP1_CTRL_BASE			0x0D00
270 #define RK3568_VP2_CTRL_BASE			0x0E00
271 #define RK3588_VP3_CTRL_BASE			0x0F00
272 #define RK3568_VP_DSP_CTRL			0x00
273 #define RK3568_VP_MIPI_CTRL			0x04
274 #define RK3568_VP_COLOR_BAR_CTRL		0x08
275 #define RK3588_VP_CLK_CTRL			0x0C
276 #define RK3568_VP_3D_LUT_CTRL			0x10
277 #define RK3568_VP_3D_LUT_MST			0x20
278 #define RK3568_VP_DSP_BG			0x2C
279 #define RK3568_VP_PRE_SCAN_HTIMING		0x30
280 #define RK3568_VP_POST_DSP_HACT_INFO		0x34
281 #define RK3568_VP_POST_DSP_VACT_INFO		0x38
282 #define RK3568_VP_POST_SCL_FACTOR_YRGB		0x3C
283 #define RK3568_VP_POST_SCL_CTRL			0x40
284 #define RK3568_VP_POST_DSP_VACT_INFO_F1		0x44
285 #define RK3568_VP_DSP_HTOTAL_HS_END		0x48
286 #define RK3568_VP_DSP_HACT_ST_END		0x4C
287 #define RK3568_VP_DSP_VTOTAL_VS_END		0x50
288 #define RK3568_VP_DSP_VACT_ST_END		0x54
289 #define RK3568_VP_DSP_VS_ST_END_F1		0x58
290 #define RK3568_VP_DSP_VACT_ST_END_F1		0x5C
291 #define RK3568_VP_BCSH_CTRL			0x60
292 #define RK3568_VP_BCSH_BCS			0x64
293 #define RK3568_VP_BCSH_H			0x68
294 #define RK3568_VP_BCSH_COLOR_BAR		0x6C
295 
296 /* Overlay registers definition    */
297 #define RK3568_OVL_CTRL				0x600
298 #define RK3568_OVL_LAYER_SEL			0x604
299 #define RK3568_OVL_PORT_SEL			0x608
300 #define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL	0x610
301 #define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL	0x614
302 #define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL	0x618
303 #define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL	0x61C
304 #define RK3568_MIX0_SRC_COLOR_CTRL		0x650
305 #define RK3568_MIX0_DST_COLOR_CTRL		0x654
306 #define RK3568_MIX0_SRC_ALPHA_CTRL		0x658
307 #define RK3568_MIX0_DST_ALPHA_CTRL		0x65C
308 #define RK3568_HDR0_SRC_COLOR_CTRL		0x6C0
309 #define RK3568_HDR0_DST_COLOR_CTRL		0x6C4
310 #define RK3568_HDR0_SRC_ALPHA_CTRL		0x6C8
311 #define RK3568_HDR0_DST_ALPHA_CTRL		0x6CC
312 #define RK3568_VP_BG_MIX_CTRL(vp)		(0x6E0 + (vp) * 4)
313 #define RK3568_CLUSTER_DLY_NUM			0x6F0
314 #define RK3568_SMART_DLY_NUM			0x6F8
315 
316 /* Cluster register definition, offset relative to window base */
317 #define RK3568_CLUSTER0_CTRL_BASE		0x1000
318 #define RK3568_CLUSTER1_CTRL_BASE		0x1200
319 #define RK3588_CLUSTER2_CTRL_BASE		0x1400
320 #define RK3588_CLUSTER3_CTRL_BASE		0x1600
321 #define RK3568_ESMART0_CTRL_BASE		0x1800
322 #define RK3568_ESMART1_CTRL_BASE		0x1A00
323 #define RK3568_SMART0_CTRL_BASE			0x1C00
324 #define RK3568_SMART1_CTRL_BASE			0x1E00
325 #define RK3588_ESMART2_CTRL_BASE		0x1C00
326 #define RK3588_ESMART3_CTRL_BASE		0x1E00
327 
328 #define RK3568_CLUSTER_WIN_CTRL0		0x00
329 #define RK3568_CLUSTER_WIN_CTRL1		0x04
330 #define RK3568_CLUSTER_WIN_CTRL2		0x08
331 #define RK3568_CLUSTER_WIN_YRGB_MST		0x10
332 #define RK3568_CLUSTER_WIN_CBR_MST		0x14
333 #define RK3568_CLUSTER_WIN_VIR			0x18
334 #define RK3568_CLUSTER_WIN_ACT_INFO		0x20
335 #define RK3568_CLUSTER_WIN_DSP_INFO		0x24
336 #define RK3568_CLUSTER_WIN_DSP_ST		0x28
337 #define RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB	0x30
338 #define RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET	0x3C
339 #define RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL	0x50
340 #define RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE	0x54
341 #define RK3568_CLUSTER_WIN_AFBCD_HDR_PTR	0x58
342 #define RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH	0x5C
343 #define RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE	0x60
344 #define RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET	0x64
345 #define RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET	0x68
346 #define RK3568_CLUSTER_WIN_AFBCD_CTRL		0x6C
347 
348 #define RK3568_CLUSTER_CTRL			0x100
349 
350 /* (E)smart register definition, offset relative to window base */
351 #define RK3568_SMART_CTRL0			0x00
352 #define RK3568_SMART_CTRL1			0x04
353 #define RK3588_SMART_AXI_CTRL			0x08
354 #define RK3568_SMART_REGION0_CTRL		0x10
355 #define RK3568_SMART_REGION0_YRGB_MST		0x14
356 #define RK3568_SMART_REGION0_CBR_MST		0x18
357 #define RK3568_SMART_REGION0_VIR		0x1C
358 #define RK3568_SMART_REGION0_ACT_INFO		0x20
359 #define RK3568_SMART_REGION0_DSP_INFO		0x24
360 #define RK3568_SMART_REGION0_DSP_ST		0x28
361 #define RK3568_SMART_REGION0_SCL_CTRL		0x30
362 #define RK3568_SMART_REGION0_SCL_FACTOR_YRGB	0x34
363 #define RK3568_SMART_REGION0_SCL_FACTOR_CBR	0x38
364 #define RK3568_SMART_REGION0_SCL_OFFSET		0x3C
365 #define RK3568_SMART_REGION1_CTRL		0x40
366 #define RK3568_SMART_REGION1_YRGB_MST		0x44
367 #define RK3568_SMART_REGION1_CBR_MST		0x48
368 #define RK3568_SMART_REGION1_VIR		0x4C
369 #define RK3568_SMART_REGION1_ACT_INFO		0x50
370 #define RK3568_SMART_REGION1_DSP_INFO		0x54
371 #define RK3568_SMART_REGION1_DSP_ST		0x58
372 #define RK3568_SMART_REGION1_SCL_CTRL		0x60
373 #define RK3568_SMART_REGION1_SCL_FACTOR_YRGB	0x64
374 #define RK3568_SMART_REGION1_SCL_FACTOR_CBR	0x68
375 #define RK3568_SMART_REGION1_SCL_OFFSET		0x6C
376 #define RK3568_SMART_REGION2_CTRL		0x70
377 #define RK3568_SMART_REGION2_YRGB_MST		0x74
378 #define RK3568_SMART_REGION2_CBR_MST		0x78
379 #define RK3568_SMART_REGION2_VIR		0x7C
380 #define RK3568_SMART_REGION2_ACT_INFO		0x80
381 #define RK3568_SMART_REGION2_DSP_INFO		0x84
382 #define RK3568_SMART_REGION2_DSP_ST		0x88
383 #define RK3568_SMART_REGION2_SCL_CTRL		0x90
384 #define RK3568_SMART_REGION2_SCL_FACTOR_YRGB	0x94
385 #define RK3568_SMART_REGION2_SCL_FACTOR_CBR	0x98
386 #define RK3568_SMART_REGION2_SCL_OFFSET		0x9C
387 #define RK3568_SMART_REGION3_CTRL		0xA0
388 #define RK3568_SMART_REGION3_YRGB_MST		0xA4
389 #define RK3568_SMART_REGION3_CBR_MST		0xA8
390 #define RK3568_SMART_REGION3_VIR		0xAC
391 #define RK3568_SMART_REGION3_ACT_INFO		0xB0
392 #define RK3568_SMART_REGION3_DSP_INFO		0xB4
393 #define RK3568_SMART_REGION3_DSP_ST		0xB8
394 #define RK3568_SMART_REGION3_SCL_CTRL		0xC0
395 #define RK3568_SMART_REGION3_SCL_FACTOR_YRGB	0xC4
396 #define RK3568_SMART_REGION3_SCL_FACTOR_CBR	0xC8
397 #define RK3568_SMART_REGION3_SCL_OFFSET		0xCC
398 #define RK3568_SMART_COLOR_KEY_CTRL		0xD0
399 
400 /* HDR register definition */
401 #define RK3568_HDR_LUT_CTRL			0x2000
402 #define RK3568_HDR_LUT_MST			0x2004
403 #define RK3568_SDR2HDR_CTRL			0x2010
404 #define RK3568_HDR2SDR_CTRL			0x2020
405 #define RK3568_HDR2SDR_SRC_RANGE		0x2024
406 #define RK3568_HDR2SDR_NORMFACEETF		0x2028
407 #define RK3568_HDR2SDR_DST_RANGE		0x202C
408 #define RK3568_HDR2SDR_NORMFACCGAMMA		0x2030
409 #define RK3568_HDR_EETF_OETF_Y0			0x203C
410 #define RK3568_HDR_SAT_Y0			0x20C0
411 #define RK3568_HDR_EOTF_OETF_Y0			0x20F0
412 #define RK3568_HDR_OETF_DX_POW1			0x2200
413 #define RK3568_HDR_OETF_XN1			0x2300
414 
415 #define RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN		BIT(15)
416 
417 #define RK3568_VP_DSP_CTRL__STANDBY			BIT(31)
418 #define RK3568_VP_DSP_CTRL__DSP_LUT_EN			BIT(28)
419 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_MODE		BIT(20)
420 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL		GENMASK(19, 18)
421 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_EN		BIT(17)
422 #define RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN		BIT(16)
423 #define RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y		BIT(15)
424 #define RK3568_VP_DSP_CTRL__DSP_RG_SWAP			BIT(10)
425 #define RK3568_VP_DSP_CTRL__DSP_RB_SWAP			BIT(9)
426 #define RK3568_VP_DSP_CTRL__DSP_BG_SWAP			BIT(8)
427 #define RK3568_VP_DSP_CTRL__DSP_INTERLACE		BIT(7)
428 #define RK3568_VP_DSP_CTRL__DSP_FILED_POL		BIT(6)
429 #define RK3568_VP_DSP_CTRL__P2I_EN			BIT(5)
430 #define RK3568_VP_DSP_CTRL__CORE_DCLK_DIV		BIT(4)
431 #define RK3568_VP_DSP_CTRL__OUT_MODE			GENMASK(3, 0)
432 
433 #define RK3588_VP_DSP_CTRL__GAMMA_UPDATE_EN		BIT(22)
434 
435 #define RK3588_VP_CLK_CTRL__DCLK_OUT_DIV		GENMASK(3, 2)
436 #define RK3588_VP_CLK_CTRL__DCLK_CORE_DIV		GENMASK(1, 0)
437 
438 #define RK3568_VP_POST_SCL_CTRL__VSCALEDOWN		BIT(1)
439 #define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN		BIT(0)
440 
441 #define RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX		GENMASK(26, 25)
442 #define RK3568_SYS_DSP_INFACE_EN_LVDS1			BIT(24)
443 #define RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX		GENMASK(22, 21)
444 #define RK3568_SYS_DSP_INFACE_EN_MIPI1			BIT(20)
445 #define RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX		GENMASK(19, 18)
446 #define RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX		GENMASK(17, 16)
447 #define RK3568_SYS_DSP_INFACE_EN_EDP_MUX		GENMASK(15, 14)
448 #define RK3568_SYS_DSP_INFACE_EN_HDMI_MUX		GENMASK(11, 10)
449 #define RK3568_SYS_DSP_INFACE_EN_RGB_MUX		GENMASK(9, 8)
450 #define RK3568_SYS_DSP_INFACE_EN_LVDS0			BIT(5)
451 #define RK3568_SYS_DSP_INFACE_EN_MIPI0			BIT(4)
452 #define RK3568_SYS_DSP_INFACE_EN_EDP			BIT(3)
453 #define RK3568_SYS_DSP_INFACE_EN_HDMI			BIT(1)
454 #define RK3568_SYS_DSP_INFACE_EN_RGB			BIT(0)
455 
456 #define RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX		GENMASK(22, 21)
457 #define RK3588_SYS_DSP_INFACE_EN_MIPI0_MUX		GENMASK(20, 20)
458 #define RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX		GENMASK(19, 18)
459 #define RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX		GENMASK(17, 16)
460 #define RK3588_SYS_DSP_INFACE_EN_DP1_MUX		GENMASK(15, 14)
461 #define RK3588_SYS_DSP_INFACE_EN_DP0_MUX		GENMASK(13, 12)
462 #define RK3588_SYS_DSP_INFACE_EN_DPI			GENMASK(9, 8)
463 #define RK3588_SYS_DSP_INFACE_EN_MIPI1			BIT(7)
464 #define RK3588_SYS_DSP_INFACE_EN_MIPI0			BIT(6)
465 #define RK3588_SYS_DSP_INFACE_EN_HDMI1			BIT(5)
466 #define RK3588_SYS_DSP_INFACE_EN_EDP1			BIT(4)
467 #define RK3588_SYS_DSP_INFACE_EN_HDMI0			BIT(3)
468 #define RK3588_SYS_DSP_INFACE_EN_EDP0			BIT(2)
469 #define RK3588_SYS_DSP_INFACE_EN_DP1			BIT(1)
470 #define RK3588_SYS_DSP_INFACE_EN_DP0			BIT(0)
471 
472 #define RK3588_DSP_IF_MIPI1_PCLK_DIV			GENMASK(27, 26)
473 #define RK3588_DSP_IF_MIPI0_PCLK_DIV			GENMASK(25, 24)
474 #define RK3588_DSP_IF_EDP_HDMI1_PCLK_DIV		GENMASK(22, 22)
475 #define RK3588_DSP_IF_EDP_HDMI1_DCLK_DIV		GENMASK(21, 20)
476 #define RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV		GENMASK(18, 18)
477 #define RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV		GENMASK(17, 16)
478 
479 #define RK3568_DSP_IF_POL__MIPI_PIN_POL			GENMASK(19, 16)
480 #define RK3568_DSP_IF_POL__EDP_PIN_POL			GENMASK(15, 12)
481 #define RK3568_DSP_IF_POL__HDMI_PIN_POL			GENMASK(7, 4)
482 #define RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL		GENMASK(3, 0)
483 
484 #define RK3588_DSP_IF_POL__DP1_PIN_POL			GENMASK(14, 12)
485 #define RK3588_DSP_IF_POL__DP0_PIN_POL			GENMASK(10, 8)
486 
487 #define RK3588_LUT_PORT_SEL__GAMMA_AHB_WRITE_SEL	GENMASK(13, 12)
488 
489 #define RK3568_VP0_MIPI_CTRL__DCLK_DIV2_PHASE_LOCK	BIT(5)
490 #define RK3568_VP0_MIPI_CTRL__DCLK_DIV2			BIT(4)
491 
492 #define RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN	BIT(31)
493 
494 #define RK3568_DSP_IF_POL__CFG_DONE_IMD			BIT(28)
495 
496 #define VOP2_SYS_AXI_BUS_NUM				2
497 
498 #define VOP2_CLUSTER_YUV444_10				0x12
499 
500 #define VOP2_COLOR_KEY_MASK				BIT(31)
501 
502 #define RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD		BIT(28)
503 #define RK3568_OVL_CTRL__YUV_MODE(vp)			BIT(vp)
504 
505 #define RK3568_VP_BG_MIX_CTRL__BG_DLY			GENMASK(31, 24)
506 
507 #define RK3568_OVL_PORT_SEL__SEL_PORT			GENMASK(31, 16)
508 #define RK3568_OVL_PORT_SEL__SMART1			GENMASK(31, 30)
509 #define RK3568_OVL_PORT_SEL__SMART0			GENMASK(29, 28)
510 #define RK3588_OVL_PORT_SEL__ESMART3			GENMASK(31, 30)
511 #define RK3588_OVL_PORT_SEL__ESMART2			GENMASK(29, 28)
512 #define RK3568_OVL_PORT_SEL__ESMART1			GENMASK(27, 26)
513 #define RK3568_OVL_PORT_SEL__ESMART0			GENMASK(25, 24)
514 #define RK3588_OVL_PORT_SEL__CLUSTER3			GENMASK(23, 22)
515 #define RK3588_OVL_PORT_SEL__CLUSTER2			GENMASK(21, 20)
516 #define RK3568_OVL_PORT_SEL__CLUSTER1			GENMASK(19, 18)
517 #define RK3568_OVL_PORT_SEL__CLUSTER0			GENMASK(17, 16)
518 #define RK3568_OVL_PORT_SET__PORT2_MUX			GENMASK(11, 8)
519 #define RK3568_OVL_PORT_SET__PORT1_MUX			GENMASK(7, 4)
520 #define RK3568_OVL_PORT_SET__PORT0_MUX			GENMASK(3, 0)
521 #define RK3568_OVL_LAYER_SEL__LAYER(layer, x)		((x) << ((layer) * 4))
522 
523 #define RK3568_CLUSTER_DLY_NUM__CLUSTER1_1		GENMASK(31, 24)
524 #define RK3568_CLUSTER_DLY_NUM__CLUSTER1_0		GENMASK(23, 16)
525 #define RK3568_CLUSTER_DLY_NUM__CLUSTER0_1		GENMASK(15, 8)
526 #define RK3568_CLUSTER_DLY_NUM__CLUSTER0_0		GENMASK(7, 0)
527 
528 #define RK3568_CLUSTER_WIN_CTRL0__WIN0_EN		BIT(0)
529 
530 #define RK3568_SMART_REGION0_CTRL__WIN0_EN		BIT(0)
531 
532 #define RK3568_SMART_DLY_NUM__SMART1			GENMASK(31, 24)
533 #define RK3568_SMART_DLY_NUM__SMART0			GENMASK(23, 16)
534 #define RK3568_SMART_DLY_NUM__ESMART1			GENMASK(15, 8)
535 #define RK3568_SMART_DLY_NUM__ESMART0			GENMASK(7, 0)
536 
537 #define VP_INT_DSP_HOLD_VALID	BIT(6)
538 #define VP_INT_FS_FIELD		BIT(5)
539 #define VP_INT_POST_BUF_EMPTY	BIT(4)
540 #define VP_INT_LINE_FLAG1	BIT(3)
541 #define VP_INT_LINE_FLAG0	BIT(2)
542 #define VOP2_INT_BUS_ERRPR	BIT(1)
543 #define VP_INT_FS		BIT(0)
544 
545 #define POLFLAG_DCLK_INV	BIT(3)
546 
547 enum vop2_layer_phy_id {
548 	ROCKCHIP_VOP2_CLUSTER0 = 0,
549 	ROCKCHIP_VOP2_CLUSTER1,
550 	ROCKCHIP_VOP2_ESMART0,
551 	ROCKCHIP_VOP2_ESMART1,
552 	ROCKCHIP_VOP2_SMART0,
553 	ROCKCHIP_VOP2_SMART1,
554 	ROCKCHIP_VOP2_CLUSTER2,
555 	ROCKCHIP_VOP2_CLUSTER3,
556 	ROCKCHIP_VOP2_ESMART2,
557 	ROCKCHIP_VOP2_ESMART3,
558 	ROCKCHIP_VOP2_PHY_ID_INVALID = -1,
559 };
560 
561 extern const struct component_ops vop2_component_ops;
562 
563 #endif /* _ROCKCHIP_DRM_VOP2_H */
564