1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/rman.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <machine/bus.h>
36
37 #include <dev/fdt/simplebus.h>
38
39 #include <dev/ofw/ofw_bus.h>
40 #include <dev/ofw/ofw_bus_subr.h>
41
42 #include <dev/clk/clk.h>
43 #include <dev/clk/clk_div.h>
44 #include <dev/clk/clk_fixed.h>
45 #include <dev/clk/clk_mux.h>
46
47 #include <dev/clk/rockchip/rk_cru.h>
48
49 #include <dt-bindings/clock/rk3288-cru.h>
50
51 #define CRU_SOFTRST_SIZE 12
52
53 #define CRU_APLL_CON(x) (0x000 + (x) * 0x4)
54 #define CRU_DPLL_CON(x) (0x010 + (x) * 0x4)
55 #define CRU_CPLL_CON(x) (0x020 + (x) * 0x4)
56 #define CRU_GPLL_CON(x) (0x030 + (x) * 0x4)
57 #define CRU_NPLL_CON(x) (0x040 + (x) * 0x4)
58 #define CRU_MODE_CON 0x050
59 #define CRU_CLKSEL_CON(x) (0x060 + (x) * 0x4)
60 #define CRU_CLKGATE_CON(x) (0x160 + (x) * 0x4)
61 #define CRU_GLB_SRST_FST_VALUE 0x1b0
62 #define CRU_GLB_SRST_SND_VALUE 0x1b4
63 #define CRU_SOFTRST_CON(x) (0x1b8 + (x) * 0x4)
64 #define CRU_MISC_CON 0x1e8
65 #define CRU_GLB_CNT_TH 0x1ec
66 #define CRU_GLB_RST_CON 0x1f0
67 #define CRU_GLB_RST_ST 0x1f8
68 #define CRU_SDMMC_CON0 0x200
69 #define CRU_SDMMC_CON1 0x204
70 #define CRU_SDIO0_CON0 0x208
71 #define CRU_SDIO0_CON1 0x20c
72 #define CRU_SDIO1_CON0 0x210
73 #define CRU_SDIO1_CON1 0x214
74 #define CRU_EMMC_CON0 0x218
75 #define CRU_EMMC_CON1 0x21c
76
77 /* GATES */
78 #define GATE(_idx, _clkname, _pname, _o, _s) \
79 { \
80 .id = _idx, \
81 .name = _clkname, \
82 .parent_name = _pname, \
83 .offset = CRU_CLKGATE_CON(_o), \
84 .shift = _s, \
85 }
86
87 static struct rk_cru_gate rk3288_gates[] = {
88 /* CRU_CLKGATE_CON0 */
89 GATE(0, "sclk_acc_efuse", "xin24m", 0, 12),
90 GATE(0, "cpll_aclk_cpu", "cpll", 0, 11),
91 GATE(0, "gpll_aclk_cpu", "gpll", 0, 10),
92 GATE(0, "gpll_ddr", "gpll", 0, 9),
93 GATE(0, "dpll_ddr", "dpll", 0, 8),
94 GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", 0, 7),
95 GATE(PCLK_CPU, "pclk_cpu", "pclk_cpu_s", 0, 5),
96 GATE(HCLK_CPU, "hclk_cpu", "hclk_cpu_s", 0, 4),
97 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0, 3),
98 GATE(0, "gpll_core", "gpll", 0, 2),
99 GATE(0, "apll_core", "apll", 0, 1),
100
101
102 /* CRU_CLKGATE_CON1 */
103 GATE(0, "uart3_frac", "uart3_frac_s", 1, 15),
104 GATE(0, "uart3_src", "uart3_src_s", 1, 14),
105 GATE(0, "uart2_frac", "uart2_frac_s", 1, 13),
106 GATE(0, "uart2_src", "uart2_src_s", 1, 12),
107 GATE(0, "uart1_frac", "uart1_frac_s", 1, 11),
108 GATE(0, "uart1_src", "uart1_src_s", 1, 10),
109 GATE(0, "uart0_frac", "uart0_frac_s", 1, 9),
110 GATE(0, "uart0_src", "uart0_src_s", 1, 8),
111 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 1, 5),
112 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 1, 4),
113 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 1, 3),
114 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 1, 2),
115 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 1, 1),
116 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 1, 0),
117
118 /* CRU_CLKGATE_CON2 */
119 GATE(0, "uart4_frac", "uart4_frac_s", 2, 13),
120 GATE(0, "uart4_src", "uart4_src_s", 2, 12),
121 GATE(SCLK_SPI2, "sclk_spi2", "sclk_spi2_s", 2, 11),
122 GATE(SCLK_SPI1, "sclk_spi1", "sclk_spi1_s", 2, 10),
123 GATE(SCLK_SPI0, "sclk_spi0", "sclk_spi0_s", 2, 9),
124 GATE(SCLK_SARADC, "sclk_saradc", "sclk_saradc_s", 2, 8),
125 GATE(SCLK_TSADC, "sclk_tsadc", "sclk_tsadc_s", 2, 7),
126 GATE(0, "hsadc_src", "hsadc_src_s", 2, 6),
127 GATE(0, "mac_pll_src", "mac_pll_src_s", 2, 5),
128 GATE(PCLK_PERI, "pclk_peri", "pclk_peri_s", 2, 3),
129 GATE(HCLK_PERI, "hclk_peri", "hclk_peri_s", 2, 2),
130 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 2, 1),
131 GATE(0, "aclk_peri_src", "aclk_peri_src_s", 2, 0),
132
133 /* CRU_CLKGATE_CON3 */
134 GATE(SCLK_ISP_JPE, "sclk_isp_jpe", "sclk_isp_jpe_s", 3, 15),
135 GATE(SCLK_ISP, "sclk_isp", "sclk_isp_s", 3, 14),
136 GATE(SCLK_EDP, "sclk_edp", "sclk_edp_s", 3, 13),
137 GATE(SCLK_EDP_24M, "sclk_edp_24m", "sclk_edp_24m_s", 3, 12),
138 GATE(0, "aclk_vdpu", "aclk_vdpu_s", 3, 11),
139 GATE(0, "hclk_vcodec_pre", "hclk_vcodec_pre_s", 3, 10),
140 GATE(0, "aclk_vepu", "aclk_vepu_s", 3, 9),
141 GATE(0, "vip_src", "vip_src_s", 3, 7),
142 /* 6 - Not in TRM, sclk_hsicphy480m in Linux */
143 GATE(0, "aclk_rga_pre", "aclk_rga_pre_s", 3, 5),
144 GATE(SCLK_RGA, "sclk_rga", "sclk_rga_s", 3, 4),
145 GATE(DCLK_VOP1, "dclk_vop1", "dclk_vop1_s", 3, 3),
146 GATE(0, "aclk_vio1", "aclk_vio1_s", 3, 2),
147 GATE(DCLK_VOP0, "dclk_vop0", "dclk_vop0_s", 3, 1),
148 GATE(0, "aclk_vio0", "aclk_vio0_s", 3, 0),
149
150 /* CRU_CLKGATE_CON4 */
151 /* 15 - Test clock generator */
152 GATE(0, "jtag", "ext_jtag", 4, 14),
153 GATE(0, "sclk_ddrphy1", "ddrphy", 4, 13),
154 GATE(0, "sclk_ddrphy0", "ddrphy", 4, 12),
155 GATE(0, "sclk_tspout", "sclk_tspout_s", 4, 11),
156 GATE(0, "sclk_tsp", "sclk_tsp_s", 4, 10),
157 GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", 4, 9),
158 GATE(0, "spdif_8ch_frac", "spdif_8ch_frac_s", 4, 8),
159 GATE(0, "spdif_8ch_pre", "spdif_8ch_pre_s", 4, 7),
160 GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", 4, 6),
161 GATE(0, "spdif_frac", "spdif_frac_s", 4, 5),
162 GATE(0, "spdif_pre", "spdif_pre_s", 4, 4),
163 GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", 4, 3),
164 GATE(0, "i2s_frac", "i2s_frac_s", 4, 2),
165 GATE(0, "i2s_src", "i2s_src_s", 4, 1),
166 GATE(SCLK_I2S0_OUT, "i2s0_clkout", "i2s0_clkout_s", 4, 1),
167
168 /* CRU_CLKGATE_CON5 */
169 GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 5, 15),
170 GATE(SCLK_USBPHY480M_SRC, "usbphy480m_src", "usbphy480m_src_s", 5, 14),
171 GATE(SCLK_PS2C, "sclk_ps2c", "xin24m", 5, 13),
172 GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 5, 12),
173 GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 5, 11),
174 GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 5, 10),
175 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 5, 9),
176 GATE(0, "pclk_pd_pmu", "pclk_pd_pmu_s", 5, 8),
177 GATE(SCLK_GPU, "sclk_gpu", "sclk_gpu_s", 5, 7),
178 GATE(SCLK_NANDC1, "sclk_nandc1", "sclk_nandc1_s", 5, 6),
179 GATE(SCLK_NANDC0, "sclk_nandc0", "sclk_nandc0_s", 5, 5),
180 GATE(SCLK_CRYPTO, "crypto", "crypto_s", 5, 4),
181 GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 5, 3),
182 GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 5, 2),
183 GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 5, 1),
184 GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 5, 0),
185
186
187 /* CRU_CLKGATE_CON6 */
188 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 6, 15),
189 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 6, 14),
190 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 6, 13),
191 GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 6, 12),
192 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 6, 11),
193 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 6, 9),
194 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 6, 8),
195 GATE(PCLK_PS2C, "pclk_ps2c", "pclk_peri", 6, 7),
196 GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 6, 6),
197 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 6, 5),
198 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 6, 4),
199 GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 6, 3),
200 GATE(0, "aclk_peri_axi_matrix", "aclk_peri", 6, 2),
201 GATE(0, "pclk_peri_matrix", "pclk_peri", 6, 1),
202 GATE(0, "hclk_peri_matrix", "hclk_peri", 6, 0),
203
204
205 /* CRU_CLKGATE_CON7 */
206 GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_peri", 7, 15),
207 GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 7, 14),
208 GATE(0, "hclk_mem", "hclk_peri", 7, 13),
209 GATE(0, "hclk_emem", "hclk_peri", 7, 12),
210 GATE(0, "aclk_peri_niu", "aclk_peri", 7, 11),
211 GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", 7, 10),
212 GATE(0, "hclk_usb_peri", "hclk_peri", 7, 9),
213 /* 8 - Not in TRM - hclk_hsic in Linux */
214 GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", 7, 7),
215 GATE(HCLK_USBHOST0, "hclk_host0", "hclk_peri", 7, 6),
216 GATE(0, "pmu_hclk_otg0", "hclk_peri", 7, 5),
217 GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", 7, 4),
218 GATE(PCLK_SIM, "pclk_sim", "pclk_peri", 7, 3),
219 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 7, 2),
220 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 7, 1),
221 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri", 7, 0),
222
223 /* CRU_CLKGATE_CON8 */
224 GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", 8, 12),
225 /* 11 - 9 27m_tsp, hsadc_1_tsp, hsadc_1_tsp */
226 GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 8, 8),
227 GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 8, 7),
228 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 8, 6),
229 GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_peri", 8, 5),
230 GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 8, 4),
231 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 8, 3),
232 GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 8, 2),
233 GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 8, 1),
234 GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 8, 0),
235
236 /* CRU_CLKGATE_CON9 */
237 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 9, 1),
238 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 9, 0),
239
240 /* CRU_CLKGATE_CON10 */
241 GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 10, 15),
242 GATE(PCLK_DDRUPCTL0, "pclk_ddrupctl0", "pclk_cpu", 10, 14),
243 GATE(0, "aclk_strc_sys", "aclk_cpu", 10, 13),
244 GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_cpu", 10, 12),
245 GATE(HCLK_SPDIF8CH, "hclk_spdif_8ch", "hclk_cpu", 10, 11),
246 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 10, 10),
247 GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 10, 9),
248 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 10, 8),
249 GATE(0, "sclk_intmem2", "aclk_cpu", 10, 7),
250 GATE(0, "sclk_intmem1", "aclk_cpu", 10, 6),
251 GATE(0, "sclk_intmem0", "aclk_cpu", 10, 5),
252 GATE(0, "aclk_intmem", "aclk_cpu", 10, 4),
253 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 10, 3),
254 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 10, 2),
255 GATE(PCLK_TIMER, "pclk_timer", "pclk_cpu", 10, 1),
256 GATE(PCLK_PWM, "pclk_pwm", "pclk_cpu", 10, 0),
257
258 /* CRU_CLKGATE_CON11 */
259 GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", 11, 11),
260 GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 11, 10),
261 GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 11, 9),
262 GATE(0, "aclk_ccp", "aclk_cpu", 11, 8),
263 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 11, 7),
264 GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", 11, 6),
265 GATE(0, "nclk_ddrupctl1", "ddrphy", 11, 5),
266 GATE(0, "nclk_ddrupctl0", "ddrphy", 11, 4),
267 GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 11, 3),
268 GATE(PCLK_EFUSE1024, "pclk_efuse_1024", "pclk_cpu", 11, 2),
269 GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 11, 1),
270 GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 11, 0),
271
272 /* CRU_CLKGATE_CON12 */
273 GATE(0, "pclk_core_niu", "pclk_dbg_pre", 12, 11),
274 GATE(0, "cs_dbg", "pclk_dbg_pre", 12, 10),
275 GATE(0, "pclk_dbg", "pclk_dbg_pre", 12, 9),
276 GATE(0, "armcore0", "armcore0_s", 12, 8),
277 GATE(0, "armcore1", "armcore1_s", 12, 7),
278 GATE(0, "armcore2", "armcore2_s", 12, 6),
279 GATE(0, "armcore3", "armcore3_s", 12, 5),
280 GATE(0, "l2ram", "l2ram_s", 12, 4),
281 GATE(0, "aclk_core_m0", "aclk_core_m0_s", 12, 3),
282 GATE(0, "aclk_core_mp", "aclk_core_mp_s", 12, 2),
283 GATE(0, "atclk", "atclk_s", 12, 1),
284 GATE(0, "pclk_dbg_pre", "pclk_dbg_pre_s", 12, 0),
285
286 /* CRU_CLKGATE_CON13 */
287 GATE(SCLK_HEVC_CORE, "sclk_hevc_core", "sclk_hevc_core_s", 13, 15),
288 GATE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", "sclk_hevc_cabac_s", 13, 14),
289 GATE(ACLK_HEVC, "aclk_hevc", "aclk_hevc_s", 13, 13),
290 GATE(0, "wii", "wifi_frac_s", 13, 12),
291 GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 13, 11),
292 GATE(SCLK_LCDC_PWM0, "sclk_lcdc_pwm0", "xin24m", 13, 10),
293 /* 9 - Not in TRM - hsicphy12m_xin12m in Linux */
294 GATE(0, "c2c_host", "aclk_cpu_src", 13, 8),
295 GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", 13, 7),
296 GATE(SCLK_OTGPHY2, "sclk_otgphy2", "xin24m", 13, 6),
297 GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", 13, 5),
298 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", 13, 4),
299 GATE(SCLK_EMMC, "sclk_emmc", "sclk_emmc_s", 13, 3),
300 GATE(SCLK_SDIO1, "sclk_sdio1", "sclk_sdio1_s", 13, 2),
301 GATE(SCLK_SDIO0, "sclk_sdio0", "sclk_sdio0_s", 13, 1),
302 GATE(SCLK_SDMMC, "sclk_sdmmc", "sclk_sdmmc_s", 13, 0),
303
304 /* CRU_CLKGATE_CON14 */
305 GATE(0, "pclk_alive_niu", "pclk_pd_alive", 14, 12),
306 GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", 14, 11),
307 GATE(PCLK_GPIO8, "pclk_gpio8", "pclk_pd_alive", 14, 8),
308 GATE(PCLK_GPIO7, "pclk_gpio7", "pclk_pd_alive", 14, 7),
309 GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 14, 6),
310 GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 14, 5),
311 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 14, 4),
312 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 14, 3),
313 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 14, 2),
314 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 14, 1),
315
316 /* CRU_CLKGATE_CON15*/
317 GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 15, 15),
318 GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 15, 14),
319 GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 15, 13),
320 GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 15, 12),
321 GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 15, 11),
322 GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 15, 10),
323 GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio",15, 9),
324 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 15, 8),
325 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 15, 7),
326 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 15, 6),
327 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 15, 5),
328 /* 4 - aclk_lcdc_iep */
329 GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 15, 3),
330 GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 15, 2),
331 GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 15, 1),
332 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 15, 0),
333
334 /* CRU_CLKGATE_CON16 */
335 GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", 16, 11),
336 GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", 16, 10),
337 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 16, 9),
338 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", 16, 8),
339 GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 16, 7),
340 GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 16, 6),
341 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 16, 5),
342 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 16, 4),
343 GATE(PCLK_ISP_IN, "pclk_isp_in", "ext_isp", 16, 3),
344 GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 16, 2),
345 GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 16, 1),
346 GATE(0, "pclk_vip_in", "ext_vip", 16, 0),
347
348 /* CRU_CLKGATE_CON17 */
349 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 17, 4),
350 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", 17, 3),
351 GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", 17, 2),
352 GATE(0, "pclk_intmem1", "pclk_pd_pmu", 17, 1),
353 GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", 17, 0),
354
355 /* CRU_CLKGATE_CON18 */
356 GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 18, 0),
357 };
358
359 /*
360 * PLLs
361 */
362 #define PLL_RATE_BA(_hz, _ref, _fb, _post, _ba) \
363 { \
364 .freq = _hz, \
365 .refdiv = _ref, \
366 .fbdiv = _fb, \
367 .postdiv1 = _post, \
368 .bwadj = _ba, \
369 }
370
371 #define PLL_RATE(_mhz, _ref, _fb, _post) \
372 PLL_RATE_BA(_mhz, _ref, _fb, _post, ((_fb < 2) ? 1 : _fb >> 1))
373
374 static struct rk_clk_pll_rate rk3288_pll_rates[] = {
375 PLL_RATE( 2208000000, 1, 92, 1),
376 PLL_RATE( 2184000000, 1, 91, 1),
377 PLL_RATE( 2160000000, 1, 90, 1),
378 PLL_RATE( 2136000000, 1, 89, 1),
379 PLL_RATE( 2112000000, 1, 88, 1),
380 PLL_RATE( 2088000000, 1, 87, 1),
381 PLL_RATE( 2064000000, 1, 86, 1),
382 PLL_RATE( 2040000000, 1, 85, 1),
383 PLL_RATE( 2016000000, 1, 84, 1),
384 PLL_RATE( 1992000000, 1, 83, 1),
385 PLL_RATE( 1968000000, 1, 82, 1),
386 PLL_RATE( 1944000000, 1, 81, 1),
387 PLL_RATE( 1920000000, 1, 80, 1),
388 PLL_RATE( 1896000000, 1, 79, 1),
389 PLL_RATE( 1872000000, 1, 78, 1),
390 PLL_RATE( 1848000000, 1, 77, 1),
391 PLL_RATE( 1824000000, 1, 76, 1),
392 PLL_RATE( 1800000000, 1, 75, 1),
393 PLL_RATE( 1776000000, 1, 74, 1),
394 PLL_RATE( 1752000000, 1, 73, 1),
395 PLL_RATE( 1728000000, 1, 72, 1),
396 PLL_RATE( 1704000000, 1, 71, 1),
397 PLL_RATE( 1680000000, 1, 70, 1),
398 PLL_RATE( 1656000000, 1, 69, 1),
399 PLL_RATE( 1632000000, 1, 68, 1),
400 PLL_RATE( 1608000000, 1, 67, 1),
401 PLL_RATE( 1560000000, 1, 65, 1),
402 PLL_RATE( 1512000000, 1, 63, 1),
403 PLL_RATE( 1488000000, 1, 62, 1),
404 PLL_RATE( 1464000000, 1, 61, 1),
405 PLL_RATE( 1440000000, 1, 60, 1),
406 PLL_RATE( 1416000000, 1, 59, 1),
407 PLL_RATE( 1392000000, 1, 58, 1),
408 PLL_RATE( 1368000000, 1, 57, 1),
409 PLL_RATE( 1344000000, 1, 56, 1),
410 PLL_RATE( 1320000000, 1, 55, 1),
411 PLL_RATE( 1296000000, 1, 54, 1),
412 PLL_RATE( 1272000000, 1, 53, 1),
413 PLL_RATE( 1248000000, 1, 52, 1),
414 PLL_RATE( 1224000000, 1, 51, 1),
415 PLL_RATE( 1200000000, 1, 50, 1),
416 PLL_RATE( 1188000000, 2, 99, 1),
417 PLL_RATE( 1176000000, 1, 49, 1),
418 PLL_RATE( 1128000000, 1, 47, 1),
419 PLL_RATE( 1104000000, 1, 46, 1),
420 PLL_RATE( 1008000000, 1, 84, 2),
421 PLL_RATE( 912000000, 1, 76, 2),
422 PLL_RATE( 891000000, 8, 594, 2),
423 PLL_RATE( 888000000, 1, 74, 2),
424 PLL_RATE( 816000000, 1, 68, 2),
425 PLL_RATE( 798000000, 2, 133, 2),
426 PLL_RATE( 792000000, 1, 66, 2),
427 PLL_RATE( 768000000, 1, 64, 2),
428 PLL_RATE( 742500000, 8, 495, 2),
429 PLL_RATE( 696000000, 1, 58, 2),
430 PLL_RATE_BA( 621000000, 1, 207, 8, 1),
431 PLL_RATE( 600000000, 1, 50, 2),
432 PLL_RATE_BA( 594000000, 1, 198, 8, 1),
433 PLL_RATE( 552000000, 1, 46, 2),
434 PLL_RATE( 504000000, 1, 84, 4),
435 PLL_RATE( 500000000, 3, 125, 2),
436 PLL_RATE( 456000000, 1, 76, 4),
437 PLL_RATE( 428000000, 1, 107, 6),
438 PLL_RATE( 408000000, 1, 68, 4),
439 PLL_RATE( 400000000, 3, 100, 2),
440 PLL_RATE_BA( 394000000, 1, 197, 12, 1),
441 PLL_RATE( 384000000, 2, 128, 4),
442 PLL_RATE( 360000000, 1, 60, 4),
443 PLL_RATE_BA( 356000000, 1, 178, 12, 1),
444 PLL_RATE_BA( 324000000, 1, 189, 14, 1),
445 PLL_RATE( 312000000, 1, 52, 4),
446 PLL_RATE_BA( 308000000, 1, 154, 12, 1),
447 PLL_RATE_BA( 303000000, 1, 202, 16, 1),
448 PLL_RATE( 300000000, 1, 75, 6),
449 PLL_RATE_BA( 297750000, 2, 397, 16, 1),
450 PLL_RATE_BA( 293250000, 2, 391, 16, 1),
451 PLL_RATE_BA( 292500000, 1, 195, 16, 1),
452 PLL_RATE( 273600000, 1, 114, 10),
453 PLL_RATE_BA( 273000000, 1, 182, 16, 1),
454 PLL_RATE_BA( 270000000, 1, 180, 16, 1),
455 PLL_RATE_BA( 266250000, 2, 355, 16, 1),
456 PLL_RATE_BA( 256500000, 1, 171, 16, 1),
457 PLL_RATE( 252000000, 1, 84, 8),
458 PLL_RATE_BA( 250500000, 1, 167, 16, 1),
459 PLL_RATE_BA( 243428571, 1, 142, 14, 1),
460 PLL_RATE( 238000000, 1, 119, 12),
461 PLL_RATE_BA( 219750000, 2, 293, 16, 1),
462 PLL_RATE_BA( 216000000, 1, 144, 16, 1),
463 PLL_RATE_BA( 213000000, 1, 142, 16, 1),
464 PLL_RATE( 195428571, 1, 114, 14),
465 PLL_RATE( 160000000, 1, 80, 12),
466 PLL_RATE( 157500000, 1, 105, 16),
467 PLL_RATE( 126000000, 1, 84, 16),
468 PLL_RATE( 48000000, 1, 64, 32),
469 {},
470 };
471
472 static struct rk_clk_armclk_rates rk3288_armclk_rates[] = {
473 { 1800000000, 1},
474 { 1704000000, 1},
475 { 1608000000, 1},
476 { 1512000000, 1},
477 { 1416000000, 1},
478 { 1200000000, 1},
479 { 1008000000, 1},
480 { 816000000, 1},
481 { 696000000, 1},
482 { 600000000, 1},
483 { 408000000, 1},
484 { 312000000, 1},
485 { 216000000, 1},
486 { 126000000, 1},
487 };
488
489 /* Standard PLL. */
490 #define PLL(_id, _name, _base, _shift) \
491 { \
492 .type = RK3066_CLK_PLL, \
493 .clk.pll = &(struct rk_clk_pll_def) { \
494 .clkdef.id = _id, \
495 .clkdef.name = _name, \
496 .clkdef.parent_names = pll_src_p, \
497 .clkdef.parent_cnt = nitems(pll_src_p), \
498 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
499 .base_offset = _base, \
500 .mode_reg = CRU_MODE_CON, \
501 .mode_shift = _shift, \
502 .rates = rk3288_pll_rates, \
503 }, \
504 }
505
506 #define ARMDIV(_id, _name, _pn, _r, _o, _ds, _dw, _ms, _mw, _mp, _ap) \
507 { \
508 .type = RK_CLK_ARMCLK, \
509 .clk.armclk = &(struct rk_clk_armclk_def) { \
510 .clkdef.id = _id, \
511 .clkdef.name = _name, \
512 .clkdef.parent_names = _pn, \
513 .clkdef.parent_cnt = nitems(_pn), \
514 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
515 .muxdiv_offset = CRU_CLKSEL_CON(_o), \
516 .mux_shift = _ms, \
517 .mux_width = _mw, \
518 .div_shift = _ds, \
519 .div_width = _dw, \
520 .main_parent = _mp, \
521 .alt_parent = _ap, \
522 .rates = _r, \
523 .nrates = nitems(_r), \
524 }, \
525 }
526
527 PLIST(pll_src_p) = {"xin24m", "xin24m", "xin32k"};
528 PLIST(armclk_p)= {"apll_core", "gpll_core"};
529 PLIST(ddrphy_p) = {"dpll_ddr", "gpll_ddr"};
530 PLIST(aclk_cpu_p) = {"cpll_aclk_cpu", "gpll_aclk_cpu"};
531
532 PLIST(cpll_gpll_p) = {"cpll", "gpll"};
533 PLIST(npll_cpll_gpll_p) = {"npll", "cpll", "gpll"};
534 PLIST(cpll_gpll_npll_p) = {"cpll", "gpll", "npll"};
535 PLIST(cpll_gpll_usb480m_p)= {"cpll", "gpll", "usbphy480m_src"};
536 PLIST(cpll_gpll_usb480m_npll_p) = {"cpll", "gpll", "usbphy480m_src", "npll"};
537
538 PLIST(mmc_p) = {"cpll", "gpll", "xin24m", "xin24m"};
539 PLIST(i2s_pre_p) = {"i2s_src", "i2s_frac", "ext_i2s", "xin12m"};
540 PLIST(i2s_clkout_p) = {"i2s_pre", "xin12m"};
541 PLIST(spdif_p) = {"spdif_pre", "spdif_frac", "xin12m"};
542 PLIST(spdif_8ch_p) = {"spdif_8ch_pre", "spdif_8ch_frac", "xin12m"};
543 PLIST(uart0_p) = {"uart0_src", "uart0_frac", "xin24m"};
544 PLIST(uart1_p) = {"uart1_src", "uart1_frac", "xin24m"};
545 PLIST(uart2_p) = {"uart2_src", "uart2_frac", "xin24m"};
546 PLIST(uart3_p) = {"uart3_src", "uart3_frac", "xin24m"};
547 PLIST(uart4_p) = {"uart4_src", "uart4_frac", "xin24m"};
548 PLIST(vip_out_p) = {"vip_src", "xin24m"};
549 PLIST(mac_p) = {"mac_pll_src", "ext_gmac"};
550 PLIST(hsadcout_p) = {"hsadc_src", "ext_hsadc"};
551 PLIST(edp_24m_p) = {"ext_edp_24m", "xin24m"};
552 PLIST(tspout_p) = {"cpll", "gpll", "npll", "xin27m"};
553 PLIST(wifi_p) = {"cpll", "gpll"};
554 PLIST(usbphy480m_p) = {"sclk_otgphy1_480m", "sclk_otgphy2_480m", "sclk_otgphy0_480m"};
555
556 /* PLIST(aclk_vcodec_pre_p) = {"aclk_vepu", "aclk_vdpu"}; */
557
558
559 static struct rk_clk rk3288_clks[] = {
560 /* External clocks */
561 LINK("xin24m"),
562 FRATE(0, "xin32k", 32000),
563 FRATE(0, "xin27m", 27000000),
564 FRATE(0, "ext_hsadc", 0),
565 FRATE(0, "ext_jtag", 0),
566 FRATE(0, "ext_isp", 0),
567 FRATE(0, "ext_vip", 0),
568 FRATE(0, "ext_i2s", 0),
569 FRATE(0, "ext_edp_24m", 0),
570
571 FRATE(0, "sclk_otgphy0_480m", 0),
572 FRATE(0, "sclk_otgphy1_480m", 0),
573 FRATE(0, "sclk_otgphy2_480m", 0),
574
575 FRATE(0, "aclk_vcodec_pre", 0),
576
577 /* Fixed dividers */
578 FFACT(0, "xin12m", "xin24m", 1, 2),
579 FFACT(0, "hclk_vcodec_pre_s", "aclk_vcodec_pre", 1, 4),
580
581 PLL(PLL_APLL, "apll", CRU_APLL_CON(0), 0),
582 PLL(PLL_DPLL, "dpll", CRU_DPLL_CON(0), 4),
583 PLL(PLL_CPLL, "cpll", CRU_CPLL_CON(0), 8),
584 PLL(PLL_GPLL, "gpll", CRU_GPLL_CON(0), 12),
585 PLL(PLL_NPLL, "npll", CRU_NPLL_CON(0), 14),
586
587 /* CRU_CLKSEL0_CON */
588 ARMDIV(ARMCLK, "armclk", armclk_p, rk3288_armclk_rates,
589 0, 8, 5, 15, 1, 0, 1),
590 CDIV(0, "aclk_core_mp_s", "armclk", 0,
591 0, 4, 4),
592 CDIV(0, "aclk_core_m0_s", "armclk", 0,
593 0, 0, 4),
594
595 /* CRU_CLKSEL1_CON */
596 CDIV(0, "pclk_cpu_s", "aclk_cpu_pre", 0,
597 1, 12, 3),
598 CDIV(0, "hclk_cpu_s", "aclk_cpu_pre", RK_CLK_COMPOSITE_DIV_EXP,
599 1, 8, 2),
600 COMP(0, "aclk_cpu_src", aclk_cpu_p, 0,
601 1, 3, 5, 15, 1),
602 CDIV(0, "aclk_cpu_pre", "aclk_cpu_src", 0,
603 1, 0, 3),
604
605 /* CRU_CLKSEL2_CON */
606 /* 12:8 testout_div */
607 CDIV(0, "sclk_tsadc_s", "xin32k", 0,
608 2, 0, 6),
609
610 /* CRU_CLKSEL3_CON */
611 MUX(SCLK_UART4, "sclk_uart4", uart4_p, 0,
612 3, 8, 2),
613 CDIV(0, "uart4_src_s", "uart_src", 0,
614 3, 0, 7),
615
616 /* CRU_CLKSEL4_CON */
617 MUX(0, "i2s_pre", i2s_pre_p, 0,
618 4, 8, 2),
619 MUX(0, "i2s0_clkout_s", i2s_clkout_p, 0,
620 4, 12, 1),
621 COMP(0, "i2s_src_s", cpll_gpll_p, 0,
622 4, 0, 7, 15, 1),
623
624 /* CRU_CLKSEL5_CON */
625 MUX(0, "spdif_src", cpll_gpll_p, 0,
626 5, 15, 1),
627 MUX(0, "spdif_mux", spdif_p, 0,
628 5, 8, 2),
629 CDIV(0, "spdif_pre_s", "spdif_src", 0,
630 5, 0, 7),
631
632 /* CRU_CLKSEL6_CON */
633 COMP(0, "sclk_isp_jpe_s", cpll_gpll_npll_p, 0,
634 6, 8, 6, 14, 2),
635 COMP(0, "sclk_isp_s", cpll_gpll_npll_p, 0,
636 6, 0, 6, 6, 2),
637
638 /* CRU_CLKSEL7_CON */
639 FRACT(0, "uart4_frac_s", "uart4_src", 0,
640 7),
641
642 /* CRU_CLKSEL8_CON */
643 FRACT(0, "i2s_frac_s", "i2s_src", 0,
644 8),
645
646 /* CRU_CLKSEL9_CON */
647 FRACT(0, "spdif_frac_s", "spdif_src", 0,
648 9),
649
650 /* CRU_CLKSEL10_CON */
651 CDIV(0, "pclk_peri_s", "aclk_peri_src", RK_CLK_COMPOSITE_DIV_EXP,
652 10, 12, 2),
653 CDIV(0, "hclk_peri_s", "aclk_peri_src", RK_CLK_COMPOSITE_DIV_EXP,
654 10, 8, 2),
655 COMP(0, "aclk_peri_src_s", cpll_gpll_p, 0,
656 10, 0, 5, 15, 1),
657
658 /* CRU_CLKSEL11_CON */
659 COMP(0, "sclk_sdmmc_s", mmc_p, 0,
660 11, 0, 6, 6, 2),
661
662 /* CRU_CLKSEL12_CON */
663 COMP(0, "sclk_emmc_s", mmc_p, 0,
664 12, 8, 6, 14, 2),
665 COMP(0, "sclk_sdio0_s", mmc_p, 0,
666 12, 0, 6, 6, 2),
667
668 /* CRU_CLKSEL13_CON */
669 MUX(0, "uart_src", cpll_gpll_p, 0,
670 13, 15, 1),
671 MUX(0, "usbphy480m_src_s", usbphy480m_p, 0,
672 13, 11, 2),
673 MUX(SCLK_UART0, "sclk_uart0", uart0_p, 0,
674 13, 8, 2),
675 COMP(0, "uart0_src_s", cpll_gpll_usb480m_npll_p, 0,
676 13, 0, 7, 13, 2),
677
678 /* CRU_CLKSEL14_CON */
679 MUX(SCLK_UART1, "sclk_uart1", uart1_p, 0,
680 14, 8, 2),
681 CDIV(0, "uart1_src_s", "uart_src", 0,
682 14, 0, 7),
683
684
685 /* CRU_CLKSEL15_CON */
686 MUX(SCLK_UART2, "sclk_uart2", uart2_p, 0,
687 15, 8, 2),
688 CDIV(0, "uart2_src_s", "uart_src", 0,
689 15, 0, 7),
690
691 /* CRU_CLKSEL16_CON */
692 MUX(SCLK_UART3, "sclk_uart3", uart3_p, 0,
693 16, 8, 2),
694 CDIV(0, "uart3_src_s", "uart_src", 0,
695 16, 0, 7),
696
697 /* CRU_CLKSEL17_CON */
698 FRACT(0, "uart0_frac_s", "uart0_src", 0,
699 17),
700
701 /* CRU_CLKSEL18_CON */
702 FRACT(0, "uart1_frac_s", "uart1_src", 0,
703 18),
704
705 /* CRU_CLKSEL19_CON */
706 FRACT(0, "uart2_frac_s", "uart2_src", 0,
707 19),
708
709 /* CRU_CLKSEL20_CON */
710 FRACT(0, "uart3_frac_s", "uart3_src", 0,
711 20),
712
713 /* CRU_CLKSEL21_CON */
714 COMP(0, "mac_pll_src_s", npll_cpll_gpll_p, 0,
715 21, 8, 5, 0, 2),
716 MUX(SCLK_MAC, "mac_clk", mac_p, 0,
717 21, 4, 1),
718
719 /* CRU_CLKSEL22_CON */
720 MUX(0, "sclk_hsadc_out", hsadcout_p, 0,
721 22, 4, 1),
722 COMP(0, "hsadc_src_s", cpll_gpll_p, 0,
723 22, 8, 8, 0, 1),
724 MUX(0, "wifi_src", wifi_p, 0,
725 22, 1, 1),
726 /* 7 - inverter "sclk_hsadc", "sclk_hsadc_out" */
727
728 /* CRU_CLKSEL23_CON */
729 FRACT(0, "wifi_frac_s", "wifi_src", 0,
730 23),
731
732 /* CRU_CLKSEL24_CON */
733 CDIV(0, "sclk_saradc_s", "xin24m", 0,
734 24, 8, 8),
735
736 /* CRU_CLKSEL25_CON */
737 COMP(0, "sclk_spi1_s", cpll_gpll_p, 0,
738 25, 8, 7, 15, 1),
739 COMP(0, "sclk_spi0_s", cpll_gpll_p, 0,
740 25, 0, 7, 7, 1),
741
742 /* CRU_CLKSEL26_CON */
743 COMP(SCLK_VIP_OUT, "sclk_vip_out", vip_out_p, 0,
744 26, 9, 5, 15, 1),
745 MUX(0, "vip_src_s", cpll_gpll_p, 0,
746 26, 8, 1),
747 CDIV(0, "crypto_s", "aclk_cpu_pre", 0,
748 26, 6, 2),
749 COMP(0, "ddrphy", ddrphy_p, RK_CLK_COMPOSITE_DIV_EXP,
750 26, 0, 2, 2, 1),
751
752 /* CRU_CLKSEL27_CON */
753 COMP(0, "dclk_vop0_s", cpll_gpll_npll_p, 0,
754 27, 8, 8, 0, 2),
755
756 MUX(0, "sclk_edp_24m_s", edp_24m_p, 0,
757 28, 15, 1),
758 CDIV(0, "hclk_vio", "aclk_vio0", 0,
759 28, 8, 5),
760 COMP(0, "sclk_edp_s", cpll_gpll_npll_p, 0,
761 28, 0, 6, 6, 2),
762
763 /* CRU_CLKSEL29_CON */
764 COMP(0, "dclk_vop1_s", cpll_gpll_npll_p, 0,
765 29, 8, 8, 6, 2),
766 /* 4 - inverter "pclk_vip" "pclk_vip_in" */
767 /* 3 - inverter "pclk_isp", "pclk_isp_in" */
768
769 /* CRU_CLKSEL30_CON */
770 COMP(0, "sclk_rga_s", cpll_gpll_usb480m_p, 0,
771 30, 8, 5, 14, 2),
772 COMP(0, "aclk_rga_pre_s", cpll_gpll_usb480m_p, 0,
773 30, 0, 5, 6, 2),
774
775 /* CRU_CLKSEL31_CON */
776 COMP(0, "aclk_vio1_s", cpll_gpll_usb480m_p, 0,
777 31, 8, 5, 14, 2),
778 COMP(0, "aclk_vio0_s", cpll_gpll_usb480m_p, 0,
779 31, 0, 5, 6, 2),
780
781 /* CRU_CLKSEL32_CON */
782 COMP(0, "aclk_vdpu_s", cpll_gpll_usb480m_p, 0,
783 32, 8, 5, 14, 2),
784 COMP(0, "aclk_vepu_s", cpll_gpll_usb480m_p, 0,
785 32, 0, 5, 6, 2),
786
787 /* CRU_CLKSEL33_CON */
788 CDIV(0, "pclk_pd_alive", "gpll", 0,
789 33, 8, 5),
790 CDIV(0, "pclk_pd_pmu_s", "gpll", 0,
791 33, 0, 5),
792
793 /* CRU_CLKSEL34_CON */
794 COMP(0, "sclk_sdio1_s", mmc_p, 0,
795 34, 8, 6, 14, 2),
796 COMP(0, "sclk_gpu_s", cpll_gpll_usb480m_npll_p, 0,
797 34, 0, 5, 6, 2),
798
799 /* CRU_CLKSEL35_CON */
800 COMP(0, "sclk_tspout_s", tspout_p, 0,
801 35, 8, 5, 14, 2),
802 COMP(0, "sclk_tsp_s", cpll_gpll_npll_p, 0,
803 35, 0, 5, 6, 2),
804
805 /* CRU_CLKSEL36_CON */
806 CDIV(0, "armcore3_s", "armclk", 0,
807 36, 12, 3),
808 CDIV(0, "armcore2_s", "armclk", 0,
809 36, 8, 3),
810 CDIV(0, "armcore1_s", "armclk", 0,
811 36, 4, 3),
812 CDIV(0, "armcore0_s", "armclk", 0,
813 36, 0, 3),
814
815 /* CRU_CLKSEL37_CON */
816 CDIV(0, "pclk_dbg_pre_s", "armclk", 0,
817 37, 9, 5),
818 CDIV(0, "atclk_s", "armclk", 0,
819 37, 4, 5),
820 CDIV(0, "l2ram_s", "armclk", 0,
821 37, 0, 3),
822
823 /* CRU_CLKSEL38_CON */
824 COMP(0, "sclk_nandc1_s", cpll_gpll_p, 0,
825 38, 8, 5, 15, 1),
826 COMP(0, "sclk_nandc0_s", cpll_gpll_p, 0,
827 38, 0, 5, 7, 1),
828
829 /* CRU_CLKSEL39_CON */
830 COMP(0, "aclk_hevc_s", cpll_gpll_npll_p, 0,
831 39, 8, 5, 14, 2),
832 COMP(0, "sclk_spi2_s", cpll_gpll_p, 0,
833 39, 0, 7, 7, 1),
834
835 /* CRU_CLKSEL40_CON */
836 CDIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0,
837 40, 12, 2),
838 MUX(0, "spdif_8ch_mux", spdif_8ch_p, 0,
839 40, 8, 2),
840 CDIV(0, "spdif_8ch_pre_s", "spdif_src", 0,
841 40, 0, 7),
842
843 /* CRU_CLKSEL41_CON */
844 FRACT(0, "spdif_8ch_frac_s", "spdif_8ch_pre", 0,
845 41),
846
847 /* CRU_CLKSEL42_CON */
848 COMP(0, "sclk_hevc_core_s", cpll_gpll_npll_p, 0,
849 42, 8, 5, 14, 2),
850 COMP(0, "sclk_hevc_cabac_s", cpll_gpll_npll_p, 0,
851 42, 0, 5, 6, 2),
852 /*
853 * not yet implemented MMC clocks
854 * id name src reg
855 * SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3288_SDMMC_CON0
856 * SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3288_SDMMC_CON1,
857
858 * SCLK_SDIO0_DRV, "sdio0_drv", "sclk_sdio0", RK3288_SDIO0_CON0, 1),
859 * SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3288_SDIO0_CON1, 0),
860
861 * SCLK_SDIO1_DRV, "sdio1_drv", "sclk_sdio1", RK3288_SDIO1_CON0, 1),
862 * SCLK_SDIO1_SAMPLE, "sdio1_sample", "sclk_sdio1", RK3288_SDIO1_CON1, 0),
863
864 * SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3288_EMMC_CON0, 1),
865 * SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3288_EMMC_CON1, 0),
866 *
867 * and GFR based mux for "aclk_vcodec_pre"
868 */
869
870 };
871
872 static int
rk3288_cru_probe(device_t dev)873 rk3288_cru_probe(device_t dev)
874 {
875
876 if (!ofw_bus_status_okay(dev))
877 return (ENXIO);
878
879 if (ofw_bus_is_compatible(dev, "rockchip,rk3288-cru")) {
880 device_set_desc(dev, "Rockchip RK3288 Clock and Reset Unit");
881 return (BUS_PROBE_DEFAULT);
882 }
883
884 return (ENXIO);
885 }
886
887 static int
rk3288_cru_attach(device_t dev)888 rk3288_cru_attach(device_t dev)
889 {
890 struct rk_cru_softc *sc;
891
892 sc = device_get_softc(dev);
893 sc->dev = dev;
894
895 sc->gates = rk3288_gates;
896 sc->ngates = nitems(rk3288_gates);
897
898 sc->clks = rk3288_clks;
899 sc->nclks = nitems(rk3288_clks);
900
901 sc->reset_num = CRU_SOFTRST_SIZE * 16;
902 sc->reset_offset = CRU_SOFTRST_CON(0);
903
904 return (rk_cru_attach(dev));
905 }
906
907 static device_method_t rk3288_cru_methods[] = {
908 /* Device interface */
909 DEVMETHOD(device_probe, rk3288_cru_probe),
910 DEVMETHOD(device_attach, rk3288_cru_attach),
911
912 DEVMETHOD_END
913 };
914
915 DEFINE_CLASS_1(rk3288_cru, rk3288_cru_driver, rk3288_cru_methods,
916 sizeof(struct rk_cru_softc), rk_cru_driver);
917
918 EARLY_DRIVER_MODULE(rk3288_cru, simplebus, rk3288_cru_driver, 0, 0,
919 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE + 1);
920