1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Ethernet driver
3 *
4 * Copyright (C) 2020 Marvell.
5 *
6 */
7
8 #ifndef OTX2_TXRX_H
9 #define OTX2_TXRX_H
10
11 #include <linux/etherdevice.h>
12 #include <linux/iommu.h>
13 #include <linux/if_vlan.h>
14 #include <net/xdp.h>
15
16 #define LBK_CHAN_BASE 0x000
17 #define SDP_CHAN_BASE 0x700
18 #define CGX_CHAN_BASE 0x800
19
20 #define OTX2_DATA_ALIGN(X) ALIGN(X, OTX2_ALIGN)
21 #define OTX2_HEAD_ROOM OTX2_ALIGN
22
23 #define OTX2_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN)
24 #define OTX2_MIN_MTU 60
25
26 #define OTX2_PAGE_POOL_SZ 2048
27
28 #define OTX2_MAX_GSO_SEGS 255
29 #define OTX2_MAX_FRAGS_IN_SQE 9
30
31 #define MAX_XDP_MTU (1530 - OTX2_ETH_HLEN)
32
33 /* Rx buffer size should be in multiples of 128bytes */
34 #define RCV_FRAG_LEN1(x) \
35 ((OTX2_HEAD_ROOM + OTX2_DATA_ALIGN(x)) + \
36 OTX2_DATA_ALIGN(sizeof(struct skb_shared_info)))
37
38 /* Prefer 2048 byte buffers for better last level cache
39 * utilization or data distribution across regions.
40 */
41 #define RCV_FRAG_LEN(x) \
42 ((RCV_FRAG_LEN1(x) < 2048) ? 2048 : RCV_FRAG_LEN1(x))
43
44 #define DMA_BUFFER_LEN(x) ((x) - OTX2_HEAD_ROOM)
45
46 /* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT]
47 * is equal to this value.
48 */
49 #define CQ_CQE_THRESH_DEFAULT 10
50
51 /* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT]
52 * is nonzero and this much time elapses after that.
53 */
54 #define CQ_TIMER_THRESH_DEFAULT 1 /* 1 usec */
55 #define CQ_TIMER_THRESH_MAX 25 /* 25 usec */
56
57 /* Min number of CQs (of the ones mapped to this CINT)
58 * with valid CQEs.
59 */
60 #define CQ_QCOUNT_DEFAULT 1
61
62 #define CQ_OP_STAT_OP_ERR 63
63 #define CQ_OP_STAT_CQ_ERR 46
64
65 /* Packet mark mask */
66 #define OTX2_RX_MATCH_ID_MASK 0x0000ffff
67
68 struct queue_stats {
69 u64 bytes;
70 u64 pkts;
71 };
72
73 struct otx2_rcv_queue {
74 struct queue_stats stats;
75 };
76
77 struct sg_list {
78 u16 num_segs;
79 u64 skb;
80 u64 size[OTX2_MAX_FRAGS_IN_SQE];
81 u64 dma_addr[OTX2_MAX_FRAGS_IN_SQE];
82 };
83
84 struct otx2_snd_queue {
85 u8 aura_id;
86 u16 head;
87 u16 cons_head;
88 u16 sqe_size;
89 u32 sqe_cnt;
90 u16 num_sqbs;
91 u16 sqe_thresh;
92 u8 sqe_per_sqb;
93 u64 io_addr;
94 u64 *aura_fc_addr;
95 u64 *lmt_addr;
96 void *sqe_base;
97 struct qmem *sqe;
98 struct qmem *tso_hdrs;
99 struct sg_list *sg;
100 struct qmem *timestamps;
101 struct queue_stats stats;
102 u16 sqb_count;
103 u64 *sqb_ptrs;
104 } ____cacheline_aligned_in_smp;
105
106 enum cq_type {
107 CQ_RX,
108 CQ_TX,
109 CQ_XDP,
110 CQ_QOS,
111 CQS_PER_CINT = 4, /* RQ + SQ + XDP + QOS_SQ */
112 };
113
114 struct otx2_cq_poll {
115 void *dev;
116 #define CINT_INVALID_CQ 255
117 u8 cint_idx;
118 u8 cq_ids[CQS_PER_CINT];
119 struct dim dim;
120 struct napi_struct napi;
121 };
122
123 struct otx2_pool {
124 struct qmem *stack;
125 struct qmem *fc_addr;
126 struct page_pool *page_pool;
127 u16 rbsize;
128 };
129
130 struct otx2_cq_queue {
131 u8 cq_idx;
132 u8 cq_type;
133 u8 cint_idx; /* CQ interrupt id */
134 u8 refill_task_sched;
135 u16 cqe_size;
136 u16 pool_ptrs;
137 u32 cqe_cnt;
138 u32 cq_head;
139 u32 cq_tail;
140 u32 pend_cqe;
141 void *cqe_base;
142 struct qmem *cqe;
143 struct otx2_pool *rbpool;
144 struct xdp_rxq_info xdp_rxq;
145 } ____cacheline_aligned_in_smp;
146
147 struct otx2_qset {
148 u32 rqe_cnt;
149 u32 sqe_cnt; /* Keep these two at top */
150 #define OTX2_MAX_CQ_CNT 64
151 u16 cq_cnt;
152 u16 xqe_size;
153 struct otx2_pool *pool;
154 struct otx2_cq_poll *napi;
155 struct otx2_cq_queue *cq;
156 struct otx2_snd_queue *sq;
157 struct otx2_rcv_queue *rq;
158 };
159
160 /* Translate IOVA to physical address */
otx2_iova_to_phys(void * iommu_domain,dma_addr_t dma_addr)161 static inline u64 otx2_iova_to_phys(void *iommu_domain, dma_addr_t dma_addr)
162 {
163 /* Translation is installed only when IOMMU is present */
164 if (likely(iommu_domain))
165 return iommu_iova_to_phys(iommu_domain, dma_addr);
166 return dma_addr;
167 }
168
169 int otx2_napi_handler(struct napi_struct *napi, int budget);
170 bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq,
171 struct sk_buff *skb, u16 qidx);
172 void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq,
173 int size, int qidx);
174 void otx2_sqe_flush(void *dev, struct otx2_snd_queue *sq,
175 int size, int qidx);
176 int otx2_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq);
177 int cn10k_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq);
178 #endif /* OTX2_TXRX_H */
179