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Searched defs:CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsid.h2431 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2378 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L macro
H A Dgfx_7_2_sh_mask.h1181 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000 macro
H A Dgfx_8_1_sh_mask.h2033 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000 macro
H A Dgfx_8_0_sh_mask.h1509 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11010 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h12487 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h12291 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK … macro
H A Dgc_9_4_3_sh_mask.h14016 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK … macro
H A Dgc_9_4_2_sh_mask.h2307 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK … macro
H A Dgc_11_5_0_sh_mask.h12236 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK … macro
H A Dgc_11_0_0_sh_mask.h15420 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK … macro
H A Dgc_12_0_0_sh_mask.h11856 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h17951 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h17575 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h16215 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK … macro