1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright (c) 2011 by Delphix. All rights reserved. 24 */ 25 /* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 */ 29 /* 30 * Copyright 2018 Joyent, Inc. 31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> 32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net> 34 * Copyright 2018 Nexenta Systems, Inc. 35 */ 36 37 #ifndef _SYS_X86_ARCHEXT_H 38 #define _SYS_X86_ARCHEXT_H 39 40 #if !defined(_ASM) 41 #include <sys/regset.h> 42 #include <sys/processor.h> 43 #include <vm/seg_enum.h> 44 #include <vm/page.h> 45 #endif /* _ASM */ 46 47 #ifdef __cplusplus 48 extern "C" { 49 #endif 50 51 /* 52 * cpuid instruction feature flags in %edx (standard function 1) 53 */ 54 55 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 56 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 57 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 58 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 59 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 60 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 61 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 62 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 63 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 64 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 65 /* 0x400 - reserved */ 66 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 67 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 68 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 69 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 70 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 71 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 72 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 73 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 74 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 75 /* 0x100000 - reserved */ 76 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 77 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 78 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 79 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 80 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 81 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 82 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 83 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 84 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 85 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 86 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 87 88 #define FMT_CPUID_INTC_EDX \ 89 "\20" \ 90 "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr" \ 91 "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat" \ 92 "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \ 93 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 94 95 /* 96 * cpuid instruction feature flags in %ecx (standard function 1) 97 */ 98 99 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 100 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 101 #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */ 102 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 103 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 104 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 105 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 106 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 107 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 108 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 109 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 110 /* 0x00000800 - reserved */ 111 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */ 112 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 113 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 114 #define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 115 /* 0x00010000 - reserved */ 116 #define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */ 117 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 118 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 119 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 120 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */ 121 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 122 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 123 #define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */ 124 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 125 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ 126 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ 127 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */ 128 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */ 129 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */ 130 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */ 131 132 #define FMT_CPUID_INTC_ECX \ 133 "\20" \ 134 "\37rdrand\36f16c\35avx\34osxsav\33xsave" \ 135 "\32aes" \ 136 "\30popcnt\27movbe\26x2apic\25sse4.2\24sse4.1\23dca" \ 137 "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \ 138 "\10est\7smx\6vmx\5dscpl\4mon\2pclmulqdq\1sse3" 139 140 /* 141 * cpuid instruction feature flags in %edx (extended function 0x80000001) 142 */ 143 144 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 145 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 146 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 147 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 148 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 149 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 150 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 151 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 152 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 153 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 154 /* 0x00000400 - sysc on K6m6 */ 155 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 156 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 157 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 158 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 159 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 160 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 161 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 162 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 163 /* 0x00040000 - reserved */ 164 /* 0x00080000 - reserved */ 165 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 166 /* 0x00200000 - reserved */ 167 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 168 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 169 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 170 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 171 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 172 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 173 /* 0x10000000 - reserved */ 174 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 175 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 176 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 177 178 #define FMT_CPUID_AMD_EDX \ 179 "\20" \ 180 "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \ 181 "\30mmx\27mmxext\25nx\22pse\21pat" \ 182 "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \ 183 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 184 185 /* 186 * AMD extended function 0x80000001 %ecx 187 */ 188 189 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 190 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 191 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 192 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 193 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 194 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 195 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 196 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 197 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 198 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 199 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 200 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: Extended AVX */ 201 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 202 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 203 /* 0x00004000 - reserved */ 204 #define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */ 205 #define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */ 206 /* 0x00020000 - reserved */ 207 /* 0x00040000 - reserved */ 208 #define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */ 209 /* 0x00100000 - reserved */ 210 #define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */ 211 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */ 212 #define CPUID_AMD_ECX_PCEC 0x00800000 /* AMD: Core ext perf counter */ 213 214 #define FMT_CPUID_AMD_ECX \ 215 "\20" \ 216 "\22topoext" \ 217 "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas" \ 218 "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64" 219 220 /* 221 * Intel now seems to have claimed part of the "extended" function 222 * space that we previously for non-Intel implementors to use. 223 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 224 * is available in long mode i.e. what AMD indicate using bit 0. 225 * On the other hand, everything else is labelled as reserved. 226 */ 227 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 228 229 /* 230 * Intel also uses cpuid leaf 7 to have additional instructions and features. 231 * Like some other leaves, but unlike the current ones we care about, it 232 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal 233 * with the potential use of additional sub-leaves in the future, we now 234 * specifically label the EBX features with their leaf and sub-leaf. 235 */ 236 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */ 237 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */ 238 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */ 239 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */ 240 #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */ 241 #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */ 242 #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */ 243 244 #define REG_PAT 0x277 245 #define REG_TSC 0x10 /* timestamp counter */ 246 #define REG_APIC_BASE_MSR 0x1b 247 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 248 249 #if !defined(__xpv) 250 /* 251 * AMD C1E 252 */ 253 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 254 #define AMD_ACTONCMPHALT_SHIFT 27 255 #define AMD_ACTONCMPHALT_MASK 3 256 #endif 257 258 #define MSR_DEBUGCTL 0x1d9 259 260 #define DEBUGCTL_LBR 0x01 261 #define DEBUGCTL_BTF 0x02 262 263 /* Intel P6, AMD */ 264 #define MSR_LBR_FROM 0x1db 265 #define MSR_LBR_TO 0x1dc 266 #define MSR_LEX_FROM 0x1dd 267 #define MSR_LEX_TO 0x1de 268 269 /* Intel P4 (pre-Prescott, non P4 M) */ 270 #define MSR_P4_LBSTK_TOS 0x1da 271 #define MSR_P4_LBSTK_0 0x1db 272 #define MSR_P4_LBSTK_1 0x1dc 273 #define MSR_P4_LBSTK_2 0x1dd 274 #define MSR_P4_LBSTK_3 0x1de 275 276 /* Intel Pentium M */ 277 #define MSR_P6M_LBSTK_TOS 0x1c9 278 #define MSR_P6M_LBSTK_0 0x040 279 #define MSR_P6M_LBSTK_1 0x041 280 #define MSR_P6M_LBSTK_2 0x042 281 #define MSR_P6M_LBSTK_3 0x043 282 #define MSR_P6M_LBSTK_4 0x044 283 #define MSR_P6M_LBSTK_5 0x045 284 #define MSR_P6M_LBSTK_6 0x046 285 #define MSR_P6M_LBSTK_7 0x047 286 287 /* Intel P4 (Prescott) */ 288 #define MSR_PRP4_LBSTK_TOS 0x1da 289 #define MSR_PRP4_LBSTK_FROM_0 0x680 290 #define MSR_PRP4_LBSTK_FROM_1 0x681 291 #define MSR_PRP4_LBSTK_FROM_2 0x682 292 #define MSR_PRP4_LBSTK_FROM_3 0x683 293 #define MSR_PRP4_LBSTK_FROM_4 0x684 294 #define MSR_PRP4_LBSTK_FROM_5 0x685 295 #define MSR_PRP4_LBSTK_FROM_6 0x686 296 #define MSR_PRP4_LBSTK_FROM_7 0x687 297 #define MSR_PRP4_LBSTK_FROM_8 0x688 298 #define MSR_PRP4_LBSTK_FROM_9 0x689 299 #define MSR_PRP4_LBSTK_FROM_10 0x68a 300 #define MSR_PRP4_LBSTK_FROM_11 0x68b 301 #define MSR_PRP4_LBSTK_FROM_12 0x68c 302 #define MSR_PRP4_LBSTK_FROM_13 0x68d 303 #define MSR_PRP4_LBSTK_FROM_14 0x68e 304 #define MSR_PRP4_LBSTK_FROM_15 0x68f 305 #define MSR_PRP4_LBSTK_TO_0 0x6c0 306 #define MSR_PRP4_LBSTK_TO_1 0x6c1 307 #define MSR_PRP4_LBSTK_TO_2 0x6c2 308 #define MSR_PRP4_LBSTK_TO_3 0x6c3 309 #define MSR_PRP4_LBSTK_TO_4 0x6c4 310 #define MSR_PRP4_LBSTK_TO_5 0x6c5 311 #define MSR_PRP4_LBSTK_TO_6 0x6c6 312 #define MSR_PRP4_LBSTK_TO_7 0x6c7 313 #define MSR_PRP4_LBSTK_TO_8 0x6c8 314 #define MSR_PRP4_LBSTK_TO_9 0x6c9 315 #define MSR_PRP4_LBSTK_TO_10 0x6ca 316 #define MSR_PRP4_LBSTK_TO_11 0x6cb 317 #define MSR_PRP4_LBSTK_TO_12 0x6cc 318 #define MSR_PRP4_LBSTK_TO_13 0x6cd 319 #define MSR_PRP4_LBSTK_TO_14 0x6ce 320 #define MSR_PRP4_LBSTK_TO_15 0x6cf 321 322 #define MCI_CTL_VALUE 0xffffffff 323 324 #define MTRR_TYPE_UC 0 325 #define MTRR_TYPE_WC 1 326 #define MTRR_TYPE_WT 4 327 #define MTRR_TYPE_WP 5 328 #define MTRR_TYPE_WB 6 329 #define MTRR_TYPE_UC_ 7 330 331 /* 332 * For Solaris we set up the page attritubute table in the following way: 333 * PAT0 Write-Back 334 * PAT1 Write-Through 335 * PAT2 Unchacheable- 336 * PAT3 Uncacheable 337 * PAT4 Write-Back 338 * PAT5 Write-Through 339 * PAT6 Write-Combine 340 * PAT7 Uncacheable 341 * The only difference from h/w default is entry 6. 342 */ 343 #define PAT_DEFAULT_ATTRIBUTE \ 344 ((uint64_t)MTRR_TYPE_WB | \ 345 ((uint64_t)MTRR_TYPE_WT << 8) | \ 346 ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 347 ((uint64_t)MTRR_TYPE_UC << 24) | \ 348 ((uint64_t)MTRR_TYPE_WB << 32) | \ 349 ((uint64_t)MTRR_TYPE_WT << 40) | \ 350 ((uint64_t)MTRR_TYPE_WC << 48) | \ 351 ((uint64_t)MTRR_TYPE_UC << 56)) 352 353 #define X86FSET_LARGEPAGE 0 354 #define X86FSET_TSC 1 355 #define X86FSET_MSR 2 356 #define X86FSET_MTRR 3 357 #define X86FSET_PGE 4 358 #define X86FSET_DE 5 359 #define X86FSET_CMOV 6 360 #define X86FSET_MMX 7 361 #define X86FSET_MCA 8 362 #define X86FSET_PAE 9 363 #define X86FSET_CX8 10 364 #define X86FSET_PAT 11 365 #define X86FSET_SEP 12 366 #define X86FSET_SSE 13 367 #define X86FSET_SSE2 14 368 #define X86FSET_HTT 15 369 #define X86FSET_ASYSC 16 370 #define X86FSET_NX 17 371 #define X86FSET_SSE3 18 372 #define X86FSET_CX16 19 373 #define X86FSET_CMP 20 374 #define X86FSET_TSCP 21 375 #define X86FSET_MWAIT 22 376 #define X86FSET_SSE4A 23 377 #define X86FSET_CPUID 24 378 #define X86FSET_SSSE3 25 379 #define X86FSET_SSE4_1 26 380 #define X86FSET_SSE4_2 27 381 #define X86FSET_1GPG 28 382 #define X86FSET_CLFSH 29 383 #define X86FSET_64 30 384 #define X86FSET_AES 31 385 #define X86FSET_PCLMULQDQ 32 386 #define X86FSET_XSAVE 33 387 #define X86FSET_AVX 34 388 #define X86FSET_VMX 35 389 #define X86FSET_SVM 36 390 #define X86FSET_TOPOEXT 37 391 #define X86FSET_F16C 38 392 #define X86FSET_RDRAND 39 393 #define X86FSET_X2APIC 40 394 #define X86FSET_AVX2 41 395 #define X86FSET_BMI1 42 396 #define X86FSET_BMI2 43 397 #define X86FSET_FMA 44 398 #define X86FSET_SMEP 45 399 #define X86FSET_ADX 47 400 #define X86FSET_RDSEED 48 401 #define X86FSET_AMD_PCEC 92 402 403 /* 404 * Intel Deep C-State invariant TSC in leaf 0x80000007. 405 */ 406 #define CPUID_TSC_CSTATE_INVARIANCE (0x100) 407 408 /* 409 * Intel Deep C-state always-running local APIC timer 410 */ 411 #define CPUID_CSTATE_ARAT (0x4) 412 413 /* 414 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3]. 415 */ 416 #define CPUID_EPB_SUPPORT (1 << 3) 417 418 /* 419 * Intel TSC deadline timer 420 */ 421 #define CPUID_DEADLINE_TSC (1 << 24) 422 423 /* 424 * x86_type is a legacy concept; this is supplanted 425 * for most purposes by x86_featureset; modern CPUs 426 * should be X86_TYPE_OTHER 427 */ 428 #define X86_TYPE_OTHER 0 429 #define X86_TYPE_486 1 430 #define X86_TYPE_P5 2 431 #define X86_TYPE_P6 3 432 #define X86_TYPE_CYRIX_486 4 433 #define X86_TYPE_CYRIX_6x86L 5 434 #define X86_TYPE_CYRIX_6x86 6 435 #define X86_TYPE_CYRIX_GXm 7 436 #define X86_TYPE_CYRIX_6x86MX 8 437 #define X86_TYPE_CYRIX_MediaGX 9 438 #define X86_TYPE_CYRIX_MII 10 439 #define X86_TYPE_VIA_CYRIX_III 11 440 #define X86_TYPE_P4 12 441 442 /* 443 * x86_vendor allows us to select between 444 * implementation features and helps guide 445 * the interpretation of the cpuid instruction. 446 */ 447 #define X86_VENDOR_Intel 0 448 #define X86_VENDORSTR_Intel "GenuineIntel" 449 450 #define X86_VENDOR_IntelClone 1 451 452 #define X86_VENDOR_AMD 2 453 #define X86_VENDORSTR_AMD "AuthenticAMD" 454 455 #define X86_VENDOR_Cyrix 3 456 #define X86_VENDORSTR_CYRIX "CyrixInstead" 457 458 #define X86_VENDOR_UMC 4 459 #define X86_VENDORSTR_UMC "UMC UMC UMC " 460 461 #define X86_VENDOR_NexGen 5 462 #define X86_VENDORSTR_NexGen "NexGenDriven" 463 464 #define X86_VENDOR_Centaur 6 465 #define X86_VENDORSTR_Centaur "CentaurHauls" 466 467 #define X86_VENDOR_Rise 7 468 #define X86_VENDORSTR_Rise "RiseRiseRise" 469 470 #define X86_VENDOR_SiS 8 471 #define X86_VENDORSTR_SiS "SiS SiS SiS " 472 473 #define X86_VENDOR_TM 9 474 #define X86_VENDORSTR_TM "GenuineTMx86" 475 476 #define X86_VENDOR_NSC 10 477 #define X86_VENDORSTR_NSC "Geode by NSC" 478 479 /* 480 * Vendor string max len + \0 481 */ 482 #define X86_VENDOR_STRLEN 13 483 484 /* 485 * Some vendor/family/model/stepping ranges are commonly grouped under 486 * a single identifying banner by the vendor. The following encode 487 * that "revision" in a uint32_t with the 8 most significant bits 488 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 489 * family, and the remaining 16 typically forming a bitmask of revisions 490 * within that family with more significant bits indicating "later" revisions. 491 */ 492 493 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 494 #define _X86_CHIPREV_VENDOR_SHIFT 24 495 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 496 #define _X86_CHIPREV_FAMILY_SHIFT 16 497 #define _X86_CHIPREV_REV_MASK 0x0000ffffu 498 499 #define _X86_CHIPREV_VENDOR(x) \ 500 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 501 #define _X86_CHIPREV_FAMILY(x) \ 502 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 503 #define _X86_CHIPREV_REV(x) \ 504 ((x) & _X86_CHIPREV_REV_MASK) 505 506 /* True if x matches in vendor and family and if x matches the given rev mask */ 507 #define X86_CHIPREV_MATCH(x, mask) \ 508 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 509 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 510 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 511 512 /* True if x matches in vendor and family, and rev is at least minx */ 513 #define X86_CHIPREV_ATLEAST(x, minx) \ 514 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 515 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 516 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 517 518 #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 519 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 520 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 521 522 /* True if x matches in vendor, and family is at least minx */ 523 #define X86_CHIPFAM_ATLEAST(x, minx) \ 524 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 525 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx)) 526 527 /* Revision default */ 528 #define X86_CHIPREV_UNKNOWN 0x0 529 530 /* 531 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 532 * sufficiently different that we will distinguish them; in all other 533 * case we will identify the major revision. 534 */ 535 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 536 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 537 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 538 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 539 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 540 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 541 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 542 543 /* 544 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 545 */ 546 #define X86_CHIPREV_AMD_10_REV_A \ 547 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 548 #define X86_CHIPREV_AMD_10_REV_B \ 549 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 550 #define X86_CHIPREV_AMD_10_REV_C2 \ 551 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004) 552 #define X86_CHIPREV_AMD_10_REV_C3 \ 553 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008) 554 #define X86_CHIPREV_AMD_10_REV_D0 \ 555 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010) 556 #define X86_CHIPREV_AMD_10_REV_D1 \ 557 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020) 558 #define X86_CHIPREV_AMD_10_REV_E \ 559 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040) 560 561 /* 562 * Definitions for AMD Family 0x11. 563 */ 564 #define X86_CHIPREV_AMD_11_REV_B \ 565 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002) 566 567 /* 568 * Definitions for AMD Family 0x12. 569 */ 570 #define X86_CHIPREV_AMD_12_REV_B \ 571 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002) 572 573 /* 574 * Definitions for AMD Family 0x14. 575 */ 576 #define X86_CHIPREV_AMD_14_REV_B \ 577 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002) 578 #define X86_CHIPREV_AMD_14_REV_C \ 579 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004) 580 581 /* 582 * Definitions for AMD Family 0x15 583 */ 584 #define X86_CHIPREV_AMD_15OR_REV_B2 \ 585 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001) 586 587 #define X86_CHIPREV_AMD_15TN_REV_A1 \ 588 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002) 589 590 /* 591 * Various socket/package types, extended as the need to distinguish 592 * a new type arises. The top 8 byte identfies the vendor and the 593 * remaining 24 bits describe 24 socket types. 594 */ 595 596 #define _X86_SOCKET_VENDOR_SHIFT 24 597 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 598 #define _X86_SOCKET_TYPE_MASK 0x00ffffff 599 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 600 601 #define _X86_SOCKET_MKVAL(vendor, bitval) \ 602 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 603 604 #define X86_SOCKET_MATCH(s, mask) \ 605 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 606 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 607 608 #define X86_SOCKET_UNKNOWN 0x0 609 /* 610 * AMD socket types 611 */ 612 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001) 613 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002) 614 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004) 615 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008) 616 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010) 617 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020) 618 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040) 619 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080) 620 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100) 621 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200) 622 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400) 623 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800) 624 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000) 625 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000) 626 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000) 627 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000) 628 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000) 629 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000) 630 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000) 631 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000) 632 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000) 633 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000) 634 635 636 /* 637 * Definitions for Intel processor models. These are all for Family 6 638 * processors. This list and the Atom set below it are not exhuastive. 639 */ 640 #define INTC_MODEL_MEROM 0x0f 641 #define INTC_MODEL_PENRYN 0x17 642 #define INTC_MODEL_DUNNINGTON 0x1d 643 644 #define INTC_MODEL_NEHALEM 0x1e 645 #define INTC_MODEL_NEHALEM2 0x1f 646 #define INTC_MODEL_NEHALEM_EP 0x1a 647 #define INTC_MODEL_NEHALEM_EX 0x2e 648 649 #define INTC_MODEL_WESTMERE 0x25 650 #define INTC_MODEL_WESTMERE_EP 0x2c 651 #define INTC_MODEL_WESTMERE_EX 0x2f 652 653 #define INTC_MODEL_SANDYBRIDGE 0x2a 654 #define INTC_MODEL_SANDYBRIDGE_XEON 0x2d 655 #define INTC_MODEL_IVYBRIDGE 0x3a 656 #define INTC_MODEL_IVYBRIDGE_XEON 0x3e 657 658 #define INTC_MODEL_HASWELL 0x3c 659 #define INTC_MODEL_HASWELL_ULT 0x45 660 #define INTC_MODEL_HASWELL_GT3E 0x46 661 #define INTC_MODEL_HASWELL_XEON 0x3f 662 663 #define INTC_MODEL_BROADWELL 0x3d 664 #define INTC_MODEL_BROADELL_2 0x47 665 #define INTC_MODEL_BROADWELL_XEON 0x4f 666 667 #define INCC_MODEL_SKYLAKE_MOBILE 0x4e 668 #define INTC_MODEL_SKYLAKE_DESKTOP 0x5e 669 670 #define INTC_MODEL_KABYLAKE_MOBILE 0x8e 671 #define INTC_MODEL_KABYLAKE_DESKTOP 0x9e 672 673 /* 674 * Atom Processors 675 */ 676 #define INTC_MODEL_SILVERTHORNE 0x1c 677 #define INTC_MODEL_LINCROFT 0x26 678 #define INTC_MODEL_PENWELL 0x27 679 #define INTC_MODEL_CLOVERVIEW 0x35 680 #define INTC_MODEL_CEDARVIEW 0x36 681 #define INTC_MODEL_BAY_TRAIL 0x37 682 #define INTC_MODEL_AVATON 0x4d 683 #define INTC_MODEL_AIRMONT 0x4c 684 #define INTC_MODEL_GOLDMONT 0x5c 685 #define INTC_MODEL_DENVERTON 0x5f 686 #define INTC_MODEL_GEMINI_LAKE 0x7a 687 688 /* 689 * xgetbv/xsetbv support 690 */ 691 692 #define XFEATURE_ENABLED_MASK 0x0 693 /* 694 * XFEATURE_ENABLED_MASK values (eax) 695 */ 696 #define XFEATURE_LEGACY_FP 0x1 697 #define XFEATURE_SSE 0x2 698 #define XFEATURE_AVX 0x4 699 #define XFEATURE_MAX XFEATURE_AVX 700 #define XFEATURE_FP_ALL \ 701 (XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX) 702 703 #if !defined(_ASM) 704 705 #if defined(_KERNEL) || defined(_KMEMUSER) 706 707 #define NUM_X86_FEATURES 93 708 extern uchar_t x86_featureset[]; 709 710 extern void free_x86_featureset(void *featureset); 711 extern boolean_t is_x86_feature(void *featureset, uint_t feature); 712 extern void add_x86_feature(void *featureset, uint_t feature); 713 extern void remove_x86_feature(void *featureset, uint_t feature); 714 extern boolean_t compare_x86_featureset(void *setA, void *setB); 715 extern void print_x86_featureset(void *featureset); 716 717 718 extern uint_t x86_type; 719 extern uint_t x86_vendor; 720 extern uint_t x86_clflush_size; 721 722 extern uint_t pentiumpro_bug4046376; 723 724 extern const char CyrixInstead[]; 725 726 #endif 727 728 #if defined(_KERNEL) 729 730 /* 731 * This structure is used to pass arguments and get return values back 732 * from the CPUID instruction in __cpuid_insn() routine. 733 */ 734 struct cpuid_regs { 735 uint32_t cp_eax; 736 uint32_t cp_ebx; 737 uint32_t cp_ecx; 738 uint32_t cp_edx; 739 }; 740 741 /* 742 * Utility functions to get/set extended control registers (XCR) 743 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK. 744 */ 745 extern uint64_t get_xcr(uint_t); 746 extern void set_xcr(uint_t, uint64_t); 747 748 extern uint64_t rdmsr(uint_t); 749 extern void wrmsr(uint_t, const uint64_t); 750 extern uint64_t xrdmsr(uint_t); 751 extern void xwrmsr(uint_t, const uint64_t); 752 extern int checked_rdmsr(uint_t, uint64_t *); 753 extern int checked_wrmsr(uint_t, uint64_t); 754 755 extern void invalidate_cache(void); 756 extern ulong_t getcr4(void); 757 extern void setcr4(ulong_t); 758 759 extern void mtrr_sync(void); 760 761 extern void cpu_fast_syscall_enable(void *); 762 extern void cpu_fast_syscall_disable(void *); 763 764 struct cpu; 765 766 extern int cpuid_checkpass(struct cpu *, int); 767 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 768 extern uint32_t __cpuid_insn(struct cpuid_regs *); 769 extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 770 extern int cpuid_getidstr(struct cpu *, char *, size_t); 771 extern const char *cpuid_getvendorstr(struct cpu *); 772 extern uint_t cpuid_getvendor(struct cpu *); 773 extern uint_t cpuid_getfamily(struct cpu *); 774 extern uint_t cpuid_getmodel(struct cpu *); 775 extern uint_t cpuid_getstep(struct cpu *); 776 extern uint_t cpuid_getsig(struct cpu *); 777 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 778 extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 779 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 780 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 781 extern int cpuid_get_chipid(struct cpu *); 782 extern id_t cpuid_get_coreid(struct cpu *); 783 extern int cpuid_get_pkgcoreid(struct cpu *); 784 extern int cpuid_get_clogid(struct cpu *); 785 extern int cpuid_get_cacheid(struct cpu *); 786 extern uint32_t cpuid_get_apicid(struct cpu *); 787 extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 788 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 789 extern uint_t cpuid_get_compunitid(struct cpu *cpu); 790 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu); 791 extern int cpuid_is_cmt(struct cpu *); 792 extern int cpuid_syscall32_insn(struct cpu *); 793 extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 794 795 extern uint32_t cpuid_getchiprev(struct cpu *); 796 extern const char *cpuid_getchiprevstr(struct cpu *); 797 extern uint32_t cpuid_getsockettype(struct cpu *); 798 extern const char *cpuid_getsocketstr(struct cpu *); 799 800 extern int cpuid_have_cr8access(struct cpu *); 801 802 extern int cpuid_opteron_erratum(struct cpu *, uint_t); 803 804 struct cpuid_info; 805 806 extern void setx86isalist(void); 807 extern void cpuid_alloc_space(struct cpu *); 808 extern void cpuid_free_space(struct cpu *); 809 extern void cpuid_pass1(struct cpu *, uchar_t *); 810 extern void cpuid_pass2(struct cpu *); 811 extern void cpuid_pass3(struct cpu *); 812 extern void cpuid_pass4(struct cpu *, uint_t *); 813 extern void cpuid_set_cpu_properties(void *, processorid_t, 814 struct cpuid_info *); 815 816 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 817 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 818 819 #if !defined(__xpv) 820 extern uint32_t *cpuid_mwait_alloc(struct cpu *); 821 extern void cpuid_mwait_free(struct cpu *); 822 extern int cpuid_deep_cstates_supported(void); 823 extern int cpuid_arat_supported(void); 824 extern int cpuid_iepb_supported(struct cpu *); 825 extern int cpuid_deadline_tsc_supported(void); 826 extern void vmware_port(int, uint32_t *); 827 #endif 828 829 struct cpu_ucode_info; 830 831 extern void ucode_alloc_space(struct cpu *); 832 extern void ucode_free_space(struct cpu *); 833 extern void ucode_check(struct cpu *); 834 extern void ucode_cleanup(); 835 836 #if !defined(__xpv) 837 extern char _tsc_mfence_start; 838 extern char _tsc_mfence_end; 839 extern char _tscp_start; 840 extern char _tscp_end; 841 extern char _no_rdtsc_start; 842 extern char _no_rdtsc_end; 843 extern char _tsc_lfence_start; 844 extern char _tsc_lfence_end; 845 #endif 846 847 #if !defined(__xpv) 848 extern char bcopy_patch_start; 849 extern char bcopy_patch_end; 850 extern char bcopy_ck_size; 851 #endif 852 853 extern void post_startup_cpu_fixups(void); 854 855 extern uint_t workaround_errata(struct cpu *); 856 857 #if defined(OPTERON_ERRATUM_93) 858 extern int opteron_erratum_93; 859 #endif 860 861 #if defined(OPTERON_ERRATUM_91) 862 extern int opteron_erratum_91; 863 #endif 864 865 #if defined(OPTERON_ERRATUM_100) 866 extern int opteron_erratum_100; 867 #endif 868 869 #if defined(OPTERON_ERRATUM_121) 870 extern int opteron_erratum_121; 871 #endif 872 873 #if defined(OPTERON_WORKAROUND_6323525) 874 extern int opteron_workaround_6323525; 875 extern void patch_workaround_6323525(void); 876 #endif 877 878 #if !defined(__xpv) 879 extern void determine_platform(void); 880 #endif 881 extern int get_hwenv(void); 882 extern int is_controldom(void); 883 884 extern void xsave_setup_msr(struct cpu *); 885 886 /* 887 * Hypervisor signatures 888 */ 889 #define HVSIG_XEN_HVM "XenVMMXenVMM" 890 #define HVSIG_VMWARE "VMwareVMware" 891 #define HVSIG_KVM "KVMKVMKVM" 892 #define HVSIG_MICROSOFT "Microsoft Hv" 893 894 /* 895 * Defined hardware environments 896 */ 897 #define HW_NATIVE (1 << 0) /* Running on bare metal */ 898 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */ 899 900 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */ 901 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */ 902 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */ 903 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */ 904 905 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT) 906 907 #endif /* _KERNEL */ 908 909 #endif /* !_ASM */ 910 911 /* 912 * VMware hypervisor related defines 913 */ 914 #define VMWARE_HVMAGIC 0x564d5868 915 #define VMWARE_HVPORT 0x5658 916 #define VMWARE_HVCMD_GETVERSION 0x0a 917 #define VMWARE_HVCMD_GETTSCFREQ 0x2d 918 919 #ifdef __cplusplus 920 } 921 #endif 922 923 #endif /* _SYS_X86_ARCHEXT_H */ 924